Data sheet acquired from Cypress Semiconductor Corporation. Data sheet modified to remove devices not offered. CY29FCT520T Multi-Level Pipeline Register SCCS011A - May 1994 - Revised April 2000 Features Functional Description • Function, pinout, and drive compatible with FCT, F Logic, and AM29520 • FCT-C speed at 6.0 ns max. (Com’l), FCT-B speed at 7.5 ns max. (Com’l), FCT-A speed at 14.0 ns max. (Com’l) • Reduced VOH (typically = 3.3V) versions of equivalent FCT functions • Edge-rate control circuitry for significantly improved noise characteristics • Power-Off disable feature • Matched rise and fall times • Fully compatible with TTL input and output logic levels • ESD > 2000V • Sink current 64 mA (Com’l), 32 mA (Mil) Source current 32 mA (Com’l), 12 mA (Mil) • Single and dual pipeline operation modes • Multiplexed data inputs and outputs Logic Block Diagram The CY29FCT520T devices are multilevel 8-bit-wide pipeline registers. The devices consist of four registers, A1, A2, B1, and B2, which are configured by the instruction inputs I0, I1 as a single 4-level pipeline or as two two-level pipelines. The contents of any register may be read at the multiplexed output at any time by using the mux-selection controls S0 and S1. The pipeline registers are positive edge triggered and data is shifted by the rising edge of the clock input. Instruction I=0 selects the four-level pipeline mode. Instruction I=1 selects the two-level B pipeline while I=2 selects the two-level A pipeline. I=3 is the HOLD instruction; no shifting is performed by the clock in this mode. In the two-level operation mode, data is shifted from level 1 to level 2 and new data is loaded into level 1. The outputs are designed with a power-off disable feature to allow for live insertion of boards. Pin Configurations D0 –D 7 8 DIP, SOIC, QSOP, CDIP Top View INSTRUCTION I0 MUX REGISTER CONTROLS I1 CLOCK OCTAL REG B1 OCTAL REG A1 MUX S0 SEL S1 OCTAL REG A2 OCTAL REG B2 I0 1 24 VCC I1 2 23 S0 D0 3 22 S1 D1 4 21 Y0 D2 5 20 Y1 D3 6 19 Y2 D4 7 18 Y3 D5 8 17 Y4 D6 9 16 Y5 D7 10 Y6 CLK 11 15 14 GND 12 13 OE Y7 MUX OE 8 Y0 –Y 7 Pipeline Instruction Table I=0 I1 = 0 I=1 I0 = 0 I1 = 0 I=2 I=3 I0 = 1 I1 = 1 I0 = 0 I1 = 1 I0 = 1 A1 B1 A1 B1 A1 B1 A1 B1 A2 B2 A2 B2 A2 B2 A2 B2 Single four-level Dual two-level Hold Copyright © 2000, Texas Instruments Incorporated CY29FCT520T Supply Voltage to Ground Potential ............... –0.5V to +7.0V Output Selection Mux Table DC Input Voltage ........................................... –0.5V to +7.0V Inputs. S1 S0 Output 1 1 0 0 1 0 1 0 A1 A2 B1 B2 DC Output Voltage......................................... –0.5V to +7.0V DC Output Current (Maximum Sink Current/Pin) ...... 120 mA Power Dissipation .......................................................... 0.5W Static Discharge Voltage............................................>2001V (per MIL-STD-883, Method 3015) Maximum Ratings[1, 2] Operating Range (Above which the useful life may be impaired. For user guidelines, not tested.) Range Ambient Temperature[3] VCC Storage Temperature .................................–65°C to +150°C Commercial –40°C to +85°C 5V ± 5% Ambient Temperature with Power Applied .............................................–65°C to +135°C Military –55°C to +125°C 5V ± 10% Electrical Characteristics Over the Operating Range Parameter VOH VOL Description Output HIGH Voltage Output LOW Voltage Test Conditions Min. Typ.[4] Max. Unit VCC=Min., IOH=–32 mA Com’l 2.0 V VCC=Min., IOH=–15 mA Com’l 2.4 3.3 V VCC=Min., IOH=–12 mA Mil 2.4 3.3 V VCC=Min., IOL=64 mA Com’l 0.3 0.55 V VCC=Min., IOL=32 mA Mil 0.3 0.55 V VIH Input HIGH Voltage VIL Input LOW Voltage 2.0 V VH Hysteresis[5] All inputs 0.2 VIK Input Clamp Diode Voltage VCC=Min., IIN=–18 mA –0.7 –1.2 V II Input HIGH Current VCC=Max., VIN=VCC 5 µA IIH Input HIGH Current VCC=Max., VIN=2.7V ±1 µA IIL Input LOW Current VCC=Max., VIN=0.5V ±1 µA IOZH Off State HIGH-Level Output Current VCC=Max., VOUT=2.7V 10 µA IOZL Off State LOW-Level Output Current VCC=Max., VOUT = 0.5V –10 µA IOS Output Short Circuit Current[6] VCC=Max., VOUT=0.0V –225 mA IOFF Power-Off Disable VCC=0V, VOUT=4.5V ±1 µA Typ.[4] Max. Unit 0.8 –60 –120 V V Capacitance[5] Parameter Description Test Conditions CIN Input Capacitance 5 10 pF COUT Output Capacitance 9 12 pF Notes: 1. Unless otherwise noted, these limits are over the operating free-air temperature range. 2. Unused inputs must always be connected to an appropriate logic voltage level, preferably either VCC or ground. 3. TA is the “instant on” case temperature. 4. Typical values are at VCC=5.0V, TA=+25˚C ambient. 5. This parameter is specified but not tested. 6. Not more than one output should be shorted at a time. Duration of short should not exceed one second. The use of high-speed test apparatus and/or sample and hold techniques are preferable in order to minimize internal chip heating and more accurately reflect operational values. Otherwise prolonged shorting of a high output may raise the chip temperature well above normal and thereby cause invalid readings in other parametric tests. In any sequence of parameter tests, IOS tests should be performed last. 2 CY29FCT520T Power Supply Characteristics Parameter ICC Description Quiescent Power Supply Current Test Conditions VCC=Max., VIN<0.2V, VIN>VCC–0.2V Typ.[4] Max. Unit 0.1 0.2 mA 0.5 2.0 mA ∆ICC Quiescent Power Supply Current (TTL inputs HIGH) VCC=Max., VIN=3.4V, f1=0, Outputs Open ICCD Dynamic Power Supply Current[8] VCC=Max., One Input Toggling, 50% Duty Cycle, Outputs Open, OE=GND, VIN<0.2V or VIN>VCC–0.2V 0.06 0.12 mA/MHz IC Total Power Supply Current[9] VCC=Max., 50% Duty Cycle, Outputs Open, f0=10 MHz, One Bit Toggling at f1=5 MHz, OE=GND, VIN<0.2V or VIN>VCC–0.2V 0.7 1.4 mA VCC=Max., 50% Duty Cycle, Outputs Open, f0=10 MHz, One Bit Toggling at f1=5 MHz, OE=GND, VIN=3.4V or VIN=GND 1.2 3.4 mA VCC=Max., 50% Duty Cycle, Outputs Open, f0=10 MHz, Eight Bits Toggling at f1=5 MHz, OE=GND, VIN<0.2V or VIN>VCC–0.2V 2.8 5.6[10] mA VCC=Max., 50% Duty Cycle, Outputs Open, f0=10 MHz, Eight Bits Toggling at f1=5 MHz, OE=GND, VIN=3.4V or VIN=GND 5.1 14.3[10] mA Notes: 7. Per TTL driven input (VIN=3.4V); all other inputs at VCC or GND. 8. This parameter is not directly testable, but is derived for use in Total Power Supply calculations. = IQUIESCENT + IINPUTS + IDYNAMIC 9. IC IC = ICC+∆ICCDHNT+ICCD(f0/2 + f1N1) ICC = Quiescent Current with CMOS input levels ∆ICC = Power Supply Current for a TTL HIGH input (VIN=3.4V) DH = Duty Cycle for TTL inputs HIGH NT = Number of TTL inputs at DH ICCD = Dynamic Current caused by an input transition pair (HLH or LHL) = Clock frequency for registered devices, otherwise zero f0 = Input signal frequency f1 N1 = Number of inputs changing at f1 All currents are in milliamps and all frequencies are in megahertz. 10. Values for these conditions are examples of the ICC formula. These limits are specified but not tested. 3 [7] CY29FCT520T Switching Characteristics Over the Operating Range[11] CY29FCT520AT Military CY29FCT520BT Commercial Military Commercial Description Min Max. Min Max. Min. Max. Min. Max. Unit Fig. No.[12] tPLH tPHL Propagation Delay Clock to Data Output 2.0 16.0 2.0 14.0 2.0 8.0 2.0 7.5 ns 1, 5 tPLH tPHL Propagation Delay S0, S1 to Data Output 2.0 15.0 2.0 13.0 2.0 8.0 2.0 7.5 ns 1, 5 tS Set-Up Time Input Data to Clock 6.0 5.0 2.8 2.5 ns 4 tH Hold Time Input Data to Clock 2.0 2.0 2.0 2.0 ns 4 tS Set-Up Time Instruction (Reg. Enable) to Clock 6.0 5.0 4.5 4.0 ns 4 tH Hold Time Instruction (Reg. Enable) to Clock 2.0 2.0 2.0 2.0 ns 4 tPHZ tPLZ Output Disable Time 1.5 13.0 1.5 12.0 1.5 7.5 1.5 7.0 ns 1, 7, 8 tPZH tPZL Output Enable Time 1.5 16.0 1.5 15.0 1.5 8.0 1.5 7.5 ns 1, 7, 8 tW Clock Pulse Width,[5] HIGH or LOW 8.0 ns 5 Parameter 7.0 6.0 5.5 CY29FCT520CT Commercial Parameter Description Min. Max. Unit Fig. No.[12] tPLH tPHL Propagation Delay Clock to Data Output 2.0 6.0 ns 1, 5 tPLH tPHL Propagation Delay S0, S1 to Data Output 2.0 6.0 ns 1, 5 tS Set-Up Time Input Data to Clock 2.5 ns 4 tH Hold Time Input Data to Clock 2.0 ns 4 tS Set-Up Time Instruction (Reg. Enable) to Clock 4.0 ns 4 tH Hold Time Instruction (Reg. Enable) to Clock 2.0 ns 4 tPHZ tPLZ Output Disable Time 1.5 6.0 ns 1, 7, 8 tPZH tPZL Output Enable Time 1.5 6.0 ns 1, 7, 8 tW Clock Pulse Width,[5] HIGH or LOW 5.5 ns 5 Notes: 11. Minimum limits are specified but not tested on Propagation Delays. 12. See “Parameter Measurement Information” in the General Information section. 4 CY29FCT520T Ordering Information Speed (ns) Ordering Code 6.0 CY29FCT520CTSOC/SOCT 7.5 8.0 14.0 CY29FCT520ATPC 16.0 Package Name Package Type Operating Range S13 24-Lead (300-Mil) Molded SOIC Commercial CY29FCT520BTSOC/SOCT S13 24-Lead (300-Mil) Molded SOIC Commercial 5962-9220504MLA (CY29FCT520BTDMB) D14 24-Lead (300-Mil) CDIP Military 24-Lead (300-Mil) Molded DIP Commercial P13/13A CY29FCT520ATSOC/SOCT S13 24-Lead (300-Mil) Molded SOIC 5962-9220502MLA (CY29FCT520ATDMB) D14 24-Lead (300-Mil) CDIP 5 Military CY29FCT520T Package Diagrams 24-Lead (300-Mil) CDIP MIL-STD-1835 D14 D- 9 Config.A 24-Lead (300-Mil) Molded DIP P13/P13A 6 CY29FCT520T Package Diagrams (continued) 24-Lead Quarter Size Outline Q13 24-Lead (300-Mil) Molded SOIC S13 7 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. 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