ETC AM29243

ADVANCE INFORMATION
Am29240, Am29245 , and Am29243
High-Performance RISC Microcontrollers
Advanced
Micro
Devices
DISTINCTIVE CHARACTERISTICS
Am29240 Microcontroller
All three microcontrollers in the Am29240 microcontroller series have the following characteristics:
The Am29240 microcontroller has the following additional features:
Completely integrated system for embedded
applications
2-Kbyte, two-way set-associative data cache
Full 32-bit architecture
4-Kbyte, two-way set-associative instruction
cache
4-Gbyte virtual address space, 304-Mbyte
physical space implemented
Glueless system interfaces with on-chip wait
state control
Single-cycle 32-bit multiplier for faster integer
math; two-cycle Multiply Accumulate (MAC)
function
16-entry on-chip Memory Management Unit
(MMU) with one Translation Look-Aside Buffer
4-channel double-buffered DMA controller with
queued reload
Two serial ports (UARTs)
36 VAX million instructions per second (MIPS)
sustained at 25 MHz
Bidirectional bit serializer/deserializer
Four banks of ROM, each separately
programmable for 8-, 16-, or 32-bit interface
Scalable Clocking feature with full- and
double-speed internal clock
Four banks of DRAM, each separately
programmable for 16- or 32-bit interface
Single-cycle ROM burst-mode and DRAM
page-mode access
6-port peripheral interface adapter
20- and 25-MHz operating frequencies
Am29245 Microcontroller
The low-cost Am29245 microcontroller is similar to the
Am29240 microcontroller, without the data cache and
32-bit multiplier. It includes the following features:
16-line programmable I/O port
16-entry on-chip MMU with one TLB
Bidirectional parallel port controller
Bidirectional bit serializer/deserializer
Interrupt controller
Two-channel DMA controller
Fully pipelined integer unit
One serial port (UART)
Three-address instruction architecture
16-MHz operating frequency
192 general purpose registers
Traceable Cache technology instruction and
data cache tracing
IEEE Std 1149.1-1990 (JTAG) compliant
Standard Test Access Port and
Boundary Scan Architecture
Am29243 Microcontroller
The Am29243 data microcontroller is similar to the
Am29240 microcontroller, without the video interface. It
includes the following features:
2-Kbyte, two-way set-associative data cache
Binary compatibility with all 29K family
microprocessors and microcontrollers
Single-cycle 32-bit multiplier for faster integer
math; two-cycle MAC
Fully static system-clock capabilities
32-entry on-chip MMU with dual TLBs
CMOS technology/TTL compatible
4-channel, double-buffered DMA controller with
queued reload
196-pin Plastic Quad Flat Pack (PQFP) package*
5-V power supply*
Note: * The new Am29240EH, Am29245EH, and Am29243EH
microcontrollers are packaged as 208-pin PQFPs and use a 3.3-V
power supply with 5-V-tolerant I/O. Before beginning a new design,
check with your field representative for schedule and availability of the
Am29240EH microcontroller series, described in Amendment 1 (order
#17787/1).
Two serial ports (UARTs)
20- and 25-MHz operating frequencies
Scalable Clocking feature with full- and
double-speed internal clock
DRAM parity
This document contains information on a product under development at Advanced Micro Devices, Inc. The information is intended
to help you evaluate this product. AMD reserves the right to change or discontinue work on this proposed product without notice.
Publication #: 17787 Rev. C Amendment: /0
Issue Date: August 1995. WWW: 11/7/94
AMD
ADVANCE INFORMATION
TABLE OF CONTENTS
DISTINCTIVE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Am29240 MICROCONTROLLER BLOCK DIAGRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Am29245 MICROCONTROLLER BLOCK DIAGRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Am29243 MICROCONTROLLER BLOCK DIAGRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
CUSTOMER SERVICE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Am29240 MICROCONTROLLER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Am29245 MICROCONTROLLER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Am29243 MICROCONTROLLER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
29K FAMILY DEVELOPMENT SUPPORT PRODUCTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
THIRD-PARTY DEVELOPMENT SUPPORT PRODUCTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
RELATED AMD PRODUCTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
KEY FEATURES AND BENEFITS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
PERFORMANCE OVERVIEW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
PIN INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
PIN DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
CONNECTION DIAGRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
LOGIC SYMBOLS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
OPERATING RANGES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
DC CHARACTERISTICS over COMMERCIAL Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
CAPACITANCE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
SWITCHING CHARACTERISTICS over COMMERCIAL Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
SWITCHING WAVEFORMS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
SWITCHING TEST CIRCUIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
THERMAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
PHYSICAL DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
PQB 196 PLASTIC QUAD FLAT PACK, TRIMMED AND FORMED . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
SOLDER LAND RECOMMENDATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
2
Am29240 Microcontroller Series
ADVANCE INFORMATION
AMD
Am29240 MICROCONTROLLER BLOCK DIAGRAM
Parallel Port
Control/Status
Lines
4
6
Serial
Data
Printer/Scanner
Video
ROM
Chip Selects
6
STAT
MEMCLK
4
JTAG
Clock/
Control
Lines
8
11
4 DREQ
4 DACK
GREQ/GACK/TDMA
Parallel Port
Controller
Am29000 CPU
4-Channel DMA
Controller
16
Dual
Serial Ports
Programmable
I/O Port
I/O
4K ICache
Serializer/
Deserializer
2K DCache
Interrupt
Controller
ROM
Controller
4
6
24
4/4
32
Instruction/Data
Bus
Address
Bus
PIA
Chip Selects
RAS/CAS
Timer/Counter
MMU
6
Interrupts, Traps
32x32 Multiply DRAM Controller
PIA
Controller
ROM
Space
Memory
5
DRAM
Peripherals
Am29245 MICROCONTROLLER BLOCK DIAGRAM
Parallel Port
Control/Status
Lines
4
4
Serial
Data
Printer/Scanner
Video
ROM
Chip Selects
4
ROM
Space
Memory
6
STAT
MEMCLK
Parallel Port
Controller
Single
Serial Port
4
JTAG
5
Clock/
Control
Lines
8
7
2 DREQ
2 DACK
GREQ/GACK/TDMA
16
Am29000 CPU
2-Channel DMA
Controller
Programmable
I/O Port
I/O
4K ICache
Serializer/
Deserializer
Interrupt
Controller
ROM
Controller
DRAM Controller
PIA
Controller
MMU
6
PIA
Chip Selects
24
Address
Bus
Timer/Counter
32
Instruction/Data
Bus
6
Interrupts, Traps
RAS/CAS
4/4
DRAM
Peripherals
Am29240 Microcontroller Series
3
AMD
ADVANCE INFORMATION
Am29243 MICROCONTROLLER BLOCK DIAGRAM
Parallel Port
Control/Status
Lines
5
6
Serial
Data
ROM
Chip Selects
STAT
MEMCLK
Clock/
Control
Lines
4
8
11
4 DREQ
4 DACK
GREQ/GACK/TDMA
Parallel Port
Controller
4-Channel DMA
Controller
16
Am29000 CPU
Dual
Serial Ports
Programmable
I/O Port
I/O
4K ICache
JTAG
2K DCache
Interrupt
Controller
ROM
Controller
4
ROM
Space
Memory
6
32x32 Multiply DRAM Controller
PIA
Controller
Interrupts, Traps
RAS/CAS
4/4
Timer/Counter
MMU
32
36
6
PIA
Chip Selects
6
24
32
Instruction/Data
Bus
Address
Bus
DRAM
Peripherals
CUSTOMER SERVICE
AMD’s customer service network includes U.S. offices,
international offices, and a customer training center. Expert technical assistance is available from AMD’s worldwide staff of field application engineers and factory
support staff.
Hotline, E-mail, and Bulletin Board Support
For answers to technical questions, AMD provides a
toll-free number for direct access to our engineering
support staff. For overseas customers, the easiest way
to reach the engineering support staff with your questions is via fax with a short description of your question.
AMD 29K family customers also receive technical support through electronic mail. This worldwide service is
available to 29K family product users via the international
Internet e-mail service. Also available is the AMD bulletin
board service, which provides the latest 29K family product information, including technical information and data
on upcoming product releases.
Engineering Support Staff
(800) 292-9263, ext. 2
0031-11-1163
(512) 602-4118
44-(0)256-811101
4
toll-free for U.S.
toll-free for Japan
direct dial worldwide
U.K. and Europe hotline
(512) 602-5031
[email protected]
fax
e-mail
Bulletin Board
(800) 292-9263, ext. 1
(512) 602-7604
toll-free for U.S.
direct dial worldwide
Product Information
A simple phone call gets you free printed publications,
such as data books, user’s manuals, data sheets, application notes, the Fusion29K Partner Solutions Catalog and Newsletter, and other literature. Internationally,
contact your local AMD sales office for complete 29K
family literature. For electronic copies of the most current product information and publications on the 29K
family, visit AMD’s worldwide web site on the Internet.
Literature Request
(800) 292-9263, ext. 3
(512) 602-5651
(512) 602-7639
(800) 222-9323, option 2
http://www.amd.com
Am29240 Microcontroller Series
toll-free for U.S.
direct dial worldwide
fax for U.S.
AMD Facts-On-Demand
fax information service
toll-free for U.S.
worldwide web
ADVANCE INFORMATION
GENERAL DESCRIPTION
The Am29240 microcontroller series is an enhanced
bus-compatible extension of the Am29200 RISC microcontroller family, with two to four times the performance. The Am29240 microcontroller series includes
the Am29240 microcontroller, the low-cost Am29245
microcontroller, and the Am29243 data microcontroller.
The on-chip caches, MMU, faster integer math, and extended DMA addressing capability of the Am29240 microcontroller series allow the embedded systems
designer to provide increasing levels of performance
and software compatibility throughout a range of products (see Table 1 on page 7).
Based on a static low-voltage design, these CMOStechnology devices offer a complete set of system peripherals and interfaces commonly used in embedded
applications. Compared to CISC processors, the
Am29240 microcontroller series offers better performance, more efficient use of low-cost memories, lower
system cost, and complete design flexibility for the designer. Coupled with hardware and software development tools from AMD and the AMD Fusion29K
partners, the Am29240 microcontroller series provides
the embedded product designer with the cost and performance edge required by today’s marketplace.
AMD
The Am29245 microcontroller also provides an easy upgrade path for Am29200, Am29202, and Am29205
microcontroller-based products.
Am29243 Microcontroller
With DRAM parity support and a full MMU, the
Am29243 data microcontroller is recommended for
communications applications that require high-speed
data movement and fast protocol processing in a faulttolerant environment.
Both the Am29243 and Am29240 microcontrollers support fly-by DMA at 100 Mbytes/s for LANs and switching
applications, and a two-cycle Multiply Accumulate function for DSP applications. The low power requirements
make either microcontroller a good choice for fielddeployed devices.
29K Family
Development Support Products
Contact your local AMD representative for information
on the complete set of development support tools. The
following software and hardware development products
are available on several hosts:
Optimizing compilers for common high-level
languages
Am29240 Microcontroller
Assembler and utility packages
For general-purpose embedded applications, such as
mass-storage controllers, communications, digital signal processing, networking, industrial control, penbased systems, and multimedia, the Am29240
microcontroller provides a high-performance solution
with a low total-system cost. The memory interface of
the Am29240 microcontroller provides even faster direct memory access than the Am29200 microcontroller.
This performance improvement minimizes the effect of
memory latency, allowing designers to use low-cost
memory with simpler memory designs. On-chip instruction and data caches provide even better performance
for time-critical code.
Source- and assembly-level software debuggers
Other on-chip functions include: a ROM controller,
DRAM controller, peripheral interface adapter controller, DMA controller, programmable I/O port, parallel port
controller, serial ports, and an interrupt controller. For a
complete description of the technical features, on-chip
peripherals, programming interface, and instruction set,
please refer to the Am29240, Am29245, and Am29243
RISC Microcontrollers User’s Manual (order #17741).
Target-resident development monitors
Simulators
Execution boards
Third-Party
Development Support Products
The Fusion29K Program of Partnerships for Application
Solutions provides the user with a vast array of products
designed to meet critical time-to-market needs. Products/solutions available from the AMD Fusion29K partners include the following:
Silicon products
Software generation and debug tools
Hardware development tools
Board-level products
Laser-printer solutions
Multiuser, kernel, and real-time operating systems
Graphics solutions
Am29245 Microcontroller
The low-cost Am29245 microcontroller is designed for
embedded applications in which cost and space
constraints, along with increased performance requirements, are primary considerations.
Networking and communication solutions
Manufacturing support
Custom software consulting, support, and training
Am29240 Microcontroller Series
5
AMD
ADVANCE INFORMATION
ORDERING INFORMATION
Standard Products
AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is
formed by a combination of the elements below.
Am29240
–25
K
C
\W
PROCESSING
\W = Trimmed and Formed (PQB 196)
TEMPERATURE RANGE
C = Commercial (TC = 0°C to +85°C)
PACKAGE TYPE
K = 196-Lead Plastic Quad Flat Pack (PQB 196)
SPEED OPTION
–25 = 25 MHz
–20 = 20 MHz
–16 = 16 MHz
Valid Combinations
Am29240–20
Am29240–25
KC\W
Am29243–20
Am29243–25
KC\W
Am29245–16
KC\W
DEVICE NUMBER/DESCRIPTION
Am29240 RISC Microcontroller
Am29245 RISC Microcontroller
Am29243 RISC Data Microcontroller
Valid Combinations
Valid Combinations lists configurations
planned to be supported in volume. Consult
the local AMD sales office to confirm
availability of specific valid combinations, to
check on newly released combinations, and
to obtain additional data on AMD standard
military grade products.
RELATED AMD PRODUCTS
29K Family Devices
Product
Description
Am29000R
32-bit RISC microprocessor
Am29005
Low-cost 32-bit RISC microprocessor with no MMU and no branch target cache
Am29030
32-bit RISC microprocessor with 8-Kbyte instruction cache
Am29035
32-bit RISC microprocessor with 4-Kbyte instruction cache
Am29040
32-bit RISC microprocessor with 8-Kbyte instruction cache and 4-Kbyte data cache
Am29050
32-bit RISC microprocessor with on-chip floating point
Am29200
32-bit RISC microcontroller
Am29202
Low-cost 32-bit RISC microcontroller with IEEE-1284-compliant parallel interface
Am29205
Low-cost 32-bit RISC microcontroller
6
Am29240 Microcontroller Series
ADVANCE INFORMATION
AMD
Table 1. Product Comparison—Am29200 Microcontroller Family
FEATURE
Am29205
Controller
Am29202
Controller
Am29200
Controller
Am29245
Controller
Am29240
Controller
Am29243
Controller
Instruction Cache
—
—
—
4 Kbytes
4 Kbytes
4 Kbytes
Data Cache
—
—
—
—
2 Kbytes
2 Kbytes
Cache Associativity
—
—
—
2-way
2-way
2-way
Software
Software
Software
Software
32 x 32-bit
32 x 32-bit
—
—
—
1 TLB
16 Entry
1 TLB
16 Entry
2 TLBs
32 Entry
32 bits
16 bits
32 bits
32 bits
32 bits
32 bits
32 bits
32 bits
32 bits
32 bits
32 bits
32 bits
3
8, 16 bits
4 Mbytes
16 bits
Not Supported
4
8, 16, 32 bits
4 Mbytes
8, 16, 32 bits
Not Supported
4
8, 16, 32 bits
16 Mbytes
8, 16, 32 bits
Supported
4
8, 16, 32 bits
16 Mbytes
8, 16, 32 bits
Supported
4
8, 16, 32 bits
16 Mbytes
8, 16, 32 bits
Supported
4
8, 16, 32 bits
16 Mbytes
8, 16, 32 bits
Supported
4
16 bits only
—
8 Mbytes/bank
Not Supported
4
16, 32 bits
16 Mbytes/bank
8 Mbytes/bank
Not Supported
4
16, 32 bits
16 Mbytes/bank
8 Mbytes/bank
Supported
4
16, 32 bits
16 Mbytes/bank
8 Mbytes/bank
Supported
4
16, 32 bits
16 Mbytes/bank
8 Mbytes/bank
Supported
4
16, 32 bits
16 Mbytes/bank
8 Mbytes/bank
Not Supported
3/2
No
3/2
No
3/2
No
3/1
No
3/1
No
3/1
Yes
On-Chip DMA
Width (ext. peripherals)
Total Number of Channels
Externally Controlled
External Master Access
External Master Burst
External Terminate Signal
8, 16 bits
2
1
No
No
No
8, 16, 32 bits
2
1
No
No
No
8, 16, 32 bits
2
2
Yes
No
Yes
8, 16, 32 bits
2
2
Yes
Yes
Yes
8, 16, 32 bits
4
4
Yes
Yes
Yes
8, 16, 32 bits
4
4
Yes
Yes
Yes
Scalable Clocking DoubleFrequency CPU Option
No
No
No
No
Yes
Yes
Low-Voltage Operation
No
No
No
Yes
Yes
Yes
2
8, 16 bits
3
2
8, 16, 32 bits
3
6
8, 16, 32 bits
3
6
8, 16, 32 bits
1
6
8, 16, 32 bits
1
6
8, 16, 32 bits
1
8
12
16
16
16
16
8
8
8
8
8
8
1 Port
PIO signals
1 Port
PIO signals
1 Port
Supported
1 Port
Supported
2 Ports
1 Port Supported
2 Ports
1 Port Supported
2
2
4
4
4
4
0
0
3
3
3
3
Parallel Port Controller
32-Bit Transfer
IEEE-1284 Interface
Yes
No
No
Yes
Yes
Yes
Yes
Yes
No
Yes
Yes
No
Yes
Yes
No
Yes
Yes
No
JTAG Debug Support
No
Yes
Yes
Yes
Yes
Yes
Integer Multiplier
Memory Management
Unit (MMU)
Data Bus Width
Internal
External
ROM Interface
Banks
Width
ROM Size (Max/Bank)
Boot-Up ROM Width
Burst-Mode Access
DRAM Interface
Banks
Width
Size: 32-Bit Mode
Size: 16-Bit Mode
Video DRAM
Access Cycles
Initial/Burst
DRAM Parity
Peripheral Interface
Adapter (PIA)
PIA Ports
Data Width
Min. Cycles Access
Programmable I/O Port
(PIO)
Signals
Signals programmable
for interrupt generation
Serial Ports
Ports
DSR/DTR
Interrupt Controller
External Interrupt Pins
External Trap and Warn
Pins
Serializer/Deserializer
Pin Count and Package
Operating Voltage
VCC
I/O Tolerance
Processor Clock Rate
Yes
Yes
Yes
Yes
Yes
No
100 PQFP
132 PQFP
168 PQFP
196 PQFP
196 PQFP
196 PQFP
5V
5V
5V
5V
5V
5V
5V
5V
5V
5V
5V
5V
12, 16 MHz
12, 16, 20 MHz
16, 20 MHz
16 MHz
20, 25 MHz
20, 25 MHz
Am29240 Microcontroller Series
7
AMD
ADVANCE INFORMATION
KEY FEATURES AND BENEFITS
Complete Set of Common Peripherals
The Am29240 microcontroller series extends the line of
RISC microcontrollers based on 29K family architecture, providing performance upgrades to the Am29205
and Am29200 microcontrollers. The RISC microcontroller product line allows users to benefit from the very high
performance of the 29K family architecture, while also
capitalizing on the very low system cost made possible
by integrating processor and peripherals.
The Am29240 microcontroller series minimizes system
cost by incorporating a complete set of system facilities
commonly found in embedded applications, eliminating
the cost of additional components. The on-chip functions include: a ROM controller, a DRAM controller, a peripheral interface adapter, a DMA controller, a
programmable I/O port, a parallel port, up to two serial
ports, and an interrupt controller. A video interface is
also included in the Am29240 and Am29245 microcontrollers for printer, scanner, and other imaging applications. These facilities allow many simple systems to be
built using only the Am29240 microcontroller series, external ROM, and/or DRAM memory.
The Am29240 microcontroller series expands the price/
performance range of systems that can be built with the
29K family. The Am29240 microcontroller series is fully
software compatible with the Am29000, Am29005,
Am29030, Am29035, Am29040, and Am29050 microprocessors, as well as the Am29200 and Am29205 microcontrollers. It can be used in existing 29K family
microcontroller applications without software modifications.
On-Chip Caches
The Am29240 microcontroller series incorporates a
4-Kbyte, two-way instruction cache that supplies most
processor instructions without wait states at the processor frequency. For best performance, the instruction
cache supports critical-word-first reloading with fetchthrough, so that the processor receives the required
instruction and the pipeline restarts with minimum delay.
The instruction cache has a valid bit per word to minimize the reload overhead. All cache array elements are
visible to software for testing and preload.
The Am29240 and Am29243 microcontrollers incorporate a 2-Kbyte, two-way set-associative data cache. The
data cache appears in the execute stage of the processor pipeline, so that loaded data is available immediately to the next instruction. This provides the maximum
performance for loads without requiring load scheduling. The data cache performs critical-word-first, wraparound, and burst-mode refill with load-through. This
minimizes the time the processor waits on external data
as well as minimizing the reload time. The data cache
uses a write-through policy with a two-entry write buffer.
Byte, half-word, and word reads and writes are supported. All cache array elements are visible to software
for testing and preload.
The ROM controller supports four individual banks of
ROM or other static memory, each with its own timing
characteristics. Each ROM bank may be a different size
and may be either 8, 16, or 32 bits wide. The ROM banks
can appear as a contiguous memory area of up to 64
Mbytes in size. The ROM controller also supports byte,
half-word, and word writes to the ROM memory space
for devices such as flash EPROMs and SRAMs.
DRAM Controller
The DRAM controller supports four separate banks of
dynamic memory. Each bank may be a different size and
may be either 16 or 32 bits wide. The DRAM banks can
appear as a contiguous memory area of up to 64 Mbytes
in size. The DRAM controller supports three-cycle accesses, with single-cycle page-mode and burst-mode
accesses.
Peripheral Interface Adapter
The Peripheral Interface Adapter (PIA) permits glueless
interfacing to as many as six external peripheral chips.
The PIA allows for additional system features implemented by external peripheral chips.
DMA Controller
The DMA controller provides up to four channels for
transferring data between the DRAM and internal or external peripherals. The DMA channels are double buffered to relax constraints on reload time.
I/O Port
Single-Cycle Multiplier
The Am29240 and Am29243 microcontrollers incorporate a full combinatorial multiplier that accepts two
32-bit input operands and produces a 32-bit result in a
single cycle. The multiplier can produce a 64-bit result
in two cycles. The multiplier permits maximum performance without requiring instruction scheduling, since
the latency of the multiply is the same as the latency of
other integer operations. High-performance multiplication benefits imaging, signal processing, and state
modeling applications.
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ROM Controller
The I/O port permits direct access to 16 individually programmable external input/output signals. Eight of these
signals can be configured to cause interrupts.
Parallel Port
The parallel port implements a bidirectional IBM PCcompatible parallel interface to a host processor.
Serial Port
The serial port implements up to two full-duplex UARTs.
Am29240 Microcontroller Series
ADVANCE INFORMATION
Serializer/Deserializer
The serializer/deserializer (video interface) on the
Am29240 and Am29245 microcontrollers permits direct
connection to a number of laser-marking engines, video
displays, or raster input devices such as scanners.
Interrupt Controller
The interrupt controller generates and reports the status
of interrupts caused by on-chip peripherals.
Wide Range of Price/Performance Points
To reduce design costs and time-to-market, the product
designer can use the Am29200 microcontroller family
and one basic system design as the foundation for an
entire product line. From this design, numerous implementations of the product at various levels of price and
performance may be derived with minimum time, effort,
and cost.
The Am29240 RISC microcontroller series supports this
capability through various combinations of on-chip
caches, programmable memory widths, programmable
wait states, burst-mode and page-mode access support, bus compatibility, and 29K family software compatibility. A system can be upgraded using various memory
architectures without hardware and software redesign.
Within the Am29240 microcontroller series, the external
interfaces and the processor operate at frequencies in
the range of 16 to 25 MHz. Using the Scalable Clocking
feature on the Am29240 and Am29243 microcontrollers, the internal processor core can operate either at
the interface frequency or twice this frequency. For example, the processor can operate at 25 MHz while the
interface operates at 12.5 MHz.
The ROM controller accommodates memories that are
either 8, 16, or 32 bits wide, and the DRAM controller accommodates dynamic memories that are either 16 or 32
bits wide. This unique feature provides a flexible interface to low-cost memory, as well as a convenient, flexible upgrade path. For example, a system can start with
a 16-bit memory design and can subsequently improve
performance by migrating to a 32-bit memory design.
One particular advantage is the ability to add memory in
half-megabyte increments. This provides significant
cost savings for applications that do not require larger
memory upgrades.
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Processor outputs have edge-rate control that allows
them to drive a wide range of load capacitances with low
noise and ringing. This eliminates the cost of external
logic and buffering.
Bus and Software Compatibility
Compatibility within a processor family is critical for
achieving a rational, easy upgrade path. Processors in
the Am29240 microcontroller series are all members of
a bus-compatible family of RISC microcontrollers. All
members of this family—the Am29205, Am29202,
Am29200, Am29240, Am29245, and Am29243 microcontrollers—allow improvements in price, performance,
and system capabilities without requiring that users redesign their system hardware or software. Bus compatibility ensures a convenient upgrade path for future
systems.
The Am29240 microcontroller series is available in a
196-pin plastic quad flat-pack (PQFP) package. The
Am29240 microcontroller series is signal-compatible
with the Am29200 and the Am29205 microcontrollers.
Moreover, the Am29240 microcontroller series is
binary compatible with existing RISC microcontrollers
and other members of the 29K family (the Am29000,
Am29005, Am29030, Am29035, Am29040, and
Am29050 microprocessors, as well as the Am29200,
Am29202, and Am29205 microcontrollers). The
Am29240 microcontroller series provides a migration
path to low-cost, high-performance, highly integrated
systems from other 29K family members, without requiring expensive rewrites of application software.
Complete Development and
Support Environment
A complete development and support environment is vital for reducing a product’s time-to-market. Advanced
Micro Devices has created a standard development environment for the 29K family of processors. In addition,
the Fusion29K third-party support organization provides
the most comprehensive customer/partner program in
the embedded processor market.
Advanced Micro Devices offers a complete set of hardware and software tools for design, integration, debugging, and benchmarking. These tools, which are
available now for the 29K family, include the following:
The Am29200, Am29202, Am29205, Am29240,
Am29245, and Am29243 microcontrollers allow users
to address an extremely wide range of cost performance
points, with higher performance and lower cost than existing designs based on CISC microprocessors.
Software development kit that includes the
High C 29K optimizing C compiler with assembler, linker, ANSI library functions, 29K family architectural simulator, and MiniMON29K debug
monitor
Glueless System Interfaces
XRAY29K source-level debugger
The Am29240 microcontroller series also minimizes
system cost by providing a glueless attachment to external ROMs, DRAMs, and other peripheral components.
A complete family of demonstration and development boards
Am29240 Microcontroller Series
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AMD
ADVANCE INFORMATION
In addition, Advanced Micro Devices has developed a
standard host interface (HIF) specification for operating
system services, the Universal Debugger Interface
(UDI) for seamless connection of debuggers to ICEs
and target hardware, and extensions for the UNIX common object file format (COFF).
This support is augmented by an engineering hotline, an
on-line bulletin board, and field application engineers.
Debugging and Testing
The Am29240 microcontroller series provides debugging and testing features at both the software and
hardware levels.
Software debugging is facilitated by the instruction
trace facility and instruction breakpoints. Instruction
tracing is accomplished by forcing the processor to trap
after each instruction has been executed. Instruction
breakpoints are implemented by the HALT instruction
or by a software trap.
The processor provides several additional features to
assist system debugging and testing:
The Test/Development Interface is composed of a
group of pins that indicate the state of the processor
and control the operation of the processor.
A Traceable Cache feature permits a hardwaredevelopment system to track accesses to the onchip caches, permitting a high level of visibility into
processor operation.
An IEEE Std 1149.1-1990 (JTAG) compliant Standard Test Access Port and Boundary-Scan Architecture. The Test Access Port provides a scan interface
for testing processor and system hardware in a production environment, and contains extensions that
allow a hardware-development system to control
and observe the processor without interposing hardware between the processor and system.
series by overlapping them with instruction execution,
by taking advantage of pipelining, by an on-chip data
cache, and by organizing the flow of external data into
the processor so that the impact of external accesses is
minimized.
Pipelining
Instruction operations are overlapped with instruction
fetch, instruction decode and operand fetch, instruction
execution, and result write-back to the Register File.
Pipeline forwarding logic detects pipeline dependencies
and routes data as required, avoiding delays that might
arise from these dependencies. Pipeline interlocks are
implemented by processor hardware. Except for a few
special cases, it is not necessary to rearrange programs
to avoid pipeline dependencies, although this is sometimes desirable for performance.
On-Chip Instruction and Data Caches
On-chip instruction and data caches satisfy most processor fetches without wait states, even when the processor operates at twice the system frequency. The
caches are pipelined for best performance. The reload
policies minimize the amount of time spent waiting for
reload, while optimizing the benefit of locality of
reference.
Burst-Mode and Page-Mode Memories
The Am29240 microcontroller series directly supports
burst-mode memories. The burst-mode memory supplies instructions at the maximum bandwidth, without
the complexity of an external cache or the performance
degradation due to cache misses.
The processor can also use the page-mode capability of
common DRAMs to improve the access time in cases
where page-mode accesses can be used. This is particularly useful in very low-cost systems with 16-bit-wide
DRAMs, where the DRAM must be accessed twice for
each 32-bit operand.
PERFORMANCE OVERVIEW
Instruction Set Overview
The Am29240 microcontroller series offers a significant
margin of performance over CISC microprocessors in
existing embedded designs, since the majority of processor features were defined for the maximum achievable performance at very low cost. This section
describes the features of the Am29240 microcontroller
series from the point of view of system performance.
All 29K family members employ a three-address instruction set architecture. The compiler or assembly-language programmer is given complete freedom to
allocate register usage. There are 192 general-purpose
registers, allowing the retention of intermediate calculations and avoiding needless data destruction. Instruction operands may be contained in any of the
general-purpose registers, and the results may be
stored into any of the general-purpose registers.
Instruction Timing
The Am29240 microcontroller series uses an arithmetic/
logic unit, a field shift unit, and a prioritizer to execute
most instructions. Each of these is organized to operate
on 32-bit operands and provide a 32-bit result. All operations are performed in a single cycle.
The performance degradation of load and store operations is minimized in the Am29240 microcontroller
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The Am29240 microcontroller series instruction set contains 117 instructions that are divided into nine classes.
These classes are integer arithmetic, compare, logical,
shift, data movement, constant, floating point, branch,
and miscellaneous. The floating-point instructions are
not executed directly, but are emulated by trap handlers.
Am29240 Microcontroller Series
ADVANCE INFORMATION
All directly implemented instructions are capable of
executing in one processor cycle, with the exception of
interrupt returns, loads, and stores.
Data Formats
The Am29240 microcontroller series defines a word as
32 bits of data, a half-word as 16 bits, and a byte as 8
bits. The hardware provides direct support for wordinteger (signed and unsigned), word-logical, word-Boolean, half-word integer (signed and unsigned), and character data (signed and unsigned).
Word-Boolean data is based on the value contained in
the most significant bit of the word. The values TRUE
and FALSE are represented by the most significant bit
values 1 and 0, respectively.
Other data formats, such as character strings, are supported by instruction sequences. Floating-point formats
(single and double precision) are defined for the processor; however, there is no direct hardware support for
these formats in the Am29240 microcontroller series.
Protection
The Am29240 microcontroller series offers two mutually
exclusive modes of execution—the User and Supervisor modes—that restrict or permit accesses to certain
processor registers and external storage locations.
The register file may be configured to restrict accesses
to Supervisor-mode programs on a bank-by-bank basis.
Memory Management Unit
The Am29240 microcontroller series provides a
memory-management unit (MMU) for translating virtual
addresses into physical addresses. The page size for
translation ranges from 1 Kbyte to 16 Mbytes in powers
of 4. The Am29245 and Am29240 microcontrollers each
have a single, 16-entry TLB. The Am29243 microcontroller has dual 16-entry TLBs, each capable of mapping
pages of different size.
Interrupts and Traps
When a member of the Am29240 microcontroller series
takes an interrupt or trap, it does not automatically save
its current state information in memory. This lightweight
interrupt and trap facility greatly improves the performance of temporary interruptions such as simple
operating-system calls that require no saving of state information.
In cases where the processor state must be saved, the
saving and restoring of state information is under the
control of software. The methods and data structures
used to handle interrupts—and the amount of state
saved—may be tailored to the needs of a particular
system.
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Interrupts and traps are dispatched through a 256-entry
vector table that directs the processor to a routine that
handles a given interrupt or trap. The vector table may
be relocated in memory by the modification of a processor register. There may be multiple vector tables in the
system, though only one is active at any given time.
The vector table is a table of pointers to the interrupt and
trap handlers, and requires only 1 Kbyte of memory. The
processor performs a vector fetch every time an interrupt or trap is taken. The vector fetch requires at least
three cycles, in addition to the number of cycles required
for the basic memory access.
PIN DESCRIPTIONS
A23–A0
Address Bus (output, synchronous)
The Address Bus supplies the byte address for all accesses, except for DRAM accesses. For DRAM accesses, multiplexed row and column addresses are
provided on A14–A1. A2–A0 are also used to provide a
clock to an optional burst-mode EPROM.
BOOTW
Boot ROM Width (input, asynchronous)
This input configures the width of ROM Bank 0, so the
ROM can be accessed before the ROM configuration
has been set by the system initialization software. The
BOOTW signal is sampled during and after a processor
reset. If BOOTW is High before and after reset (tied
High), the boot ROM is 32 bits wide. If BOOTW is Low
before and after reset (tied Low), the boot ROM is 16 bits
wide. If BOOTW is Low before reset and High after reset
(tied to RESET), the boot ROM is 8 bits wide. This signal
has special hardening against metastable states, allowing it to be driven with a slow-rise-time signal and permitting it to be tied to RESET.
BURST
Burst-Mode Access (output, synchronous)
This signal is asserted to perform sequential accesses
from a burst-mode device.
CAS3–CAS0
Column Address Strobes, Byte 3–0
(output, synchronous)
A High-to-Low transition on these signals causes the
DRAM selected by RAS3–RAS0 to latch the column address and complete the access. To support byte and
half-word writes, column address strobes are provided
for individual DRAM bytes. CAS3 is the column address
strobe for the DRAMs, in all banks, attached to
ID31–ID24. CAS2 is for the DRAMs attached to
ID23–ID16, and so on. These signals are also used in
other special DRAM cycles.
Am29240 Microcontroller Series
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ADVANCE INFORMATION
CNTL1–CNTL0
GACK
CPU Control
(input, asynchronous, internal pull-ups)
External Memory Grant Acknowledge
(output, synchronous)
These inputs specify the processor mode: Load Test
Instruction, Step, Halt, or Normal.
This signal indicates to an external device that it has
been granted an access to the processor’s ROM or
DRAM, and that the device should provide an address.
DACKD–DACKA
DMA Acknowledge D through A
(output, synchronous)
These signals acknowledge an external transfer on a
DMA channel. DMA acknowledgments are not dedicated to a particular DMA channel—each channel specifies which acknowledge line, if any, it is using. Only one
channel at a time can use either DACKD, DACKC,
DACKB, or DACKA, and the same channel uses the respective DREQD–DREQA signal for transfer requests.
DMA transfers can occur to and from internal peripherals independent of these acknowledgments. The
DACKD and DACKC signals are supported on the
Am29240 and Am29243 microcontrollers only.
The processor can be placed into a slave configuration
that allows tracing of a master processor. In this configuration, GACK is used to indicate that the processor pipeline was held during the previous processor cycle.
GREQ
External Memory Grant Request
(input, synchronous, pull-up resistor)
This signal is used by an external device to request an
access to the processor’s ROM or DRAM. To perform
this access, the external device supplies an address to
the ROM controller or DRAM controller.
DREQD–DREQA
To support a hardware-development system, GREQ
should be either tied High or held at a high-impedance
state during a processor reset.
DMA Request D through A
(input, asynchronous, pull-up resistors)
ID31–ID0
These inputs request an external transfer on a DMA
channel. DMA requests are not dedicated to a particular
channel—each channel specifies which request line, if
any, it is using. Only one channel at a time can use either
DREQD, DREQC, DREQB, or DREQA. This channel acknowledges a transfer using the respective DACKD–
DACKA signal. These requests are individually programmable to be either level- or edge-sensitive for either polarity of level or edge. DMA transfers can occur to and
from internal peripherals independent of these requests.
The DMA request/acknowledge pairs DREQA/ DACKA
and DREQB/ DACKB correspond to the Am29200 microcontroller signals DREQ0/DACK0 and DREQ1/DACK1,
respectively. The pin placement reflects this correspondence, and a processor reset dedicates these request/
acknowledge pairs to DMA channels 0 and 1,
respectively. This permits backward-compatible upgrade to an Am29200 microcontroller. The DREQD and
DREQC signals are supported on the Am29240 and
Am29243 microcontrollers only.
Instruction/Data Bus (bidirectional, synchronous)
The Instruction/Data Bus (ID Bus) transfers instructions
to, and data to and from the processor.
IDP3–IDP0
Instruction/Data Parity
(bidirectional, synchronous)
If parity checking is enabled by the PCE bit of the
DRAM Control Register, IDP3–IDP0 are parity bits for
the ID Bus during DRAM accesses. IDP3 is the parity
bit for ID31–ID24, IDP2 is the parity bit for ID23–ID16,
and so on. If parity is enabled, the processor drives
IDP3–IDP0 with valid parity during DRAM writes, and
expects IDP3–IDP0 to be driven with valid parity during
DRAM reads. These signals are supported on the
Am29243 microcontroller only.
INCLK
Input Clock (input)
This indicates to the host that the serial port is ready to
transmit or receive data on Serial Port A.
This is an oscillator input at twice the system operating
frequency. The processor operates either at the system
operating frequency or at the INCLK frequency, as controlled by the TBO bit in the Configuration Register. The
processor can operate at the INCLK frequency only if
MEMCLK is an output.
DTRA
INTR3–INTR0
Data Terminal Ready, Port A
(input, asynchronous)
Interrupt Requests 3–0
(input, asynchronous, internal pull-up resistors)
This indicates to the processor that the host is ready to
transmit or receive data on Serial Port A.
These inputs generate prioritized interrupt requests.
The interrupt caused by INTR0 has the highest priority,
DSRA
Data Set Ready, Port A (output, synchronous)
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Am29240 Microcontroller Series
ADVANCE INFORMATION
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and the interrupt caused by INTR3 has the lowest priority. The interrupt requests are masked in prioritized order by the Interrupt Mask field in the Current Processor
Status Register and are disabled by the DA and DI bits of
the Current Processor Status Register. These signals
have special hardening against metastable states, allowing them to be driven with slow-transition-time
signals.
PIACS5–PIACS0
LSYNC
PIAOE
Line Synchronization (input, asynchronous)
Peripheral Output Enable (output, synchronous)
This signal indicates the start of a raster line. This signal
is supported on the Am29240 and Am29245 microcontrollers only.
This signal enables the selected peripheral device to
drive the ID bus.
MEMCLK
Peripheral Write Enable (output, synchronous)
Memory Clock (input/output)
This signal causes data on the ID bus to be written into
the selected peripheral.
This is either a clock output or an input from an external
clock generator, as determined by the MEMDRV input. It
operates at the system operating frequency, which is
half of the INCLK frequency. Most processor inputs and
outputs are synchronous to MEMCLK. MEMCLK must
be driven with CMOS levels. MEMCLK must be an output if the processor operates at the INCLK frequency.
MEMDRV
MEMCLK Drive Enable
(input, internal pull-up resistor)
This input determines whether MEMCLK is an output or
an input. If this pin is High, the processor generates a
clock on the MEMCLK output. If this pin is Low, the processor accepts a clock generated by the system on the
MEMCLK input. This signal is tied High through an internal pull-up resistor so the signal can be left unconnected
to configure MEMCLK as an output.
Peripheral Chip Selects, Regions 5–0
(output, synchronous)
These signals are used to select individual peripheral
devices. DMA channels may be programmed to use
dedicated chip selects during an external peripheral
access.
PIAWE
PIO15–PIO0
Programmable Input/Output
(input/output, asynchronous)
These signals are available for direct software control
and inspection. PIO15–PIO8 may be individually programmed to cause processor interrupts. These signals
have special hardening against metastable states, allowing them to be driven with slow-transition-time
signals.
PACK
The PIO signals are sampled during a processor reset.
After reset, the sampled value is held in the PIO Input
Register. This sampled value is supplied the first time
this register is read, unless the read is preceded by write
to the PIO Input Register or by a read or write of any other PIO register. This may be used to indicate system
configuration information to the processor during a
reset.
Parallel Port Acknowledge (output, synchronous)
POE
This signal is used by the processor to acknowledge a
transfer from the host or to indicate to the host that data
has been placed on the port.
Parallel Port Output Enable (output, synchronous)
PAUTOFD
This signal enables an external data buffer containing
data from the host to drive the ID Bus.
PSTROBE
Parallel Port Autofeed (input, asynchronous)
This signal is used by the host to indicate how line feeds
should be performed or is used to indicate that the host
is busy and cannot accept a data transfer.
PBUSY
Parallel Port Strobe (input, asynchronous)
This signal is used by the host to indicate that data is on
the Parallel Port or to acknowledge a transfer from the
processor.
PSYNC
Parallel Port Busy (output, synchronous)
This indicates to the host that the Parallel Port is busy
and cannot accept a data transfer.
Page Synchronization
(input/output, asynchronous)
This signal indicates the beginning of a raster page. This
signal is supported on the Am29240 and Am29245 microcontrollers only.
Am29240 Microcontroller Series
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ADVANCE INFORMATION
PWE
RXDB
Parallel Port Write Enable (output, synchronous)
Receive Data, Port B (input, asynchronous)
This signal writes a buffer with data on the ID Bus. Then,
the buffer drives data to the host.
This input is used to receive data to Serial Port B. This
signal is supported on the Am29240 and Am29243 microcontrollers only.
R/W
STAT2–STAT0
Read/Write (output, synchronous)
During an external ROM, DRAM, DMA, or PIA access,
this signal indicates the direction of transfer: High for a
read and Low for a write.
RAS3–RAS0
CPU Status (output, synchronous)
These outputs indicate information about the processor
or the current access for the purposes of hardware
debug.
TCK
Row Address Strobe, Banks 3–0
(output, synchronous)
A High-to-Low transition on one of these signals causes
a DRAM in the corresponding bank to latch the row address and begin an access. RAS3 starts an access in
DRAM Bank 3, and so on. These signals also are used in
other special DRAM cycles.
RESET
Reset (input, asynchronous)
Test Clock Input
(input, asynchronous, pull-up resistor)
This input is used to operate the Test Access Port. The
state of the Test Access Port must be held if this clock is
held either High or Low. This clock is internally synchronized to MEMCLK for certain operations of the Test Access Port controller, so signals internally driven and
sampled by the Test Access Port are synchronous to
processor internal clocks.
This input places the processor in the Reset mode. This
signal has special hardening against metastable states,
allowing it to be driven with a slow-rise-time signal.
TDI
ROMCS3–ROMCS0
This input supplies data to the test logic from an external
source. It is sampled on the rising edge of TCK. If it is not
driven, it appears High internally.
ROM Chip Selects, Banks 3–0
(output, synchronous)
A Low level on one of these signals selects the memory
devices in the corresponding ROM bank. ROMCS3 selects devices in ROM Bank 3, and so on. The timing and
access parameters of each bank are individually programmable.
ROMOE
ROM Output Enable (output, synchronous)
This signal enables the selected ROM Bank to drive the
ID bus. It is used to prevent bus contention when switching between different ROM banks or switching between
a ROM bank and another device or DRAM bank.
RSWE
ROM Space Write Enable (output, synchronous)
This signal is used to write an alterable memory in a
ROM bank (such as an SRAM or Flash EPROM).
RXDA
Test Data Input
(input, synchronous to TCK, pull-up resistor)
TDMA
Terminate DMA (input/output, synchronous)
This signal is either an input or an output as controlled by
the corresponding DMA Control Register. As an input,
this signal can be asserted during an external DMA
transfer (non-fly-by) to terminate the transfer after the
current access. The TDMA input is ignored during fly-by
transfers. As an output, this signal is asserted to indicate
the final transfer of a sequence.
TDO
Test Data Output
(three-state output, synchronous to TCK)
This output supplies data from the test logic to an external destination. It changes on the falling edge of TCK. It
is in the high-impedance state except when scanning is
in progress.
TMS
Receive Data, Port A (input, asynchronous)
This input is used to receive serial data to Serial Port A.
Test Mode Select
(input, synchronous to TCK, pull-up resistor)
This input is used to control the Test Access Port. If it is
not driven, it appears High internally.
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Am29240 Microcontroller Series
ADVANCE INFORMATION
TR/OE
UCLK
Video DRAM Transfer/Output Enable
(output, synchronous)
UART Clock (input)
AMD
This signal is used with video DRAMs to transfer data to
the video shift register. It is also used as an output enable in normal video DRAM read cycles. This signal is
supported on the Am29240 and Am29245 microcontrollers only.
This is an oscillator input for generating the UART (Serial Port) clock. To generate the UART clock, the oscillator
frequency may be divided by any amount up to 65,536.
The UART clock operates at 16 times the Serial Port’s
baud rate. As an option, UCLK may be driven with
MEMCLK or INCLK. It can be driven with TTL levels.
TRAP1–TRAP0
VCLK
Trap Requests 1–0
(input, asynchronous, internal pull-ups)
Video Clock (input, asynchronous)
These inputs generate prioritized trap requests. The
trap caused by TRAP0 has the highest priority. These
trap requests are disabled by the DA bit of the Current
Processor Status Register. These signals have special
hardening against metastable states, allowing them to
be driven with slow-transition-time signals.
This clock is used to synchronize the transfer of video
data. As an option, VCLK may be driven with MEMCLK
or INCLK. It can be driven with TTL levels. This signal is
supported on the Am29240 and Am29245 microcontrollers only.
VDAT
Video Data (input/output, synchronous to VCLK)
TRIST
Three-State Control
(input, asynchronous, pull-up resistor)
This is serial data to or from the video device. This signal
is supported on the Am29240 and Am29245 microcontrollers only.
This input is asserted to force all processor outputs into
the high-impedance state. This signal is tied High
through an internal pull-up resistor.
WAIT
Note: TRIST does not control the MEMCLK pin. To
three-state MEMCLK, the user must drive MEMDRV
Low.
Add Wait States
(input, synchronous, internal pull-up)
TRST
External accesses are normally timed by the processor.
However, the WAIT signal may be asserted during a
PIA, ROM, or DMA access to extend the access
indefinitely.
Test Reset Input
(input, asynchronous, pull-up resistor)
WARN
This input asynchronously resets the Test Access Port.
If TRST is not driven, it appears High internally. TRST
must be tied to RESET, even if the Test Access Port is
not being used.
TXDA
Transmit Data, Port A (output, asynchronous)
This output is used to transmit serial data from Serial
Port A.
Warn (input, asynchronous, edge-sensitive,
internal pull-up)
A High-to-Low transition on this input causes a nonmaskable WARN trap to occur. This trap bypasses the
normal trap vector fetch sequence, and is useful in situations where the vector fetch may not work (e.g., when
data memory is faulty). This signal has special hardening against metastable states, allowing it to be driven
with a slow-transition-time signal.
WE
TXDB
Transmit Data, Port B (output, asynchronous)
This output is used to transmit data from Serial Port B.
This signal is supported on the Am29240 and Am29243
microcontrollers only.
Write Enable (output, synchronous)
This signal is used to write the selected DRAM bank.
“Early write” cycles are used so the DRAM data inputs
and outputs can be tied to the common ID Bus.
Am29240 Microcontroller Series
15
AMD
ADVANCE INFORMATION
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
CONNECTION DIAGRAM
196-Pin PQFP
Top Side View
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
Am29240 Microcontroller Series
Note:
Pin 1 marked for orientation.
16
Am29240 Microcontroller Series
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
ADVANCE INFORMATION
AMD
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ÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
PQFP PIN DESIGNATIONS (Pin Number)
Pin No.
Pin Name
Pin No.
Pin Name
Pin No.
Pin Name
Pin No.
Pin Name
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
VCC
MEMCLK
MEMDRV
INCLK
ID31
ID30
ID29
ID28
ID27
ID26
ID25
ID24
GND
VCC
ID23
ID22
ID21
ID20
ID19
ID18
ID17
ID16
GND
VCC
ID15
ID14
ID13
ID12
ID11
ID10
ID9
ID8
GND
VCC
ID7
ID6
ID5
ID4
ID3
ID2
ID1
ID0
GND
VCC
IDP3 1, 3
IDP2 1, 3
IDP1 1, 3
IDP0 1, 3
GND
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
VCC
Reserved
Reserved
TXDB 3
RXDB 3
DTRA
RXDA
UCLK
DSRA
TXDA
ROMCS3
ROMCS2
ROMCS1
ROMCS0
VCC
GND
BURST
RSWE
ROMOE
RAS3
RAS2
RAS1
RAS0
CAS3
CAS2
VCC
GND
CAS1
CAS0
TR/ OE
WE
GACK
PIACS5
PIACS4
PIACS3
PIACS2
VCC
GND
PIACS1
PIACS0
PIAWE
PIAOE
R/ W
DACKB
DACKA
DACKD 3
DACKC 3
Reserved
GND
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
VCC
Reserved
Reserved
A23
A22
A21
A20
A19
A18
A17
A16
GND
VCC
A15
A14
A13
A12
A11
A10
A9
A8
GND
VCC
A7
A6
A5
A4
A3
A2
A1
A0
GND
VCC
BOOTW
WAIT
PAUTOFD
PSTROBE
PWE
POE
PACK
PBUSY
GND
VCC
PIO15
PIO14
PIO13
DREQD 3
DREQC 3
GND
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
VCC
Reserved
PIO12
PIO11
PIO10
PIO9
PIO8
PIO7
PIO6
PIO5
PIO4
GND
VCC
PIO3
PIO2
PIO1
PIO0
TDO
STAT2
STAT1
STAT0
VDAT 2
PSYNC 2
GND
VCC
GREQ
DREQB
DREQA
TDMA
TRAP0
TRAP1
INTR0
INTR1
INTR2
INTR3
GND
VCC
WARN
VCLK 2
LSYNC 2
TMS
TRST
TCK
TDI
RESET
CNTL1
CNTL0
TRIST
GND
Notes: All values are typical and preliminary.
1. Defined as a no-connect on the Am29240 microcontroller.
2. Defined as a no-connect on the Am29243 microcontroller.
3. Defined as a no-connect on the Am29245 microcontroller.
Am29240 Microcontroller Series
17
AMD
ADVANCE INFORMATION
ÁÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁÁ
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ÁÁÁÁÁ
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ÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁÁ
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PQFP PIN DESIGNATIONS (Pin Name)
Pin Name
Pin No.
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
BOOTW
BURST
CAS0
CAS1
CAS2
CAS3
CNTL0
CNTL1
DACKA
DACKB
DACKC 3
DACKD 3
DREQA
DREQB
DREQC 3
DREQD 3
DSRA
DTRA
GACK
GND
GND
GND
GND
GND
GND
129
128
127
126
125
124
123
122
119
118
117
116
115
114
113
112
109
108
107
106
105
104
103
102
132
66
78
77
74
73
194
193
94
93
96
95
175
174
146
145
58
55
81
13
23
33
43
49
65
Pin Name
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GREQ
ID0
ID1
ID2
ID3
ID4
ID5
ID6
ID7
ID8
ID9
ID10
ID11
ID12
ID13
ID14
ID15
ID16
ID17
ID18
ID19
ID20
ID21
ID22
ID23
ID24
ID25
ID26
ID27
ID28
ID29
ID30
ID31
IDP0 1, 3
IDP1 1, 3
IDP2 1, 3
IDP3 1, 3
Pin No.
Pin Name
Pin No.
Pin Name
Pin No.
76
87
98
110
120
130
140
147
159
171
183
196
173
42
41
40
39
38
37
36
35
32
31
30
29
28
27
26
25
22
21
20
19
18
17
16
15
12
11
10
9
8
7
6
5
48
47
46
45
INCLK
INTR0
INTR1
INTR2
INTR3
LSYNC 2
MEMCLK
MEMDRV
PACK
PAUTOFD
PBUSY
PIACS0
PIACS1
PIACS2
PIACS3
PIACS4
PIACS5
PIAOE
PIAWE
PIO0
PIO1
PIO2
PIO3
PIO4
PIO5
PIO6
PIO7
PIO8
PIO9
PIO10
PIO11
PIO12
PIO13
PIO14
PIO15
POE
PSTROBE
PSYNC 2
PWE
R/ W
RAS0
RAS1
RAS2
RAS3
Reserved
Reserved
Reserved
Reserved
Reserved
4
179
180
181
182
187
2
3
138
134
139
89
88
85
84
83
82
91
90
164
163
162
161
158
157
156
155
154
153
152
151
150
144
143
142
137
135
170
136
92
72
71
70
69
51
52
97
100
101
Reserved
RESET
ROMCS0
ROMCS1
ROMCS2
ROMCS3
ROMOE
RSWE
RXDA
RXDB 3
STAT0
STAT1
STAT2
TCK
TDI
TDMA
TDO
TMS
TR/ OE
TRAP0
TRAP1
TRIST
TRST
TXDA
TXDB 3
UCLK
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCLK 2
VDAT 2
WAIT
WARN
WE
149
192
63
62
61
60
68
67
56
54
168
167
166
190
191
176
165
188
79
177
178
195
189
59
53
57
1
14
24
34
44
50
64
75
86
99
111
121
131
141
148
160
172
184
186
169
133
185
80
Notes: All values are typical and preliminary.
1. Defined as a no-connect on the Am29240 microcontroller.
18
2. Defined as a no-connect on the Am29243 microcontroller.
3. Defined as a no-connect on the Am29245 microcontroller.
Am29240 Microcontroller Series
ADVANCE INFORMATION
AMD
Am29240 MICROCONTROLLER LOGIC SYMBOL
INCLK
MEMDRV
2
TRIST
CNTL1–CNTL0
3
A23–A0
24
R/ W
RESET
WARN
ROMCS3–ROMCS0
INTR3–INTR0
4
2
STAT2–STAT0
4
ROMOE
RSWE
BURST
TRAP1–TRAP0
WAIT
RAS3–RAS0
4
CAS3–CAS0
4
BOOTW
WE
TR/ OE
PIACS5–PIACS0
Am29240 Microcontroller
4
PIAOE
PIAWE
DACKD–DACKA
DREQD–DREQA
GREQ
4
GACK
PBUSY
PACK
POE
PWE
PSTROBE
PAUTOFD
2
6
UCLK
RXDB–RXDA
DTRA
TXDB–TXDA
DSRA
2
VCLK
LSYNC
TCK
TDI
TMS
TRST
TDO
MEMCLK VDAT PSYNC TDMA
PIO15–PIO0
ID31–ID0
16
32
Am29240 Microcontroller Series
19
AMD
ADVANCE INFORMATION
Am29245 MICROCONTROLLER LOGIC SYMBOL
INCLK
MEMDRV
2
TRIST
CNTL1–CNTL0
3
A23–A0
24
R/ W
RESET
WARN
ROMCS3–ROMCS0
INTR3–INTR0
4
2
STAT2–STAT0
4
ROMOE
RSWE
BURST
TRAP1–TRAP0
WAIT
RAS3–RAS0
4
CAS3–CAS0
4
BOOTW
WE
TR/ OE
PIACS5–PIACS0
PIAOE
PIAWE
Am29245 Microcontroller
2
DACKB–DACKA
DREQB–DREQA
GREQ
GACK
PBUSY
PACK
POE
PWE
PSTROBE
PAUTOFD
UCLK
RXDA
DTRA
TXDA
DSRA
VCLK
LSYNC
TCK
TDI
TMS
TRST
TDO
MEMCLK VDAT PSYNC TDMA
20
6
PIO15–PIO0
ID31–ID0
16
32
Am29240 Microcontroller Series
2
ADVANCE INFORMATION
AMD
Am29243 MICROCONTROLLER LOGIC SYMBOL
INCLK
MEMDRV
2
TRIST
CNTL1–CNTL0
STAT2–STAT0
3
A23–A0
24
R/ W
RESET
WARN
ROMCS3–ROMCS0
INTR3–INTR0
4
2
4
ROMOE
RSWE
BURST
TRAP1–TRAP0
WAIT
RAS3–RAS0
4
CAS3–CAS0
4
BOOTW
WE
TR/ OE
PIACS5–PIACS0
Am29243 Microcontroller
4
PIAOE
PIAWE
DACKD–DACKA
DREQD–DREQA
GREQ
PBUSY
PACK
POE
PWE
UCLK
RXDB–RXDA
DTRA
TXDB–TXDA
DSRA
TCK
TDI
TMS
TRST
MEMCLK
4
GACK
PSTROBE
PAUTOFD
2
6
2
TDO
TDMA
PIO15–PIO0
16
ID31–ID0
32
Am29240 Microcontroller Series
IDP3–IDP0
4
21
AMD
ADVANCE INFORMATION
ABSOLUTE MAXIMUM RATINGS
OPERATING RANGES
Storage Temperature . . . . . . . . . . . . –65°C to +125°C
Voltage on any Pin
with Respect to GND . . . . . . . –0.5 V to VCC +0.5 V
Commercial (C) Devices
Stresses above those listed under Absolute Maximum Ratings
may cause permanent device failure. Functionality at or above
these limits is not implied. Exposure to absolute maximum ratings for extended periods may affect device reliability.
Case Temperature (TC) . . . . . . . . . . . . . . 0°C to +85°C
Supply Voltage (VCC) . . . . . . . . . . . +4.75 V to +5.25 V
Operating ranges define those limits between which the functionality of the device is guaranteed.
DC CHARACTERISTICS over COMMERCIAL Operating Ranges
Advance Information
Symbol
Parameter Description
VIL
Test Conditions
Min
Max
Unit
Input Low Voltage
–0.5
0.8
V
VIH
Input High Voltage
2.0
VCC +0.5
V
VILINCLK
INCLK Input Low Voltage
Note 1
–0.5
0.8
V
VIHINCLK
INCLK Input High Voltage
Note 1
VCC –0.8
VCC +0.5
V
VOL
Output Low Voltage for
All Outputs except MEMCLK
IOL = 3.2 mA
0.45
V
VOH
Output High Voltage for
All Outputs except MEMCLK
IOH = –400 µA
ILI
Input Leakage Current
0.45 V ≤ VIN ≤ VCC –0.45 V
Note 2
ILO
Output Leakage Current
ICCOP
2.4
V
±10 or
+10/–200
µA
0.45 V ≤ VOUT ≤ VCC –0.45 V
±10
µA
Operating Power-Supply Current with
respect to MEMCLK
VCC = 5.25 V, Outputs Floating;
Holding RESET active at 25 MHz
14
mA/MHz
VOLC
MEMCLK Output Low Voltage
IOLC = 20 mA
0.6
V
VOHC
MEMCLK Output High Voltage
IOHC = –20 mA
IOSGND
MEMCLK GND Short Circuit Current
IOSVCC
MEMCLK VCC Short Circuit Current
VCC –0.6
V
VCC = 5.0 V
100
mA
VCC = 5.0 V
100
mA
Notes:
1. INCLK is driven with CMOS input levels.
2. The Low input leakage current for the inputs CNTL1–CNTL0, INTR3–INTR0, TRAP1–TRAP0, DREQD–DREQA, TCK, TDI,
TRST, TMS, GREQ, WARN, MEMDRV, WAIT, and TRIST is –200 µA. These pins have internal pull-up resistors.
CAPACITANCE
Advance Information
Symbol
Parameter Description
CIN
Test Conditions
Max
Unit
Input Capacitance
15
pF
CINCLK
INCLK Input Capacitance
15
pF
CMEMCLK
MEMCLK Capacitance
20
pF
COUT
Output Capacitance
20
pF
CI/O
I/O Pin Capacitance
20
pF
fC = 10 MHz
Note: Limits guaranteed by characterization.
22
Am29240 Microcontroller Series
Min
ADVANCE INFORMATION
AMD
SWITCHING CHARACTERISTICS over COMMERCIAL Operating Ranges
Advance Information
16 MHz
Parameter Description
Test Conditions 1, 8
1
INCLK Period (=0.5T)
2
No.
20 MHz
25 MHz
Min
Max
Min
Max
Min
Max
Unit
Notes 9, 10, 11
30
25
20
ns
INCLK High Time
Note 9
12
10
8
ns
3
INCLK Low Time
Note 9
12
10
8
ns
4
INCLK Rise Time
Note 9
1
7
1
7
1
7
ns
5
INCLK Fall Time
Note 9
1
7
1
7
1
7
ns
6
MEMCLK Delay from INCLK
MEMCLK Output
Notes 3, 8
1
7
1
7
1
7
ns
8
MEMCLK High Time
MEMCLK Output
Notes 3, 8
0.5T–3
0.5T–3
0.5T–3
ns
9
MEMCLK Low Time
MEMCLK Output
Notes 3, 8
0.5T–3
0.5T–3
0.5T–3
ns
10
MEMCLK Rise Time
Notes 3, 8
1
4
1
4
1
4
ns
11
MEMCLK Fall Time
Notes 3, 8
1
4
1
4
1
4
ns
12a
12b
Synchronous Output Valid Delay from MEMCLK Rising Edge
PIO15–PIO0, STAT2–STAT0,
and PIACS5–PIACS0
MEMCLK Output
Note 1A
1
13
1
12
1
11
ns
CAS3–CAS0 Rising Edge/
CAS3–CAS0 Falling Edge
MEMCLK Output
Notes 1B, 4B
1
17/11
1
15/9
1
13/7
ns
All others
MEMCLK Output
Note 1B
1
12
1
11
1
10
ns
Synchronous Output Valid from MEMCLK Falling Edge
PIO15–PIO0, STAT2–STAT0,
and PIACS5–PIACS0
MEMCLK Output
Note 1A
1
12
1
11
1
10
ns
CAS3–CAS0 Falling Edge
MEMCLK Output
Notes 1B, 4B
1
11
1
9
1
7
ns
All others
MEMCLK Output
Note 1B
1
11
1
10
1
9
ns
MEMCLK Output
1
12
1
11
1
10
ns
13
Synchronous Output Disable
Delay from MEMCLK Rising
Edge
14
Synchronous Input Setup Time to MEMCLK Rising Edge
ID31–ID0 and IDP3–IDP0 for
DRAM access
Parity Enabled
Note 4A
18
16
15
ID31–ID0 for DRAM access
Parity Disabled
Note 4A
10
8
7
10
8
7
All others
15
Available CAS Access Time
(TCAS–TSetup)
Notes 4A, 4B
24
16a
Synchronous Input Hold Time to
MEMCLK Rising Edge
Note 4A
0
0
0
16b
Synchronous Input Hold Time to
CAS Rising Edge
Note 4B
3
3
3
Am29240 Microcontroller Series
23
ns
ns
ns
18
ns
ns
ns
23
AMD
ADVANCE INFORMATION
SWITCHING CHARACTERISTICS over COMMERCIAL Operating Ranges (continued)
Advance Information
16 MHz
No.
Parameter Description
17
Asynchronous Input Pulse Width
Test Conditions 1, 8
LSYNC and PSYNC
All others
Min
Max
20 MHz
Min
Max
25 MHz
Min
Max
Unit
Note 5
Note 5
Note 5
4T
4T
4T
ns
UCLK Period
Note 2
30
25
20
ns
VCLK Period
Note 2
25
20
15
ns
UCLK High Time
Note 2
10
8
6
ns
VCLK High Time
Note 2
8
6
4
ns
UCLK Low Time
Note 2
10
8
6
ns
VCLK Low Time
Note 2
8
6
4
ns
UCLK Rise time
Note 2
0
3
0
3
0
3
ns
VCLK Rise time
Note 2
0
3
0
3
0
3
ns
UCLK Fall Time
Note 2
0
3
0
3
0
3
ns
VCLK Fall Time
Note 2
0
3
0
3
0
3
ns
23
Synchronous Output Valid Delay
from VCLK Rise and Fall
Note 6
1
16
1
14
1
14
ns
24
Input Setup Time to VCLK Rise
and Fall
Notes 6, 7
10
9
9
ns
25
Input Hold Time to VCLK Rise
and Fall
Notes 6, 7
0
0
0
ns
18
19
20
21
22
Notes:
1. All outputs driving 80 pF, measured at VOL = 1.5 V and VOH = 1.5 V. For higher capacitance:
A. Add 1-ns output delay per 15 pF loading up to 150-pF total. The minimum delay from PIAOE to PIACSx is 0 ns if the
capacitance loading on PIACSx is equal to or higher than the capacitance loading on PIAOE.
B. Add 1-ns output delay per 25 pF loading up to 300-pF total.
2. VCLK and UCLK can be driven with TTL inputs. UCLK must be tied High if it is unused.
3. MEMCLK can drive an external load of 100 pF.
4. ID31–ID0 and IDP3–IDP0 are sampled on the rising edge of MEMCLK for all non-DRAM accesses, simple DRAM accesses,
and the first access of a DRAM page-mode access. ID31–ID0 and IDP3–IDP0 are sampled on the rising edge of CASx for all
DRAM page-mode accesses, except the first access of a DRAM page-mode access. (See Figures 1–4 on pages 26–27.)
A. Applies to ID31–ID0 and IDP3–IDP0 for simple DRAM accesses and the first access of a DRAM page-mode access.
B. Applies to ID31–ID0 and IDP3–IDP0 for DRAM page-mode accesses, except the first access of a DRAM page-mode access.
When ID31–ID0 and IDP3–IDP0 are sampled on CASx, there is no additional setup time required for ID31–ID0 and
IDP3–IDP0 when the parity is enabled.
5. LSYNC and PSYNC minimum width is two bit-times. A bit-time is one period of the internal video clock, which is determined by
the CLKDIV field in the Video Control Register and VCLK.
6. Active VCLK edge depends on the CLKI bit in the Video Control Register.
7. LSYNC and PSYNC can be treated as synchronous signals by meeting the setup and hold times, though the synchronization
delay still applies.
8. The MEMCLK as an input option (i.e., MEMDRV pin is connected to GND) is not supported.
9. INCLK is driven with CMOS input levels.
10. When the user sets the TBO bit, the INCLK period must not be greater than the operating frequency of the part.
11. For the 25 MHz part, INCLK = 20 ns minimum (50 MHz maximum) when turbo mode is disabled. When turbo mode is enabled,
INCLK = 30 ns minimum (33 MHz maximum).
24
Am29240 Microcontroller Series
ADVANCE INFORMATION
AMD
SWITCHING WAVEFORMS
1
3
2
4
5
VCC – 0.5 V
2.5 V
0.5 V
INCLK
6
8
9
10
11
VCC –1.0 V
1.5 V
0.8 V
MEMCLK
12a
SYNCHRONOUS
OUTPUTS
12b
13
1.5 V
14
SYNCHRONOUS
INPUTS
CASx
1.5 V
Note: Applies to ID31–ID0 and
IDP3–IDP0 for DRAM page-mode
accesses, except the first access
of a DRAM page-mode access.
See Note 4 on page 24.
16a
1.5 V
15
16b
17
ASYNCHRONOUS
INPUTS
1.5 V
1.5 V
18
19
21
UCLK, VCLK
20
22
2.0 V
1.5 V
0.8 V
23
VCLK-RELATIVE
OUTPUTS
25
24
VCLK-RELATIVE
INPUTS
1.5 V
Note: Video Timing may be
relative to VCLK falling edge
if CLK = 1.
1.5 V
Note:
During AC testing, all inputs are driven at VIL = 0.4 V, VIH = 2.4 V.
Am29240 Microcontroller Series
25
AMD
ADVANCE INFORMATION
SWITCHING WAVEFORMS (continued)
1.5 V
MEMCLK
A14–A1
Row Address
Column Address
R/W
RAS3–RAS0
CAS3–CAS0
WE
TR/OE
16a
14
ID31–ID0
IDP3–IDP0
1.5 V
1.5 V
Note: The RAS3–RAS0 signals are asserted and deasserted on the falling edge of MEMCLK.
Figure 1. Simple 3/1 DRAM Read Cycle, Am29240 Microcontroller Series
MEMCLK
A14–A1
Row Address
Column Address
R/W
RAS3–RAS0
CAS3–CAS0
WE
TR/OE
ID31–ID0
IDP3–IDP0
Data
Figure 2. Simple 3/1 DRAM Write Cycle, Am29240 Microcontroller Series
26
Am29240 Microcontroller Series
ADVANCE INFORMATION
AMD
SWITCHING WAVEFORMS (continued)
1.5 V
MEMCLK
A14–A1
Row Address
+2/4
Column Address
+4/8
+6/12
R/W
RAS3–RAS0
CAS3–CAS0
1.5 V
1.5 V
1.5 V
WE
TR/OE
14
ID31–ID0
IDP3–IDP0
1.5 V
16a
15
1.5 V
16b
1.5 V
15
16b
15
1.5 V
16b
1.5 V
Note: The RAS3–RAS0 signals are asserted and deasserted on the falling edge of MEMCLK.
Figure 3. 3/1 DRAM Page-Mode Read, Am29240 Microcontroller Series
MEMCLK
A14–A1
Row Address
Column Address
+2/4
+4/8
+6/12
R/W
RAS3–RAS0
CAS3–CAS0
WE
TR/OE
ID31–ID0
IDP3–IDP0
Data
Data
Data
Data
Figure 4. 3/1 DRAM Page-Mode Write, Am29240 Microcontroller Series
Am29240 Microcontroller Series
27
AMD
ADVANCE INFORMATION
SWITCHING TEST CIRCUIT
VL
IOL = 3.2 mA
CL
V
Am29240 Microcontroller
Pin Under Test
VREF = 1.5 V
IOH = 400 µA
VH
THERMAL CHARACTERISTICS
The Am29240 microcontroller series is specified for operation with case temperature ranges for a commercial
temperature device. Case temperature is measured at
the top center of the PQFP package as shown in Figure 5.
The various temperatures and thermal resistances can
be determined using the equations shown in Figure 6
along with information given in Table 2. (The variable P
is power in watts.)
θJA = θJC + θCA
θJA
P = ICCOP ⋅ freq ⋅ VCC
θCA
TC
TJ = TC + P ⋅ θJC
ÉÉÉÉ
θJC
TJ = TA + P ⋅ θJA
TC = TJ – P ⋅ θJC
TC = TA + P ⋅ θCA
TA = TJ – P ⋅ θJA
TA = TC – P ⋅ θCA
θJA = θJC + θCA
Figure 5. Thermal Resistance — °C/Watt
Figure 6. Thermal Characteristics Equations
Table 2. Thermal Characteristics (°C/Watt) Surface Mounted
Parameter
28
°C/Watt
θJA
Junction-to-Ambient
38
θJC
Junction-to-Case
8
θCA
Case-to-Ambient
30
Am29240 Microcontroller Series
ADVANCE INFORMATION
AMD
PHYSICAL DIMENSIONS
PQB 196, Trimmed and Formed
Plastic Quad Flat Pack (measured in inches)
1.495
1.505
1.475
1.485
1.345
1.355
Pin 196
Pin 1
Pin
147
Pin 1 ID
1.345
1.355
–A–
–B–
1.475
1.485
1.495
1.505
Pin 49
–D–
Pin 98
0.008
0.012
Top View
See Detail
X
0.025 Basic
S
1.20 Ref.
S
0.020
0.040
0.130
0.150
0.160
0.180
Seating
–C–
Plane
Side View
Note:
Not to scale. For reference only.
Am29240 Microcontroller Series
29
AMD
ADVANCE INFORMATION
PHYSICAL DIMENSIONS (continued)
PQB 196, Trimmed and Formed
Plastic Quad Flat Pack (measured in inches)
0.008
0.012
0.006
0.008
Section S–S
7° Typ.
0.010 Min
Flat Shoulder
0.045 x 45° Chamfer
0° Min
0.015
0.008
Pin 147
Gage Plane
0°≤0≤8°
0.010
0.036
0.046
0.065 Ref.
7° Typ.
Detail X
Note:
Not to scale. For reference only.
30
Am29240 Microcontroller Series
ADVANCE INFORMATION
AMD
PHYSICAL DIMENSIONS (continued)
Solder Land Recommendations—196-Lead PQFP
1.500
1.500
0.075
0.025
0.012
Note:
Not to scale. For reference only.
Trademarks
Copyright  1995 Advanced Micro Devices, Inc. All rights reserved.
AMD, the AMD logo, Am29000, MiniMON29K, and Fusion29K are registered trademarks; 29K, AMD Facts-On-Demand, Am29005, Am29030,
Am29035, Am29040, Am29050, Am29200, Am29202, Am29205, Am29240, Am29243, Am29245, Traceable Cache, Scalable Clocking, and
XRAY29K are trademarks of Advanced Micro Devices, Inc.
High C is a registered trademark of MetaWare, Inc.
Product names used in this publication are for identification purposes only and may be trademarks of their respective companies.
Am29240 Microcontroller Series
31