ETC AT90LS2323-10SC

Features
• Utilizes the AVR® RISC Architecture
• AVR – High-performance and Low-power RISC Architecture
•
•
•
•
•
•
•
•
– 118 Powerful Instructions – Most Single Clock Cycle Execution
– 32 x 8 General-purpose Working Registers
– Up to 10 MIPS Throughput at 10 MHz
Data and Nonvolatile Program Memory
– 2K Bytes of In-System Programmable Flash
Endurance: 1,000 Write/Erase Cycles
– 128 Bytes Internal RAM
– 128 Bytes of In-System Programmable EEPROM
Endurance: 100,000 Write/Erase Cycles
– Programming Lock for Flash Program and EEPROM Data Security
Peripheral Features
– One 8-bit Timer/Counter with Separate Prescaler
– Programmable Watchdog Timer with On-chip Oscillator
– SPI Serial Interface for In-System Programming
Special Microcontroller Features
– Low-power Idle and Power-down Modes
– External and Internal Interrupt Sources
– Power-on Reset Circuit
– Selectable On-chip RC Oscillator
Specifications
– Low-power, High-speed CMOS Process Technology
– Fully Static Operation
Power Consumption at 4 MHz, 3V, 25°C
– Active: 2.4 mA
– Idle Mode: 0.5 mA
– Power-down Mode: <1 µA
I/O and Packages
– Three Programmable I/O Lines (AT90S/LS2323)
– Five Programmable I/O Lines (AT90S/LS2343)
– 8-pin PDIP and SOIC
Operating Voltages
– 4.0 - 6.0V (AT90S2323/AT90S2343)
– 2.7 - 6.0V (AT90LS2323/AT90LS2343)
Speed Grades
– 0 - 10 MHz (AT90S2323/AT90S2343)
– 0 - 4 MHz (AT90LS2323/AT90LS2343)
8-bit
Microcontroller
with 2K Bytes of
In-System
Programmable
Flash
AT90S2323
AT90LS2323
AT90S2343
AT90LS2343
Description
The AT90S/LS2323 and AT90S/LS2343 are low-power, CMOS, 8-bit microcontrollers
based on the AVR RISC architecture. By executing powerful instructions in a single
clock cycle, the AT90S2323/2343 achieves throughputs approaching 1 MIPS per MHz
allowing the system designer to optimize power consumption versus processing
speed.
(continued)
Pin Configuration
PDIP/SOIC
RESET
(CLOCK) PB3
PB4
GND
1
2
3
4
8
7
6
5
AT90S/LS2343
VCC
PB2 (SCK/T0)
PB1 (MISO/INT0)
PB0 (MOSI)
RESET
XTAL1
XTAL2
GND
1
2
3
4
8
7
6
5
VCC
PB2 (SCK/T0)
PB1 (MISO/INT0)
PB0 (MOSI)
Rev. 1004CS–10/00
AT90S/LS2323
Note: This is a summary document. A complete document is
available on our web site at www.atmel.com.
1
The AVR core combines a rich instruction set with 32 general-purpose working registers. All the 32 registers are directly
connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one single instruction
executed in one clock cycle. The resulting architecture is more code efficient while achieving throughputs up to ten times
faster than conventional CISC microcontrollers.
Block Diagram
Figure 1. The AT90S/LS2343 Block Diagram
VCC
8-BIT DATA BUS
INTERNAL
OSCILLATOR
GND
PROGRAM
COUNTER
STACK
POINTER
WATCHDOG
TIMER
PROGRAM
FLASH
SRAM
MCU CONTROL
REGISTER
INSTRUCTION
REGISTER
INSTRUCTION
DECODER
CONTROL
LINES
TIMING AND
CONTROL
TIMER/
COUNTER
GENERAL
PURPOSE
REGISTERS
X
Y
Z
INTERRUPT
UNIT
ALU
EEPROM
STATUS
REGISTER
PROGRAMMING
LOGIC
SPI
DATA REGISTER
PORTB
DATA DIR.
REG. PORTB
PORTB DRIVERS
PB0 - PB4
2
AT90S2323/LS2323 and AT90S2343/LS2343
RESET
AT90S2323/LS2323 and AT90S2343/LS2343
Figure 2. The AT90S/LS2323 Block Diagram
VCC
8-BIT DATA BUS
INTERNAL
OSCILLATOR
GND
PROGRAM
COUNTER
STACK
POINTER
WATCHDOG
TIMER
PROGRAM
FLASH
SRAM
MCU CONTROL
REGISTER
INSTRUCTION
REGISTER
INSTRUCTION
DECODER
CONTROL
LINES
TIMING AND
CONTROL
RESET
TIMER/
COUNTER
GENERAL
PURPOSE
REGISTERS
X
Y
Z
INTERRUPT
UNIT
ALU
EEPROM
STATUS
REGISTER
PROGRAMMING
LOGIC
OSCILLATOR
SPI
DATA REGISTER
PORTB
DATA DIR.
REG. PORTB
PORTB DRIVERS
PB0 - PB2
The AT90S2323/2343 provides the following features: 2K bytes of In-System Programmable Flash, 128 bytes EEPROM,
128 bytes SRAM, 3 (AT90S/LS2323)/5 (AT90S/LS2343) general-purpose I/O lines, 32 general-purpose working registers,
an 8-bit timer/counter, internal and external interrupts, programmable Watchdog Timer with internal oscillator, an SPI serial
port for Flash Memory downloading and two software-selectable power-saving modes. The Idle Mode stops the CPU while
allowing the SRAM, timer/counters, SPI port and interrupt system to continue functioning. The Power-down Mode saves
the register contents but freezes the oscillator, disabling all other chip functions until the next interrupt or hardware reset.
The device is manufactured using Atmel’s high-density nonvolatile memory technology. The on-chip Flash allows the program memory to be reprogrammed in-system through an SPI serial interface. By combining an 8-bit RISC CPU with ISP
Flash on a monolithic chip, the Atmel AT90S2323/2343 is a powerful microcontroller that provides a highly flexible and
cost-effective solution to many embedded control applications.
3
The AT90S2323/2343 AVR is supported with a full suite of program and system development tools including: C compilers,
macro assemblers, program debugger/simulators, in-circuit emulators and evaluation kits.
Comparison between AT90S/LS2323 and AT90S/LS2343
The AT90S/LS2323 is intended for use with external quartz crystal or ceramic resonator as the clock source. The start-up
time is fuse-selectable as either 1 ms (suitable for ceramic resonator) or 16 ms (suitable for crystal). The device has three
I/O pins.
The AT90S/LS2343 is intended for use with either an external clock source or the internal RC oscillator as clock source.
The device has five I/O pins.
Table 1 summarizes the differences in features of the two devices.
Table 1. Feature Difference Summary
Part
AT90S/LS2323
AT90S/LS2343
On-chip Oscillator Amplifier
yes
no
Internal RC Clock
no
yes
PB3 available as I/O pin
never
internal clock mode
PB4 available as I/O pin
never
always
Start-up time
1 ms/16 ms
16 µs fixed
Pin Descriptions AT90S/LS2323
VCC
Supply voltage pin.
GND
Ground pin.
Port B (PB2..PB0)
Port B is a 3-bit bi-directional I/O port with internal pull-up resistors. The Port B output buffers can sink 20 mA. As inputs,
Port B pins that are externally pulled low will source current if the pull-up resistors are activated.
Port B also serves the functions of various special features.
Port pins can provide internal pull-up resistors (selected for each bit). The Port B pins are tri-stated when a reset condition
becomes active.
RESET
Reset input. An external reset is generated by a low level on the RESET pin. Reset pulses longer than 50 ns will generate
a reset, even if the clock is not running. Shorter pulses are not guaranteed to generate a reset.
XTAL1
Input to the inverting oscillator amplifier and input to the internal clock operating circuit.
XTAL2
Output from the inverting oscillator amplifier.
4
AT90S2323/LS2323 and AT90S2343/LS2343
AT90S2323/LS2323 and AT90S2343/LS2343
Pin Descriptions AT90S/LS2343
VCC
Supply voltage pin.
GND
Ground pin.
Port B (PB4..PB0)
Port B is a 5-bit bi-directional I/O port with internal pull-up resistors. The Port B output buffers can sink 20 mA. As inputs,
Port B pins that are externally pulled low will source current if the pull-up resistors are activated.
Port B also serves the functions of various special features.
Port pins can provide internal pull-up resistors (selected for each bit). The Port B pins are tri-stated when a reset condition
becomes active.
RESET
Reset input. An external reset is generated by a low level on the RESET pin. Reset pulses longer than 50 ns will generate
a reset, even if the clock is not running. Shorter pulses are not guaranteed to generate a reset.
CLOCK
Clock signal input in external clock mode.
Clock Options
Crystal Oscillator
The AT90S/LS2323 contains an inverting amplifier that can be configured for use as an on-chip oscillator, as shown in
Figure 3. XTAL1 and XTAL2 are input and output respectively. Either a quartz crystal or a ceramic resonator may be used.
It is recommended that the AT90S/LS2343 be used if an external clock source is used, since this gives an extra I/O pin.
Figure 3. Oscillator Connection
External Clock
The AT90S/LS2343 can be clocked by an external clock signal, as shown in Figure 4, or by the on-chip RC oscillator. This
RC oscillator runs at a nominal frequency of 1 MHz (VCC = 5V). A fuse bit (RCEN) in the Flash memory selects the on-chip
RC oscillator as the clock source when programmed (“0”). The AT90S/LS2343 is shipped with this bit programmed. The
AT90S/LS2343 is recommended if an external clock source is used, because this gives an extra I/O pin.
The AT90S/LS2323 can be clocked by an external clock as well, as shown in Figure 4. No fuse bit selects the clock source
for AT90S/LS2323.
5
Figure 4. External Clock Drive Configuration
AT90S/LS2343
EXTERNAL
OSCILATOR
SIGNAL
AT90S/LS2323
PB3
NC
XTAL2
EXTERNAL
OSCILATOR
SIGNAL
XTAL1
GND
GND
Architectural Overview
The fast-access register file concept contains 32 x 8-bit general-purpose working registers with a single clock cycle access
time. This means that during one single clock cycle, one ALU (Arithmetic Logic Unit) operation is executed. Two operands
are output from the register file, the operation is executed and the result is stored back in the register file – in one clock
cycle.
Six of the 32 registers can be used as three 16-bit indirect address register pointers for Data Space addressing, enabling
efficient address calculations. One of the three address pointers is also used as the address pointer for the constant table
look-up function. These added function registers are the 16-bit X-register, Y-register and Z-register.
Figure 5. The AT90S2323/2343 AVR RISC Architecture
AVR AT90S2323/2343 Architecture
Data Bus 8-bit
1K x 16
Program
Flash
Program
Counter
Status
and Test
32 x 8
General
Purpose
Registers
Control Lines
Direct Addressing
Instruction
Decoder
Indirect Addressing
Instruction
Register
Control
Registers
Interrupt
Unit
SPI
Unit
8-bit
Timer/Counter
ALU
Watchdog
Timer
128 x 8
Data
SRAM
I/O Lines
128 x 8
EEPROM
6
AT90S2323/LS2323 and AT90S2343/LS2343
AT90S2323/LS2323 and AT90S2343/LS2343
The ALU supports arithmetic and logic functions between registers or between a constant and a register. Single register
operations are also executed in the ALU. Figure 5 shows the AT90S2323/2343 AVR RISC microcontroller architecture.
In addition to the register operation, the conventional memory addressing modes can be used on the register file as well.
This is enabled by the fact that the register file is assigned the 32 lowermost Data Space addresses ($00 - $1F), allowing
them to be accessed as though they were ordinary memory locations.
The I/O memory space contains 64 addresses for CPU peripheral functions such as Control Registers, Timer/Counters,
A/D converters and other I/O functions. The I/O memory can be accessed directly or as the Data Space locations following
those of the register file, $20 - $5F.
The AVR has Harvard architecture – with separate memories and buses for program and data. The program memory is
accessed with a two-stage pipeline. While one instruction is being executed, the next instruction is pre-fetched from the
program memory. This concept enables instructions to be executed in every clock cycle. The program memory is in-system
downloadable Flash memory.
With the relative jump and call instructions, the whole 1K address space is directly accessed. Most AVR instructions have a
single 16-bit word format. Every program memory address contains a 16- or 32-bit instruction.
During interrupts and subroutine calls, the return address Program Counter (PC) is stored on the stack. The stack is effectively allocated in the general data SRAM and consequently, the stack size is only limited by the total SRAM size and the
usage of the SRAM. All user programs must initialize the SP in the reset routine (before subroutines or interrupts are
executed). The 8-bit stack pointer (SP) is read/write-accessible in the I/O space.
The 128 bytes data SRAM + register file and I/O registers can be easily accessed through the five different addressing
modes supported in the AVR architecture.
The memory spaces in the AVR architecture are all linear and regular memory maps.
Figure 6. Memory Maps
EEPROM Data Memory
$000
EEPROM
(128 x 8)
$07F
7
A flexible interrupt module has its control registers in the I/O space with an additional global interrupt enable bit in the status
register. All the different interrupts have a separate interrupt vector in the interrupt vector table at the beginning of the program memory. The different interrupts have priority in accordance with their interrupt vector position. The lower the interrupt
vector address, the higher the priority.
8
AT90S2323/LS2323 and AT90S2343/LS2343
AT90S2323/LS2323 and AT90S2343/LS2343
AT90S2323/2343 Register Summary
Address
Name
$3F ($5F)
$3E ($5E)
$3D ($5D)
$3C ($5C)
$3B ($5B)
$3A ($5A)
$39 ($59)
$38 ($58)
$37 ($57)
$36 ($56)
$35 ($55)
$34 ($54)
$33 ($53)
$32 ($52)
$31 ($51)
$30 ($50)
$2F ($4F)
$2E ($4E)
$2D ($4D)
$2C ($4C)
$2B ($4B)
$2A ($4A)
$29 ($49)
$28 ($48)
$27 ($47)
$26 ($46)
$25 ($45)
$24 ($44)
$23 ($43)
$22 ($42)
$21 ($41)
$20 ($40)
$1F ($3F)
$1E ($3E)
$1D ($3D)
$1C ($3C)
$1B ($3B)
$1A ($3A)
$19 ($39)
$18 ($38)
$17 ($37)
$16 ($36)
$15 ($35)
…
$00 ($20)
SREG
Reserved
SPL
Reserved
GIMSK
GIFR
TIMSK
TIFR
Reserved
Reserved
MCUCR
MCUSR
TCCR0
TCNT0
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
WDTCR
Reserved
Reserved
EEAR
EEDR
EECR
Reserved
Reserved
Reserved
PORTB
DDRB
PINB
Reserved
Reserved
Reserved
Notes:
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Page
I
T
H
S
V
N
Z
C
page 17
SP7
SP6
SP5
SP4
SP3
SP2
SP1
SP0
page 17
-
INT0
INTF0
-
-
-
-
-
-
-
-
-
-
-
TOIE0
TOV0
-
page 22
page 23
page 23
page 23
-
-
SE
-
CS02
ISC01
EXTRF
CS01
ISC00
PORF
CS00
page 24
page 21
page 27
page 28
-
-
-
WDP2
WDP1
WDP0
page 29
EEWE
EERE
page 30
page 30
page 30
PORTB
DDB1
PINB1
PORTB
DDB0
PINB0
page 32
page 32
page 33
-
-
-
-
-
-
SM
Timer/Counter0 (8 Bits)
WDTO
WDE
EEPROM Address Register
EEPROM Data Register
EEMW
PORTB
DDB4
PINB4
PORTB
DDB3
PINB3
PORTB
DDB2
PINB2
1. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses
should never be written.
2. Some of the status flags are cleared by writing a logical “1” to them. Note that the CBI and SBI instructions will operate on all
bits in the I/O register, writing a one back into any flag read as set, thus clearing the flag. The CBI and SBI instructions work
with registers $00 to $1F only.
9
Instruction Set Summary
Mnemonic
Operands
Description
ARITHMETIC AND LOGIC INSTRUCTIONS
ADD
Rd, Rr
Add Two Registers
ADC
Rd, Rr
Add with Carry Two Registers
ADIW
Rdl, K
Add Immediate to Word
SUB
Rd, Rr
Subtract Two Registers
SUBI
Rd, K
Subtract Constant from Register
SBIW
Rdl,K
Subtract Immediate from Word
SBC
Rd, Rr
Subtract with Carry Two Registers
SBCI
Rd, K
Subtract with Carry Constant from Reg.
AND
Rd, Rr
Logical AND Registers
ANDI
Rd, K
Logical AND Register and Constant
OR
Rd, Rr
Logical OR Registers
ORI
Rd, K
Logical OR Register and Constant
EOR
Rd, Rr
Exclusive OR Registers
COM
Rd
One’s Complement
NEG
Rd
Two’s Complement
SBR
Rd, K
Set Bit(s) in Register
CBR
Rd, K
Clear Bit(s) in Register
INC
Rd
Increment
DEC
Rd
Decrement
TST
Rd
Test for Zero or Minus
CLR
Rd
Clear Register
SER
Rd
Set Register
BRANCH INSTRUCTIONS
RJMP
k
Relative Jump
IJMP
Indirect Jump to (Z)
RCALL
k
Relative Subroutine Call
ICALL
Indirect Call to (Z)
RET
Subroutine Return
RETI
Interrupt Return
CPSE
Rd, Rr
Compare, Skip if Equal
CP
Rd, Rr
Compare
CPC
Rd, Rr
Compare with Carry
CPI
Rd, K
Compare Register with Immediate
SBRC
Rr, b
Skip if Bit in Register Cleared
SBRS
Rr, b
Skip if Bit in Register is Set
SBIC
P, b
Skip if Bit in I/O Register Cleared
SBIS
P, b
Skip if Bit in I/O Register is Set
BRBS
s, k
Branch if Status Flag Set
BRBC
s, k
Branch if Status Flag Cleared
BREQ
k
Branch if Equal
BRNE
k
Branch if Not Equal
BRCS
k
Branch if Carry Set
BRCC
k
Branch if Carry Cleared
BRSH
k
Branch if Same or Higher
BRLO
k
Branch if Lower
BRMI
k
Branch if Minus
BRPL
k
Branch if Plus
BRGE
k
Branch if Greater or Equal, Signed
BRLT
k
Branch if Less Than Zero, Signed
BRHS
k
Branch if Half-carry Flag Set
BRHC
k
Branch if Half-carry Flag Cleared
BRTS
k
Branch if T-flag Set
BRTC
k
Branch if T-flag Cleared
BRVS
k
Branch if Overflow Flag is Set
BRVC
k
Branch if Overflow Flag is Cleared
BRIE
k
Branch if Interrupt Enabled
BRID
k
Branch if Interrupt Disabled
10
Operation
Flags
Rd ← Rd + Rr
Rd ← Rd + Rr + C
Rdh:Rdl ← Rdh:Rdl + K
Rd ← Rd − Rr
Rd ← Rd − K
Rdh:Rdl ← Rdh:Rdl − K
Rd ← Rd − Rr − C
Rd ← Rd − K − C
Rd ← Rd • Rr
Rd ← Rd • K
Rd ← Rd v Rr
Rd ← Rd v K
Rd ← Rd ⊕ Rr
Rd ← $FF − Rd
Rd ← $00 − Rd
Rd ← Rd v K
Rd ← Rd • ($FF − K)
Rd ← Rd + 1
Rd ← Rd − 1
Rd ← Rd • Rd
Rd ← Rd ⊕ Rd
Rd ← $FF
Z,C,N,V,H
Z,C,N,V,H
Z,C,N,V,S
Z,C,N,V,H
Z,C,N,V,H
Z,C,N,V,S
Z,C,N,V,H
Z,C,N,V,H
Z,N,V
Z,N,V
Z,N,V
Z,N,V
Z,N,V
Z,C,N,V
Z,C,N,V,H
Z,N,V
Z,N,V
Z,N,V
Z,N,V
Z,N,V
Z,N,V
None
1
1
2
1
1
2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
PC ← PC + k + 1
PC ← Z
PC ← PC + k + 1
PC ← Z
PC ← STACK
PC ← STACK
if (Rd = Rr) PC ← PC + 2 or 3
Rd − Rr
Rd − Rr − C
Rd − K
if (Rr(b) = 0) PC ← PC + 2 or 3
if (Rr(b) = 1) PC ← PC + 2 or 3
if (P(b) = 0) PC ← PC + 2 or 3
if (R(b) = 1) PC ← PC + 2 or 3
if (SREG(s) = 1) then PC ←=PC + k + 1
if (SREG(s) = 0) then PC ←=PC + k + 1
if (Z = 1) then PC ← PC + k + 1
if (Z = 0) then PC ← PC + k + 1
if (C = 1) then PC ← PC + k + 1
if (C = 0) then PC ← PC + k + 1
if (C = 0) then PC ← PC + k + 1
if (C = 1) then PC ← PC + k + 1
if (N = 1) then PC ← PC + k + 1
if (N = 0) then PC ← PC + k + 1
if (N ⊕ V = 0) then PC ← PC + k + 1
if (N ⊕ V = 1) then PC ← PC + k + 1
if (H = 1) then PC ← PC + k + 1
if (H = 0) then PC ← PC + k + 1
if (T = 1) then PC ← PC + k + 1
if (T = 0) then PC ← PC + k + 1
if (V = 1) then PC ← PC + k + 1
if (V = 0) then PC ← PC + k + 1
if (I = 1) then PC ← PC + k + 1
if (I = 0) then PC ← PC + k + 1
None
None
None
None
None
I
None
Z,N,V,C,H
Z,N,V,C,H
Z,N,V,C,H
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
2
2
3
3
4
4
1/2/3
1
1
1
1/2/3
1/2/3
1/2/3
1/2/3
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
AT90S2323/LS2323 and AT90S2343/LS2343
# Clocks
AT90S2323/LS2323 and AT90S2343/LS2343
Instruction Set Summary (Continued)
Mnemonic
Operands
Description
DATA TRANSFER INSTRUCTIONS
MOV
Rd, Rr
Move between Registers
LDI
Rd, K
Load Immediate
LD
Rd, X
Load Indirect
LD
Rd, X+
Load Indirect and Post-inc.
LD
Rd, -X
Load Indirect and Pre-dec.
LD
Rd, Y
Load Indirect
LD
Rd, Y+
Load Indirect and Post-inc.
LD
Rd, -Y
Load Indirect and Pre-dec.
LDD
Rd, Y+q
Load Indirect with Displacement
LD
Rd, Z
Load Indirect
LD
Rd, Z+
Load Indirect and Post-inc.
LD
Rd, -Z
Load Indirect and Pre-dec.
LDD
Rd, Z+q
Load Indirect with Displacement
LDS
Rd, k
Load Direct from SRAM
ST
X, Rr
Store Indirect
ST
X+, Rr
Store Indirect and Post-inc.
ST
-X, Rr
Store Indirect and Pre-dec.
ST
Y, Rr
Store Indirect
ST
Y+, Rr
Store Indirect and Post-inc.
ST
-Y, Rr
Store Indirect and Pre-dec.
STD
Y+q, Rr
Store Indirect with Displacement
ST
Z, Rr
Store Indirect
ST
Z+, Rr
Store Indirect and Post-inc.
ST
-Z, Rr
Store Indirect and Pre-dec.
STD
Z+q, Rr
Store Indirect with Displacement
STS
k, Rr
Store Direct to SRAM
LPM
Load Program Memory
IN
Rd, P
In Port
OUT
P, Rr
Out Port
PUSH
Rr
Push Register on Stack
POP
Rd
Pop Register from Stack
BIT AND BIT-TEST INSTRUCTIONS
SBI
P, b
Set Bit in I/O Register
CBI
P, b
Clear Bit in I/O Register
LSL
Rd
Logical Shift Left
LSR
Rd
Logical Shift Right
ROL
Rd
Rotate Left through Carry
ROR
Rd
Rotate Right through Carry
ASR
Rd
Arithmetic Shift Right
SWAP
Rd
Swap Nibbles
BSET
s
Flag Set
BCLR
s
Flag Clear
BST
Rr, b
Bit Store from Register to T
BLD
Rd, b
Bit Load from T to Register
SEC
Set Carry
CLC
Clear Carry
SEN
Set Negative Flag
CLN
Clear Negative Flag
SEZ
Set Zero Flag
CLZ
Clear Zero Flag
SEI
Global Interrupt Enable
CLI
Global Interrupt Disable
SES
Set Signed Test Flag
CLS
Clear Signed Test Flag
SEV
Set Two’s Complement Overflow
CLV
Clear Two’s Complement Overflow
SET
Set T in SREG
CLT
Clear T in SREG
SEH
Set Half-carry Flag in SREG
CLH
Clear Half-carry Flag in SREG
NOP
No Operation
SLEEP
Sleep
WDR
Watchdog Reset
Operation
Flags
# Clocks
Rd ← Rr
Rd ← K
Rd ← (X)
Rd ← (X), X ← X + 1
X ← X − 1, Rd ← (X)
Rd ← (Y)
Rd ← (Y), Y ← Y + 1
Y ← Y − 1, Rd ← (Y)
Rd ← (Y + q)
Rd ← (Z)
Rd ← (Z), Z ← Z + 1
Z ← Z - 1, Rd ← (Z)
Rd ← (Z + q)
Rd ← (k)
(X) ← Rr
(X) ← Rr, X ← X + 1
X ← X - 1, (X) ← Rr
(Y) ← Rr
(Y) ← Rr, Y ← Y + 1
Y ← Y - 1, (Y) ← Rr
(Y + q) ← Rr
(Z) ← Rr
(Z) ← Rr, Z ← Z + 1
Z ← Z - 1, (Z) ← Rr
(Z + q) ← Rr
(k) ← Rr
R0 ← (Z)
Rd ← P
P ← Rr
STACK ← Rr
Rd ← STACK
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
1
1
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
3
1
1
2
2
I/O(P,b) ← 1
I/O(P,b) ← 0
Rd(n+1) ← Rd(n), Rd(0) ← 0
Rd(n) ← Rd(n+1), Rd(7) ← 0
Rd(0) ←=C, Rd(n+1) ← Rd(n), C ←=Rd(7)
Rd(7) ←=C, Rd(n) ← Rd(n+1), C ←=Rd(0)
Rd(n) ← Rd(n+1), n = 0..6
Rd(3..0) ←=Rd(7..4), Rd(7..4) ←=Rd(3..0)
SREG(s) ← 1
SREG(s) ← 0
T ← Rr(b)
Rd(b) ← T
C←1
C←0
N←1
N←0
Z←1
Z←0
I←1
I←0
S←1
S←0
V←1
V←0
T←1
T←0
H←1
H←0
None
None
Z,C,N,V
Z,C,N,V
Z,C,N,V
Z,C,N,V
Z,C,N,V
None
SREG(s)
SREG(s)
T
None
C
C
N
N
Z
Z
I
I
S
S
V
V
T
T
H
H
None
None
None
2
2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
3
1
(see specific descr. for Sleep function)
(see specific descr. for WDR/timer)
11
Ordering Information
Power Supply
Speed (MHz)
2.7 - 6.0V
4
4.0 - 6.0V
2.7 - 6.0V
4.0 - 6.0V
Note:
10
4
10
Ordering Code
Package
AT90LS2323-4PC
AT90LS2323-4SC
8P3
8S2
Commercial
(0°C to 70°C)
AT90LS2323-4PI
AT90LS2323-4SI
8P3
8S2
Industrial
(-40°C to 85°C)
AT90S2323-10PC
AT90S2323-10SC
8P3
8S2
Commercial
(0°C to 70°C)
AT90S2323-10PI
AT90S2323-10SI
8P3
8S2
Industrial
(-40°C to 85°C)
AT90LS2343-4PC
AT90LS2343-4SC
8P3
8S2
Commercial
(0°C to 70°C)
AT90LS2343-4PI
AT90LS2343-4SI
8P3
8S2
Industrial
(-40°C to 85°C)
AT90S2343-10PC
AT90S2343-10SC
8P3
8S2
Commercial
(0°C to 70°C)
AT90S2343-10PI
AT90S2343-10SI
8P3
8S2
Industrial
(-40°C to 85°C)
The speed grade refers to maximum clock rate when using an external crystal or external clock drive. The internal RC oscillator
has the same nominal clock frequency for all speed grades.
Package Type
8P3
8-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP)
8S2
8-lead, 0.200" Wide, Plastic Gull Wing Small Outline Package (EIAJ SOIC)
12
Operation Range
AT90S2323/LS2323 and AT90S2343/LS2343
AT90S2323/LS2323 and AT90S2343/LS2343
Packaging Information
8P3, 8-lead, 0.300" Wide, Plastic Dual Inline
Package (PDIP)
Dimensions in Inches and (Millimeters)
8S2, 8-lead, 0.200" Wide, Plastic Gull Wing Small
Outline (EIAJ SOIC)
Dimensions in Inches and (Millimeters)
JEDEC STANDARD MS-001 BA
.020 (.508)
.012 (.305)
.400 (10.16)
.355 (9.02)
PIN
1
.280 (7.11)
.240 (6.10)
.300 (7.62) REF
.210 (5.33) MAX
.037 (.940)
.027 (.690)
.330 (8.38)
.300 (7.62)
.050 (1.27) BSC
.100 (2.54) BSC
.212 (5.38)
.203 (5.16)
SEATING
PLANE
.080 (2.03)
.070 (1.78)
.015 (.380) MIN
.150 (3.81)
.115 (2.92)
.070 (1.78)
.045 (1.14)
.022 (.559)
.014 (.356)
.013 (.330)
.004 (.102)
.325 (8.26)
.300 (7.62)
.012 (.305)
.008 (.203)
.213 (5.41)
.205 (5.21)
PIN 1
0
REF
15
.430 (10.9) MAX
0
REF
8
.010 (.254)
.007 (.178)
.035 (.889)
.020 (.508)
13
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© Atmel Corporation 2000.
Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company’s standard warranty which is detailed in Atmel’s Terms and Conditions located on the Company’s web site. The Company assumes no responsibility for
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