APPROVED PRODUCT C9815 Low EMI Clock Generator for Intel 133MHz/2DIMM Chipset Systems Product Features • • • • • • • • • • • • Frequency Table (MHz) Meets Intel’s 133MHz/SDRAM chipset specification 3 copies of CPU Clock (CPU[0:1] and CPU2_ITP) 9 copies of SDRAM Clock (SDRAM[0:7] and DCLK) 7 copies of PCI Clock 3 copies of 3V66 Clock 2 copies of IOAPIC Clock 1 REF Clock 1 USB Clock (Non SSC) 1 DOT Clock (Non SSC) Cypress Spread Spectrum for best EMI reduction SMBUS Support with read back 56 Pin SSOP package SEL2 SEL1 SEL0 X 0 0 CPU SDRAM PCI Tri-state X 0 1 0 1 0 Test Mode 0 1 1 1 1 0 1 1 1 133.3 MHz 66.6 MHz 100 MHz* 33.3 100 MHz 100 MHz* 33.3 133.3 MHz 133.3 MHz 33.3 100 MHz* 33.3 Table 1 Note: The following clocks remain fixed frequencies except in Test Mode: 3V66=66.6MHz, USB/DOT=48MHz, REF=14.318MHz and IOAPIC=33.3MHz. *SMBUS programmable to 133 MHz, Byte 3, Bit 0 Block Diagram Pin Configuration XIN 36pF 300K 36pF XOUT VDD REF / SEL2 1 VDDI s2 apic IOAPIC(0:1) 2 VDDC cpu CPU(0:2) 3 Rin SCLK SDATA SEL1 SEL0 PD# i2c-clk i2c-data VDDS s1 s0 sdram SDRAM(0:7), DCLK 9 VDD pwr_dwn# 3V66 3V66(0:2) 2 VDD pci Rin PCI(0:6) 8 PLL1 VDD 48 DOT 1 VDD PD# 1 i2c-clk i2c-data USB REF/SEL2 VDD XIN XOUT VSS VSS 3V66_0 3V66_1 3V66_2(AGP) VDD VDD PCI0(ICH) PCI1 VSS PCI2 PCI3 VSS PCI4 PCI5 PCI6 VDD VDDA VSSA VSS USB DOT VDD SEL0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 56 C 9 8 1 5 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 VSS IOAPIC0 IOAPIC1 VDDI CPU0 VDDC CPU1 CPU2(ITP) VSS VSS SDRAM0 SDRAM1 VDDS SDRAM2 SDRAM3 VSS SDRAM4 SDRAM5 VDDS SDRAM6 SDRAM7 VSS DCLK VDD PD# SCLK SDATA SEL1 PLL2 Fig.1 Cypress Semiconductor Corporation 525 Los Coches St. Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571 http://www.cypress.com Document#: 38-07054 Rev. ** 05/03/2001 Page 1 of 19 APPROVED PRODUCT C9815 Low EMI Clock Generator for Intel 133MHz/2DIMM Chipset Systems Pin Description PWR I/O Description 1 PIN No. SEL2/REF Pin Name VDD I/O 3 XIN VDD I 4 XOUT VDD O 12,13,15, 16,18,19, 20 7, 8, 9 25 26 28, 29 PCI0_ICH PCI(1..6) 3V66(0:2) USB DOT SEL(0,1) VDD O This is a bi-directional pin (see app. note, p.5). At power up, it is an input pin Sel2 for selecting the CPU/SDRAM frequencies (see table 1 p.1). When the power reaches the rail, the state of Sel2 is latched, and this pin becomes REF, a buffer output of the signal applied at Xin, typically 14.318MHz. This pin has an Internal Pull-Down. Typical 50KΩ (range 20KΩ to 70KΩ) On-chip reference oscillator input pin. Requires either an external parallel resonant crystal (nominally 14.318 MHz) or externally generated reference signal On-chip reference oscillator pin. Drives an external parallel resonant crystal. When an externally generated reference signal is used at Xin, this pin remains unconnected. 3.3V PCI clock outputs. They are Synchronous to CPU clocks. See fig.3, page4. VDD VDD VDD VDD O O O I 30 SDATA VDD I/O 31 32 SCLK PD# VDD VDD I I 34 DCLK VDD O 36,37,39,40, 42,43,45, 46 49, 50, 52 SDRAM(7..0) VDDS O CPU(2)_ITP,C PU(1,0) IOAPIC(1,0) VDD VDDC O 3.3V Fixed 66.6 MHz clock outputs. See fig.3 page 4. 3.3V Fixed 48 MHz clock outputs 3.3V Fixed 48 MHz clock outputs 3.3V LVTTL inputs for logic selection. This pin has an Internal Pull-Up. Typical 250KΩ (range 200KΩ to 500KΩ) Serial data input pin. Conforms to the SMBUS specification of a Slave Receive/Transmit device. This pin is an input when receiving data. It is an open drain output when acknowledging or transmitting data. See SMBUS function description, pp.6,7,8. Serial clock input pin. Conforms to the SMBUS specification. 3.3V LVTTL compatible input. When held LOW, the device enters a power down mode. See description page 3. This pin has an Internal Pull-Up. Typical 250KΩ (range 200KΩ to 500KΩ) 3.3V SDRAM feedback clock. See table1, p.1 for frequency selection. See fig.3, page 4 for timing relationship. 3.3V SDRAM DIMM clocks. See table1, p.1 for frequency selection. See fig.3, page 4 for timing relationship. 2.5V Host clock outputs. See table 1 p. 1 for frequency selection. 54, 55 VDDI O 2.5V IOAPIC clock outputs. See fig.3 p.4 for timing relationship. 2,10, 11, 21, 3.3V Common Power Supply 27, 33 22 Analog circuitry 3.3V Power Supply VDDA 23 Analog circuitry power supply Ground pins. VSSA 51, 53 2.5V Power Supply’s VDDC, VDDI Common Ground pins. 5, 6,14, 17, VSS 24, 35, 41, 47, 48, 56 38, 44 3.3V power support for SDRAM clock output drivers. VDDS A bypass capacitor (0.1µF) should be placed as close as possible to each positive power pin. If these bypass capacitors are not close to the pins their high frequency filtering characteristic will be cancelled by the lead inductance of the traces. Cypress Semiconductor Corporation 525 Los Coches St. Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571 http://www.cypress.com Document#: 38-07054 Rev. ** 05/03/2001 Page 2 of 19 APPROVED PRODUCT C9815 Low EMI Clock Generator for Intel 133MHz/2DIMM Chipset Systems Test Mode Function Test Mode Functionality SEL2 SEL1 SEL0 x 0 1 CPU TCLK/2 SDRAM TCLK/2 3V66 TCLK/3 PCI TCLK/6 USB/DOT TCLK/2 REF TCLK IOAPIC TCLK/6 Table 2 Note: TCLK is a test clock over driven on the XIN input during test mode. Power Management Functions Power Management on this device is controlled by a single pin, PD# (pin32). When PD# is high (default) the device is in normal running mode and all signals are active. When PD# is asserted (forced) low, the device is in shutdown (or in power down) mode and all power supplies (3.3V and 2.5V except for VDDA/pin 27) may be removed. When in power down, all outputs are synchronously stopped in a low state (see Fig.2 below), all PLL’s are shut off, and the crystal oscillator is disabled. When the device is shutdown, the I²C function is also disabled. Power Management Timing 10nS 0nS 20nS 30nS 40nS 50nS CPU 100MHz 3V66 66MHz PCI 33MHz IOAPIC 33MHz PWRDN# Undefined SDRAM 100MHz Undefined REF 14.3MHz USB Undefined 48MHz Fig.2 Power Management Current Maximum 2.5 Volt Current Consumption (VDDC = VDDI =2.625) 10mA Maximum 3.3 Volt Current Consumption (VDD = VDDA = VDDS = 3.465 V) 10mA 1010 (66MHz) 70 mA 280 mA 1011 (100MHz) 100 mA 280 mA 1101 (133MHz) 133 mA 365 mA PD#, SEL2, SEL1, SEL0 0XXX (Power down) Table 3 When exiting the power down mode, the designer must supply power to the VDD pins first, a minimum of 200mS before releasing the PD# pin high. Cypress Semiconductor Corporation 525 Los Coches St. Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571 http://www.cypress.com Document#: 38-07054 Rev. ** 05/03/2001 Page 3 of 19 APPROVED PRODUCT C9815 Low EMI Clock Generator for Intel 133MHz/2DIMM Chipset Systems IOAPIC Clock Synchronization and Phase Alignment This device incorporates IOAPIC clock synchronization. With this feature, the IOAPIC clocks are derived from the CPU clock. The IOAPIC clock lags the CPU clock by the specified 1.5 to 3.5 nSec. Figure 3 shows the relationship between the CPU and IOAPIC clocks. Clock Phase Relationships 0nS CPU CLOCK 10nS 20nS 30nS Sync 66MHz CPU CLOCK 100MHz 2.5nS CPU CLOCK 133MHz 5nS 5nS SDRAM CLOCK 100MHz 40nS 0nS 7.5nS 0nS 3.75nS SDRAM CLOCK 133MHz 0nS 3.75nS 3V66 CLOCK 66MHz 1.5~3.5nS PCI CLOCK 33MHz IOAPIC CLOCK 33MHz Fig.3 Cypress Semiconductor Corporation 525 Los Coches St. Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571 http://www.cypress.com Document#: 38-07054 Rev. ** 05/03/2001 Page 4 of 19 APPROVED PRODUCT C9815 Low EMI Clock Generator for Intel 133MHz/2DIMM Chipset Systems Group Timing Relationships and Tolerances CPU = 66.6 MHz, SDRAM = 100 MHz Offset (nS) Tolerance (pS) CPU to SDRAM 2.5 500 SDRAM Leads CPU to 3V66 7.5 500 180 degrees phase shift 0 500 When rising edges line-up 1.5-3.5 500 3V66 leads 0 1000 Offset (nS) Tolerance (pS) CPU to SDRAM 5 500 180 degrees phase shift CPU to 3V66 5 500 CPU leads SDRAM to 3V66 0 500 When rising edges line-up 1.5-3.5 500 3V66 leads 0 1000 SDRAM to 3V66 3V66 to PCI PCI to IOAPIC Conditions CPU = 100 MHz, SDRAM = 100 MHz 3V66 to PCI PCI to IOAPIC Conditions CPU = 133.3 MHz, SDRAM = 100 MHz Offset (nS) Tolerance (pS) CPU to SDRAM 0 500 CPU to 3V66 0 500 SDRAM to 3V66 0 500 When rising edges line-up 1.5-3.5 500 3V66 leads 0 1000 3V66 to PCI PCI to IOAPIC Conditions When rising edges line-up CPU = 133.3 MHz, SDRAM = 133.3 MHz CPU to SDRAM CPU to 3V66 SDRAM to 3V66 3V66 to PCI PCI to IOAPIC Offset (nS) Tolerance (pS) 3.75 500 0 500 3.75 500 1.5-3.5 500 0 1000 Cypress Semiconductor Corporation 525 Los Coches St. Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571 http://www.cypress.com Conditions 180 degrees phase shift 3V66 leads Document#: 38-07054 Rev. ** 05/03/2001 Page 5 of 19 APPROVED PRODUCT C9815 Low EMI Clock Generator for Intel 133MHz/2DIMM Chipset Systems Power on Bi-Directional Pins Power Up Condition: Pin1 is a Power up bi-directional pin and is used for selecting the host frequency in page 1, table 1. During power-up of the device, this pin is in input mode (see Fig 4, below), therefore; it is considered input select pin, Sel2 internal to the IC. After a settling time, the selection data is latch into the internal control register and this pin becomes a clock output. VDD Rail ower Supply amp REF / SEL2 (Pin 1) Hi-Z Inputs - Toggle Outputs Select data is latched into register, then pin becomes a REF clock output signal. Fig.4 V dd Strapping Resistor Options: The power up bi-directional pin has a large value pulldown (50KΩ+/−20KΩ), therefore, a selection “0” is the default. If the system uses a slow power supply (over 10mS settling time), then it is recommended to use an external Pull-down (Rdn) in order to insure a low selection. In this case, the designer may choose one of two configurations, see Fig.5A and 5B. R up 1K IM I C 9 8 1 5 B id ire c tio n a l JP 1 JU M P E R Rd Load R dn 5K Fig. 5A represents an additional pull down resistor 5KΩ connected from the pin to the power line, which allows a faster down to a high level. If a selection “1” is desired, then a jumper is placed on JP1 to a 1 KΩ resistor as shown in Fig.5A. Please note the selection resistors (Rup and Rdn) are placed before the Damping resistor (Rd) close to the pin. F ig . 5 A V dd JP 2 3 W ay Jum per 3 Fig. 5B represent a single resistor 5KΩ connected to a 3-way jumper, JP2. When a “1” selection is desired, a jumper is placed between leads1 and 3. When a “0” selection is desired, a jumper is placed between leads 1 and 2. IM I C 9 8 1 5 2 1 R sel 5K Rd Load B id ire c tio n a l F ig . 5 B Cypress Semiconductor Corporation 525 Los Coches St. Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571 http://www.cypress.com Document#: 38-07054 Rev. ** 05/03/2001 Page 6 of 19 APPROVED PRODUCT C9815 Low EMI Clock Generator for Intel 133MHz/2DIMM Chipset Systems 2-Wire SMBUS Control Interface The 2-wire control interface implements a read/write slave only interface according to SMBus specification. (See Fig. 6 below). The device can be read back by using standard SMBUS command bytes. Sub addressing is not supported, thus all preceding bytes must be sent in order to change one of the control bytes. The 2-wire control interface allows each clock output to be individually enabled or disabled. 100 Kbits/second (standard mode) data transfer is supported. During normal data transfer, the SDATA signal only changes when the SCLK signal is low, and is stable when SCLK is high. There are two exceptions to this. A high to low transition on SDATA while SCLK is high is used to indicate the start of a data transfer cycle. A low to high transition on SDATA while SCLK is high indicates the end of a data transfer cycle. Data is always sent as complete 8-bit bytes, after which an acknowledge is generated. The first byte of a transfer cycle is an 8-bit address. The LSB address Byte = 0 in write mode. The device will respond to transfers of 10 bytes (max) of data. The device will generate an acknowledge (low) signal on the SDATA wire following reception of each byte. Data is transferred MSB first at a max rate of 100kbits/S. This device will also respond to a D3 address which sets it in a read mode. It will not respond to any other control interface conditions, and previously set control registers are retained. Transmit Receive 1 1 0 1 0 0 1 ACK 0 ACK (Don’t Care) (Don’t Care) ACK BYTE 0 BYTE N (Valid) (Valid) 8 8 CLK START CONDITION 1 0 1 0 0 1 ACK BYTE COUNT ACK 1 DATA BYTE1 ACK BYTE N ACK (Valid) (Valid) 8 8 ACK (Valid) LSB 8 CLK START CONDITION 8 STOP CONDITION BYTE 0 (Valid) MSB 8 Fig.6a (WRITE) Transmit 1 ACK LSB MSB Receiv BYTE COUNT COMMAND BYTE DATA ACK 8 STOP CONDITION Fig.6b (READ) Figure 6 SMBUS Communications Waveforms Cypress Semiconductor Corporation 525 Los Coches St. Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571 http://www.cypress.com Document#: 38-07054 Rev. ** 05/03/2001 Page 7 of 19 APPROVED PRODUCT C9815 Low EMI Clock Generator for Intel 133MHz/2DIMM Chipset Systems Serial Control Registers NOTE: The Pin# column lists the relevant pin number where applicable. The @Pup column gives the default state at power up. Following the acknowledge of the Address Byte, two additional bytes must be sent: 1) “Command Code “ byte, and 2) “Byte Count” byte. Although the data (bits) in these two bytes are considered “don’t care”; they must be sent and will be acknowledged. After the Command Code and the Count bytes have been acknowledged, the sequence described below (Byte 0, Byte 1, and Byte 2) will be valid and acknowledged. Byte 0: CPU Clock Register (1=Enable, 0=Disable) Bit 7 6 5 4 3 2 1 0 @Pup 0 0 0 0 0 1 1 1 Pin# 26 25 49 Description Reserved Reserved Reserved Reserved Spread spectrum mode DOT USB CPU2_ITP Byte 2: PCI Clock Register (1=Enable, 0=Disable) Bit 7 6 5 4 3 2 1 0 @Pup 1 1 1 1 1 1 1 0 Pin# 9 20 19 18 16 15 13 - Description 3V66-2 (AGP) PCI6 PCI5 PCI4 PCI3 PCI2 PCI1 Reserved Byte 1: SDRAM Clock Register (1=Enable, 0=Disable) Bit 7 6 5 4 3 2 1 0 @Pup 1 1 1 1 1 1 1 1 Pin# 36 37 39 40 42 43 45 46 Description SDRAM7 SDRAM6 SDRAM5 SDRAM4 SDRAM3 SDRAM2 SDRAM1 SDRAM0 Byte 3: Reserved Register Bit @Pup Pin# 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0 - Description RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED 0 = SDRAM runs at 100MHz 1= SDRAM runs at 133.3MHz Byte 4: Reserved Register Byte 5: SSCG Control Register Bit 7 6 5 4 3 2 1 0 Cypress Semiconductor Corporation 525 Los Coches St. Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571 http://www.cypress.com @Pup 0 0 0 0 0 0 0 0 Pin# - Description Spread Mode (0=down, 1=center) Selects spread bandwidth. Ref. Table 4 Selects spread bandwidth. Ref. Table 4 Reserved Reserved Reserved Reserved Reserved Document#: 38-07054 Rev. ** 05/03/2001 Page 8 of 19 APPROVED PRODUCT C9815 Low EMI Clock Generator for Intel 133MHz/2DIMM Chipset Systems SMBUS Test Circuitry + 5V Device under Test 2.2 K DATAIN SDATA + 5V SCLK 2.2 K + 5V DATAOUT 2.2 K CLOCK Fig.7 Note: Buffer is 7407 with VCC @ 5.0 V Spread Spectrum Clock Generation (SSCG) Spread Spectrum is a modulation technique applied here for maximum efficiency in minimizing Electro-Magnetic Interference radiation generated from repetitive digital signals mainly clocks. A clock accumulates EM energy at the center frequency it is generating. Spread Spectrum distributes this energy over a small frequency bandwidth therefore distributing an even amount of energy over a wider spectrum. This technique is achieved by modulating the clock either down (Fig.8A) or around the center (Fig.8B) of its resting frequency by a certain percentage (which also determines the energy distribution bandwidth). In this device, Spread Spectrum is enabled by setting SMBUS byte0, bit3 = 1. The default of the device at power up keeps the Spread Spectrum disabled, it is therefore, important to have SMBUS accessibility to turn-on the Spread Spectrum function. Once the Spread Spectrum is enabled, the spread bandwidth option is selected by SST(0:2) in SMBUS byte 5, bits 5, 6 & 7 following tables 4A, and 4B below. In Down Spread mode the center frequency is shifted down from its rested (non-spread) value by ½ of the total spread %. (eg.: assuming the center frequency is 100MHz in non-spread mode; when down spread of –0.5% is enabled, the center frequency shifts to 99.75MHz.). Cypress Semiconductor Corporation 525 Los Coches St. Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571 http://www.cypress.com Document#: 38-07054 Rev. ** 05/03/2001 Page 9 of 19 APPROVED PRODUCT C9815 Low EMI Clock Generator for Intel 133MHz/2DIMM Chipset Systems In Center Spread mode, the Center frequency remains the same as in the non-spread mode. Down Spread Center Spread Figure 8A Figure 8B Spread Spectrum Selection Tables I²C BYTE5 Bit[7:5] 000 001 010 011 Spread % - 0.5 - 0.7 - 1.0 - 0.25 Table 4A Spread % ± 0.25 ± 0.35 ± 0.5 +/- 0.125 I²C BYTE5 Bit[7:5] 100 101 110 111 Table 4B Maximum Ratings Maximum Input Voltage Relative to VSS: VSS - 0.3V Maximum Input Voltage Relative to VDD: VDD + 0.3V Storage Temperature: -65ºC to + 150ºC Operating Temperature: 0ºC to +85ºC Maximum ESD protection 2KV Maximum Power Supply: 5.5V This device contains circuitry to protect the inputs against damage due to high static voltages or electric field; however, precautions should be taken to avoid application of any voltage higher than the maximum rated voltages to this circuit. For proper operation, Vin and Vout should be constrained to the range: VSS<(Vin or Vout)<VDD Unused inputs must always be tied to an appropriate logic voltage level (either VSS or VDD). Cypress Semiconductor Corporation 525 Los Coches St. Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571 http://www.cypress.com Document#: 38-07054 Rev. ** 05/03/2001 Page 10 of 19 APPROVED PRODUCT C9815 Low EMI Clock Generator for Intel 133MHz/2DIMM Chipset Systems DC Parameters (All outputs loaded per table 5 below) (VDD=VDDS = 3.3V ±5%, VDDC = VDDI = 2.5 ± 5%, TA = 0º to +85ºC) Characteristic Min Typ Units Conditions Input Low Voltage VIL1 - - 1.0 Vdc Note 1 Input High Voltage VIH1 2.0 - - Vdc Input Low Voltage VIL2 - - 1.0 Vdc Input High Voltage VIH2 2.2 - - Vdc Input Low Current (@VIL = VSS) IIL1 -66 -5 µA Input High Current (@VIL =VDD) IIH1 5 µA Input Low Current (@VIL = VSS) IIL2 Input High Current (@VIL = VDD) IIH2 Tri-State leakage Current Ioz - - 10 µA Dynamic Supply Current Idd3.3V - - 280 mA Dynamic Supply Current Idd2.5V - - 100 mA Sel2 = 0, Sel1 = Sel0 = 1 Isdd - - 10 mA Sel1 = Sel0 = x, PD# = 0 Cin - - 5 pF Cout - - 6 pF Static Supply Current Input pin capacitance Output pin capacitance Symbol Max µA µA Pin inductance Lpin - - 7 nH Crystal pin capacitance Cxtal 32 34 38 pF Crystal DC Bias Voltage VBIAS 0.3Vdd Vdd/2 0.7Vdd V Crystal Startup time Txs - - 40 µS Note1: Note2: Note3: Note5: Note6: Note 2 For internal Pull up resistors, Note 6 For internal Pull Down resistors, Note 6 Sel2 = 0, Sel1 = Sel0 = 1 Measured from Pin to Ground. Note 5 From Stable 3.3V power supply. Applicable to input signals: Sel(0:1), PD# (pull up), SEL2 (pull down) Applicable to Sdata, and Sclk. Although internal pull-up resistors have a typical value of 250K, this value may vary between 200K and 500K. Although the device will reliably interface with crystals of a 17pF – 20pF CL range, it is optimized to interface with a typical CL = 18pF crystal specifications. Internal Pull up and Pull down resistors have a typical value of 50k (it may vary between 30K and 70K). Clock Name CPU(0:2), IOAPIC(0:1), REF, USB PCI(0:6), SDRAM(0:7), DCLK, 3V66(0:2) DOT Table 5. Max Load (in pF) 20 30 15 Cypress Semiconductor Corporation 525 Los Coches St. Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571 http://www.cypress.com Document#: 38-07054 Rev. ** 05/03/2001 Page 11 of 19 APPROVED PRODUCT C9815 Low EMI Clock Generator for Intel 133MHz/2DIMM Chipset Systems AC Parameters Symbol TPeriod 133 MHz Host 100 MHz Host 66 MHz Host Min Max Min Max Min Max Units 7.5 8.0 10.0 10.5 14.75 15.25 nS 1.87 - 3.0 - 5.2 - nS 1.67 - 2.8 - 5.0 - nS 0.4 1.6 0.4 1.6 0.4 1.6 nS - 175 - 175 - 175 pS 6,9 - 250 - 250 - 250 pS 5,6 7.5 8.0 10.0 10.5 10.0 10.5 nS 1.87 - 3.0 - 3.0 - nS 1.67 - 2.8 - 2.8 - nS 0.4 1.6 0.4 1.6 0.4 1.6 nS - 250 - 250 - 250 pS - 250 - 250 - 250 pS 30.0 - 30.0 - 30.0 - nS 12.0 - 12.0 - 12.0 - nS 12.0 - 12.0 N/S 12.0 - nS 0.4 1.6 0.4 1.6 0.4 1.6 nS Parameter CPU(0:2) period 5,8 THIGH CPU(0:2) high time TLOW CPU(0:2) low time 10 11 7 Tr / Tf CPU(0:2) rise and fall times TSKEW CPU0 to CPU Skew TCCJ CPU(0:2) Cycle to Cycle Jitter TPeriod SDRAM(0:7) and DCLK period THIGH SDRAM(0:7) and DCLK high time TLOW 6,9 SDRAM(0:7) and DCLK low time 10 11 Tr / Tf SDRAM(0:7) and DCLK rise and fall times TSKEW SDRAM(0:7) and DCLK Skew TCCJ SDRAM(0:7), DCLK Cycle to Cycle Jitter 6,9 6,9 5,6 TPeriod IOAPIC(0:1) period THIGH IOAPIC(0:1) high time 10 11 TLOW IOAPIC(0:1) low time Tr / Tf IOAPIC(0:1) rise and fall times 7 6,9 TCCJ IOAPIC(0:1) Cycle to Cycle Jitter TPeriod 3V66-(0:2) period THIGH 3V66-(0:2) high time TLOW 7 - 500 - 500 - 500 pS 15.0 16.0 15.0 16.0 15.0 16.0 nS 10 5.25 - 5.25 - 5.25 - nS 11 5.05 - 5.05 - 5.05 - nS 5,6 3V66-(0:2) low time 7 Tr / Tf 3V66-(0:2) rise and fall times TSKEW (Any 3V66) to (any 3V66) Skew 0.5 2.0 0.5 2.0 0.5 2.0 nS 6,9 - 175 - 175 - 175 pS TCCJ 3V66-(0:2) Cycle to Cycle Jitter 6,9 - 500 - 500 - 500 pS 5,6 30.0 - 30.0 - 30.0 - nS 10 12.0 - 12.0 - 12.0 - nS 12.0 - 12.0 - 12.0 - nS 0.5 2.0 0.5 2.0 0.5 2.0 nS 6,9 - 500 - 500 - 500 pS 6,9 - 500 - 500 - 500 pS 20.8299 20.8333 20.8299 20.8333 20.829 20.833 nS 1.0 4.0 1.0 4.0 1.0 4.0 nS - 500 - 500 - 500 pS TPeriod PCI(0:6) period THIGH PCI(0:6) period 11 TLOW PCI(0:6) low time Tr / Tf PCI(0:6) rise and fall times TSKEW (Any PCI) to (Any PCI) Skew TCCJ PCI(0:6) Cycle to Cycle Jitter 7 TPeriod DOT & USB period (conforms to +167ppm 5,6 max) Tr / Tf DOT & USB rise and fall times TCCJ DOT & USB Cycle to Cycle Jitter Cypress Semiconductor Corporation 525 Los Coches St. Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571 http://www.cypress.com 7 6,9 Document#: 38-07054 Rev. ** 05/03/2001 Page 12 of 19 APPROVED PRODUCT C9815 Low EMI Clock Generator for Intel 133MHz/2DIMM Chipset Systems 133 MHz Host Symbol Parameter 5,6 TPeriod REF period Tr / Tf REF rise and fall times TCCJ REF Cycle to Cycle Jitter tpZL, tpZH Output enable delay (all outputs) tpLZ, tpHZ Output disable delay (all outputs) tstable All clock Stabilization from power-up Tduty Duty Cycle for All outputs 7 6 8 13 14 100 MHz Host 66 MHz Host Units Min Max Min Max Min Max 69.8413 71.0 69.8413 71.0 69.8413 71.0 nS 1.0 4.0 1.0 4.0 1.0 4.0 nS - 1000 - 1000 - 1000 pS 1.0 10.0 1.0 10.0 1.0 10.0 nS 1.0 10.0 1.0 10.0 1.0 10.0 nS 3 mS 55 % 12 3 45 55 3 45 55 45 Note 5: This parameter is measured as an average over 1uS duration, with a crystal center frequency of 14.31818MHz Note 6: All outputs loaded as per table 5, page 11. Probes are placed on the pins and taken at 1.5V levels for 3.3V signals and at 1.25V for 2.5V signals (figs. 9A and 9B). Note 7: Probes are placed on the pins, and measurements are acquired between 0.4V and 2.4V for 3.3V signals and between 0.4V and 2.0V for 2.5V signals (see Fig.9A and Fig.9B) Note 8: Measured from when both SEL1 and SEL0 are switched to high (enable). Note 9: This measurement is applicable with Spread ON or Spread OFF. Note 10:Probes are placed on the pins, and measurements are acquired at 2.4V for 3.3V signals and at 2.0V for 2.5V signals, (see Figs. 9A & 9B) Note 11:Probes are placed on the pins, and measurements are acquired at 0.4V. Note 12:The time specified is measured from when all VDD’s reach their respective supply rail (3.3V and 2.5V) till the frequency output is stable and operating within the specifications Note 13:Measured from when both SEL1 and SEL0 are switched to low (disable). Note 14: Device designed for Typical Duty Cycle of 50%. Cypress Semiconductor Corporation 525 Los Coches St. Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571 http://www.cypress.com Document#: 38-07054 Rev. ** 05/03/2001 Page 13 of 19 APPROVED PRODUCT C9815 Low EMI Clock Generator for Intel 133MHz/2DIMM Chipset Systems Output Buffer Characteristics (VDD=VDDS=3.3V ±5%, VDDC=VDDI=2.5±5%, TA=0 to 85ºC) CPU and IOAPIC Characteristic Symbol Min Typ Pull-Up Current IOH1 -15 -31 Max -51 Units mA Conditions Vout =VDDC - 0.5V (or VDDI –0.5V) Pull-Up Current IOH2 -26 -58 -101 mA Vout = 1.2 V Pull-Down Current IOL1 12 24 40 mA Vout = 0.4 V Pull-Down Current IOL2 27 56 93 mA Vout = 1.2 V Characteristic Symbol Min Typ Max Units Pull-Up Current IOH1 -20 -25 -33 mA Vout =VDD - 1.0 V Pull-Up Current IOH2 -30 -54 -184 mA Vout = 1. 5 V Pull-Down Current IOL1 9.4 18 38 mA Vout = 0.4 V Pull-Down Current IOL2 28 55 148 mA Vout = 1.5 V Characteristic Symbol Min Typ Pull-Up Current IOH1 -12 -20 -30 mA Vout =VDD - 1.0 V Pull-Up Current IOH2 -27 -43 -92 mA Vout = 1. 5 V Pull-Down Current IOL1 9 13 27 mA Vout = 0.4 V Pull-Down Current IOL2 26 39 79 mA Vout = 1.5 V Typ Max Units PCI, 3V66 and DOT Conditions USB and REF Max Units Conditions Buffer Characteristics for SDRAM Characteristic Symbol Min Pull-Up Current IOH1 -30 -40 -60 mA Vout =VDD - 1. 0 V Pull-Up Current IOH2 -68 -110 -188 mA Vout = 1. 4 V Pull-Down Current IOL1 23 34 53 mA Vout = 0.4 V Pull-Down Current IOL1 64 98 159 mA Vout = 1.5 V Cypress Semiconductor Corporation 525 Los Coches St. Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571 http://www.cypress.com Conditions Document#: 38-07054 Rev. ** 05/03/2001 Page 14 of 19 APPROVED PRODUCT C9815 Low EMI Clock Generator for Intel 133MHz/2DIMM Chipset Systems Test and Measurement Condition Output under Test Probe Load Cap 3.3V signals 2.5V signals tDC tDC - - - - 3.3V 2.5V 2.4V 2.0V 1.5V 1.25V 0.4V 0.4V 0V 0V Tr Fig.9A Tf Cypress Semiconductor Corporation 525 Los Coches St. Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571 http://www.cypress.com Tr Fig.9B Document#: 38-07054 Rev. ** Tf 05/03/2001 Page 15 of 19 APPROVED PRODUCT C9815 Low EMI Clock Generator for Intel 133MHz/2DIMM Chipset Systems Suggested Oscillator Crystal Parameters Characteristic Symbol Min Typ Max Units Frequency Fo 12.00 14.31818 16.00 MHz Tolerance TC - - +/-100 PPM Note 1 TS - - +/- 100 PPM Stability (TA -10 to +60C) Note 1 TA - - 5 PPM Aging (first year @ 25C) Note 1 - - - - CXTAL - 20 - Operating Mode Load Capacitance Conditions Parallel Resonant, Note 1 pF The crystal’s rated load. Note 1 Effective Series RESR 40 Ohms Note 2 Resistance (ESR) Note1: For best performance and accurate frequencies from this device, It is recommended but not mandatory that the chosen crystal meets or exceeds these specifications Note 2: Larger values may cause this device to exhibit oscillator startup problems To obtain the maximum accuracy, the total circuit loading capacitance should be equal to CXTAL. This loading capacitance is the effective capacitance across the crystal pins and includes the clock generating device pin capacitance (CFTG), any circuit traces (CPCB), and any onboard discrete load capacitors (CDISC). The following formula and schematic may be used to understand and calculate either the loading specification of a crystal for a design or the additional discrete load capacitance that must be used to provide the correct load to a known load rated crystal. CL = (CXINPCB + CXINFTG + CXINDISC) X (CXOUTPCB + CXOUTFTG + CXOUTDISC) (CXINPCB + CXINFTG + CXINDISC) + (CXOUTPCB + CXOUTFTG + COUTDISC) Where: CXTAL CXOUTFTG CXOUTFTG CXINPCB CXOUTPCB CXINDISC CXOUTDISC = = = = = = = the load rating of the crystal the clock generators XIN pin effective device internal capacitance to ground the clock generators XOUT pin effective device internal capacitance to ground the effective capacitance to ground of the crystal to device PCB trace the effective capacitance to ground of the crystal to device PCB trace any discrete capacitance that is placed between the XIN pin and ground any discrete capacitance that is placed between the XOUT pin and ground CXINPCB CXINDISC CXOUTPCB CXOUTDISC XIN CXINFTG XOUT CXOUTFTG Clock Generator Cypress Semiconductor Corporation 525 Los Coches St. Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571 http://www.cypress.com Document#: 38-07054 Rev. ** 05/03/2001 Page 16 of 19 APPROVED PRODUCT C9815 Low EMI Clock Generator for Intel 133MHz/2DIMM Chipset Systems Suggested Oscillator Crystal Parameters (Cont.) As an example, and using this formula for this datasheet’s device, a design that has no discrete loading capacitors (CDISC) and each of the crystal to device PCB traces has a capacitance (CPCB) to ground of 4pF (typical value) would calculate as: CL = (4pF + 36pF + 0pF) X (4pF + 36pF + 0pF) (4pF + 36pF + 0pF) + (4pF + 36pF + 0pF) = 40 X 40 40 + 40 = 1600 80 = 20pF Therefore to obtain output frequencies that are as close to this data sheets specified values as possible, in this design example, you should specify a parallel cut crystal that is designed to work into a load of 20pF. Package Drawing and Dimensions 56 Pin SSOP Outline Dimensions INCHES SYMBOL C MIN MILLIMETERS NOM MAX MIN NOM MAX A 0.095 0.102 0.110 2.41 2.59 2.79 A1 0.008 0.012 0.016 0.203 0.305 0.406 A2 0.088 - 0.092 2.24 - 2.34 B 0.008 - 0.0135 0.203 - 0.343 C 0.005 - 0.010 0.127 - 0.254 D 0.720 0.725 0.730 18.29 18.42 18.54 E 0.291 0.295 0.299 7.39 7.49 7.60 L H E D a A2 A A1 B e Cypress Semiconductor Corporation 525 Los Coches St. Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571 http://www.cypress.com e 0.025 BSC 0.635 BSC H 0.395 - 0.420 10.03 - 10.67 L 0.020 - 0.040 0.508 - 1.016 a 0º - 0º - 8º Document#: 38-07054 Rev. ** 8º 05/03/2001 Page 17 of 19 APPROVED PRODUCT C9815 Low EMI Clock Generator for Intel 133MHz/2DIMM Chipset Systems Ordering Information Part Number Package Type Production Flow C9815DY 56 PIN SSOP Commercial, 0 to 85ºC Marking: Example: Cypress C9815DY Date Code, Lot # C9815DY Package Y = SSOP Revision Device Number Notice Cypress Semiconductor Corporation reserves the right to make changes to its products in order to improve design, performance or reliability. Cypress Semiconductor Corporation assumes no responsibility for the use of its products in life supporting and medical applications where the failure or malfunction of the product could cause failure of the life supporting and medical systems. Products are not authorized for use in such applications unless a written approval is requested by the manufacturer and an approval is given in writing by Cypress Semiconductor Corporation for the use of its products in the life supporting and medical applications. Cypress Semiconductor Corporation 525 Los Coches St. Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571 http://www.cypress.com Document#: 38-07054 Rev. ** 05/03/2001 Page 18 of 19 APPROVED PRODUCT C9815 Low EMI Clock Generator for Intel 133MHz/2DIMM Chipset Systems Document Title: C9815 Low EMI Clock Generator for Intel® 133 MHz/2DIMM Chipset Systems Document Number: 38-07054 Rev. ECN No. ** 107062 Issue Date 06/11/01 Orig. of Change IKA Cypress Semiconductor Corporation 525 Los Coches St. Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571 http://www.cypress.com Description of Change Convert from IMI to Cypress Document#: 38-07054 Rev. ** 05/03/2001 Page 19 of 19