APPROVED PRODUCT C9801 Low EMI Clock Generator for Pentiumä ä II CPU Systems with Power Management Product Features Frequency Table • • • • • • • • SEL133/100# CPU PCI 0 100* 33.3* REF OSC 1 56 VDDI 2 55 IOAPIC2 REF1 3 54 IOAPIC1 VDD 4 53 IOAPIC0 XIN 5 52 VSS XOUT 6 51 VDDC VSS 7 50 CPU_0/2 PCI_F 8 49 CPU_1/2 PCI1 9 48 VSS VDDP 10 47 VDDC PCI2 11 46 CPU3 REF[0:1] PCI3 12 45 CPU2 VSS 13 IOAPIC[0:2] PCI4 14 VDDI VDDC CPU[0:3] SEL[0:1] SEL133/100# CPU_(0:1)/2 PLL1 VDDP PD# PCI [1:7], F CS# VDDA PS# 3V66 [0:3] VDDF PLL2 Pin Configuration VSS VDDF Xout 33.3* REF0 Block Diagram Xin 1 133* *See complete table on page 3. 48M Cypress Semiconductor Corporation 525 Los Coches St. Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571 http://www.cypress.com C9801 • • • • • • • Supports Intel Pentiumä II CPU designs. 133 and 100 Mhz CPU clock support Designed to meet Intel chipset specification 4 CPU clocks with isolated power supply 2 CPU/2 clock with isolated power supply 8 PCI clocks with isolated power supply 3 IOAPIC clocks with isolated power supply One 48 MHz fixed clock for USB/Super IO with isolated power supply 4 3V66 clocks with isolated power supply 2 reference clocks with isolated power supply <175 pS Max. skew among CPU clocks <500 pS Max. skew among PCI clocks Power management control of CPU and PCI clocks 56-pin SSOP package Spread Spectrum EMI reduction mode 44 VSS 43 VDDC PCI5 15 42 CPU1 VDDP 16 41 CPU0 PCI6 17 40 VSS PCI7 18 39 VDD VSS 19 38 VSS VSS 20 37 PS# 3V66_0 21 36 CS# 3V66_1 22 35 PD# VDDA 23 34 SS# VSS 3V66_2 24 25 33 3V66_3 VDDA 26 27 32 31 30 SEL1 SEL0 VDDF SEL133/100# 28 29 Document#: 38-07049 Rev. ** 48M VSS 05/03/2001 Page 1 of 11 APPROVED PRODUCT C9801 Low EMI Clock Generator for Pentiumä ä II CPU Systems with Power Management Pin Description PIN No. 5 Pin Name Xin PWR VDD I/O I TYPE OSC1 6 Xout VDD O OSC1 41,42, 45,46 49, 50 8 CPU(0:3) VDDC 0 BUF1 CPU/2 [0,1] PCI_F VDDC VDDP O O BUF4 BUF4 PCI (1:7) VDDP O BUF4 VSS - P - Ground pins for the device. VDDP VDDF VDDI VDDC VDD VDDA 3V66 (0:3) - P P P P - VDDA P O BUF VDDR VDDF - O O I BUF# BUF3 PAD 3.3 Volt power supply pins for PCI and PCI_F clock output buffers. 3.3 Volt power supply pins for 48 MHz clock output buffers. 2.5 Volt power supply pins for IOAPIC clock buffers. 3.3 or 2.5 Volt power supply pins for CPU clock output buffers. Power supply pins for analog circuits and core logic. 3.3 Volt power supply pins for 3V66 clock output buffers. Fixed 66.6 Mhz Advanced Graphics Processor Clock. This clock is rising edgy synchronous with the CPU clock. Buffered outputs of on-chip reference oscillator. Fixed 48 MHz frequency clock output. CPU frequency select pin. By design this input does not contain any internal pull-up or pulldown resistor. Device power down signal. Removes power from all internal logic when at a logic low level. See page 4. PCI clock stop signal. Stops all PCI clocks when at a logic low level, except for the PCI_F clock. See page 4. CPU clock stop signal. Stop all CPU clocks when at a logic low level. See page 4. Function selector pins. See description on page 3. 9, 11, 12, 14, 15, 17, 18 1, 7,13, 19,20, 24,29, 38, 40, 44, 48,52 10, 16 31 56 43, 47 4, 39 23, 27 21, 22, 25, 26 2,3 30 28 35 REF (0:1) 48M SEL133/ 100# PD# 37 PS# PU 36 CS# PU 32, 33 SEL (0:1) - I 34 SS# - I 53,54, 55 IOAPIC(0:2) VDDI 0 PU PAD PU PAD PU PAD Cypress Semiconductor Corporation 525 Los Coches St. Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571 http://www.cypress.com Description On-chip reference oscillator input pin. Requires either an external parallel resonant crystal (nominally 14.318 MHz) or externally generated reference signal On-chip reference oscillator output pin. Drives an external parallel resonant crystal when an externally generated reference signal is used, is left unconnected Clock outputs. CPU frequency table specified on page 1. CPU Synchronous clocks. Its frequency is half CPU clocks. Free running PCI clock. Does not stop when PS# is brought to a logic 0 (low) level. PCI bus clocks. See frequency select table on page 1. When driven to a logic low level, this pin enables the device’s EMI reducing Spread Spectrum mode (affects only CPU, PCI, 3V66, and IOAPIC clocks). 2.5 volt copies of a 16.67 Mhz clock that is synchronized with the CPU clock. See note on page 3 Document#: 38-07049 Rev. ** 05/03/2001 Page 2 of 11 APPROVED PRODUCT C9801 Low EMI Clock Generator for Pentiumä ä II CPU Systems with Power Management SEL 133/100# SEL1 SEL0 CPU CPU/2 3V66 PCI 48M REF IOAPIC 0 0 0 High-Z High-Z High-Z High-Z High-Z High-Z High-Z 0 0 1 105 MHz 52.5 MHz 70.0 MHz 35.0 MHz 48 MHz 14.5 MHz 17.50 MHz 0 1 0 100 MHz* 50 MHz* 66.6 MHz* 33.3 MHz* High-Z 14.3 MHz 16.67MHz* 0 1 1 100 MHz* 50 MHz* 66.6 MHz* 33.3 MHz* 48 MHz 14.3 MHz 16.67MHz* 1 0 0 REF/2 REF/4 REF/4 REF/8 REF/2 REF REF/16 1 0 1 139.7 MHz 69.8 MHz 69.8 MHz 34.9 MHz 48 MHz 14.3 MHz 17.40 MHz 1 1 0 133 MHz 66.6 MHz 66.6 MHz 33.3 MHz High-Z 14.3 MHz 16.67MHz 1 1 1 133 MHz 66.6 MHz 66.6 MHz 33.3 MHz 48 MHz 14.3 MHz 16.67MHz IOAPIC Clock Synchronization This device incorporates IOAPIC clock synchronization. With this feature, the IOAPIC clocks are derived from the CPU clock and represent a divided by 8 (133 MHz CPU clock mode) or divided by 6 (100 MHz CPU clock mode) clock. The IOAPIC clock lags the CPU clock by the specified 1.5 to 4.0 nSEC. Power Management Functions All PCI (excluding PCI_F) and CPU clocks can be enabled or stopped via the PSTOP and CSTOP input pins. All clocks are stopped in the low state. All clocks maintain a valid high period on transitions from running to stopped and on transitions from stopped to running when the chip was not powered down. On power up, (after bring PD from a low to high state) the VCOs will stabilize to the correct pulse widths within about 0.2 mS. The CPU, and PCI clocks transition between running and stopped by waiting for one positive edge on PCI_F followed by a negative edge on the clock of interest, after which high levels of the output are either enabled or disabled. CS# PS# PD# CPU CPU/2 3V66 PCI PCIF IOAPIC 48M REF XTAL & VCOs X X 0 LOW LOW LOW LOW LOW LOW LOW LOW OFF 0 0 1 LOW ON LOW LOW ON ON ON ON ON 0 1 1 LOW ON LOW ON ON ON ON ON ON 1 0 1 ON ON ON LOW ON ON ON ON ON 1 1 1 ON ON ON ON ON ON ON ON ON Cypress Semiconductor Corporation 525 Los Coches St. Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571 http://www.cypress.com Document#: 38-07049 Rev. ** 05/03/2001 Page 3 of 11 APPROVED PRODUCT C9801 Low EMI Clock Generator for Pentiumä ä II CPU Systems with Power Management Power Management Functions (Cont.) CPU, 3V66, and CPU/2 Clock Phase Alignment CPU (0:3) 3V66(0:3) CPU/2 (0,1) Power Management Timing PCICLK_F PS# PCICLK(1:7) CS# CPUCLK(0:3) Cypress Semiconductor Corporation 525 Los Coches St. Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571 http://www.cypress.com Document#: 38-07049 Rev. ** 05/03/2001 Page 4 of 11 APPROVED PRODUCT C9801 Low EMI Clock Generator for Pentiumä ä II CPU Systems with Power Management Power Management Timing Signal CS# PS# PD# Latency No. of rising edges of free running PCICLK (PCIF) Signal State 0 (disabled) 1 1 (enabled) 1 0 (disabled) 1 1 (enabled) 1 1 (normal operation) 3 mS 0 (power down) 2 mS max. Notes: 1. Clock on/off latency is defined in the number of rising edges of free running PCICLKs between the clock disable goes low/high to the first valid clock comes out of the device. 2. Power up latency is when PD# goes inactive (high) to when the first valid clocks are driven from the device. Power Management Timing PD# CPU, PCI, 3V66, PCI_F, CPU/2, Ref, IOAPIC Cypress Semiconductor Corporation 525 Los Coches St. Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571 http://www.cypress.com Document#: 38-07049 Rev. ** 05/03/2001 Page 5 of 11 APPROVED PRODUCT C9801 Low EMI Clock Generator for Pentiumä ä II CPU Systems with Power Management Spectrum Spread Clocking Spectrum Analysis Spectrum Spreading Selection Table Min(MHz) Center(MHz) Max(MHz) CPU Frequency % OF Frequency Spreading Mode 99.5 99.75 100 100 0.5% (-0.5%% + 0%) Down Spread 126.4 129.7 133 133.3 0.5% (-0.5% + 0%) Down Spread Maximum Ratings Voltage Relative to VSS: -0.3V Voltage Relative to VDD: Storage Temperature: Operating Temperature: 0.3V -65ºC to + 150ºC 0ºC to +70ºC Maximum Power Supply: 5V This device contains circuitry to protect the inputs against damage due to high static voltages or electric field; however, precautions should be taken to avoid application of any voltage higher than the maximum rated voltages to this circuit. For proper operation, Vin and Vout should be constrained to the range: VSS<(Vin or Vout)<VDD DC Parameters Characteristic Symbol Min Typ Max Units Conditions Input Low Voltage VIL2 0.8 Vdc SDATA, SCLK Input High Voltage VIH2 2.0 Vdc SDATA, SCLK Input Low Current (@VIL = VSS) IIL -66 -5 µA Pull up Input High Current (@VIL = VDD) IIH 5 µA Pull up Tri-State leakage Current Ioz 10 µA Dynamic Supply Current Iddmax 175 mA Note 1 Static Supply Current Isdd 0.3 mA PD# pin at logic low level VDD = VDDS = 3.3V ±5%, VDDC = 2.5 + 5%, TA = 0ºC to +70ºC Note1: CPU frequency = 133 MHz, all outputs loaded to datasheet maximum capacitive loading values and Vdd = 3.465V Cypress Semiconductor Corporation 525 Los Coches St. Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571 http://www.cypress.com Document#: 38-07049 Rev. ** 05/03/2001 Page 6 of 11 APPROVED PRODUCT C9801 Low EMI Clock Generator for Pentiumä ä II CPU Systems with Power Management AC Parameters Characteristic Symbol Min Typ Max Units Conditions 50 55 % Measured at 1.5V for 3.3 Volt VDD clocks and 1.25V for 2.5V VDD clocks Output Duty Cycle - 45 CPU to CPU Skew tSKEW cc 0 - 175 pS CPU load = 20 pF, measured at 1.25V CPU/2 to CPU/2 Skew tSKEW cc2 0 - 175 pS CPU/2 load 20 pF, measured at 1.25V tSKEW II 0 - 250 pS IOAPIC load = 20 pF, measured at 1.25V 3V66 to 3V66 Skew tSKEW AA 0 - 250 pS 3V66 load = 30 pF, measured at 1.5V PCI to PCI Skew tSKEW PP 0 - 500 pS PCI load = 30 pF measured at 1.5V SKEW PERFORMANCE IOAPIC to IOAPIC Skew CLOCK OFFSETS CPU to 3V66 Offset tOFFCA 0 - 1.5 nS CPU load = 20 pF, 3V66 load = 30 pF measured at 1.25V, 3V66 = 1.5V (CPU leads) 3V66 to PCI Offset tOFFCP 1.5 - 4.0 nS 3V66 load = 30 pF, PCI load = 30 pF measured at 1.5V CPU to IOAPIC Offset tOFFCL 1.5 - 4.0 nS CPU load = 20 pF, IOAPIC load = 20 pF measured at 1.25V (CPU leads) JITTER PERFORMANCE ∆Period Adjacent Cycles CPU, CPU/2 and IOAPIC ∆P - - +250 pS Measured at 1.25 volts, 20 pF load ∆Period Adjacent Cycles 48M, 3V66, PCI and REF ∆P - - + 500 pS Measured at 1.50 volts, 3V66 at 30 pF load, all others at 20 pF load VDD = VDDP = VDDF =VDDR =3.3V ±5%, VDDC, & VDDI = 2.5V ±5%, TA = 0°°C to +70°°C Buffer Characteristics for IOAPIC (0:2), and CPU/2 (0,1) Characteristic Symbol Min Typ Max Units Conditions Pull-Up Current Min IOHmin -27 - - mA Vout = VDD/2 Pull-Up Current Max IOHmax - - -13.6 mA Vout = VDD – 0.5V Pull-Down Current Min IOLmin 27.7 - - mA Vout = VDD/2 Pull-Down Current Max IOLmax - - 11.8 mA Vout = 0.4 V Rise Time Min Between 0.4 V and 2.0 V TRmin 0.4 - 1.6 nS 20 pF Load Fall Time Max Between 0.4 V and 2.0 V TRFmax 0.4 - 1.6 nS 20 pF Load Dynamic Output Impedance ZO - Ohms VDD = VDDP = VDDF =VDDR =3.3V ±5%, VDDC, & VDDI =2.5V ±5%, TA = 0°°C to +70°°C Cypress Semiconductor Corporation 525 Los Coches St. Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571 http://www.cypress.com Document#: 38-07049 Rev. ** 05/03/2001 Page 7 of 11 APPROVED PRODUCT C9801 Low EMI Clock Generator for Pentiumä ä II CPU Systems with Power Management Buffer Characteristics for CPU(0:3) Characteristic Symbol Min Typ Max Units Conditions Pull-Up Current Min IOHmin -32.2 - - mA Vout = VDD/2V Pull-Up Current Max IOHmax - - -15.8 mA Vout = VDD – 0.5V Pull-Down Current Min IOLmin 35.3 - - mA Vout = VDD/2 Pull-Down Current Max IOLmax - - 14.4 mA Vout = 0.4 V Rise Time Min Between 0.4 V and 2.0 V TRmin 0.4 - 1.6 nS 20 pF Load Fall Time Max Between 0.4 V and 2.0 V TRFmax 0.4 - 1.6 nS 20 pF Load Dynamic Output Impedance ZO - Ohms VDD = VDDP = VDDF =VDDR =3.3V ±5%, VDDC, & VDDI =2.5V ±5%, TA = 0°°C to +70°°C Buffer Characteristics for REF(1:3) and 48(1:2) MHz Characteristic Symbol Min Typ Max Units Conditions Pull-Up Current Min IOHmin -17.7 - - mA Vout = VDD/2V Pull-Up Current Max IOHmax - - -6.1 mA Vout = VDD – 0.5V Pull-Down Current Min IOLmin 21.3 - - mA Vout = VDD/2V Pull-Down Current Max IOLmax - - 5.9 mA Vout = 0.4 V Rise Time Min Between 0.4 V and 2.4 V TRmin 1.0 - 4.0 nS 20 pF Load Fall Time Max Between 0.4 V and 2.4 V TFmax 1.0 - 4.0 nS 20 pF Load Dynamic Output Impedance ZO - Ohms VDD = VDDP = VDDF =VDDR =3.3V ±5%, VDDC, & VDDI =2.5V ±5%,, TA = 0°°C to +70°°C Buffer Characteristics for PCICLK(0:7), 3V66 (0,7) Characteristic Symbol Min Typ Max Units Conditions Pull-Up Current Min IOHmin -41.6 - - mA Vout = VDD/2V Pull-Up Current Max IOHmax - - -15.5 mA Vout = VDD – 0.5V Pull-Down Current Min IOLmin 44.1 - - mA Vout = VDD/2V Pull-Down Current Max IOLmax - - 13.7 mA Vout = 0.4 V Rise Time Min Between 0.4 V and 2.4 V TRmin 0.5 - 2.0 nS 30 pF Load Fall Time Max Between 0.4 V and 2.4 V TFmax 0.5 - 2.0 nS 30 pF Load Dynamic Output Impedance ZO - Ohms VDD = VDDP = VDDF =VDDR =3.3V ±5%, VDDC, & VDDI =2.5V ±5%,, TA = 0ºC to +70ºC Cypress Semiconductor Corporation 525 Los Coches St. Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571 http://www.cypress.com Document#: 38-07049 Rev. ** 05/03/2001 Page 8 of 11 APPROVED PRODUCT C9801 Low EMI Clock Generator for Pentiumä ä II CPU Systems with Power Management Crystal and Reference Oscillator Parameters Characteristic Symbol Min Typ Max Units Frequency Fo 12.00 14.31818 16.00 MHz Tolerance TC - - +/-100 PPM Calibration note 1 TS - - +/- 100 PPM Stability (Ta -10 to +60C) Note 1 PPM TA - - 5 Mode OM - - - DC Bias Voltage VBIAS 0.3Vdd Vdd/2 0.7Vdd V Startup time Ts - - 30 µS Load Capacitance CL - 20 - pF Effective Series resonant resistance R1 - - 40 Ohms Power Dissipation DL - - 0.10 mW X1 and X2 Load CL 36 Conditions Aging (first year @ 25C) Note 1 Parallel Resonant pF Note 1 Note 1 Internal crystal loading capacitors on each pin (to ground). Provided by C9801. For maximum accuracy, the total circuit loading capacitance should be equal to CL. This loading capacitance is the effective capacitance across the crystal pins and includes the device pin capacitance (CP) in parallel with any circuit traces, the clock generator and any onboard discrete load capacitors. Typical trace capacitance, (< half inch) is 4 pF, Load to the crystal is therefore 2.0 pF Clock generator internal pin capacitance of 36 pF, Load to the crystal is therefore 18.0 pF the total parasitic capacitance would therefore be = 20.0 pF.(matching CL) Note 1: It is recommended but not mandatory that a crystal meets these specifications. Cypress Semiconductor Corporation 525 Los Coches St. Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571 http://www.cypress.com Document#: 38-07049 Rev. ** 05/03/2001 Page 9 of 11 APPROVED PRODUCT C9801 Low EMI Clock Generator for Pentiumä ä II CPU Systems with Power Management Package Drawing and Dimensions 56 Pin SSOP Outline Dimensions INCHES C SYMBOL L H E NOM MAX MIN NOM MAX A 0.095 0.102 0.110 2.41 2.59 2.79 A1 0.008 0.012 0.016 0.203 0.305 0.406 A2 0.088 - 0.092 2.24 - 2.34 B 0.008 - 0.0135 0.203 - 0.343 C 0.005 - 0.010 0.127 - 0.254 D 0.720 0.725 0.730 18.29 18.42 18.54 E 0.291 0.295 0.299 7.39 7.49 7.60 a D A2 A e A1 B MIN MILLIMETERS e 0.025 BSC 0.635 BSC H 0.395 - 0.420 10.03 - 10.67 L 0.020 - 0.040 0.508 - 1.016 a 0º - 0º - 8º 8º Ordering Information Part Number Package Type C9801CY 56 Pin SSOP Note: Production Flow Commercial, 0ºC to +70ºC The ordering part number is formed by a combination of device number, device revision, package style, and screening as shown below. Marking: Example: Cypress C9801CY Date Code, Lot # C9801CY Package Y = SSOP Revision Device Number Notice Cypress Semiconductor Corp. reserves the right to make changes to its products in order to improve design, performance or reliability. Cypress Semiconductor Corp. assumes no responsibility for the use of its products in life supporting and medical applications where the failure or malfunction of the product could cause failure of the life supporting and medical systems. Products are not authorized for use in such applications unless a written approval is requested by the manufacturer and an approval is given in writing by Cypress Semiconductor Corp. for the use of its products in the life supporting and medical applications. Cypress Semiconductor Corporation 525 Los Coches St. Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571 http://www.cypress.com Document#: 38-07049 Rev. ** 05/03/2001 Page 10 of 11 APPROVED PRODUCT C9801 Low EMI Clock Generator for Pentiumä ä II CPU Systems with Power Management Document Title: C9801 Low EMI Clock Generator for Pentium™II CPU Systems with Power Management Document Number: 38-07049 Rev. ** ECN No. 107057 Issue Date 06/12/01 Orig. of Change IKA Cypress Semiconductor Corporation 525 Los Coches St. Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571 http://www.cypress.com Description of Change Convert from IMI to Cypress Document#: 38-07049 Rev. ** 05/03/2001 Page 11 of 11