CYPRESS C9812

APPROVED PRODUCT
C9812
Low EMI Clock Generator for Intel 810E Chipset Systems
Product Features
Frequency Table (MHz)
•
•
•
•
•
•
•
•
•
•
•
•
SEL2
Intel’s 810E clock solution
3 copies of CPU Clock (CPU[0:1] and CPU_ITP)
9 copies of SDRAM Clock (SDRAM[0:7] and DCLK)
8 copies of PCI Clock
2 copies of 3V66 Clock
2 copies of APIC Clock, synchronous to PCI Clock
1 REF Clock
1 USB Clock (Non SSC)
1 DOT Clock (Non SSC)
Power Down Feature
Spread Spectrum Support
SMBUS Support for turning off unused clocks
SDRAM
PCI
Tristate
Tristate
Tristate
0
0
X
0
1
0
1
0
66.6
100
33.3
0
1
1
100
100
33.3
1
1
X
133.3
100
33.3
Test mode (see table2)
Table 1
Note: The following clocks remain fixed frequencies
except in Test Mode.
3V66=66.6MHz, USB/DOT=48MHz, REF=14.318MHz
and IOAPIC=33.3MHz.
SEL2/REF
VDD
XIN
XOUT
VSS
VSS
36pF
300K
36pF
XOUT
VDD
REF / SE L2
1
VDDI
s2
ioapic
IOAP IC(0:1)
2
Rin
VDDC
i2c-clk
i2c-data
cpu
3
sdram
9
CPU(0:2)
VDDS
VDD
SEL1
s1
SEL0
s0
SDRA M(0:7), DC LK
VDD
PD#
CPU
X
XIN
VDD
SEL0
Pin Configuration
Block Diagram
SCLK
SDATA
SEL1
66m
3V66(0:1)
2
pwr_dwn#
VDD
pci
PCI(0:7)
8
PLL1
VDD
Rin
48
DOT
1
VDD
3V660
3V661
VDD
VDD
PCI0_ICH
PCI1
PCI2
VSS
PCI3
PCI4
VSS
PCI5
PCI6
PCI7
VDD
VDDA
VSSA
VSS
USB
DOT
VDD
SEL0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
C
9
8
1
2
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
VSS
IOAPIC0
IOAPIC1
VDDI
CPU0
VDDC
CPU1
CPU2_ITP
VSS
VSS
SDRAM0
SDRAM1
VDDS
SDRAM2
SDRAM3
VSS
SDRAM4
SDRAM5
VDDS
SDRAM6
SDRAM7
VSS
DCLK
VDD
PD#
SCLK
SDATA
SEL1
PD#
1
USB
i2c-clk
i2c-data
PLL2
Fig.1
Cypress Semiconductor Corporation
525 Los Coches St.
Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571
http://www.cypress.com
Document#: 38-07053 Rev. **
05/03/01
Page 1 of 18
APPROVED PRODUCT
C9812
Low EMI Clock Generator for Intel 810E Chipset Systems
Pin Description
PIN No.
Pin Name
SEL2/REF
PWR
VDD
I/O
I/O
TYPE
3
4
11, 12, 13,
15, 16, 18,
19, 20
7, 8
25
26
28, 29
XIN
XOUT
PCI0/ICH
PCI(1..7)
VDD
VDD
VDD
I
O
O
OSC1
3V66(0,1)
USB
DOT
SEL(0,1)
VDD
VDD
VDD
VDD
O
O
O
I
30
31
32
SDATA
SCLK
PD#
VDD
VDD
VDD
I
I
I
34
36, 37, 39,
40, 42, 43,
45, 46
49, 50, 52
DCLK
SDRAM(7..0)
VDD
VDDS
O
O
CPU(2)_ITP,
CPU(1,0)
IOAPIC(1,0)
VDDC
O
VDDI
O
1
54, 55
2, 9, 10, 21,
27, 33
22
23
51, 53
5, 6,14, 17,
24, 35, 41,
47, 48, 56
38, 44
Description
3.3V 14.318 MHz clock output.
This pin also serves as the select strap (associates with SEL0 &
1, see app. note page 5) for clock frequencies during power up.
Refer to Table 1 for detail. This pin has an internal pull-down
(Typ. 70KΩ).
14.318MHz Crystal input
14.318MHz Crystal output
3.3V PCI clock outputs
3.3V Fixed 66.6 MHz clock outputs
3.3V Fixed 48 MHz clock outputs
3.3V Fixed 48 MHz clock outputs
3.3V LVTTL compatible inputs for logic selection. Has an
internal pull-up (Typ. 250KΩ)
I²C compatible SDATA input. Has an internal pull-up (>100KΩ)
I²C compatible SCLK input. Has an internal pull-up (>100KΩ)
3.3V LVTTL compatible input. Device enters powerdown mode
When held LOW. Has an internal pull-up (>100KΩ)
3.3V output running 100MHz
3.3V output running 100MHz. All SDRAM outputs can be turned
off through SMBUS.
VDD
-
2.5V Host bus clock outputs. 66, 100 or 133MHz depending on
state of SEL(2..0)
2.5V clock outputs running rising edge synchronous with the
PCI clock.
3.3V Power Supply
VDDA
VSSA
VDDC, VDDI
VSS
-
-
Analog circuitry 3.3V Power Supply
Analog circuitry power supply Ground pins.
2.5V Power Supply’s
Common Ground pins.
VDDS
-
-
3.3V power support for SDRAM clock output drivers.
A bypass capacitor (0.1µF) should be placed as close as possible to each positive power pin. If these bypass capacitors
are not close to the pins their high frequency filtering characteristic will be cancelled by the lead inductance of the traces.
Cypress Semiconductor Corporation
525 Los Coches St.
Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571
http://www.cypress.com
Document#: 38-07053 Rev. **
05/03/01
Page 2 of 18
APPROVED PRODUCT
C9812
Low EMI Clock Generator for Intel 810E Chipset Systems
Test Mode Function
Test Mode Functionality
SEL2 SEL1
SEL0
x
0
1
CPU
TCLK/2
SDRAM
TCLK/2
3V66
TCLK/3
PCI
TCLK/6
48 MHz
TCLK/2
REF
TCLK
IOAPIC
TCLK/6
Table 2
Note: TCLK is a test clock over driven on the XIN input during test mode.
Power Management Functions
Power Management on this device is controlled by a single pin, PD# (pin32). When PD# is high (default) the device is in
running and all signals are active.
When PD# is asserted (forced) low, the device is in shutdown (or in power down) mode and all power supplies (3.3V and
2.5V except for VDDA/pin 27) may be removed. When in power down, all outputs are synchronously stopped in a low
state (see Fig.2 below), all PLL’s are shut off, and the crystal oscillator is disabled. When the device is shutdown the I²C
function is also disabled.
Power Management Timing
0nS
10nS
20nS
30nS
40nS
50nS
CPU 100MHz
3V66
66MHz
PCI
33MHz
IOAPIC
33MHz
PWRDN#
Undefined
SDRAM 100MHz
CLOCK
REF 14.3MHz
USB
Undefined
Undefined
48MHz
Fig.2
Power Management Current
PD#, SEL[2..0]
(CPU Clock)
0XXX (Power down)
Maximum 2.5 Volt Current
Consumption (VDD2.5 =2.625)
100 µA
Maximum 3.3 Volt Current Consumption
(VDD3.3 = 3.465 V)
200 µA
1010 (66MHz)
70 mA
280 mA
1011 (100MHz)
100 mA
280 mA
111X (133MHz)
133 mA
280 mA
Table 3
When exiting the power down mode, the designer must supply power to the VDD pins first, a minimum of 200mS before
releasing the PD# pin high.
Cypress Semiconductor Corporation
525 Los Coches St.
Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571
http://www.cypress.com
Document#: 38-07053 Rev. **
05/03/01
Page 3 of 18
APPROVED PRODUCT
C9812
Low EMI Clock Generator for Intel 810E Chipset Systems
Clock Synchronization and Phase Alignment
This device incorporates IOAPIC clock synchronization. With this feature, the IOAPIC clocks are derived from the CPU
clock. The IOAPIC clock lags the CPU clock by the specified 1.5 to 3.5 nSec. Figure 3 shows the relationship between
the CPU and IOAPIC clocks.
Device Clock Phase Relationships
0nS
CPU CLOCK
10nS
20nS
30nS
40nS
66MHz
2.5nS
CPU CLOCK 100MHz
CPU CLOCK 133MHz
5nS
7.5nS
Sync
5nS
SDRAM CLOCK 100MHz
3V66 CLOCK 66MHz
PCI CLOCK 33MHz1.5~3.5nS
IOAPIC CLOCK 33MHz
Fig.3
Cypress Semiconductor Corporation
525 Los Coches St.
Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571
http://www.cypress.com
Document#: 38-07053 Rev. **
05/03/01
Page 4 of 18
APPROVED PRODUCT
C9812
Low EMI Clock Generator for Intel 810E Chipset Systems
Power on Bi-Directional Pins
Power Up Condition:
Pin1 is a Power up bi-directional pin and is used for selecting the host frequency in page 1, table 1. During power-up of
the device, this pin is in input mode (see Fig 4, below), therefore; it is considered an input select pins internal to the IC.
After a settling time, the selection data is latch into the internal control register and this pin becomes a clock output.
VDD RAIL
POWER SUPPLY
RAMP
REF / SEL2
(Pin 1)
-
Hi-Z INPUTS
TOGGLE OUTPUTS
SELECT DATA IS LATCHED INTO REGISTER THEN PIN BECOMES A REF CLOCK OUTPUT SIGNAL
Fig.4
Strapping Resistor Options:
The power up bi-directional pins have a large value pull-down each (70KΩ), therefore, a selection “0” is the default. If the
system uses a slow power supply (over 5mS settling time), then it is recommended to use an external Pull-down in
order to insure a low selection.
Fig. 5 If a selection “0” is desired, then a jumper is placed on JP1 to a 10KΩ resistor as implemented as shown in Fig.5.
Please note the selection resistor (Rdn) is placed before the Damping resistor (Rd) close to the pin.
Vdd
JP1
Jumper
3
IMI C9812
2
1
Rsel
10K
Rd
Load
Bidirectional
Fig. 5
70K
Cypress Semiconductor Corporation
525 Los Coches St.
Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571
http://www.cypress.com
Document#: 38-07053 Rev. **
05/03/01
Page 5 of 18
APPROVED PRODUCT
C9812
Low EMI Clock Generator for Intel 810E Chipset Systems
2-Wire SMBUS Control Interface
The 2-wire control interface implements a write slave only interface according to SMBus specification. (See Fig. 7 / P. 8).
The device can be read back by using standard SMBUS command bytes. Sub addressing is not supported, thus all
preceding bytes must be sent in order to change one of the control bytes. The 2-wire control interface allows each clock
output to be individually enabled or disabled. 100 Kbits/second (standard mode) data transfer is supported.
During normal data transfer, the SDATA signal only changes when the SDCLK signal is low, and is stable when SDCLK
is high. There are two exceptions to this. A high to low transition on SDATA while SDCLK is high is used to indicate the
start of a data transfer cycle. A low to high transition on SDATA while SDCLK is high indicates the end of a data transfer
cycle. Data is always sent as complete 8-bit bytes, after which an acknowledge is generated. The first byte of a transfer
cycle is an 8-bit address. W#=0 in write mode.
The device will respond to writes to 10 bytes (max) of data to address D2 by generating the acknowledge (low) signal on
the SDATA wire following reception of each byte. Data is transferred MSB first at a max rate of 100kbits/S. The device
will not respond to any other control interface conditions, and previously set control registers are retained.
SMBUS Test Circuitry
+ 5V
Device under Test
2.2 K
DATAIN
SDATA
+ 5V
SCLK
2.2 K
+ 5V
DATAOUT
2.2 K
CLOCK
Fig.6
Note: Buffer is 7407 with VCC @ 5.0 V
Cypress Semiconductor Corporation
525 Los Coches St.
Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571
http://www.cypress.com
Document#: 38-07053 Rev. **
05/03/01
Page 6 of 18
APPROVED PRODUCT
C9812
Low EMI Clock Generator for Intel 810E Chipset Systems
Serial Control Registers
NOTE: The Pin# column lists the affected pin number where applicable. The @Pup column gives the state at true
power up. Bytes are set to the values shown only on true power up.
Following the acknowledge of the Address Byte, two additional bytes must be sent:
1) “Command Code “ byte, and
2) “Byte Count” byte.
Although the data (bits) in these two bytes are considered “don’t care”; they must be sent and will be acknowledged.
After the Command Code and the Count bytes have been acknowledged, the below described sequence (Byte 0, Byte 1,
and Byte2) will be valid and acknowledged.
Byte 0: CPU Clock Register (1=Enable, 0=Disable, Default=07)
Bit
7
6
5
4
3
2
1
0
@Pup
0
0
0
0
0
1
1
1
Pin#
26
25
49
Description
Reserved
Reserved
Reserved
Reserved
Spread spectrum mode
DOT
USB
CPU2_ITP
Byte 2: PCI Clock Register (1=Enable, 0=Disable, Default=FE)
Bit
7
6
5
4
3
2
1
0
@Pup
1
1
1
1
1
1
1
0
Pin#
20
19
18
16
15
13
12
-
Description
PCI7
PCI6
PCI5
PCI4
PCI3
PCI2
PCI1
Reserved
Cypress Semiconductor Corporation
525 Los Coches St.
Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571
http://www.cypress.com
Byte 1: SDRAM Clock Register (1=Enable, 0=Disable, Default=FF)
Bit
7
6
5
4
3
2
1
0
@Pup
1
1
1
1
1
1
1
1
Pin#
36
37
39
40
42
43
45
46
Description
SDRAM7
SDRAM6
SDRAM5
SDRAM4
SDRAM3
SDRAM2
SDRAM1
SDRAM0
Byte 3: Reserved Register (Default=00)
Byte 4: Reserved Register (Default=00)
Byte 5: SSCG Control Register (Default=00)
Bit
7
6
5
4
3
2
1
0
@Pup
0
0
0
0
0
0
0
0
Pin#
-
Description
Spread Mode (0=down, 1=center)
Ref. Table 4
Ref. Table 4
Reserved
Reserved
Reserved
Reserved
Reserved
Document#: 38-07053 Rev. **
05/03/01
Page 7 of 18
APPROVED PRODUCT
C9812
Low EMI Clock Generator for Intel 810E Chipset Systems
ACK
SDATA IS OUTPUT PIN
SDATA IS INPUT PIN
1
1
0
1
0
0
1
ACK
COMMAND BYTE
(DON'TCARE)
0
SDATA
MSB
LSB
SCLK
8
START CONDITION
CONTINUED
ACK
ACK
COUNT BYTE
(DON'TCARE)
ACK
BYTE 0
(VALID DATA)
BYTE N (LAST
VALID DATA)
CONTINUED
8
8
8
STOP CONDITION
Figure 7
SMBUS Communications Waveforms
Test and Measurement Condition
Output under Test
Probe
Load Cap
3.3V signals
2.5V signals
tDC
tDC
-
-
-
-
3.3V
2.5V
2.4V
2.0V
1.5V
1.25V
0.4V
0.4V
0V
0V
Tr
Tr
Tf
Tf
Fig.8
Cypress Semiconductor Corporation
525 Los Coches St.
Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571
http://www.cypress.com
Document#: 38-07053 Rev. **
05/03/01
Page 8 of 18
APPROVED PRODUCT
C9812
Low EMI Clock Generator for Intel 810E Chipset Systems
Spread Spectrum Clock Generation (SSCG)
Spread Spectrum is a modulation technique applied here for maximum efficiency in minimizing Electro-Magnetic
Interference radiation generated from repetitive digital signals mainly clocks. A clock accumulates EM energy at the
center frequency it is generating. Spread Spectrum distributes this energy over a small frequency bandwidth therefore
spreading the same amount of energy over a spectrum. This technique is achieved by modulating the clock down from
(Fig.9A) or around the center (Fig.9B) of its resting frequency by a certain percentage (which also determines the
energy distribution bandwidth). In this device, Spread Spectrum is enabled by setting SMBUS byte0, bit3 = 1. The
default of the device at power up keeps the Spread Spectrum disabled, it is therefore, important to have SMBUS
accessibility to turn-on the Spread Spectrum function. Once the Spread Spectrum is enabled, the spread bandwidth
option is selected by SST(0:2) in SMBUS byte 5, bits 5, 6 & 7 following tables 4A, and 4B below.
In Down Spread mode the center frequency is shifted down from its rested (non-spread) value by ½ of the total spread
%. (eg.: assuming the center frequency is 100MHz in non-spread mode; when down spread of –0.5% is enabled, the
center frequency shifts to 99.75MHz.).
In Center Spread mode, the Center frequency remains the same as in the non-spread mode.
Down Spread
Center Spread
Fig.9A
Fig.9B
Spread Spectrum Selection Tables
I²C BYTE5
Bit[7:5]
100
101
110
111
Center Frequency
(MHz)
66/100/133.3
66/100/133.3
66/100/133.3
66/100/133.3
Spread
%
± 0.25
± 0.35
± 0.5
± 0.7
Table 4A
Cypress Semiconductor Corporation
525 Los Coches St.
Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571
http://www.cypress.com
I²C BYTE5
Bit[7:5]
000
001
010
011
Table 4B
Down Frequency
(MHz)
66/100/133.3
66/100/133.3
66/100/133.3
66/100/133.3
Document#: 38-07053 Rev. **
Spread
%
- 0.5
- 0.7
- 1.0
- 1.5
05/03/01
Page 9 of 18
APPROVED PRODUCT
C9812
Low EMI Clock Generator for Intel 810E Chipset Systems
Maximum Ratings
This device contains circuitry to protect the inputs
Maximum Input Voltage Relative to VSS: VSS - 0.3V
against damage due to high static voltages or electric
Maximum Input Voltage Relative to VDD: VDD + 0.3V
field; however, precautions should be taken to avoid
Storage Temperature:
application of any voltage higher than the maximum
-65ºC to + 150ºC
Operating Temperature:
rated voltages to this circuit. For proper operation, Vin
0ºC to +70ºC
Maximum ESD protection
2KV
Maximum Power Supply:
5.5V
and Vout should be constrained to the range:
VSS<(Vin or Vout)<VDD
Unused inputs must always be tied to an appropriate
logic voltage level (either VSS or VDD).
DC Parameters
Characteristic
Symbol
Min
Typ
Max
Units
Conditions
Note 1
Input Low Voltage
VIL1
-
-
1.0
Vdc
Input High Voltage
VIH1
2.0
-
-
Vdc
Input Low Voltage
VIL2
-
-
1.0
Vdc
Input High Voltage
VIH2
2.2
-
-
Vdc
Input Low Current (@VIL = VSS)
IIL
-66
-5
µA
Input High Current (@VIL =VDD)
IIH
5
µA
Note 2
For internal Pull up resistors,
Notes 1,3
Tri-State leakage Current
Ioz
-
-
10
µA
Dynamic Supply Current
Idd3.3V
-
-
280
mA
Sel2 = Sel1 = Sel0 = 1, Note 4
Dynamic Supply Current
Idd2.5V
-
-
100
mA
Sel2 = Sel1 = Sel0 = 1, Note 4
Static Supply Current
Isdd
-
-
300
µA
Sel2 = Sel1 = Sel0 = x, Note 4
Input pin capacitance
Cin
-
-
5
pF
Output pin capacitance
Cout
-
-
6
pF
Pin capacitance
Lpin
-
-
7
nH
Clock Stablization Time
tstab
3
-
-
mSec
Measured from VDD – 3.15 volts
Crystal pin capacitance
Cxtal
32
34
38
pF
Measured from Pin to Ground. Note 5
Crystal DC Bias Voltage
VBIAS
0.3Vdd
Vdd/2
0.7Vdd
V
Crystal Startup time
Txs
-
-
40
µS
From Stable 3.3V power supply.
VDD=VDDS = 3.3V ±5%, VDDC = VDDI = 2.5 ± 5%, TA = 0º to +70ºC
Note1:
Note2:
Note3:
Note4:
Note5:
Applicable to input signals: Sel(0:1), PD#
Applicable to Sdata, and Sclk.
Although internal pull-up resistors have a typical value of 250K, this value may vary between 200K and 500K. Internal Pull-down resisters
are typically 70K in value.
All outputs loaded as per table below.
Although the device will reliably interface with crystals of a 17pF – 20pF CL range, it is optimized to interface with a typical CL = 18pF
crystal specifications.
Clock Name
CPU, IOAPIC, REF, USB
PCI, SDRAM, 3V66(0,1)
DOT
Table 5.
Max Load (in pF)
20
30
15
Cypress Semiconductor Corporation
525 Los Coches St.
Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571
http://www.cypress.com
Document#: 38-07053 Rev. **
05/03/01
Page 10 of 18
APPROVED PRODUCT
C9812
Low EMI Clock Generator for Intel 810E Chipset Systems
AC Parameters
Symbol
Parameter
133 MHz Host
100 MHz Host
Min
Max
Min
Max
Units
Notes
TPeriod
CPU(0:1) period
7.5
8.0
10.0
10.5
nS
5, 6, 8
THIGH
CPU(0:1) high time
1.87
-
3.0
-
nS
6,10
TLOW
CPU(0:1) low time
1.67
-
2.8
-
nS
6, 11
Tr / Tf
CPU(0:1) rise and fall times
0.4
1.6
0.4
1.6
nS
6, 7
TSKEW
CPU0 to CPU1 Skew time
-
175
-
175
pS
6, 8, 9
TCCJ
CPU(0:1) Cycle to Cycle Jitter
-
250
-
250
pS
6, 8, 9
TPeriod
APIC(0:1) period
60.0
-
60.0
-
nS
5, 6, 8
THIGH
APIC(0:1) high time
25.5
-
25.5
-
nS
6,10
TLOW
APIC(0:1) low time
25.3
-
25.3
N/S
nS
6, 11
Tr / Tf
APIC(0:1) rise and fall times
0.4
1.6
0.4
1.6
nS
6, 7
TCCJ
APIC(0:1) Cycle to Cycle Jitter
-
500
-
500
pS
6, 8, 9
TPeriod
3V66-(0:1) period
15.0
16.0
15.0
16.0
nS
5, 6, 8
THIGH
3V66-(0:1) high time
5.25
-
5.25
-
nS
6,10
TLOW
3V66-(0:1) low time
5.05
-
5.05
-
nS
6, 11
Tr / Tf
3V66-(0:1) rise and fall times
0.4
1.6
0.4
1.6
nS
6, 7
TSKEW
3V66-0 to 3V66-1 Skew time
-
250
-
250
pS
6, 8, 9
TCCJ
3V66-(0:1) Cycle to Cycle Jitter
-
500
-
500
pS
6, 8, 9
TPeriod
PCI(0:7) period
30.0
-
30.0
-
nS
5, 6, 8
THIGH
PCI(0:7) period
12.0
-
12.0
-
nS
6,10
TLOW
PCI(0:7) low time
12.0
-
12.0
-
nS
6, 11
Tr / Tf
PCI(0:7) rise and fall times
0.5
2.0
0.5
2.0
nS
6, 7
TSKEW
(Any PCI clock) to (Any PCI clock)
Skew time
-
500
-
500
pS
6, 8, 9
TCCJ
PCI(0:7) Cycle to Cycle Jitter
-
500
-
500
pS
6, 8, 9
TPeriod
48MHz period ( conforms to
+167ppm max)
20.8299
20.8333
20.8299
20.8333
nS
5, 6, 8
Tr / Tf
48MHz rise and fall times
1.0
4.0
1.0
4.0
nS
6, 7
TCCJ
48MHz Cycle to Cycle Jitter
-
500
-
500
pS
6, 8, 9
TPeriod
REF period
69.8413
71.0
69.8413
71.0
nS
5, 6, 8
Tr / Tf
REF rise and fall times
1.0
4.0
1.0
4.0
nS
6, 7
TCCJ
REF Cycle to Cycle Jitter
-
1000
-
1000
pS
6, 8
tpZL, tpZH
Output enable delay (all outputs)
1.0
10.0
1.0
10.0
nS
13
tpLZ, tpZH
Output disable delay (all outputs)
1.0
10.0
1.0
10.0
nS
13
tstable
All clock Stabilization from power-up
3
mS
12
Cypress Semiconductor Corporation
525 Los Coches St.
Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571
http://www.cypress.com
3
Document#: 38-07053 Rev. **
05/03/01
Page 11 of 18
APPROVED PRODUCT
C9812
Low EMI Clock Generator for Intel 810E Chipset Systems
Switching Characteristics
Characteristic
Output Duty Cycle
Symbol
Min
Typ
Max
Units
Conditions
-
45
50
55
%
Note 6
CPU to SDRAM
TPD1
-
-
500
pS
CPU = 133.3MHz, Notes 6, 7
CPU to 3V66
TPD2
-
-
500
pS
CPU = 133.3MHz, Notes 6, 7
SDRAM to 3V66
TPD3
-
-
500
pS
CPU = 66.6/100/133.3MHz Notes 6, 7
tPD
1.5
-
-
nS
CPU = 66.6/100/133.3MHz Notes 6, 7
3V66 to PCI
PCI to IOAPIC
tPD
-
0
1
nS
CPU = 66.6/100/133.3MHz Notes 6, 7
Skew (CPU0-CPU1)
tSKEW1
-
-
175
pS
see Notes 6, 7
Skew (SDRAM-SDRAM)
tSKEW2
-
-
250
pS
see Notes 6, 7
Skew (APIC-APIC)
tSKEW3
-
-
250
pS
Skew (3V66-3V66)
tSKEW4
-
-
175
pS
Skew (PCI – PCI)
TSKEW5
-
-
500
pS
Cycle to Cycle Jitter
∆P1
-
-
250
pS
CPU, and SDRAM, Notes 6 & 7
Cycle to Cycle Jitter
∆P2
-
-
500
pS
IOAPIC, USB, DOT, 3V66, PCI,
Notes 6, 7
Cycle to Cycle Jitter
∆P3
-
-
1,000
pS
REF, Notes 6& 7
VDD=VDDS=3.3V ±5%, VDDC=VDDI=2.5±5%, TA=0 to 70ºC
Note 6:
Note 7:
All outputs loaded as per table 5 below. Probes are placed on the pins and taken at 1.5V levels for 3.3V signals and at 1.25V for 2.5V
signals.
This measurement is applicable with Spread Spectrum ON or OFF.
Output Buffer Characteristics
Buffer Characteristics for CPU
Characteristic
Symbol
Min
Typ
Pull-Up Current
IOH1
-28
-61
-107
mA
Vout =VDDC - 0.4V
Pull-Up Current
IOH2
-26
-58
-101
mA
Vout = 1.2 V
Pull-Down Current
IOL1
12
24
40
mA
Vout = 0.4 V
Pull-Down Current
IOL1
27
56
93
mA
Vout = 1.2 V
Z0
Tr
13.5
0.4
-
45
1.6
Ω
nS
20pF Load
Tf
0.4
-
1.6
nS
20pF Load
Dynamic Output Impedance
Rise Time Min
Between 0.4 and 2.0 V
Fall Time Max
Between 0.4 and 2.0 V
Cypress Semiconductor Corporation
525 Los Coches St.
Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571
http://www.cypress.com
Max
Units
Conditions
Document#: 38-07053 Rev. **
05/03/01
Page 12 of 18
APPROVED PRODUCT
C9812
Low EMI Clock Generator for Intel 810E Chipset Systems
Output Buffer Characteristics (Cont.)
Buffer Characteristics for PCI, 3V66 and DOT
Characteristic
Symbol
Min
Typ
Pull-Up Current
IOH1
-33
-58
-194
mA
Vout =VDDC - 1.0 V
Pull-Up Current
IOH2
-30
-54
-184
mA
Vout = 1. 5 V
Pull-Down Current
IOL1
9.4
18
38
mA
Vout = 0.4 V
Pull-Down Current
IOL1
28
55
148
mA
Vout = 1.5 V
Z0
Tr
12
0.5
-
55
2.0
Ω
nS
30pF Load
Tf
0.5
-
2.0
nS
30pF Load
Dynamic Output Impedance
Rise Time Min
Between 0.4 and 2.4 V
Fall Time Max
Between 0.4 and 2.4 V
Max
Units
Conditions
Buffer Characteristics for USB and REF
Characteristic
Symbol
Min
Typ
Pull-Up Current
IOH1
-29
-46
-99
mA
Vout =VDD - 1.0 V
Pull-Up Current
IOH2
-27
-43
-92
mA
Vout = 1. 5 V
Pull-Down Current
IOL1
9
13
27
mA
Vout = 0.4 V
Pull-Down Current
IOL1
26
39
79
mA
Vout = 1.5 V
Z0
Tr
20
1.0
-
60
4.0
Ω
nS
20pF Load
Tf
1.0
-
4.0
nS
20pF Load
Dynamic Output Impedance
Rise Time Min
Between 0.4 and 2.4 V
Fall Time Max
Between 0.4 and 2.4 V
Max
Units
Conditions
Buffer Characteristics for IOAPIC
Characteristic
Symbol
Min
Typ
Pull-Up Current
IOH1
-28
-61
-107
mA
Vout =VDDI - 0.5V
Pull-Up Current
IOH2
-26
-58
-107
mA
Vout = 1. 0 V
Pull-Down Current
IOL1
12
24
40
mA
Vout = 0.4 V
Pull-Down Current
IOL1
28
60
100
mA
Vout = 1.4 V
Dynamic Output Impedance
Z0
13.5
45
Ω
Rise Time Min
Between 0.4 and 2.0 V
Tr
0.4
-
1.6
nS
20pF Load
Fall Time Max
Between 0.4 and 2.0 V
Tf
0.4
-
1.6
nS
20pF Load
Cypress Semiconductor Corporation
525 Los Coches St.
Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571
http://www.cypress.com
Max
Units
Conditions
Document#: 38-07053 Rev. **
05/03/01
Page 13 of 18
APPROVED PRODUCT
C9812
Low EMI Clock Generator for Intel 810E Chipset Systems
Output Buffer Characteristics (Cont.)
Buffer Characteristics for SDRAM
Characteristic
Symbol
Min
Typ
Max
Units
Conditions
Pull-Up Current
IOH1
-72
-116
-198
mA
Vout =VDD - 1. 0 V
Pull-Up Current
IOH2
-68
-110
-188
mA
Vout = 1. 4 V
Pull-Down Current
IOL1
23
34
53
mA
Vout = 0.4 V
Pull-Down Current
IOL1
64
98
159
mA
Vout = 1.5 V
Dynamic Output Impedance
Z0
10
24
Ω
Rise Time Min
Between 0.4 and 2.4 V
Tr
0.4
-
1.6
nS
30pF Load
Fall Time Max
Between 0.4 and 2.4 V
Tf
0.4
-
1.6
nS
30pF Load
VDD=VDDS=3.3V ±5%, VDDC=VDDI=2.5±5%, TA=0 to 70ºC
Cypress Semiconductor Corporation
525 Los Coches St.
Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571
http://www.cypress.com
Document#: 38-07053 Rev. **
05/03/01
Page 14 of 18
APPROVED PRODUCT
C9812
Low EMI Clock Generator for Intel 810E Chipset Systems
Suggested Crystal Oscillator Parameters
Characteristic
Symbol
Min
Typ
Max
Units
Conditions
Frequency
Fo
12.00
14.31818
16.00
MHz
Tolerance
TC
-
-
+/-100
PPM
Note 1
TS
-
-
+/- 100
PPM
Stability (Ta -10 to +60C) Note 1
TA
-
-
5
PPM
Aging (first year @ 25C) Note 1
Mode
OM
-
-
-
Load Capacitance
CL
-
18
-
pF
Effective Series
resistance (ESR)
R1
-
40
-
Ohms
Power Dissipation
DL
-
-
0.10
mW
Parallel Resonant, Note 1
The crystal’s rated load. Note 1
Note 1
Note 1
Crystal’s
internal package
Shunt Capacitance
CO
-8
pF
capacitance (total)
Note1: For best performance and accurate Center frequencies of this device, It is recommended but not mandatory that
the chosen crystal meets these specifications
For maximum accuracy, the total circuit loading capacitance should be equal to CL. This loading capacitance is the
effective capacitance across the crystal pins and includes the device pin capacitance (CP) in parallel with any circuit
traces, the clock generator and any onboard discrete load capacitors.
Budgeting Calculations
Device pin capacitance: Cxtal = 34pF
In order to meet the specification for CL = 18pF following the formula:
CL =
C XIN xC XOUT
C XIN + C XOUT
Then the board trace capacitance between Xin and the crystal should be no more than 2pF. (same is applicable to the
trace between Xout and the crystal)
In this case the total capacitance from the crystal to Xin will be 36pF. Similarly the total capacitance between the crystal
and Xout will be 36pF. Hence using the above formula:
CL =
36 pFx36 pF
= 18 pF
36 pF + 36 pF
Cypress Semiconductor Corporation
525 Los Coches St.
Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571
http://www.cypress.com
Document#: 38-07053 Rev. **
05/03/01
Page 15 of 18
APPROVED PRODUCT
C9812
Low EMI Clock Generator for Intel 810E Chipset Systems
Package Drawing and Dimensions
56 Pin SSOP Outline Dimensions
INCHES
SYMBOL
C
L
H
E
D
a
A2
A
A1
e
B
MILLIMETERS
MIN
NOM
MAX
MIN
NOM
MAX
A
0.095
0.102
0.110
2.41
2.59
2.79
A1
0.008
0.012
0.016
0.20
0.31
0.41
A2
0.088
0.090
0.092
2.24
2.29
2.34
B
0.008
0.010
0.0135
0.203
0.254
0.343
C
0.005
-
0.010
0.127
-
0.254
D
.720
.725
.730
18.29
18.42
18.54
E
0.292
0.296
0.299
7.42
7.52
7.59
e
0.025 BSC
0.635 BSC
H
0.400
0.406
0.410
10.16
10.31
10.41
L
0.024
0.032
0.040
0.61
0.81
1.02
a
0º
5º
8º
0º
5º
8º
X
0.085
0.093
0.100
2.16
2.36
2.54
Ordering Information
Part Number
Package Type
Production Flow
C9812DYB
56 PIN SSOP
Commercial, 0 to 70ºC
Marking: Example:
Cypress
C9812
Date Code, Lot #
C9812DYB
Flow
B = Commercial, 0 to 70ºC
Package
Y = SSOP
Revision
Device Number
Cypress Semiconductor Corporation
525 Los Coches St.
Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571
http://www.cypress.com
Document#: 38-07053 Rev. **
05/03/01
Page 16 of 18
APPROVED PRODUCT
C9812
Low EMI Clock Generator for Intel 810E Chipset Systems
Notice
Cypress Semiconductor Corporation reserves the right to change or modify the information contained in this data sheet,
without notice Cypress Semiconductor Corporation does not assume any liability arising out of the application or use of
any product or circuit described herein. Cypress Semiconductor Corporation does not convey any license under its
patent rights nor the rights of others Cypress Semiconductor Corporation does not authorize its products for use as
critical components in life-support systems or critical medical instruments, where a malfunction or failure may reasonably
be expected to result in significant injury to the user.
Cypress Semiconductor Corporation
525 Los Coches St.
Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571
http://www.cypress.com
Document#: 38-07053 Rev. **
05/03/01
Page 17 of 18
APPROVED PRODUCT
C9812
Low EMI Clock Generator for Intel 810E Chipset Systems
Document Title: C9812 Low EMI Clock Generator for Intel® 810E Chipset Systems
Document Number: 38-07053
Rev.
**
ECN
No.
107061
Issue
Date
06/07/01
Orig. of
Change
IKA
Cypress Semiconductor Corporation
525 Los Coches St.
Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571
http://www.cypress.com
Description of Change
Convert from IMI to Cypress
Document#: 38-07053 Rev. **
05/03/01
Page 18 of 18