CYPRESS C9851

PRELIMINARY
C9851
Clock Generator for PentiumIII Server and Workstation Applications
Product Features
Product Description
•
•
•
•
•
This device provides the necessary clocks for a
differential host bus system in multi-processor servers
and workstations. It also generates a 66.6MHz hub
clock for interfacing with a complimentary part, the
Cypress B9852. The 2 Mref clock outputs are 180
degrees out of phase and are used for interfacing with
the Direct Rambus Clock Generator (DRCG), C9820,
C9821, or C9822. This device integrates the Cypress
spread spectrum technology for optimum EMI
reduction.
•
•
Six pairs of current referenced differential clocks
Two 3V 180° displaced Mref clocks for DRCG
One 66.6 MHz reference output
One 14.318 MHz reference output
Select logic for Differential Swing Control, Test
mode, Hi-Z, Power-down, Spread spectrum, and
limited frequency select
Cypress Spread Spectrum for EMI reduction
48 Pin SSOP Package
Frequency Selection Table
SEL 100/133
SELA
SELB
CPU(1:6), CPU#(1:6)
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
100 MHz
100 MHz
200 MHz
Hi-Z
133.3 MHz
25 MHz
200 MHz
REF/2
3VMref,
3Vmref_b
50 MHz
Low
50 MHz
Hi-Z
66.67 MHz
50 MHz
66.7 MHz
REF/4
Table 1
3V66
REF
66.67 MHz
Low
66.67 MHz
Hi-Z
66.67 MHz
66.67 MHz
66.67 MHz
REF
14.318 MHz
Low
14.318 MHz
Hi-Z
14.318 MHz
14.318 MHz
14.318 MHz
REF
Block Diagram
Pin Configuration
XIN
XOUT
VDDR
REF
VSSR
OSC
VDDA
I
Control
MultSel(0:1)
Spread#
SelA
SelB
SEL100/133
PwrDwn#
VCO
I_Ref
VSSI
CPU (1:6)
CPU (1:6)#
VDDM
3VMRef
3VMRef_b
VSSM
VDDL
3V66
VSSL
Cypress Semiconductor Corporation
525 Los Coches St.
Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571
http://www.cypress.com
VSSR
Ref
VDDR
XIN
XOUT
VSSR
VDDM
3VMref
3VMref_b
VSSM
VDD
VSS
VDDL
3V66
VSSL
SEL100/133
MultSel0
MultSel1
VDDA
VSSA
SelA
SelB
Spread#
PwrDwn#
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
Document#: 38-07068 Rev. **
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
VDD
VSS
VDDC
CPU1
CPU1#
VSSC
CPU2
CPU2#
VDDC
CPU3
CPU3#
VSSC
CPU4
CPU4#
VDDC
CPU5
CPU5#
VSSC
CPU6
CPU6#
VDDC
I_Ref
VSSA
VDDA
05/04/2001
Page 1 of 14
PRELIMINARY
C9851
Clock Generator for PentiumIII Server and Workstation Applications
Pin Description
PIN No.
8
9
Pin Name
3VMref
3VMref_b
I/O
O
O
23
Spread#
PU
45,42,39,36,
33,30
44,41,38,35,
32,29
27
CPU(1:6)
O
CPU(1:6)#
I_Ref
P
14
24
3V66
PwrDwn#
O
PU
22, 21
16
5
SelA, SelB
SEL100/133
XOUT
PD
PU
O
4
XIN
I
2
18, 17
REF
MultSel (0,1)
O
I
3
46,40,34,28
11, 48
13
19, 25
7
1, 6
31, 37, 43
12, 47
15
20, 26
10
VDDR
VDDC
VDD
VDDL
VDDA
VDDM
VSSR
VSSC
VSS
VSSL
VSSA
VSSM
P
P
P
P
P
P
P
P
P
P
P
P
Description
Output clock for driving the DRCG device. See table 1, page1 for frequency selection.
Output clock for driving the DRCG device. See table 1, page1 for frequency selection. It
is 180 degrees out of phase (inverted) from the 3VMref clock.
When asserted low, this pin invokes Spread Spectrum functionality. Spread spectrum is
applicable to CPU(1:6), CPU(1:6)#, 3VMref, 3VMref_b, and 3V66 clocks. This pin has a
250KΩ internal Pull-up.
Differential host clock outputs. These outputs are used in pairs, (CPU1-1#, CPU2-2#,
CPU3-3#, CPU4-4#, CPU5-5#, and CPU6-6#) for differential clocking of the host bus.
CPU(1:6)# are 180 degrees out of phase with their complements, CPU(1:6). See table 1,
page 1 for frequency selection.
This pin establishes the reference current for the internal current steering buffers of the
CPU clocks. A resistor is connected from this pin to ground to set the value of this current.
See applications data on page 9 of this data sheet for details.
Fixed 66.67 MHz clock output for driving the IMI B9852 buffer device.
When asserted low, this pin Invokes power-down mode by shutting off all the clocks,
disabling all internal circuitry, and shutting down the crystal oscillator. The 3VMref,
3VMref_B, 3V66, REF and CPU clocks are driven low during this condition. It has a
250KΩ internal Pull-up.
Input select pins. See table 1, page 1. Each pin has a 250KΩ internal Pull-down
Input select pin. See table 1, page 1. It has a 250KΩ internal Pull-up
Crystal Buffer output pin. Connects to a crystal only. When an external signal other than
a crystal is used or when in Test mode, this pin is kept unconnected.
Crystal Buffer input pin. Connects to a crystal, or an external single ended input clock
signal.
A buffered output clock of the signal applied at Xin. Typically, 14.31818MHz.
These input select pins configure the LOH current (and thus the VOH swing amplitude) of
the CPU clock output pairs. Each pin has a 250KΩ internal Pull-up. See the table 5 for
current and resistor values.
3.3V power supply pins for Ref clock and crystal buffer.
3.3V power supply pins for CPU(1:6) / CPU(1:6)# outputs.
3.3V power supply pins for common supply to the core.
3.3V power supply pins for 3V66 output.
3.3V power supply pins for internal current reference circuitry and internal PLL.
3.3V power supply pin for 3Vmref and 3Vmref_b outputs
Ground pins for the Ref clock and crystal buffer.
Ground pins for the CPU(1:6)/CPU(1:6)# outputs.
Ground pins for common supply to the core.
Ground pin for the 3V66 output.
Ground pin for internal current reference circuitry and internal PLL.
Ground pin for 3Vmref and 3Vmref_b outputs.
Note: Definition of I/O column pneumonic on pin description table above:
I = Input pin, O = output pin, P = power supply pin, PU = This indicated that a bi-directional pin contains a device internal pull-up
resistor. This will insure that this pin of the device will be seen by the internal logic as a logic 1 level. Likewise pins with a PD
designation are guaranteed to be seen as a logic 0 level if no external level setting circuitry is present at power up.
Cypress Semiconductor Corporation
525 Los Coches St.
Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571
http://www.cypress.com
Document#: 38-07068 Rev. **
05/04/2001
Page 2 of 14
PRELIMINARY
C9851
Clock Generator for PentiumIII Server and Workstation Applications
Maximum Ratings
This device contains circuitry to protect the inputs
against damage due to high static voltages or electric
field; however, precautions should be taken to avoid
application of any voltage higher than the maximum
rated voltages to this circuit. For proper operation, Vin
and Vout should be constrained to the range:
VSS<(Vin or Vout)<VDD
Unused inputs must always be tied to an appropriate
logic voltage level (either VSS or VDD).
Maximum Input Voltage Relative to VSS: VSS - 0.5V
Maximum Input Voltage Relative to VSS: VDD + 0.7V
Storage Temperature:
-65ºC to + 150ºC
Operating Temperature:
0ºC to +70ºC
Maximum ESD protection
2000V
Maximum Power Supply:
5.5V
DC Parameters (VDDI = VDD = VDDR = VDDL = VDDM = VDDC = 3.3V ±5%, TA = 0°C to +70°C)
Characteristic
Symbol
Min
Typ
Max
Units
Conditions
Note 1
Input Low Voltage
VIL1
-
-
0.8
Vdc
Input High Voltage
VIH1
2.0
-
-
Vdc
Input Low Current (@Vin =
VSS)
IIL
-16
-4
µA
Input High Current (@Vin =
VDD)
IIH
0
5
µA
Input Low Current (@Vin =
VSS)
IIL
0
-
µA
Input High Current (@Vin =
VDD)
IIH
4
16
µA
Tri-State leakage Current
Ioz
-
-
10
µA
Static Supply Current
Idd
-
-
30
mA
PwrDwn=Low
Dynamic Supply Current
Isdd
-
-
200
mA
133 MHz CPU, Note 3
Input pin capacitance
Cin
-
-
5
pF
Output pin capacitance
Cout
-
-
6
pF
Pin Inductance
Lpin
-
-
7
nH
Crystal pin capacitance
Cxtal
34
36
38
pF
Measured from Pin to Ground. See
crystal specification section presented
later in this data sheet.
Crystal Startup time
Txs
-
-
40
µS
From Stable 3.3V power supply.
Internal Pull-up and Pulldown resistor value
Rpi
200
250
500
KΩ
Note1:
Note2:
Note3:
For internal Pull up resistors, Note 1
and Note 2
For internal Pull down resistors, Note
1 and Note 2
Applicable to input signals: Sel100/133, Sel(A:B)), Spread#, PWRDN#, MultSel(0:1)
Although internal pull-up or Pull-Down resistors have a typical value of 250K, this value may vary between 200K and 500K.
All outputs loaded as per the maximum capacitive table in this data sheet.
Cypress Semiconductor Corporation
525 Los Coches St.
Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571
http://www.cypress.com
Document#: 38-07068 Rev. **
05/04/2001
Page 3 of 14
PRELIMINARY
C9851
Clock Generator for PentiumIII Server and Workstation Applications
AC Parameters (VDDI = VDD = VDDR = VDDL = VDDM = VDDC = 3.3V ±5%, TA = 0°C to +70°C)
Symbol
Parameter
TPeriod
Tr / Tf
TSKEW1
TSKEW2
TCCJ
Vover
Vunder
Vcrossover
Tduty
CPU[(1:6), (1:6)#] period CPU[(1:6), (1:6)#] rise and fall times
skew from any CPU pair to any CPU pair
skew from package to package
CPU[(1:6), (1:6)#] Cycle to Cycle Jitter
CPU[(1:6), (1:6)#] Overshoot
CPU[(1:6), (1:6)#] Undershoot
CPU(1:6) to CPU(1:6)# crossover point
Duty Cycle
TPeriod
THIGH
TLOW
Tr / Tf
TSKEW
TCCJ
Tduty
133 MHz Host
Min
Max
100 MHz Host
Min
Max
7.35
175
-
9.85
175
-
Units
Notes
45%Voh
45
10.2
450
150
100
150
Voh+0.2
-0.2
55%Voh
55
nS
pS
pS
pS
pS
V
V
V
%
1, 2
2, 3
2, 4, 5
2, 4, 5
2, 4, 5
2,10
2, 10
2, 4
2, 4
15.3
1.6
250
250
55
20.0
7.5
7.3
0.4
45
20.4
1.6
250
250
55
nS
nS
nS
nS
pS
pS
%
4, 5
2, 6
2, 7
2, 3
2, 4, 5, 11
2, 4, 5
2, 4
15.0
5.25
5.05
0.5
45
16.0
2.0
300
55
15.0
5.25
5.05
0.5
45
15.2
2.0
300
55
nS
nS
nS
nS
pS
%
1, 2, 4
2,6
2, 7
2, 3
2, 4, 5
2, 4
69.8413
1.0
45
71.0
4.0
1000
55
69.8413
1.0
45
71.0
4.0
1000
55
nS
nS
pS
%
1, 2, 4
2, 3
2, 4
2, 4
1.0
1.0
10.0
10.0
3
1.0
1.0
10.0
10.0
3
nS
nS
mS
9
9
45%Voh
45
7.65
450
150
100
150
Voh+0.2
-0.2
55%Voh
55
3V(MREF, MREF_B) period
3V(MREF, MREF_B) high time
3V(MREF, MREF_B) low time
3V(MREF, MREF_B) rise and fall times
3VMREF to 3VMREF_B skew
3V(MREF, MREF_B) Cycle to Cycle Jitter
Duty Cycle
15.0
5.25
5.05
0.4
45
TPeriod
THIGH
TLOW
Tr / Tf
TCCJ
Tduty
3V66 period
3V66 high time
3V66 low time
3V66 rise and fall times
3V66 Cycle to Cycle Jitter
Duty Cycle
TPeriod
Tr / Tf
TCCJ
Tduty
REF period
REF rise and fall times
REFCycle to Cycle Jitter
Duty Cycle
tpZL, tpZH
tpLZ, tpZH
tstable
Output enable delay (all outputs)
Output disable delay (all outputs)
All clock Stabilization from power-up
Group Limits and Parameters (applicable to all settings: Sel133/100# = x) continued
Note 1:
This parameter is measured at the crossing points of the differential signals, and acquired as an average over 1uS duration, with a crystal
center frequency of 14.31818MHz
Note 2: All outputs loaded as per table 2 below.
Note 3: Probes are placed on the pins, and measurements are acquired between 0.4V and 2.4V for 3.3V signals and at 20% and 80% for
CPU[(1:6), (1:6)#] signals. (see Figs.7A & 7B)
Note 4: Probes are placed on the pins, and measurements are acquired at 1.5V for 3.3V signals and at crossing points for CPU clocks (see Figs.7A
& 7B).
Note 5: This measurement is applicable with Spread ON or Spread OFF.
Note 6: Probes are placed on the pins, and measurements are acquired at 2.4V (see Figs. 7A & 7B)
Note 7: Probes are placed on the pins, and measurements are acquired at 0.4V. (see Figs. 7A & 7B)
Note 9: As this function is available through SEL(A,B), therefore, the time specified is guaranteed by design.
Note 10: Determined as a fraction of 2*(Trp-Trn) / (Trp+Trn) where Trp is a rising edge and Trn is an intersecting falling edge.
Note 11: 3VMref and 3VMref_b are 180 degrees out of phase, therefore, the skew is measured between the rising edge of one and the falling edge
of the other.
Cypress Semiconductor Corporation
525 Los Coches St.
Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571
http://www.cypress.com
Document#: 38-07068 Rev. **
05/04/2001
Page 4 of 14
PRELIMINARY
C9851
Clock Generator for PentiumIII Server and Workstation Applications
Group Limits and Parameters (applicable to all settings: Sel133/100# = x) (Continued)
Output name
CPU[(1:6), (1:6)#]
3VMref, 3VMref_b
REF
3V66
Max Load
Rs = 33.2Ω, Rp = 49.9Ω
30 pF
20 pF
30 pF
Table 2.
Lumped Test Load Configurations
The following shows lumped test load configurations for the differential Host Clock Outputs.
(MULTsel1 = 0, MULTsel0 = 1)
Rs
33.2ohm
Rp
49.9ohm
Test Nodes
Rs
33.2ohm
Rp
49.9ohm
Fig.1A
Cypress Semiconductor Corporation
525 Los Coches St.
Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571
http://www.cypress.com
Document#: 38-07068 Rev. **
05/04/2001
Page 5 of 14
PRELIMINARY
C9851
Clock Generator for PentiumIII Server and Workstation Applications
Lumped Test Load Configurations (Cont.)
3.3V signals
tDC
-
-
3.3V
Output under Test
Probe
Load Cap
2.4V
1.5V
0.4V
0V
Tr
Tf
Fig. 1B
Spread Spectrum Clock Generation (SSCG)
Spread Spectrum is a modulation technique applied here for maximum efficiency in minimizing Electro-Magnetic
Interference radiation generated from repetitive digital signals mainly clocks. A clock accumulates EM energy at the
center frequency it is generating. Spread Spectrum distributes this energy over a small frequency bandwidth therefore
spreading the same amount of energy over a spectrum. This technique is achieved by modulating the clock down from
(Fig.2) its resting frequency by a certain percentage (which also determines the energy distribution bandwidth). The
default of the device at power up keeps the Spread Spectrum disabled, therefore, in order to enable this function pin23,
Spread#, must be connect to ground (a low state.). See table 3 for Spread bandwidth description.
In Down Spread mode the center frequency is shifted down from its rested (non-spread) value by -0.25%. (ex.:
assuming the center frequency is 100MHz in non-spread mode; when down spread is enabled, the center frequency
shifts to 99.75MHz.).
In Center Spread mode, the Center frequency remains the same as in the non-spread mode.
Cypress Semiconductor Corporation
525 Los Coches St.
Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571
http://www.cypress.com
Document#: 38-07068 Rev. **
05/04/2001
Page 6 of 14
PRELIMINARY
C9851
Clock Generator for PentiumIII Server and Workstation Applications
Spread Spectrum Clock Generation (SSCG) (Cont.)
Down Spread
Fig. 2
Spectrum Spreading Selection Table
Unspread
Frequency in MHz
100
133.3
Spread Spectrum Parameter
Down Spreading
F Min
(MHz)
99.5
132.66
F Center
(MHz)
99.75
132.67
F Max
(MHz)
100
133
Spread
(%)
- 0.5%
- 0.5%
Table 3.
Cypress Semiconductor Corporation
525 Los Coches St.
Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571
http://www.cypress.com
Document#: 38-07068 Rev. **
05/04/2001
Page 7 of 14
PRELIMINARY
C9851
Clock Generator for PentiumIII Server and Workstation Applications
Power Management Functions
Host Swing Select Functions
MultSel0
MultSel1
Board Target
Trace/TermZ
60 Ohms
Reference Rr, Iref =
Output Current
Voh @Z, Iref =
Vdd/(3*Rr) Note2
2.32mA
0
0
Rf = 475 1%,
Ioh = 5*Iref
0.7V @ 60
Iref = 2.32mA
0
0
50 Ohms
Rr = 475 1%,
Ioh = 5*Iref
0.59V @ 50
Iref = 2.32mA
0
1
60 Ohms
Rr = 475 1%,
Ioh = 6*Iref
0.85V @ 60
Iref = 2.32mA
0
1
50 Ohms
Rr = 475 1%,
Ioh = 6*Iref
0.71V @ 50
Iref = 2.32mA
1
0
60 Ohms
Rr = 475 1%,
Ioh = 4*Iref
0.56V @ 60
Iref = 2.32mA
1
0
50 Ohms
Rr = 475 1%,
Ioh = 4*Iref
0.47V @ 50
Iref = 2.32mA
1
1
60 Ohms
Rr = 475 1%,
Ioh = 7*Iref
0.99V @ 60
Iref = 2.32mA
1
1
50 Ohms
Rr = 475 1%,
Ioh = 7*Iref
0.82V @ 50
Iref = 2.32mA
Note1: The entries in boldface are the primary system configurations of interest. The outputs should be optimized for
these configurations.
Note2: Rr refers to the resistance placed in series with the Iref input and Vss.
Table 4
Cypress Semiconductor Corporation
525 Los Coches St.
Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571
http://www.cypress.com
Document#: 38-07068 Rev. **
05/04/2001
Page 8 of 14
PRELIMINARY
C9851
Clock Generator for PentiumIII Server and Workstation Applications
Buffer Characteristics
Current Mode CPU Clock Buffer Characteristics
The current mode output buffer detail and current reference circuit details are contained elsewhere in this datasheet.
The following parameters are used to specify output buffer characteristics:
1. Output impedance of the current mode buffer circuit - Ro (see Figure 3).
2. Minimum and maximum required voltage operation range of the circuit – Vop (see Figure 3).
3. Series resistance in the buffer circuit – Ros (see Figure 3).
4. Current accuracy at given configuration into nominal test load for given configuration.
VDD3 (3.3V +/- 5%)
Ro
Iout
Ros
0V
1.2V
Iout
Vout = 1.2V max
Vout
Figure 3
Host Clock (HCSL) Buffer Characteristics
Characteristic
Minimum
Maximum
Ro
3000 Ohms (recommended)
N/A
Ros
Unspecified
Unspecified
Vout
N/A
1.2 Volt
Iout is selectable depending on implementation. The parameters above apply to all configurations. Vout is the voltage
at the pin of the device.
The various output current configurations are shown in the host swing select functions table. For all configurations, the
deviation from the expected output current is +/- 7% as shown in the table current accuracy (page 12).
Cypress Semiconductor Corporation
525 Los Coches St.
Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571
http://www.cypress.com
Document#: 38-07068 Rev. **
05/04/2001
Page 9 of 14
PRELIMINARY
C9851
Clock Generator for PentiumIII Server and Workstation Applications
Current Accuracy
Configuration
Load
All combinations of M0, M1
Nominal test load for
and Rr shown in host Swing
given configuration
Select Function Table 5, p. 8
Nominal test load for
Iout
VDD = 3.30 +/- 5%
All combinations of M0, m1
given configuration
and Rr shown in Host Swing
Select Function Table 5, p. 8
Note: Inom refers to the expected current based on the configuration of the device.
Iout
Conditions
VDD = nominal (3.30V)
Min
-7% Inom
Max
+ 7% Inom
-12% Inom
+ 12% Inom
Buffer Characteristics for REF
Characteristic
Pull-Up Current Min
Pull-Up Current Max
Pull-Down Current Min
Pull-Down Current Max
3.3V Output Rise Edge Rate
3.3V Output Fall Edge Rate
Symbol
IOHmin
IOHmax
IOLmin
IOLmax
Trh
Tfh
Min
-12
-27
9
26
0.5
0.5
Typ
-
Max
-53
-92
27
79
2.0
2.0
Units
mA
mA
mA
mA
V/nS
V/nS
Conditions
VOH=VDDmin-0.5V (2.64V)
VOH=VDDmin/2 (1.56V)
VOL=0.4V
VOL=VDDmin/2 (1.56V)
3.3V +/- 5% @ 0.4V – 2.4 V
3.3V +/- 5% @ 2.4V – 0.4 V
Max
-83
-184
38
148
4/1
4/1
Units
mA
mA
mA
mA
V/nS
V/nS
Conditions
VOH=VDD-0.5V (2.64V)
V OH=VDD/2 (1.56V)
VOL=0.4V
VOL=VDD/2 (1.56V)
3.3V +/- 5% @ 0.4V – 2.4 V
3.3V +/- 5% @ 2.4V – 0.4 V
Buffer Characteristics for 3V66, Mref, Mref_b
Characteristic
Pull-Up Current Min
Pull-Up Current Max
Pull-Down Current Min
Pull-Down Current Max
3.3V Output Rise Edge Rate
3.3V Output Fall Edge Rate
Symbol
IOHmin
IOHmax
IOLmin
IOLmax
Trh
Tfh
Cypress Semiconductor Corporation
525 Los Coches St.
Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571
http://www.cypress.com
Min
-11
-30
9
28
1/1
1/1
Typ
-
Document#: 38-07068 Rev. **
05/04/2001
Page 10 of 14
PRELIMINARY
C9851
Clock Generator for PentiumIII Server and Workstation Applications
Suggested Oscillator Crystal Parameters
Characteristic
Symbol
Min
Typ
Max
Units
Frequency
Fo
14.17
14.31818
14.46
MHz
Tolerance
TC
-
-
+/-100
PPM
Note 1
Frequency Stability
TS
-
-
+/- 100
PPM
Stability (TA -10 to +60C) Note 1
-
-
-
-
CXTAL
-
20
-
Operating Mode
Load Capacitance
Conditions
Parallel Resonant, Note 1
pF
The crystal’s rated load. Note 1
Effective Series
RESR
40
Ohms
Note 2
Resistance (ESR)
Note1: For best performance and accurate frequencies from this device, It is recommended but not mandatory that the chosen
crystal meets or exceeds these specifications
Note 2: Larger values may cause this device to exhibit oscillator startup problems
To obtain the maximum accuracy, the total circuit loading capacitance should be equal to CXTAL. This loading capacitance is the
effective capacitance across the crystal pins and includes the clock generating device pin capacitance (CFTG), any circuit trace
capacitance (CPCB), and any onboard discrete load capacitance (CDISC).
The following formula and schematic illustrates the application of the loading specification of a crystal (CXTAL)for a design.
CL = (CXINPCB + CXINFTG + CXINDISC) X (CXOUTPCB + CXOUTFTG + CXOUTDISC)
(CXINPCB + CXINFTG + CXINDISC) + (CXOUTPCB + CXOUTFTG + COUTDISC)
Where:
CXTAL
CXOUTFTG
CXOUTFTG
CXINPCB
CXOUTPCB
CXINDISC
CXOUTDISC
=
=
=
=
=
=
=
the load rating of the crystal
the clock generators XIN pin effective device internal capacitance to ground
the clock generators XOUT pin effective device internal capacitance to ground
the effective capacitance to ground of the crystal to device PCB trace
the effective capacitance to ground of the crystal to device PCB trace
any discrete capacitance that is placed between the XIN pin and ground
any discrete capacitance that is placed between the XOUT pin and ground
CXINPCB
CXINDISC
CXOUTPCB
CXOUTDISC
XIN
CXINFTG
XOUT
CXOUTFTG
Clock Generator
As an example, and using this formula for this datasheet’s device, a design that has no discrete loading capacitors (CDISC) and each
of the crystal to device PCB traces has a capacitance (CPCB) to ground of 4pF (typical value) would calculate as:
CL = (4pF + 36pF + 0pF) X (4pF + 36pF + 0pF)
(4pF + 36pF + 0pF) + (4pF + 36pF + 0pF)
= 40 X 40
40 + 40
= 1600
80
= 20pF
Therefore to obtain output frequencies that are as close to this data sheets specified values as possible, in this design
example, you should specify a parallel cut crystal that is designed to work into a load of 20pF
Cypress Semiconductor Corporation
525 Los Coches St.
Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571
http://www.cypress.com
Document#: 38-07068 Rev. **
05/04/2001
Page 11 of 14
PRELIMINARY
C9851
Clock Generator for PentiumIII Server and Workstation Applications
Package Drawing and Dimensions (48 Pin TSSOP)
48 Pin TSSOP Outline Dimensions
INCHES
SYMBOL
C
L
H
E
a
D
A2
A
A1
B
e
MIN
NOM
MILLIMETERS
MAX
MIN
NOM
MAX
A
-
-
0.047
-
-
1.20
A1
0.002
-
0.006
0.05
-
0.15
A2
0.031
0.039
0.041
0.80
1.00
1.05
B
0.007
-
0.011
0.17
-
0.27
C
0.004
-
0.008
0.09
-
0.20
D
0.488
0.492
0.496
12.40
12.50
12.60
E
0.236
0.240
0.244
6.00
6.10
6.20
e
0.02 BSC
0.50 BSC
H
0.315
0.319
0.323
8.00
8.10
8.20
L
0.018
0.024
0.030
0.45
0.60
0.75
a
0º
-
0º
-
8º
8º
48 Pin SSOP Outline Dimensions
INCHES
SYMBOL
MIN
NOM
MAX
MIN
NOM
MAX
A
0.095
0.102
0.110
2.41
2.59
2.79
A1
0.008
0.012
0.016
0.203
0.305
0.406
A2
0.088
-
0.092
2.24
-
2.34
B
0.008
-
0.0135
0.203
-
0.343
C
0.005
-
0.010
0.127
-
0.254
D
0.620
0.625
0.630
15.75
15.88
16.00
E
0.291
0.295
0.299
7.39
7.49
7.60
e
Cypress Semiconductor Corporation
525 Los Coches St.
Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571
http://www.cypress.com
MILLIMETERS
0.025 BSC
0.635 BSC
H
0.395
-
0.420
10.03
-
10.67
L
0.020
-
0.040
0.508
-
1.016
a
0º
-
0º
-
8º
Document#: 38-07068 Rev. **
8º
05/04/2001
Page 12 of 14
PRELIMINARY
C9851
Clock Generator for PentiumIII Server and Workstation Applications
Ordering Information
Part Number
Package Type
C9851BY
48 Pin SSOP
Commercial, 0ºC to +70ºC
C9851BT
48 Pin TSSOP
Commercial, 0ºC to +70ºC
Marking: Example:
Production Flow
Cypress
C9851
Date Code, Lot #
C9851BY
Package
Y = SSOP
T = TSSOP
Revision
Device Number
Notice
Cypress Semiconductor Corporation reserves the right to make changes to its products in order to improve design,
performance or reliability. Cypress Semiconductor Corporation assumes no responsibility for the use of its products in
life supporting and medical applications where the failure or malfunction of the product could cause failure of the life
supporting and medical systems. Products are not authorized for use in such applications unless a written approval is
requested by the manufacturer and an approval is given in writing by Cypress Semiconductor Corporation for the use of
its products in the life supporting and medical applications.
Cypress Semiconductor Corporation
525 Los Coches St.
Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571
http://www.cypress.com
Document#: 38-07068 Rev. **
05/04/2001
Page 13 of 14
PRELIMINARY
C9851
Clock Generator for PentiumIII Server and Workstation Applications
Document Title: C9851 Clock Generator for Pentium®III Server and Workstation Applications
Document Number: 38-07068
Rev.
**
ECN
No.
107104
Issue
Date
06/12/01
Orig. of
Change
IKA
Cypress Semiconductor Corporation
525 Los Coches St.
Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571
http://www.cypress.com
Description of Change
Convert from IMI to Cypress
Document#: 38-07068 Rev. **
05/04/2001
Page 14 of 14