CYM8210BPM 2M x 16 Static RAM Module Features structed using eight 512K x 8 SRAMs (CY62148) in SOJ packages mounted on an epoxy laminate board with pins. • High-density 32-megabit SRAM module • Low active power Writing to each byte is accomplished by enabling the appropriate Chip Select (E0, E1, E2, E3) and write enable (WH or WL). Data on the input/output pins (I/O) is written into the memory location specified on the address pins (A0 through A17). — 5.3W (max.) at 25 ns • SMD technology • TTL-compatible inputs and outputs • Low profile Reading the device is accomplished by taking the appropriate chip select (E0, E1, E2, E3) LOW while write enable (WE) remains HIGH. Under these conditions, the contents of the memory location specified on the address pins will appear on the data input/output pins (I/O). — Max. height of 0.725 in. • Available in 80 pin SIMM Package Functional Description The CYM8210 is a high-performance 8-megabit static RAM module organized as 2M words by 16 bits. This module is con- The data input/output pins stay at the high-impedance state when write enable is LOW or the appropriate chip selects are HIGH. The CYM8210 module is shipped as a 80 pin SIMM. Logic Block Diagram A 0 –A17 G 18 WH WL 512K x 8 SRAM 8 512K x 8 SRAM 8 512K x 8 SRAM 8 512K x 8 SRAM 8 I/O0 – I/O7 512K x 8 SRAM 8 I/O0 – I/O7 512K x 8 SRAM 8 I/O0 – I/O7 512K x 8 SRAM 8 I/O0 – I/O7 512K x 8 SRAM 8 I/O8 – I/O15 E0 I/O8 – I/O15 E1 I/O8 – I/O15 E2 I/O8 – I/O15 E3 8210 –1 Cypress Semiconductor Corporation Document #: 38-05008 Rev. ** • 3901 North First Street • San Jose • CA 95134 • 408-943-2600 Revised April 26, 2001 CYM8210BPM Selection Guide 8210-70 Maximum Access Time (ns) 70 Maximum Operating Current (mA) 158 Maximum Standby Current (µA) 150 Pin Configurations 80-Pin SIMM Top View Vss NC WH NC NC NC NC NC NC NC E3 E1 Vss NC NC NC NC A17 A15 A13 A11 A9 A7 A5 A3 A1 Vss I/O15 I/O13 I/O11 I/O9 I/O7 I/O5 I/O3 I/O1 NC NC NC Vss NC 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 Vcc G WL NC NC NC NC NC NC NC E2 E0 NC NC NC NC A18 A16 A14 A12 A10 A8 A6 A4 A2 A0 Vss I/O14 I/O12 I/O10 I/O8 I/O6 I/O4 I/O2 I/O0 Vcc Vss Vss NC Vss 8210 –2 Document #: 38-05008 Rev. ** Page 2 of 8 CYM8210BPM Maximum Ratings (Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature – 55°C to +125°C DC Voltage Applied to Outputs in High Z State– 0.5V to +7.0V DC Input Voltage– 0.5V to +7.0V Operating Range Ambient Temperature with Power Applied– 10°C to +85°C Supply Voltage to Ground Potential– 0.5V to +7.0V Range Ambient Temperature VCC Commercial 0°C to +70°C 5V ± 10% Electrical Characteristics Over the Operating Range CYM8210-70 Parameter Description Test Conditions VOH Output HIGH Voltage VCC = Min., IOH = –1.0 mA VOL Output LOW Voltage VCC = Min., IOL = 2.1 mA VIH Input HIGH Voltage VIL Input LOW Voltage IIX Input Leakage Current IOZ Min. Max. Unit 2.4 V 0.4 V 2.2 VCC V –0.3 0.8 V GND < VI < VCC –10 +10 µA Output Leakage Current GND < VO < VCC, Output Disabled –10 +10 µA ICC VCC Operating Supply Current VCC = Max., IOUT = 0 mA, CS < VIL 158 mA ISB1 Automatic CS PowerDown Current[1] Max. VCC, CS > VIH, Min. Duty Cycle = 100% 120 mA ISB2 Automatic CS PowerDown Current[1] Max. VCC, CS > VCC - 0.2V, VIN > VCC – 0.2V, or VIN < 0.2V 150 µA Capacitance[2] Parameter Description CIN Input Capacitance COUT Output Capacitance Test Conditions TA = 25°C, f = 1 MHz, VCC = 5.0V Max. Unit 60 pF 50 pF AC Test Loads and Waveforms R1481 Ω R1481 Ω 5V ALL INPUT PULSES 5V OUTPUT R2 255Ω 30 pF INCLUDING JIG AND SCOPE OUTPUT 90% OUTPUT R2 255Ω 5 pF INCLUDING JIG AND SCOPE (a) Equivalent to: 3.0V GND < 5 ns 10% 90% 10% < 5 ns 8210–4 (b) 8210–5 THÉVENIN EQUIVALENT 167Ω 1.73V Notes: 1. A pull-up resistor to VCC on the E3/E2/E1/E0 input is required to keep the device deselected during VCC power-up, otherwise ISB will exceed values given. 2. Tested on a sample basis. Document #: 38-05008 Rev. ** Page 3 of 8 CYM8210BPM Switching Characteristics Over the Operating Range[3] 70 ns Parameter Description Min. Max. Unit READ CYCLE tRC Read Cycle Time 70 ns tAA Address to Data Valid tOHA Output Hold from Address Change tACS E3/E2/E1/E0 LOW to Data Valid 70 ns tDOE G LOW to Data Valid 35 ns tLZOE G LOW to Low Z tHZOE G HIGH to High Z 70 10 ns 5 [4] ns 25 ns ns tLZCS E3/E2/E1/E0 LOW to Low Z tHZCS E3/E2/E1/E0 HIGH to High Z[4, 5] 25 E3/E2/E1/E0 HIGH to Power-Down 70 tPD ns 10 ns [6] WRITE CYCLE tWC Write Cycle Time 70 ns tSCS E3/E2/E1/E0 LOW to Write End 60 ns tAW Address Set-Up to Write End 60 ns tHA Address Hold from Write End 0 ns tSA Address Set-Up to Write Start 0 ns tPWE WH/WL Pulse Width 55 ns tSD Data Set-Up to Write End 25 ns tHD Data Hold from Write End 0 ns tLZWE WH/WL HIGH to Low Z 5 tHZWE WH/WL LOW to High Z[5] ns 25 ns Notes: 3. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified IOL/IOH and 30-pF load capacitance. 4. At any given temperature and voltage condition, tHZCS is less than tLZCS for any given device. These parameters are guaranteed by design and not 100% tested. 5. tHZCS and tHZWE are specified with CL = 5 pF as in part (b) of AC Test Loads and Waveforms. Transition is measured ±500 mV from steady-state voltage. 6. The internal write time of the memory is defined by the overlap of E3/E2/E1/E0 LOW and WH/WL LOW. Both signals must be LOW to initiate a write and either signal can terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write. Document #: 38-05008 Rev. ** Page 4 of 8 CYM8210BPM Switching Waveforms Read Cycle No. 1[7, 8] tRC ADDRESS tAA tOHA DATA OUT PREVIOUS DATA VALID DATA VALID 1841A–6 Read Cycle No. 2[7, 9] tRC E3/E2/E1/E0 tACS G tHZOE tDOE tHZCS tLZOE HIGH IMPEDANCE HIGH IMPEDANCE DATA VALID DATA OUT tLZCS 8210–7 Write Cycle No. 1 (WE Controlled)[6] tWC ADDRESS tSCS E3/E2/E1/E0 tAW tSA tHA tPWE WH/WL tSD DATA IN DATA VALID tHZWE DATA OUT tHD tLZWE HIGH IMPEDANCE DATA UNDEFINED 8210–8 Notes: 7. WH/WL is HIGH for read cycle. 8. Device is continuously selected, E3/E2/E1/E0 = VIL and G = VIL. 9. Address valid prior to or coincident with E3/E2/E1/E0 transition LOW. Document #: 38-05008 Rev. ** Page 5 of 8 CYM8210BPM Switching Waveforms (continued) Write Cycle No. 2 (E3/E2/E1/E0 Controlled)[6, 10] tWC ADDRESS tSCS tSA E3/E2/E1/E0 tAW tHA tPWE WH/WL tSD DATA IN tHD DATA VALID tHZWE DATA OUT HIGH IMPEDANCE DATA UNDEFINED 8210–9 Note: 10. If E3/E2/E1/E0 goes HIGH simultaneously with WH/WL HIGH, the output remains in a high-impedance state. Document #: 38-05008 Rev. ** Page 6 of 8 CYM8210BPM Ordering Information Speed (ns) Ordering Code Package Name 70 CYM8210BPM-70C PM49 Package Type 80-Pin Plastic SIMM Module Operating Range Commercial Package Diagrams 80-Pin Plastic SIMM Module PM49 Document #: 38-05008 Rev. ** Page 7 of 8 © Cypress Semiconductor Corporation, 2001. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. CYM8210BPM Document Title: CYM8210BPM 2M X 16 SRAM Module Datasheet Document Number: 38-05008 REV. ECN NO. Issue Date Orig. of Change Description of Change ** 106011 05/07/01 MEG New Data Sheet Document #: 38-05008 Rev. ** Page 8 of 8