CYM9275 CYM9276A CYM9277B CYM9278 1CYM9277 64K x 36 SRAM Module 128K x 36 SRAM Module 256K x 36 SRAM Module 512K x 36 SRAM Module Features surface mount packages on an epoxy laminate board with pins. The modules are designed to be incorporated into large memory arrays. • Operates at 133 MHz • Uses 64K x 18 / 128K x 18 or 256K x 18 high-performance synchronous SRAMs • 144-Position Angled DIMM from Berg p/n 61178 • 3.3V inputs/data outputs The modules are configured as single banks or multiple banks depending on the SRAM used to make the module. Separate clock are provided for each of the banks. Separate clocks are provided for each of the SRAMs. Functional Description Multiple ground pins and on-board decoupling capacitors ensure high performance with maximum noise immunity. The CYM9275, CYM9276A, CYM9277B, and the CYM9278 are high-performance synchronous pipelined memory modules organized as 64K, 128K, 256K, 512K by 36 bits. These modules are constructed using either 128K x 18 SRAMs (9275, 9276A, 9277B) or 256K x 18 SRAMs (9278) in plastic All components on the cache modules are surface mounted on a multi-layer epoxy laminate (FR-4) substrate. The contact pins are plated with 150 micro-inches of nickel covered by 30 micro-inches of gold flash. Logic Block Diagram - CYM9275 A[15:0] (2) 128K x 18 SRAMs A15:0 WE SGW OE OE CS CS BW[0:3] OE D[0:15] CS DQ[0:1] DQ[0:3] BWE WEH ADSP WEL CLK[0:1] ADSC Bank 0 64Kx36 D[0:31] PD1 PD0 GND NC CLK CLK[0:1] Bank0 Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600 April 2, 2001 CYM9275 CYM9276A CYM9277B CYM9278 Logic Block Diagram - CYM9276A A[16:0] (2) 128K x 18 SRAMs A16:0 WE SGW OE[0:1] OE0 CS[0:1] CS0 BW[0:3] OE D[0:15] CS DQ[0:1] D[0:31] DQ[0:3] BWE ADSP WEH WEL CLK[0:3] ADSC CLK Bank0 CLK[0:1] (2) 128K x 18 SRAMs A16:0 SGW OE1 CS1 OE D[0:15] CS DQ[0:1] BWE WEH WEL ADSC CLK Bank1 128Kx36 PD1 NC PD 0 GND CLK[2:3] 9276A Bank0 2 CYM9275 CYM9276A CYM9277B CYM9278 Logic Block Diagram - CYM9277B / CYM9278 A[17:0] (2) 256K x 18 SRAMs A17:0 WE SGW OE[0:1] OE0 OE D[0:15] CS[0:1] CS[0] CS DQ[0:1] BW[0:3] D[0:31] DQ[0:3] BWE ADSP WEH CLK[0:3] WEL ADSC CLK Bank0 CLK[0:1] (2) 256K x 18 SRAMs A17:0 SGW OE1 CS[1] OE D[0:15] CS DQ[0:1] BWE WEH WEL ADSC CLK Bank1 PD1 256KX36 512KX36 PD 0 GND GND NC NC CLK[2:3] 9277B/9278 Bank0 Bank0 and 1 Selection Guide Synchronous Cache Module CYM9275 Part Number 133 Module Size 100 CYM9276A 133 64 K x 72 CYM9277B 100 133 128 K x 72 CYM9278 100 133 100 256 K x 72 512 K x 72 8 of 128K x 18 8 of 256K x 18 SRAMs Used 4 of 128K x 18 (High address bit tied Off) 8 of 128K x 18 (High address bit tied Off) System Clock (MHz) 133 100 133 100 133 100 133 100 Data tCO 4.5 ns 5.5 ns 4.5 ns 5.5 ns 4.5 ns 5.5 ns 4.5 ns 5.5 ns 3 CYM9275 CYM9276A CYM9277B CYM9278 Pin Configuration Dual Read-Out SIMM (DIMM) Top View GND A0 A2 A4 VCC3 NC NC GND A6 A8 A10 NC VCC3 A12 A 14 A16 GND PD 0 GND BW[0] CS[0] GND CLK1 GND D0 VCC3 D2 D4 D6 GND VCC3 D8 D10 GND D12 D14 DQ0 NC NC GND WE NC VCC3 NC NC NC VCC3 NC NC NC GND BW[2] CS[1] VCC3 D16 D18 NC NC NC GND CLK3 GND D 20 GND D 22 D 24 D 26 D 28 VCC3 D 30 DQ2 GND 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 GND A1 A3 A5 VCC3 NC NC GND A7 A9 A11 NC VCC3 A13 A15 A17 GND PD1 GND BW[1] OE[0] GND CLK0 GND D1 VCC3 D3 D5 D7 GND 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 VCC3 D9 D11 GND D13 D15 DQ1 NC NC GND ADSP NC VCC3 NC NC NC VCC3 NC NC NC GND BW[3] OE[1] VCC3 D17 D19 NC NC NC GND CLK2 GND D21 GND D23 D25 D27 D 29 V CC3 D31 DQ3 GND 4 CYM9275 CYM9276A CYM9277B CYM9278 Pin Definitions Signal Description VCC3 3V Supply GND Ground A[17:0] Addresses from processor ADSP Address strobe from the processor OE[1:0] Output Enables for each of the banks BW[0:3] Byte writes WE Global Write CS[1:0] Chip Select for the two banks PD0–PD1 Presence Detect output pins D[31:0] Data lines from processor DQ[3:0] Data Parity lines from processor CLK[0:3] Clock lines to the module NC Signal not connected on module RSVD Reserved Presence Detect Pins PD1 CYM9275 – 64K x 36 PD0 GND NC CYM9276A – 128K x 36 NC GND CYM9277B – 256K x 36 GND GND NC NC CYM9278 – 512K x 36 5 CYM9275 CYM9276A CYM9277B CYM9278 Maximum Ratings DC Input Voltage ........................................... –0.5V to +4.6V Output Current into Outputs (LOW)............................. 20 mA (Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ................................. –55°C to +125°C Operating Range Ambient Temperature with Power Applied......................................... –0°C to +70°C Range Ambient Temperature VCC Commercial 0°C to +70°C 3.3V ± 5% 3.3V Supply Voltage to Ground Potential...... –0.5V to +4.5V DC Voltage Applied to Outputs in High Z State .............................................. –0.5V to +4.6V Electrical Characteristics Over the Operating Range Parameter Description Test Condition Min. Max. Unit 2.2 VCC + 0.3 V –0.3 0.8 V VIH Input HIGH Voltage VIL Input LOW Voltage VOH Output HIGH Voltage VCC = Min. IOH = −4 mA VOL Output LOW Voltage VCC = Min. IOL = 8 mA 0.4 V ICC (9275) VCC Operating Supply Current VCC = Max., IOUT = 0 mA, f = fMAX = 1/tRC 350 mA ICC (9276A) VCC Operating Supply Current VCC = Max., IOUT = 0 mA, f = fMAX = 1/tRC 500 mA ICC (9277B) ICC (9278) VCC Operating Supply Current VCC = Max., IOUT = 0 mA, f = fMAX = 1/tRC 1000 mA VCC Operating Supply Current VCC = Max., IOUT = 0 mA, f = fMAX = 1/tRC 1200 mA 2.4 V Capacitance[1] Parameter CA Description Address Input Capacitance Test Conditions TA = 25°C, f = 1 MHz, VCC = 5.0V CI Control Input Capacitance TA = 25°C, f = 1 MHz, VCC = 5.0V CO Input / Output Capacitance TA = 25°C, f = 1 MHz, VCC = 5.0V CCLK Clock Capacitance TA = 25°C, f = 1 MHz, VCC = 5.0V Note: 1. Tested initially and after any design or process changes that may affect these parameters. 6 Part No. 9275 9276A 9277B 9278 9275 9276A 9277B 9278 9275 9276A 9277B 9278 9275 9276A 9277B 9278 Max. 12 7 14 20 12 8 16 20 9 5 10 16 6 3 3 5 Unit pF CYM9275 CYM9276A CYM9277B CYM9278 AC Test Loads and Waveforms[3] R1 VCCQ OUTPUT ALL INPUT PULSES OUTPUT 3.3V RL = 50 Ω VL = 1.5V INCLUDING JIGAND SCOPE (a) 10% R2 5 pF 90% 10% 90% GND ≤ 3 ns ≤ 3 ns (b) [2] Switching Characteristics Over the Operating Range CYM9275/76A/77B/78 133 MHz Parameter Description Min. 100 MHz Max. Min. Max. Unit tCYC Clock Cycle Time 7.5 10 ns tCH Clock HIGH 1.9 3.5 ns tCL Clock LOW 1.9 3.5 ns tAS Address Set-Up Before CLK Rise 2 2 ns tAH Address Hold After CLK Rise 0.5 0.5 ns tCO Data Output Valid After CLK Rise tDOH Data Output Hold After CLK Rise 3 3 ns tADS ADSP, ADSC Set-Up Before CLK Rise 2 3.1 ns tADSH ADSP, ADSC Hold After CLK Rise 0. 5 0.5 ns tWES WH, WL Set-Up Before CLK Rise 2 2 ns tWEH WH, WL Hold After CLK Rise 0.5 0.5 ns tDS Data Input Set-Up Before CLK Rise 2 2 ns tDH Data Input Hold After CLK Rise 0.5 0.5 ns tCSS Chip Select Set-Up 2 2 ns tCSH Chip Select Hold After CLK Rise tEOZ OE HIGH to Output High Z[4] tEOV OE LOW to Output Valid 4.5 0.5 5.5 0.5 ns ns 7 7 ns 4.5 5.5 ns Notes: 2. Resistor values for VCCQ = 3.3V are R1 = 317Ω and R2 = 351 Ω. 3. Unless otherwise noted, test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified IOL/IOH and load capacitance. Shown in (a) and (b) of AC test loads. All measurements are made at room temperature. 4. tEOZ is specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured ± 500 mV from steady-state voltage. 7 CYM9275 CYM9276A CYM9277B CYM9278 Switching Waveforms Write Single Write Burst Write Pipelined Write tCH Unselected tCYC CLK tADH tADS tCL ADSP ignored with CE1 inactive ADSP tADH tADS ADSC initiated write ADSC tADVH tADVS ADV tAS ADD ADV Must Be Inactive for ADSP Write WD1 WD3 WD2 tAH GW tWS tWH WE tCES tWH tWS tCEH CE1 masks ADSP CE1 tCES tCEH Unselected with CE2 CE2 CE3 tCES tCEH OE tDH tDS Data- High-Z In 1a 1a 2a 2c 2b = UNDEFINED 2d = DON’T CARE 8 3a High-Z CYM9275 CYM9276A CYM9277B CYM9278 Switching Waveforms (continued) Read [5, 6, 7] Single Read tCYC Burst Read Unselected tCH Pipelined Read CLK tADH tADS tCL ADSP ignored with CE1 inactive ADSP tADS ADSC initiated read ADSC tADVS tADH Suspend Burst ADV tADVH tAS ADD RD1 RD3 RD2 tAH GW tWS tWS tWH WE tCES tCEH tWH CE1 masks ADSP CE1 Unselected with CE2 CE2 tCES tCEH CE3 tCES OE tCEH tEOV tOEHZ tDOH Data Out tCO 1a 1a 2a 2b 2c 2c 2d 3a tCLZ tCHZ = DON’T CARE = UNDEFINED Notes: 5. OE is LOW throughout this operation. 6. If ADSP is asserted while CS is HIGH, ADSP will be ignored. 7. ADSP has no effect on ADV, WL, and WH if CS is HIGH. 9 CYM9275 CYM9276A CYM9277B CYM9278 Switching Waveforms (continued) Read / Write Single Read tCYC Single Write Unselected Burst Read tCH Pipelined Read CLK tADH tADS tCL ADSP ignored with CE1 inactive ADSP tADS ADSC tADVS tADH ADV tAS ADD tADVH RD1 WD2 RD3 tAH GW tWS tWS tWH WE tCES tCEH tWH CE1 masks ADSP CE1 CE2 tCES tCEH CE3 tCES tCEH tEOV OE Data In/Out tEOHZ tEOLZ tCO 1a 1a Out 2a In tDS See Note. 2a Out tDH 3a Out = UNDEFINED = DON’T CARE 10 tDOH 3b Out 3c Out 3d Out tCHZ CYM9275 CYM9276A CYM9277B CYM9278 Switching Waveforms (continued) Pipeline Timing tCH tCYC tCL CLK tAS ADD RD1 tADS RD2 RD3 WD1 RD4 WD2 WD3 WD4 tADH ADSC initiated Reads ADSC ADSP initiated Reads ADSP ADV tCEH tCES CE1 CE tWEH tWES WE ADSP ignored with CE1 HIGH OE tCLZ Data In/Out 1a Out 2a Out 3a Out 1a In 4a Out 2a In 3a In tCO tDOH Back to Back Reads tCHZ = UNDEFINED = DON’T CARE 11 4a D(C) In CYM9275 CYM9276A CYM9277B CYM9278 Ordering Information Speed (MHz) 100 133 Ordering Code Package Name Package Type Description CYM9275PM-100C PM45 144-Pin Dual-Readout SIMM (DIMM) Sync 64K x 72 CYM9276APM-100C PM45 144-Pin Dual-Readout SIMM (SIMM) Sync 128K x 72 CYM9277BPM-100C PM46 144-Pin Dual-Readout SIMM (DIMM) Sync 256K x 72 CYM9278PM-100C PM46 144-Pin Dual-Readout SIMM (DIMM) Sync 512K x 72 CYM9275PM-133C PM45 144-Pin Dual-Readout SIMM (DIMM) Sync 64K x 72 CYM9276APM-133C PM45 144-Pin Dual-Readout SIMM (SIMM) Sync 128K x 72 CYM9277BPM-133C PM46 144-Pin Dual-Readout SIMM (DIMM) Sync 256K x 72 CYM9278PM-133C PM46 144-Pin Dual-Readout SIMM (DIMM) Sync 512K x 72 Document #: 38-M-00083-*B Package Diagrams 144-Pin Single-Sided DIMM PM45 12 Operating Range Commercial CYM9275 CYM9276A CYM9277B CYM9278 Package Diagrams 144-Pin Dual-Sided DIMM PM46 © Cypress Semiconductor Corporation, 2001. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.