EDI416S4030A White Electronic Designs 1M x 16 Bits x 4 Banks Synchronous DRAM FEATURES DESCRIPTION n n n n n The EDI416S4030A is 67,108,864 bits of synchronous high data rate DRAM organized as 4 x 1,048,576 words x 16 bits. Synchronous design allows precise cycle control with the use of system clock, I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable burst lengths and programmable latencies allow the same device to be useful for a variety of high bandwidth, high performance memory system applications. Single 3.3V power supply Fully Synchronous to positive Clock Edge Clock Frequency = 100, 83MHz SDRAM CAS Latentency = 3 (100MHz), 2 (83MHz) Burst Operation •Sequential or Interleave •Burst length = programmable 1,2,4,8 or full page Available in a 54 pin TSOP type II package the EDI416S4030A is tested over the industrial temp range (-40C to +85C) providing a solution for rugged main memory applications. •Burst Read and Write •Multiple Burst Read and Single Write n DATA Mask Control per byte n Auto Refresh (CBR) and Self Refresh •4096 refresh cycles across 64ms n Automatic and Controlled Precharge Commands n Suspend Mode and Power Down Mode n Industrial Temperature Range January 2003 Rev.2 ECO # 14194 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 (TOP VEIW) VDD DQ0 VDDQ DQ1 DQ2 VSSQ DQ3 DQ4 VDDQ DQ5 DQ6 VSSQ DQ7 VDD LDQM WE CAS RAS CE BA0 BA1 A10/AP A0 A1 A2 A3 VDD PIN CONFIGURATION TERMINAL CONNECTIONS FIG. 1 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 VSS DQ15 VSSQ DQ14 DQ13 VDDQ DQ12 DQ11 VSSQ DQ10 DQ9 VDDQ DQ8 VSS NC/RFU UDQM CLK CKE NC A11 A9 A8 A7 A6 A5 A4 VSS PIN DESCRIPTION A0-11 BA0, BA1 CE WE CLK CKE DQ0-15 L(U)DQM RAS CAS VDD VDDQ VSS VSSQ NC 1 Address Inputs Bank Select Addresses Chip Select Write Enable Clock Input Clock Enable Data Input/Output Data Input/Output Mask Row Address Strobe Column Address Strobe Power (3.3V) Data Output Power Ground Data Output Ground No Connection White Electronic Designs Corporation • (508) 366-5151 • www.whiteedc.com White Electronic Designs EDI416S4030A INPUT/OUTPUT FUNCTIONAL DESCRIPTION Symbol CLK CKE Type Input Input Signal Pulse Level Polarity Positive Edge Active High CE RAS, CAS WE BA0,BA1 Input Input Pulse Pulse Active Low Active Low Input Level — A0-11, A10/AP Input Level — DQ0-15 Input/Output Level — L(U)DQM Input Pulse Mask Active High VDD, VSS VDDQ, VSSQ Supply Supply Function The system clock input. All of the SDRAM inputs are sampled on the rising edge of the clock. Activates the CLK signal when high and deactivates the CLK signal when low. By deactivating the clock, CKE low initiates the Power Down mode, Suspend mode, or the Self Refresh mode. CE disable or enable device operation by masking or enabling all inputs except CLK, CKE and DQM. When sampled at the positive rising edge of the clock, CAS, RAS, and WE define the operation to be executed by the SDRAM. Selects which SDRAM bank is to be active. During a Bank Activate command cycle, A0-11 defines the row address (RA0-11) when sampled at the rising clock edge. During a Read or Write command cycle, A0-7 defines the column address (CA0-7) when sampled at the rising clock edge. In addition to the row address, A10/AP is used to invoke Autoprecharge operation at the end of the Burst Read or Write cycle. If A10/AP is high, autoprecharge is selected and BA0, BA1 defines the bank to be precharged . If A10/AP is low, autoprecharge is disabled. During a Precharge command cycle, A10/AP is used in conjunction with BA0, BA1 to control which bank(s) to precharge. If A10/AP is high, all banks will be precharged regardless of the state of BA0, BA1. If A10/AP is low, then BA0, BA1 is used to define which bank to precharge. Data Input/Output are multiplexed on the same pins. The Data Input/Output mask places the DQ buffers in a high impedance state when sampled high. In Read mode, DQM has a latency of two clock cycles and controls the output buffers like an output enable. In Write mode, DQM has a latency of zero and operates as a word mask by allowing input data to be written if it is low but blocks the Write operation if DQM is high. Power and ground for the input buffers and the core logic. Isolated power and ground for the output buffers to improve noise immunity. White Electronic Designs Corporation • Westborough, MA • (508) 366-5151 2 White Electronic Designs A BSOLUTE MAXIMUM RATINGS Parameter Power Supply Voltage Input Voltage Output Voltage Operating Temperature Storage Temperature Power Dissipation Short Circuit Output Current Symbol VDD VIN VOUT TOPR TSTG PD IOS Min -1.0 -1.0 -1.0 -40 -55 Max +4.6 +4.6 +4.6 +85 +125 1.0 50 Units V V V °C °C W mA EDI416S4030A RECOMMENDED DC OPERATING CONDITIONS (VOLTAGE REFERENCED TO: VSS = 0V, TA = -40°C TO +85°C) Parameter Symbol Min Typ Max Unit Notes Supply Voltage VDD 3.0 3.3 3.6 V Input High Voltage VIH 2.0 3.0 VDD +0.3 V Input Low Voltage VIL -0.3 — 0.8 V Output High Voltage VOH 2.4 — — V (IOH = -2mA) Output Low Voltage VOL — — 0.4 V (IOL = 2mA) Input Leakage Voltage I IL -5 — 5 mA Output Leakage Voltage I OL -5 — 5 mA Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions greater than those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. CAPACITANCE (TA = 25C, f = 1MH Z , V DD = 3.0V Parameter Symbol Input Capacitance (A0-11, BA0-1) CI1 Input Capacitance (CLK, CKE, RAS, CI2 CAS, WE, CE, DQM) Input/Output Capacitance (DQ0-15) COUT TO 3.6V) Max 4 4 Unit pF pF 5 pF OPERATING CURRENT CHARACTERISTICS (V CC = 3.6V, TA = -40°C TO +85°C) Parameter Operating Current (One Bank Active) Operating Current (Burst Mode) Precharge Standby Current in Power Down Mode Symbol I CC 1 I CC 4 ICC2P ICC2PS ICC 1N Precharge Standby Current in Non-Power Down Mode ICC1NS Active Standby Current in Non-Power Down Mode ICC3P ICC3PS ICC 2N Active Standby Current in Power Down Mode Refresh Current Self Refresh Current ICC2NS I CC 5 I CC 6 Test Condition Burst Length = 1, tRC ³ tRC (min) Page Burst, 2 banks active, tCCD = 2 clocks CKE £ VIL (max), tCC = 15ns CKE, CLK £ VIL(max), tCC = ¥, Inputs Stable CKE = VIH, tCC = 15ns Input Change every 30ns CKE ³ VIH (min), tCC = ¥ No Input Change CKE £ VIL (max), tCC = 15ns CKE £ VIL (max), tCC = ¥ CKE = VIH, tCC = 15ns Input Change every 30ns CKE ³ VIH (min), tCC = ¥, No Input Change tRC ³ tRC (min) CKE £ 0.2V -10 140 200 2 2 50 -12 125 165 2 2 50 Units Notes mA 1 mA 1 mA mA mA 35 35 mA 12 12 30 12 12 30 mA mA mA 20 210 3 20 210 3 mA mA mA 2 NOTES: 1. Measured with outputs open. 2. Refresh period is 64ms. 3 White Electronic Designs Corporation • (508) 366-5151 • www.whiteedc.com EDI416S4030A White Electronic Designs AC CHARACTERISTICS OPERATING AC PARAMETIERS (VCC = 3.0V TO 3.6V, TA = -40°C TO +85°C) Parameter Symbol Clock Cycle Time CAS latency = 3 CAS latency = 2 Clock to Valid Output Delay Output Data Hold Time Clock High Pulse Width Clock Low Pulse Width Input Setup Time Input Hold Time Clock to Output in Low-Z Clock to Output in High-Z Row Active to Row Active Delay RAS to CAS Delay Row Precharge Time Row Active Time Row Cycle Time - Operation Row Cycle Time - Auto Refresh Last Data In to New Column Address Delay Last Data In to Row Precharge Last Data In to Burst Stop Column Address to Column Address Delay Number of Valid Output Data tCC tSAC tOH tCH tCL tSS tSH tSLZ tSHZ tRRD tRCD tRP tRAS tRC tRFC tCDL tRDL tBDL tCCD CAS latency = 3 CAS latency = 2 Min 10 13 -10 Max 1000 1000 7 3 3.5 3.5 2.5 1 1 Min 12 15 Max 1000 1000 8 3 4.0 4.0 3 1 1 7 20 24 24 50 80 80 1 1 1 1 2 1 -12 100,000 8 24 26 26 60 90 90 1 1 1 1 2 1 100,000 Units Notes ns 1 ns ns ns ns ns ns ns ns ns ns ns ns ns ns CLK CLK CLK CLK 1, 2 2 3 3 3 3 2 ea 7 4 4 4 4 4 4, 8 5 5 5 6 NOTES: 1. Parameters depend on programmed CAS latency. 2. If clock rise time is longer than 1ns, (trise/2 - 0.5ns) should be added to the parameter. 3. Assumed input rise and fall time = 1ns. If trise & tfall are longer than 1ns, [(trise + tfall)/2]-1ns should be added to the parameter. 4. The minimum number of clock cycles required is determined by dividing the minimum time required by the clock cycle time and then rounding up to the next higher integer. 5. Minimum delay is required to complete write. 6. All devices allow every cycle column address changes. 7. In case of row precharge interrupt, auto precharge and read burst stop. 8. A new command may be given tRFC after self refresh exit. REFRESH CYCLE PARAMETERS Parameter Refresh Period Self Refresh Exit Time Symbol tREF tSREX Min — tRFC -10 Max 64 — Min — tRFC -12 Max 64 — Units ms ns Notes 1, 2 3 NOTES: 1. 4096 cycles. 2. Any time that the Refresh Period has been exceeded, a minimum of two Auto (CBR) Refresh commands must be given to “wake-up” the device. 3. The self refresh is exited by restarting the external clock and then asserting CKE high. This must be followed by NOPs for a minimum time of tRFC before the SDRAM reaches idle state to begin normal operation. White Electronic Designs Corporation • Westborough, MA • (508) 366-5151 4 EDI416S4030A White Electronic Designs CLOCK FREQUENCY A ND LATENCY PARAMETERS - 100MHZ (U NITS = NUMBER OF CLOCKS) Frequency 100MHz (10ns) 83MHz (12ns) 75MHz (12ns) 66MHz (15ns) CAS Latency 3 3 2 2 tRC 80ns 8 7 6 6 t RAS 50ns 5 5 4 4 t RP 24ns 3 2 2 2 t RRD 20ns 2 2 2 2 t RCD 24ns 3 2 2 2 t CCD 10ns 1 1 1 1 t CDL 10ns 1 1 1 1 tRDL 10ns 1 1 1 1 t CCD 12ns 1 1 1 t CDL 12ns 1 1 1 tRDL 12ns 1 1 1 CLOCK FREQUENCY A ND LATENCY PARAMETERS - 83MHZ (U NITS = NUMBER OF CLOCKS) Frequency 83MHz (12ns) 75MHz (13ns) 66MHz (15ns) CAS Latency 3 3 2 tRC 90ns 8 7 6 t RAS 60ns 5 5 4 5 t RP 26ns 3 2 2 t RRD 24ns 2 2 2 t RCD 26ns 3 2 2 White Electronic Designs Corporation • (508) 366-5151 • www.whiteedc.com EDI416S4030A White Electronic Designs COMMAND TRUTH TABLE Command Register Refresh Precharge Mode Register Set Auto(CBR) Entry Self Single Bank All Banks Bank Activate Write Read Burst Stop No Operation Device Deselect Clock Suspend/Standby Mode Auto Precharge Disable Auto Precharge Enable Auto Precharge Disable Auto Precharge Enable CKE Previous Current CE RAS Cycle Cycle H X L L H H L L L CAS WE DQM L L X L H X BA A10/AP A11, A9-0 OP CODE X X L X H X Row Address L Column Address H H X L L H L X H H H X L L H H X BA X BA X L H L L X BA H X L H L H X BA H H H L X X X X L L H X H H X X H H X X L H X X X X X X L H X X X X L H X X X X X Column Address X X X X Write/Output Enable H X X X X X X X X Mask/Output Disable Entry L Power Down Mode X H X X X X X X X Exit H (X = Don’t Care, H = Logic High, L = Logic Low) NOTES: 1. All of the SDRAM operations are defined by states of CE, WE, RAS, CAS, and DQM at the positive rising edge of the clock. 2. Bank Select (BA), if BA0, BA1 = 0, 0 then bank A is selected, if BA0, BA1 = 1, 0 then bank B, if BA0, BA1 = 0, 1 then bank C, if BA0, BA1 = 1, 1 then bank D is selected, respectively. 3. During a Burst Write cycle there is a zero clock delay, for a Burst Read cycle the delay is equal to the CAS latency. 4. During normal access mode, CKE is held high and CLK is enabled. When it is low, it freezes the internal clock and extends data Read and Write operations. One clock delay is required for mode entry and exit. 5. The DQM has two functions for the data DQ Read and Write operations. During a Read cycle, when DQM goes high at a clock timing the data outputs are disabled and become high impedance after a two clock delay. DQM also provides a data mask function for Write cycles. When it activates, the Write operation at the clock is prohibited (zero clock latency). 6. All banks must be precharged before entering the Power Down Mode. The Power Down Mode does not perform any Refresh operations, therefore the device can’t remain in this mode longer than the Refresh period (tREF) of the device. One clock delay is required for mode entry and exit. Data White Electronic Designs Corporation • Westborough, MA • (508) 366-5151 6 Notes 2 2 2 2 2 2 3 4 5 5 6 6 EDI416S4030A White Electronic Designs CLOCK ENABLE (CKE 0) TRUTH TABLE Current State Self Refresh Power Down All Banks Idle Any State other than listed above CKE Previous Current H X L H L H L H L H L H L L H X L H L H L L H H H H H H H H H H H L H L H L H L H L L X H H H L L L H L CE X H L L L L X X H L X H L L L L H L L L L X X RAS X X H H H L X X X X X X H L L L X H L L L X X CAS X X H H L X X X X X X X X H L L X X H L L X X X X X X X X X X X Command WE BA A0-11 X X X X X X H X X L X X X X X X X X X X X X X X X X X X X X X X X X X X H X X L OP Code X X X H X X L OP Code X X X X X X X X X X X X X X X Action INVALID Exit Self Refresh with Device Deselect Exit Self Refresh with No Operation ILLEGAL ILLEGAL ILLEGAL Maintain Self Refresh INVALID Power Down Mode exit, all banks idle ILLEGAL Maintain Power Down Mode Refer to the Idle State section of the Current State Truth Table CBR Refresh Mode Register Set Refer to the Idle State section of the Current State Truth Table Entry Self Refresh Mode Register Set Power Down Refer to the Operations in the Current State Truth Table Begin Clock Suspend next cycle Exit Clock Suspend next cycle Maintain Clock Suspend Notes 1 2 2 2 2 2 1 2 2 3 4 3 4 4 5 NOTES: 1. For the given Current State CKE must be low in the previous cycle. 2. When CKE has a low to high transition, the clock and other inputs are re-enabled asynchronously. The minimum setup time for CKE (tCKS) must be satisfied before any command other than Exit is issued. 3. The address inputs (A11-0) depend on the command that is issued. See the Idle State section of the Current State Truth Table for more information. 4. The Power Down Mode, Self Refresh Mode, and the Mode Register Set can only be entered from the all banks idle state. Must be a legal command as defined in the Current State Truth Table. 7 White Electronic Designs Corporation • (508) 366-5151 • www.whiteedc.com White Electronic Designs EDI416S4030A CURRENT STATE TRUTH TABLE Current State Idle Row Active Read Write Read with Auto Precharge CE RAS CAS WE L L L L L L L L H L L L L L L L L H L L L L L L L L H L L L L L L L L H L L L L L L L L H L L L L H H H H X L L L L H H H H X L L L L H H H H X L L L L H H H H X L L L L H H H H X L L H H L L H H X L L H H L L H H X L L H H L L H H X L L H H L L H H X L L H H L L H H X L H L H L H L H X L H L H L H L H X L H L H L H L H X L H L H L H L H X L H L H L H L H X BA X X BA BA BA X X X X X BA BA BA X X X X X BA BA BA X X X X X BA BA BA X X X X X BA BA BA X X X Command A11, A10/AP-A0 OP Code X X Row Address Column Column X X X OP Code X X Row Address Column Column X X X OP Code X X Row Address Column Column X X X OP Code X X Row Address Column Column X X X OP Code X X Row Address Column Column X X X White Electronic Designs Corporation • Westborough, MA • (508) 366-5151 Description Mode Register Set Auto or Self Refresh Start Precharge Bank Activate Write w/o Precharge Read w/o Precharge Burst Termination No Operation Device Deselect Mode Register Set Auto orSelf Refresh Precharge Bank Activate Write Read Burst Termination No Operation Device Deselect Mode Register Set Auto or Self Refresh Precharge Bank Activate Write Read Burst Termination No Operation Device Deselect Mode Register Set Auto or Self Refresh Precharge Bank Activate Write Read Burst Termination No Operation Device Deselect Mode Register Set Auto or Self Refresh Precharge Bank Activate Write Read Burst Termination No Operation Device Deselect 8 Action Notes Set the Mode Register Auto orSelf Refresh No Operation Activate the specified bank and row ILLEGAL ILLEGAL No Operation No Operation No Operation or Power Down ILLEGAL ILLEGAL Precharge ILLEGAL Start Write; Determine if Auto Precharge Start Read; Determine if Auto Precharge No Operation No Operation No Operation ILLEGAL ILLEGAL Terminate Burst; Start the Precharge ILLEGAL Terminate Burst; Start the Write cycle Terminate Burst; Start a new Read cycle Terminate the Burst Continue the Burst Continue the Burst ILLEGAL ILLEGAL Terminate Burst; Start the Precharge ILLEGAL Terminate Burst; Start a new Write cycle Terminate Burst; Start the Read cycle Terminate the Burst Continue the Burst Continue the Burst ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL Continue the Burst Continue the Burst 2 2,3 4 4 5 6 4 7,8 7,8 4 8,9 8,9 4 8,9 8,9 4 4 EDI416S4030A White Electronic Designs CURRENT STATE TRUTH TABLE (CONT.) Current State Write with Auto Precharge Precharging Row Activating Write Recovering Write Recovering with Auto Precharge CE RAS CAS WE L L L L L L L L H L L L L L L L L H L L L L L L L L H L L L L L L L L H L L L L L L L L H L L L L H H H H X L L L L H H H H X L L L L H H H H X L L L L H H H H X L L L L H H H H X L L H H L L H H X L L H H L L H H X L L H H L L H H X L L H H L L H H X L L H H L L H H X L H L H L H L H X L H L H L H L H X L H L H L H L H X L H L H L H L H X L H L H L H L H X BA X X BA BA BA X X X X X BA BA BA X X X X X BA BA BA X X X X X BA BA BA X X X X X BA BA BA X X X Command A11, A10/AP-A0 OP Code X X Row Address Column Column X X X OP Code X X Row Address Column Column X X X OP Code X X Row Address Column Column X X X OP Code X X Row Address Column Column X X X OP Code X X Row Address Column Column X X X Description Mode Register Set Auto or Self Refresh Precharge Bank Activate Write Read Burst Termination No Operation Device Deselect Mode Register Set Auto or Self Refresh Precharge Bank Activate Write Read Burst Termination No Operation Device Deselect Mode Register Set Auto or Self Refresh Precharge Bank Activate Write Read Burst Termination No Operation Device Deselect Mode Register Set Auto or Self Refresh Precharge Bank Activate Write Read Burst Termination No Operation Device Deselect Mode Register Set Auto or Self Refresh Precharge Bank Activate Write Read Burst Termination No Operation Device Deselect 9 Action ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL Continue the Burst Continue the Burst ILLEGAL ILLEGAL No Operation; Bank(s) idle after tRP ILLEGAL ILLEGAL ILLEGAL No Operation; Bank(s) idle after tRP No Operation; Bank(s) idle after tRP No Operation; Bank(s) idle after tRP ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL No Operation; Row active after tRCD No Operation; Row active after tRCD No Operation; Row active after tRCD ILLEGAL ILLEGAL ILLEGAL ILLEGAL Start Write; Determine if Auto Precharge Start Read; Determine if Auto Precharge No Operation; Row active after tDPL No Operation; Row active after tDPL No Operation; Row active after tDPL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL No Operation; Precharge after tDPL No Operation; Precharge after tDPL No Operation; Precharge after tDPL Notes 4 4 4 4 4 4 4,10 4 4 4 4 9 9 4 4 4,9 4,9 White Electronic Designs Corporation • (508) 366-5151 • www.whiteedc.com EDI416S4030A White Electronic Designs CURRENT STATE TRUTH TABLE (CONT.) Current State Refreshing Mode Register Accessing CE RAS CAS WE L L L L L L L L H L L L L L L L L H L L L L H H H H X L L L L H H H H X L L H H L L H H X L L H H L L H H X L H L H L H L H X L H L H L H L H X BA X X BA BA BA X X X X X BA BA BA X X X Command A11, A10/AP-A0 OP Code X X Row Address Column Column X X X OP Code X X Row Address Column Column X X X Description Action Mode Register Set Auto or Self Refresh Precharge Bank Activate Write Read Burst Termination No Operation Device Deselect Mode Register Set Auto or Self Refresh Precharge Bank Activate Write Read Burst Termination No Operation Device Deselect ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL No Operation; Idle after tRC No Operation; Idle after tRC No Operation; Idle after tRC ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL No Operation; Idle after two clock cycles No Operation; Idle after two clock cycles Notes NOTES: 1. CKE is assumed to be active (high) in the previous cycle for all entries. The Current State is the state of the bank that the command is being applied to. 2. All Banks must be idle otherwise it is an illegal action. 3. If CKE is active (high) the SDRAM starts the Auto (CBR) Refresh operation, if CKE is inactive (low) then the Self Refresh mode is entered. 4. The Current State refers only to one of the banks, if BA0, BA1 selects this bank then the action is illegal. If BA0, BA1 selects the bank not being referenced by the Current State then the action may be legal depending on the state of that bank. 5. If CKE is inactive (low) then the Power Down mode is entered, otherwise there is a No Operation. 6. The minimum and maximum Active time (tRAS) must be satisfied. 7. The RAS to CAS Delay (tRCD) must occur before the command is given. 8. Address A10 is used to determine if the Auto Precharge function is activated. 9. The command must satisfy any bus contention, bus turn around, and/or write recovery requirements. The command is illegal if the minimum bank to bank delay time (tRRD) is not satisfied. White Electronic Designs Corporation • Westborough, MA • (508) 366-5151 10 EDI416S4030A White Electronic Designs MODE REGISTER SET TABLE Address Function BA0-BA1 RFU An ~ A10/AP RFU Test Mode A7 Type 0 Mode Register Set 1 Reserved 0 Reserved 1 Reserved Write Burst Length Length A9 Burst 0 1 Single Bit A8 0 0 1 1 A6 0 0 0 0 1 1 1 1 A9 W.B.L. A8 A7 TM CAS Latency A5 A4 Latency 0 0 Reserved 0 1 Reserved 1 0 2 1 1 3 0 0 Reserved 0 1 Reserved 1 0 Reserved 1 1 Reserved A6 A5 A4 CAS Latency Burst Type A3 Type 0 Sequential 0 Interleave A2 0 0 0 0 0 1 1 1 A3 BT A1 0 0 1 1 1 0 1 1 A2 A1 A0 Burst Length Burst Length A0 BT = 0 0 1 1 2 0 4 1 8 1 Reserved 1 Reserved 0 Reserved 1 Full Page BT = 1 1 2 4 8 Reserved Reserved Reserved Reserved Note: 1. If A9 is high during MRS cycle, “Burst Read Single Bit Write” function will be enabled. 2. RFU (Reserved for future use) should stay “0” during MRS cycle. 11 White Electronic Designs Corporation • (508) 366-5151 • www.whiteedc.com EDI416S4030A White Electronic Designs FIG. 2 SINGLE BIT READ-WRITE CYCLE (SAME PAGE) @ CAS LATENCY=3, BURST LENGTH=1 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 CLOCK t CH t CC t CL HIGH CKE t RCD t RAS CE t SS t RCD t SS t SH t RP t SH RAS t SS t CCD t SH CAS t SS ADDR t SS t SH t SH Ra Ca Cb Cc Rb Note 2 Note 2, 3 Note 2, 3 BA BS BS BS BS BS BS A10/AP Ra Note 3 Note 3 Note 3 Note 4 Rb t RAC t SS t SAC t SLZ Note 2 t SH Qa DQ Note 2, 3 Note 4 Db t OH Qc t SS t SH t SS t SH WE DQM Row Active Read Write Read Row Active DON’T CARE Precharge NOTES: 1. All input except CKE & DQM can be don’t care when CE is high at the CLK high going edge. 2. Bank active & read/write are controlled by BA0~BA1. 3. Enable and disable auto precharge function are controlled by A10/AP in read/ write command. BA 0 BA 1 Active &Read/Write 0 0 Bank A 0 1 Bank B 1 0 Bank C 1 1 Bank D A 10 /AP BA 0 BA 1 Operation 0 0 Disable auto precharge,leave bank A active at end of burst. 0 1 Disable auto precharge,leave bank B active at end of burst. 1 0 Disable auto precharge,leave bank C active at end of burst. 1 1 Disable auto precharge,leave bank D active at end of burst. Bank A 0 0 Enable auto precharge,precharge bank A at end of burst. Bank B 0 1 Enable auto precharge,precharge bank B at end of burst. 0 Enable auto precharge,precharge bank C at end of burst. 1 Enable auto precharge,precharge bank D at end of burst. 0 A 10 /AP BA 0 BA 1 Precharge 4. A10/AP and BA0-BA1 control bank precharge when precharge command is asserted. 0 0 0 0 0 1 1 0 1 0 Bank C 1 0 1 1 Bank D 1 1 x x All Banks White Electronic Designs Corporation • Westborough, MA • (508) 366-5151 12 EDI416S4030A White Electronic Designs FIG. 3 POWER UP SEQUENCE 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 CLOCK CKE High level is necessary CE t RFC t RP t RFC RAS CAS Key ADDR RAa BA RAa A10/AP HIGH-Z DQ WE DQM High level is necessary Precharge (All Banks) Auto Refresh Auto Refresh Mode Register Set Row Active (A-Bank) DON’T CARE 13 White Electronic Designs Corporation • (508) 366-5151 • www.whiteedc.com EDI416S4030A White Electronic Designs FIG. 4 READ & WRITE CYCLE AT SAME BANK @ BURST LENGTH=4 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 CLOCK HIGH CKE Note 1 t RC CE t RCD RAS Note 2 CAS ADDR Ra Ca0 Rb Cb0 BA A10/AP Ra Rb t SHZ t RAC Note 3 Qa0 CL = 2 Qa1 t RAC DQ Note 3 Qa2 t RDL Qa3 Db0 t SHZ t OH t SAC Qa0 CL = 3 Note 4 t OH t SAC Qa1 Qa2 Db1 Db2 Note 4 Qa3 Db3 t RDL Db0 Db1 Db2 Db3 WE DQM Row Active (A-Bank) Read (A-Bank) Precharge (A-Bank) Row Active (A-Bank) Write (A-Bank) Precharge (A-Bank) DON’T CARE NOTES: 1. Minimum row cycle times are required to complete internal DRAM operation. 2. Row precharge can interrupt burst on any cycle. (CAS Latency - 1) number of valid output data is available after Row precharge. Last valid output will be Hi-Z(tSHZ) after the clock. 3. Access time from Row active command. tCC *(tRCD + CAS latency - 1) + tSAC. 4. Output will be Hi-Z after the end of burst (1, 2, 4, 8 & full page bit burst). White Electronic Designs Corporation • Westborough, MA • (508) 366-5151 14 EDI416S4030A White Electronic Designs FIG. 5 PAGE READ & WRITE CYCLE AT SAME BANK @ BURST LENGTH=4 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 CLOCK HIGH CKE CE t RCD RAS Note 2 CAS ADDR Ra Ca0 Cb0 Cc0 Cd0 BA A10/AP Ra t RDL Qa0 CL = 2 Qa1 Qb0 Qb1 Qb2 Dc0 DQ Dc1 Dd0 Dd1 t CDL Qa0 CL = 3 Qa1 Qb0 Qb1 Dc0 Dc1 Dd0 Dd1 WE Note 1 Note 3 DQM Row Active (A-Bank) Read (A-Bank) Read (A-Bank) Write (A-Bank) Write (A-Bank) Precharge (A-Bank) DON’T CARE NOTES: 1. To write data before burst read ends, DQM should be asserted three cycles prior to write command to avoid bus contention. 2. Row precharge will interrupt writing. Last data input, tRDL before Row precharge, will be written. 3. DQM should mask invalid input data on precharge command cycle when asserting precharge before end of burst. Input data after Row precharge cycle will be masked internally. 15 White Electronic Designs Corporation • (508) 366-5151 • www.whiteedc.com EDI416S4030A White Electronic Designs FIG. 6 PAGE READ CYCLE AT DIFFERENT BANK @ BURST LENGTH=4 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 CLOCK HIGH CKE Note 1 CE RAS Note 2 CAS ADDR RAa CAa RBb CBb CAc CBd CAe BA A10/AP RAa RBb QAa0 CL = 2 QAa1 QAa2 QAa3 QBb0 QBb1 QBb2 QBb3 QAc0 QAc1 QBd0 QBd1 QAe0 QAe1 QAa0 QAa1 QAa2 QAa3 QBb0 QBb1 QBb3 QAc0 QAc1 QBd0 QBd1 QAe0 DQ CL = 3 QBb2 QAe1 WE DQM Row Active (A-Bank) Row Active (B-Bank) Read (B-Bank) Read (A-Bank) Read (B-Bank) Read (A-Bank) Precharge (A-Bank) DON’T CARE NOTES: 1. CE can be don’t cared when RAS, CAS and WE are high at the clock high going edge. 2. To interrupt a burst read by row precharge, both the read and the precharge banks must be the same. White Electronic Designs Corporation • Westborough, MA • (508) 366-5151 Read (A-Bank) 16 EDI416S4030A White Electronic Designs FIG. 7 PAGE WRITE CYCLE AT DIFFERENT BANK @ BURST LENGTH=4 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 CLOCK HIGH CKE CE RAS Note 2 CAS ADDR RAa CAa RBb CBb CAc CBd BA A10/AP RAa RBb t CDL DAa0 DQ DAa1 DAa2 DAa3 DBb0 t RDL DBb1 DBb2 DBb3 DAc0 DAc1 DBd0 DBd1 WE Note 1 DQM Row Active (A-Bank) Row Active (B-Bank) Write (B-Bank) Write (A-Bank) Write (A-Bank) Write (B-Bank) Precharge (Both Banks) DON’T CARE NOTES: 1. To interrupt burst write by Row precharge, DQM should be asserted to mask invalid input data. 2. To interrupt burst write by Row precharge, both the write and the precharge banks must be the same. 17 White Electronic Designs Corporation • (508) 366-5151 • www.whiteedc.com EDI416S4030A White Electronic Designs FIG. 8 READ & WRITE CYCLE AT DIFFERENT BANK @ BURST LENGTH=4 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 QAc0 QAc1 QAc2 QAc0 QAc1 CLOCK HIGH CKE CE RAS CAS ADDR RAa RBb CAa CBb RAc CAc BA A10/AP RAa RBb RAc t CDL QAa0 CL = 2 QAa1 QAa2 QAa3 QAa0 QAa1 QAa2 DBb0 DBb1 DBb2 DBb3 DBb0 DBb1 DBb2 DBb3 Note 1 DQ CL = 3 QAa3 WE DQM Row Active (A-Bank) Read (A-Bank) Precharge (A-Bank) Write (B-Bank) Row Active (B-Bank) Row Active (A-Bank) NOTE: 1. tCDL should be met to complete write. White Electronic Designs Corporation • Westborough, MA • (508) 366-5151 18 Read (A-Bank) DON’T CARE EDI416S4030A White Electronic Designs FIG. 9 READ & WRITE CYCLE WITH AUTO PRECHARGE @ BURST LENGTH=4 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 CLOCK HIGH CKE CE RAS CAS ADDR Ra Rb Ra Rb Ca Cb BA A10/AP Qa0 CL = 2 Qa1 Qa2 Qa3 Qa0 Qa1 Qa2 Db0 Db1 Db2 Db3 Db0 Db1 Db2 Db3 DQ CL = 3 Qa3 WE DQM Row Active (A-Bank) Read with Auto Precharge (A-Bank) Row Active (B-Bank) Auto Precharge Start Point (A-Bank) Write with Auto Precharge (B-Bank) Auto Precharge Start Point (B-Bank) DON’T CARE Note: 1. tCDL should be controlled to meet minimum tRAS before internal precharge start. (In the case of Burst Length=1 & 2 and BRSW mode) 19 White Electronic Designs Corporation • (508) 366-5151 • www.whiteedc.com EDI416S4030A White Electronic Designs FIG. 10 CLOCK SUSPENSION & DQM OPERATION CYCLE @ CAS LATENCY=2, BURST LENGTH=4 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 CLOCK CKE CE RAS CAS ADDR Ra Ca Cb Cc BA A10/AP Ra t SHZ Qa0 DQ Qa1 Qa2 t SHZ Qa3 Qb1 Qb1 Dc0 Dc2 WE Note 1 DQM Row Active Read Clock Suspension Read Write DQM Read DQM Write Write DQM Clock Suspension DON’T CARE Note: 1. DQM is needed to prevent bus contention. White Electronic Designs Corporation • Westborough, MA • (508) 366-5151 20 EDI416S4030A White Electronic Designs FIG. 11 READ INTERRUPTED BY PRECHARGE COMMAND & READ BURST STOP @ BURST LENGTH=FULL PAGE 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 QAb0 QAb1 QAb2 QAb3 QAb4 QAb5 QAb0 QAb1 QAb2 QAb3 QAb4 19 CLOCK HIGH CKE CE RAS CAS ADDR RAa CAa CAb BA A10/AP RAa Note 2 QAa0 CL = 2 1 QAa1 QAa2 QAa3 QAa4 QAa0 QAa1 QAa2 QAa3 1 DQ 2 CL = 3 QAa4 2 QAb5 WE DQM Row Active (A-Bank) Read (A-Bank) Burst Stop Read (A-Bank) Precharge (A-Bank) DON’T CARE NOTES: 1. At full page mode, burst is end at the end of burst. So auto precharge is possible. 2. About the valid DQs after burst stop, it is same as the case of RAS interrupt. Both cases are illustrated in above timing diagram. See the label 1, 2. But at burst write, Burst stop and RAS interrupt should be compared carefully. Refer to the timing diagram of “Full page write burst stop cycle.” 3. Burst stop is valid at every burst length. 21 White Electronic Designs Corporation • (508) 366-5151 • www.whiteedc.com EDI416S4030A White Electronic Designs FIG. 12 WRITE INTERRUPTED BY PRECHARGE COMMAND & WRITE BURST STOP CYCLE @ BURST LENGTH=FULL PAGE 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 CLOCK HIGH CKE CE RAS CAS ADDR RAa CAa CAb BA A10/AP RAa t BDL t RDL Note 2 DAa0 DQ DAa1 DAa2 DAa3 DAa4 DAb0 DAb1 DAb2 DAb3 DAb4 DAb5 WE DQM Row Active (A-Bank) Write (A-Bank) Burst Stop Write (A-Bank) Precharge (A-Bank) DON’T CARE NOTES: 1. At full page mode, burst is end at the end of burst. So auto precharge is possible. 2. Data-in at the cycle of interrupted by precharge cannot be written into the corresponding memory cell. It is defined by AC parameter of tRDL. DQM at write interrupted by precharge command is needed to prevent invalid write. DQM should mask invalid input data on precharge command cycle when asserting precharge before end of burst. Input data after Row precharge cycle will be masked internally. 3. Burst stop is valid at every burst length. White Electronic Designs Corporation • Westborough, MA • (508) 366-5151 22 EDI416S4030A White Electronic Designs FIG. 13 BURST READ SINGLE BIT WRITE CYCLE @ BURST LENGTH=2 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 QAd0 QAd1 19 CLOCK Note 1 HIGH CKE CE RAS Note 2 CAS ADDR RAa CAa RBb CAb RAc CBc CAd BA A10/AP RAa RBb DAa0 CL = 2 RAc QAb0 QAb1 DBc0 DQ DAa0 CL = 3 QAb0 QAb1 DBc0 QAd0 QAd1 WE DQM Row Active (A-Bank) Row Active (B-Bank) Write (A-Bank) Row Active (A-Bank) Read with Auto Precharge (A-Bank) Read (A-Bank) Write with Auto Precharge (B-Bank) Precharge (Both Banks) DON’T CARE NOTES: 1. BRSW mode is enabled by setting A9 “High” at MRS (Mode Register Set). At the BRSW Mode, the burst length at write is fixed to “1” regardless of programmed burst length. 2. When BRSW write command with auto precharge is executed, keep it in mind that tRAS should not be violated. Auto precharge is executed at the burst-end cycle, so in the case of BRSW write command, the next cycle starts the precharge. 23 White Electronic Designs Corporation • (508) 366-5151 • www.whiteedc.com EDI416S4030A White Electronic Designs FIG. 14 ACTIVE/PRECHARGE POWER DOWN MODE @ CAS LATENCY=2, BURST LENGTH=4 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 CLOCK Note 2 t SS t SS CKE t SS Note 1 Note 3 CE RAS CAS Ra ADDR Ca BA Ra A10/AP t SHZ Qa0 DQ Qa1 Qa2 WE DQM Precharge Power-Down Entry Row Active Read Precharge Active Power-Down Power-Down Exit Entry Active Power-Down Exit NOTES: 1 .Both banks should be in idle state prior to entering precharge power down mode. 2. CKE should be set high at least 1CLK + tss prior to Row active command. 3. Can not violate minimum refresh specification (64ms). White Electronic Designs Corporation • Westborough, MA • (508) 366-5151 24 Precharge DON’T CARE EDI416S4030A White Electronic Designs FIG. 15 SELF REFRESH ENTRY & EXIT CYCLE 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 CLOCK t SS CKE Note 2 t RFC min Note 3 Note 1 Note 6 Note 4 Note 5 CE RAS Note 7 CAS ADDR BA A10/AP DQ HI-Z HI-Z WE DQM Self Refresh Entry Self Refresh Exit Auto Refresh DON’T CARE NOTES: TO ENTER SELF REFRESH MODE 1. CE, RAS & CAS with CKE should be low at the same clock cycle. 2. After 1 clock cycle, all the inputs including the system clock can be don’t care except for CKE. 3. The device remains in self refresh mode as long as CKE stays “Low.” Once the device enters self refresh mode, minimum tRAS is required before exit from self refresh. TO EXIT SELF REFRESH MODE 4. System clock restart and be stable before returning CKE high. 5. CE starts from high. 6. Minimum tRFC is required after CKE going high to complete self refresh exit. 7. 4K cycle of burst auto refresh is required before self refresh entry and after self refresh exit if the system uses burst refresh. 25 White Electronic Designs Corporation • (508) 366-5151 • www.whiteedc.com EDI416S4030A White Electronic Designs FIG. 16 MODE REGISTER SET CYCLE 0 1 2 3 4 5 6 7 FIG. 17 AUTO REFRESH CYCLE 8 0 1 2 3 4 5 6 7 8 9 10 CLOCK HIGH HIGH CKE CE Note 2 t RFC RAS Note 1 CAS Note 3 Key ADDR DQ Ra HI-Z HI-Z WE DQM MRS New Command Auto Refresh New Command DON’T CARE NOTES: Both banks precharge should be completed before Mode Register Set cycle and auto refresh cycle. MODE REGISTER SET CYCLE 1. CE, RAS, CAS, & WE activation at the same clock cycle with address key will set internal mode register. 2. Minimum 2 clock cycles should be met before new RAS activation. 3. Please refer to Mode Register Set table. White Electronic Designs Corporation • Westborough, MA • (508) 366-5151 26 EDI416S4030A White Electronic Designs PACKAGE DIMENSION: 54 PIN TSOP II 22.35 (0.880) 22.10 (0.870) Note 1 VIEW A 1.20 (0.047) MAX 11.96 (0.471) 11.56 (0.455) 10.29 (0.405) 10.03 (0.395) Note 2 0.15 (0.006) 0.05 (0.002) 0.80 (0.0315) TYP 0.61 (0.024) 0.41 (0.016) 0.51 (0.020) 0.25 (0.010) SEE VIEW A NOTES: 1. Dimension does not include 0.006 inch Flash each side. 2. Dimension does not include 0.010 inch Flash each side. 0-8 0.203 (0.008) 0.125 (0.005) ALL LINEAR DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES ORDERING INFORMATION Part Number Organization Operating Frequency Package EDI416S4030A10SI 1Mx16bitsx4banks 100MHz 54 TSOP II EDI416S4030A12SI 1Mx16bitsx4banks 83MHz 54 TSOP II NOTE: This product does not include the prefix "EDI" for part marking due to package size constraints. 27 White Electronic Designs Corporation • (508) 366-5151 • www.whiteedc.com