EDI88130CS White Electronic Designs 128Kx8 Monolithic SRAM, SMD 5962-89598 FEATURES The EDI88130CS is a high speed, high performance, 128Kx8 bits monolithic Static RAM. ■ Access Times of 15*, 17, 20, 25, 35, 45, 55ns ■ Battery Back-up Operation 2V Data Retention (EDI88130LPS) An additional chip enable line provides system memory security during power down in non-battery backed up systems and memory banking in high speed battery backed systems where large multiple pages of memory are required. ■ CS1, CS2 & OE Functions for Bus Control ■ Inputs and Outputs Directly TTL Compatible ■ Organized as 128Kx8 ■ Commercial, Industrial and Military Temperature Ranges The EDI88130CS has eight bi-directional input-output lines to provide simultaneous access to all bits in a word. ■ Thru-hole and Surface Mount Packages JEDEC Pinout A low power version, EDI88130LPS, offers a 2V data retention function for battery back-up applications. 32 pin Sidebrazed Ceramic DIP, 400 mil (Package 102) 32 pin Sidebrazed Ceramic DIP, 600 mil (Package 9) Military product is available compliant to MIL-PRF-38535. 32 lead Ceramic SOJ (Package 140) *15ns access time is advanced information, contact factory for availability. 32 pad Ceramic Quad LCC (Package 12) 32 pad Ceramic LCC (Package 141) 32 lead Ceramic Flatpack (Package 142) ■ Single +5V (±10%) Supply Operation PIN CONFIGURATION 32 DIP 32 SOJ 32 CLCC 32 FLATPACK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 TOP VIEW I/O0-7 Data Inputs/Outputs A0-16 Address Inputs A12 A14 A16 NC VCC A15 CS2 TOP VIEW NC A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 AØ I/OØ I/O1 I/O2 VSS WE Write Enable CS1, CS2 Chip Selects 4 32 VCC 31 A15 30 CS2 29 WE 28 A13 27 A8 26 A9 25 A11 24 OE 23 A10 22 CS1 21 I/O7 20 I/O6 19 I/O5 18 I/O4 17 I/O3 PIN DESCRIPTION 32 QUAD LCC A7 A6 A5 A4 A3 A2 A1 A0 I/O0 3 2 1 32 31 30 5 29 6 28 7 27 8 26 9 25 10 24 11 23 12 22 WE A13 A8 A9 A11 OE A10 CS1 I/O7 21 13 14 15 16 17 18 19 OE Output Enable VCC Power (+5V ±10%) V SS Ground NC Not Connected BLOCK DIAGRAM Memory Array 20 I/O1 I/O2 VSS I/O3 I/O4 I/O5 I/O6 FIG. 1 Aÿ-16 Address Buffer Address Decoder I/O Circuits I/Oÿ-7 WE CS1 CS2 OE March 2002 Rev. 11 1 White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com EDI88130CS White Electronic Designs TRUTH TABLE ABSOLUTE MAXIMUM RATINGS Parameter Voltage on any pin relative to Vss Operating Temperature TA (Ambient) Industrial Military Storage Temperature, Ceramic Power Dissipation Output Current Junction Temperature, TJ -0.2 to 7.0 Unit V -40 to +85 -55 to +125 -65 to +150 1.7 40 175 °C °C °C W mA °C Typ 5.0 0 CS2 WE Mode Output Power H X L L L X L H H H X X H H L Standby Standby Output Deselect Read Write High Z High Z High Z Data Out Data In Icc 2 , Icc 3 Icc 2 , Icc 3 Icc 1 Icc 1 Icc 1 Parameter Address Lines Data Lines Max LCC CSOJ,DIP, Unit Symbol Condition CI CO VIN = Vcc or Vss, f = 1.0MHz VOUT = Vcc or Vss, f = 1.0MHz Flatpack 6 8 12 14 pF pF These parameters are sampled, not 100% tested. RECOMMENDED OPERATING CONDITIONS Min 4.5 0 2.2 -0.5 CS1 X X H L X CAPACITANCE (TA = +25°C) NOTE: Stress greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions greater than those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Parameter Symbol Supply Voltage VCC Supply Voltage V SS Input High Voltage VIH Input Low Voltage VIL OE Max Unit 5.5 V 0 V Vcc +0.5 V +0.8 V DC CHARACTERISTICS (VCC = 5V, TA = -55°C TO +125°C) Parameter Symbol Conditions Input Leakage Current Output Leakage Current IL I ILO VIN = 0V to VCC VI /O = 0V to VCC Operating Power Supply Current I CC 1 WE, CS1 = VIL, II /O = 0mA, CS2 = VIH Standby (TTL) Power Supply Current I CC 2 Full Standby Power Supply Current I CC 3 Output Low Voltage Output High Voltage VOL VOH (15-17ns) (20ns) (25-55ns) CS1 ³ VIH and/or CS2 £ VIL, (17-55ns) VIN ³ VIH or £ VIL (15ns) CS (17-55ns) CS1 ³ VCC -0.2V and/or CS2 £ 0.2V CS (15ns) VIN ³ VCC -0.2V or VIN £ 0.2V LPS I OL = 8.0mA I OH = -4.0mA Min 2.4 Typ 3 Max ±5 ±10 300 225 200 25 60 10 15 5 0.4 Units µA µA mA mA mA mA mA mA mA mA V V AC TEST CONDITIONS Figure 1 Figure 2 Vcc 480Ω Q Input Pulse Levels Input Rise and Fall Times Input and Output Timing Levels Output Load Vcc 480Ω NOTE: For tEHQZ, tGHQZ and tWLQZ, CL = 5pF Figure 2) Q 255Ω 30pF VSS to 3.0V 3ns 1.5V Figure 1 255Ω White Electronic Designs Corporation Phoenix AZ (602) 437-1520 5pF 2 EDI88130CS White Electronic Designs AC CHARACTERISTICS READ CYCLE (15 TO 20NS) (VCC = 5.0V, VSS = 0V, TA = -55°C TO +125°C) Parameter Read Cycle Time Address Access Time Chip Enable Access Time Chip Enable to Output in Low Z (1) Chip Disable to Output in Low Z (1) Output Hold from Address Change Output Enable to Output Valid Output Enable to Output in Low Z (1) Output Disable to Output in High Z(1) Chip Enable to Power Up (1) Chip Enable to Power Down (1) Symbol JEDEC Alt. t AVAV t RC t AVQV t AA t E1LQV t E2HQV t E1LQX t E2HQX t E1HQZ t E2LQZ t AVQX t GLQV t GLQX tGHQZ t E1LICCH t E2HICCH t E1HICCL t E2LICCL 15ns* Min 15 t ACS t ACS t CLZ t CLZ t CHZ t CHZ t OH t OE tOLZ tOHZ t PU t PU t PD t PD 17ns Max Min 17 20ns Max Min 20 Max 15 17 20 15 15 17 17 20 20 5 5 5 5 7 7 3 8 8 3 3 6 6 0 7 0 0 5 6 0 0 ns ns ns ns ns ns ns ns ns ns ns ns ns ns 5 5 6 6 8 0 0 0 0 15 15 17 17 Units ns ns 20 20 1. This parameter is guaranteed by design but not tested. * 15ns access time is advanced information, contact factory for availability. AC CHARACTERISTICS READ CYCLE (25 TO 55NS) (VCC = 5.0V, VSS = 0V, TA = -55°C TO +125°C) Parameter Read Cycle Time Address Access Time Chip Enable Access Time Chip Enable Access Time Chip Enable to Output in Low Z (1) Chip Disable to Output in Low Z (1) Output Hold from Address Change Output Enable to Output Valid Output Enable to Output in Low Z (1) Output Disable to Output in High Z(1) Chip Enable to Power Up (1) Chip Enable to Power Down (1) Symbol JEDEC Alt. t AVAV t RC t AVQV t AA t E1LQV t E2HQV t E1LQX t E2HQX t E1HQZ t E2LQZ t AVQX t GLQV t GLQX tGHQZ t E1LICCH t E2HICCH t E1HICCL t E2LICCL t ACS t ACS t CLZ t CLZ t CHZ t CHZ t OH t OE tOLZ tOHZ t PU t PU t PD t PD Min 25 25ns Max Min 35 35ns Max 45ns Min 45 Max Min 55 55ns Max 25 35 45 55 25 25 35 35 45 45 55 55 5 5 5 5 10 10 0 5 5 15 15 0 10 0 10 0 15 0 25 0 20 0 0 35 35 20 20 20 0 0 0 25 25 20 20 15 0 0 0 5 5 20 0 0 45 45 55 55 Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 1. This parameter is guaranteed by design but not tested. 3 White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com EDI88130CS White Electronic Designs AC CHARACTERISTICS WRITE CYCLE (15 TO 20NS) (VCC = 5.0V, VSS = 0V, TA = -55°C TO +125°C) Parameter Write Cycle Time Chip Enable to End of Write Address Setup Time Address Valid to End of Write Write Pulse Width Write Recovery Time Data Hold Time Write to Output in High Z (1) Data to Write Time Output Active from End of Write (1) Symbol JEDEC Alt. t AVAV t WC t E1LWH t CW t E1LE1H t CW t CW t E2HWH t E2HE2L t CW t AVWL t AS t AVE1L t AS t AVE2H t AS t AVWH t AW t WLWH t WP t WLE1H t WP t WLE2L t WP t WHAX t WR t E1HAX t WR tE2LAX t WR t WHDX t DH t E1HDX t DH t E2LDX t DH t WLQZ t WHZ t DW t DVWH t DVE1H t DW t DVE2L t DW t WHQX t WLZ 15ns* Min 15 12 12 12 12 0 0 0 12 12 12 12 0 0 0 0 0 0 0 7 7 7 3 17ns Max 7 Min 17 13 13 13 13 0 0 0 13 13 13 13 0 0 0 0 0 0 0 8 8 8 3 20ns Max Min 20 15 15 15 15 0 0 0 15 15 15 15 0 0 0 0 0 0 0 10 10 10 3 8 Max Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 8 1. This parameter is guaranteed by design but not tested. AC CHARACTERISTICS WRITE CYCLE (25 TO 55NS) (VCC = 5.0V, VSS = 0V, TA = -55°C TO +125°C) Symbol JEDEC Alt. t AVAV t WC t E1LWH t CW t E1LE1H t CW t E2HWH t CW t E2HE2L t CW Address Setup Time t AVWL t AS t AVE1L t AS t AVE2H t AS Address Valid to End of Write t AVWH t AW t AVEH t AW Write Pulse Width t WLWH t WP t WLE1H t WP t WLE2L t WP Write Recovery Time t WHAX t WR tE1HAX t WR tE2LAX t WR Data Hold Time t WHDX t DH t E1HDX t DH t E2LDX t DH Write to Output in High Z (1) t WLQZ t WHZ Data to Write Time t DVWH t DW t DVE1H t DW t DVE2L t DW t WLZ Output Active from End of Write (1) t WHQX Parameter Write Cycle Time Chip Enable to End of Write Min 25 20 16 0 0 0 20 20 20 20 20 0 0 0 0 0 0 0 15 15 15 3 25ns Max 16 16 10 1. This parameter is guaranteed by design but not tested. White Electronic Designs Corporation Phoenix AZ (602) 437-1520 4 35ns Min 35 25 20 0 0 0 25 25 30 30 30 0 0 0 0 0 0 0 20 20 20 3 45ns Max 20 20 13 Min 45 35 25 0 0 0 35 35 30 30 30 5 5 5 0 0 0 0 20 20 20 3 Max 25 25 15 Min 55 45 40 0 0 0 45 45 35 35 35 5 5 5 0 0 0 0 25 25 25 3 55ns Max 40 40 20 Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns EDI88130CS White Electronic Designs FIG. 2 TIMING WAVEFORM - READ CYCLES tAVAV ADDRESS tAVQV CS1 tE1HQZ tE1HICCL tE2HQV tE2LICCL Icc tAVAV ADDRESS tE1LQV tE1LQX tE1LICCH ADDRESS 1 ADDRESS 2 CS2 tAVQX tAVQV DATA I/O tE2HICCH tE2HQX OE DATA 1 tGLQV tGLQX DATA 2 tGHQZ DATA I/O READ CYCLE 1 (WE HIGH; OE, CS LOW) READ CYCLE 2 (CS1 AND/OR CS2 CONTROLLED, WE HIGH) FIG. 3 WRITE CYCLE 1 tAVAV ADDRESS tAVWL tAVWH tWLWH tWHAX WE tE1LWH CS1 CS2 tE2HWH tDVWH tWHDX DATA IN tWLQZ tWHQX DATA OUT WRITE CYCLE 1 - LATE WRITE, WE CONTROLLED FIG. 4 WRITE CYCLES 2 WRITE CYCLES 3 tAVAV tAVAV ADDRESS ADDRESS tAVE1L tE1LE1H t WS32K32-XHX t AVE2H tE1HAX WE WE CS1 CS1 CS2 E2HE2L tE2LAX CS2 tDVE1H tDVE2L tE1HDX DATA I/O tE2LDX DATA I/O WRITE CYCLE 2 - EARLY WRITE, CS1 CONTROLLED WRITE CYCLE 3 - EARLY WRITE, CS2 CONTROLLED 5 White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com EDI88130CS White Electronic Designs DATA RETENTION CHARACTERISTICS (EDI88130LPS ONLY) (TA = -55°C TO +125°C) Characteristic Low Power Version only Data Retention Voltage Data Retention Quiescent Current Chip Disable to Data Retention Time (1) Operation Recovery Time (1) Sym Conditions Min Typ Max Units VDD I CCDR TCDR TR VDD = 2.0V CS1 ³ VDD -0.2V and/or CS2 ³ V SS +0.2V VIN ³ VDD -0.2V or VIN £ 0.2V 2 0 0.5 2 V mA ns ns TAVAV* NOTE: 1. Parameter guaranteed by design, but not tested. * Read Cycle Time FIG. 5 DATA RETENTION - CS1 CONTROLLED WS32K32-XHX Data Retention Mode Vcc 4.5V 4.5V VDD tCDR tR CS1 CS1 VDD -0.2V DATA RETENTION, CS1 CONTROLLED FIG. 6 DATA RETENTION - CS2 CONTROLLED WS32K32-XHX Data Retention Mode Vcc 4.5V 4.5V VDD tCDR CS2 tR CS2 0.2V DATA RETENTION, CS2 CONTROLLED White Electronic Designs Corporation Phoenix AZ (602) 437-1520 6 EDI88130CS White Electronic Designs PACKAGE 12: 32 PIN CERAMIC QUAD LCC 0.120 0.060 0.028 0.022 0.020 X 45 REF. 0.050 BSC. 0.560 0.540 0.055 0.045 0.458 0.442 0.040 X 45 REF. ALL DIMENSIONS ARE IN INCHES PACKAGE 9: 32 PIN SIDEBRAZED CERAMIC DIP (600 MILS WIDE) 1.616 1.584 0.200 0.125 0.061 0.017 0.620 0.600 0.060 0.040 Pin 1 Indicator 0.100 TYP 0.020 0.016 0.155 0.115 0.600 NOM 15 x 0.100 = 1.500 ALL DIMENSIONS ARE IN INCHES PACKAGE 102: 32 PIN SIDEBRAZED CERAMIC DIP (400 MILS WIDE) 1.616 1.584 0.200 0.125 0.061 0.017 0.420 0.400 0.060 0.040 Pin 1 Indicator 0.100 TYP 0.020 0.016 0.155 0.115 0.400 NOM 15 x 0.100 = 1.500 ALL DIMENSIONS ARE IN INCHES 7 White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com EDI88130CS White Electronic Designs PACKAGE 140: 32 LEAD CERAMIC SOJ 0.108 0.088 0.840 0.820 0.040 0.030 0.440 0.430 0.379 REF 0.155 0.120 0.050 TYP ALL DIMENSIONS ARE IN INCHES PACKAGE 141: 32 PAD CERAMIC LCC 0.096 0.080 0.028 0.022 0.840 0.820 0.050 TYP 0.405 0.395 ALL DIMENSIONS ARE IN INCHES PACKAGE 142: 32 PIN CERAMIC FLATPACK 0.830 0.810 0.007 0.003 0.420 0.400 1.00 REF 0.290 0.270 0.040 0.030 Pin 1 0.045 0.020 0.370 0.250 0.019 0.015 0.050 TYP ALL DIMENSIONS ARE IN INCHES White Electronic Designs Corporation Phoenix AZ (602) 437-1520 8 0.116 0.100 White Electronic Designs EDI88130CS ORDERING INFORMATION EDI 8 8 130 CS X X X WHITE ELECTRONIC DESIGNS SRAM ORGANIZATION, 128Kx8 (130 = Dual CS) TECHNOLOGY: CS = CMOS Standard Power (5V) LPS = Low Power ACCESS TIME (ns) PACKAGE TYPE: C = 32 lead Sidebrazed DIP, 600 mil (Package 9) F = 32 lead Ceramic Flatpack (Package 142) L = 32 pad Ceramic LCC (Package 141) L32 = 32 pad Ceramic Quad LCC (Package 12) N = 32 lead Ceramic SOJ (Package 140) T = 32 lead Sidebrazed DIP, 400 mil (Package 102) DEVICE GRADE: B = MIL-STD-883 Compliant M = Military Screened I = Industrial C = Commercial -55°C to +125°C -40°C to +85°C 0°C to +70°C 9 White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com