EDI88257CA HI-RELIABILITY PRODUCT 256Kx8 Monolithic SRAM FEATURES ■ Access Times of 20, 25, 35, 45, 55ns The EDI88257CA is a 2 Megabit 256Kx8 bit Monolithic CMOS Static RAM. ■ Data Retention Function (LPA Versions) The 32 pin DIP pinout adheres to the JEDEC evolutionary standard for the two megabit device. The device is upgradeable to the 512Kx8 SRAM, the EDI88512CA. Pin 1 becomes the higher order address. ■ TTL Compatible Inputs and Outputs ■ Fully Static, No Clocks ■ Organized as 256Kx8 ■ Commercial, Industrial and Military Temperature Ranges A Low Power version, EDI88257LPA, offers a data retention function for battery back-up opperation. Military product is available compliant to Appendix A of MIL-PRF-38535. ■ JEDEC Approved Evolutionary Pinout • 32 pin Ceramic DIP, 0.6 mils wide (Package 9) ■ Single +5V (±10%) Supply Operation FIG. 1 PIN CONFIGURATION PIN DESCRIPTION 32 DIP TOP VIEW NC A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 AØ I/OØ I/O1 I/O2 VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 VCC 31 A15 30 A17 29 WE 28 A13 27 A8 26 A9 25 A11 24 OE 23 A10 22 CS 21 I/O7 20 I/O6 19 I/O5 18 I/O4 17 I/O3 BLOCK DIAGRAM I/O0-7 Data Inputs/Outputs A0-17 Address Inputs WE Write Enable CS Chip Selects OE Output Enable VCC Power (+5V ±10%) VSS Ground NC Not Connected Memory Array AØ-17 Address Buffer Address Decoder I/O Circuits I/OØ-7 WE CS OE May 2000 Rev. 2 1 White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com EDI88257CA TRUTH TABLE ABSOLUTE MAXIMUM RATINGS Parameter Voltage on any pin relative to Vss Unit OE CS WE Mode Output Power V X H L X H L L L X H H L Standby Output Deselect Read Write High Z High Z Data Out Data In Icc 2 , Icc 3 Icc 1 Icc 1 Icc 1 -0.5 to 7.0 Operating Temperature TA (Ambient) Industrial -40 to +85 °C Military -55 to +125 °C Storage Temperature, Ceramic -65 to +150 °C Power Dissipation 1.5 W Output Current 20 mA Junction Temperature, TJ 175 °C RECOMMENDED OPERATING CONDITIONS Parameter NOTE: Stress greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions greater than those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Symbol Min Typ Max Supply Voltage VCC 4.5 5.0 5.5 Unit V Supply Voltage VSS 0 0 0 V Input High Voltage VIH 2.2 — Vcc +0.5 V Input Low Voltage VIL -0.3 — +0.8 V CAPACITANCE (T A = +25°C) Parameter Symbol Condition Max Unit Address Lines CI VIN = Vcc or Vss, f = 1.0MHz 12 pF Input/Output Lines CO VOUT = Vcc or Vss, f = 1.0MHz 14 pF These parameters are sampled, not 100% tested. DC CHARACTERISTICS (VCC = 5V, TA = +25°C) Parameter Symbol Conditions Units Min Typ Max µA Input Leakage Current ILI VIN = 0V to VCC -10 — +10 Output Leakage Current ILO VI/O = 0V to VCC -10 — +10 µA — 225 mA — 200 mA — 60 mA Operating Power Supply Current I CC1 WE, CS = VIL, II/O = 0mA, Min Cycle Standby (TTL) Power Supply Current I CC2 CS ≥ VIH, VIN ≤ VIL, VIN ≥ VIH Full Standby Power Supply Current I CC3 CS ≥ VCC -0.2V VIN ≥ Vcc -0.2V or VIN ≤ 0.2V Output Low Voltage VOL Output High Voltage VOH (20-25ns) (35-55ns) CA — — 25 mA LPA — — 20 mA IOL = 8.0mA — — 0.4 V IOH = -4.0mA 2.4 — — V NOTE: DC test conditions: VIL = 0.3V, VIH = Vcc -0.3V White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com 2 EDI88257CA AC CHARACTERISTICS – READ CYCLE (VCC = 5.0V, VSS = 0V, TA = -55°C to +125°C)) Parameter Symbol JEDEC Alt. 20ns Min Max Min 25ns Read Cycle Time tAVAV tRC 20 25 Address Access Time tAVQV tAA Chip Select Access Time tELQV tACS Chip Select to Output in Low Z (1) tELQX tCLZ 3 Chip Disable to Output in High Z (1) tEHQZ tCHZ 0 Output Hold from Address Change tAVQX tOH 0 Output Enable to Output Valid tGLQV tOE 20 tGLQX tOLZ 0 tGHQZ tOHZ 0 45ns Min Max 55ns Min Max 35 45 55 35 25 8 0 3 10 0 0 0 0 0 10 0 20 0 ns 55 ns 20 ns 25 ns 20 ns ns 0 0 ns 25 0 15 55 3 0 15 0 8 15 0 12 45 3 Units ns 45 35 3 10 Output Enable to Output in Low Z (1) 35ns Min Max 25 20 Output Disable to Output in High Z (1) Max 0 20 ns 0 1. This parameter is guaranteed by design but not tested. AC CHARACTERISTICS – WRITE CYCLE (VCC = 5.0V, VSS = 0V, TA = -55°C to +125°C) Parameter Symbol JEDEC Alt. 20ns Min Max Min Write Cycle Time tAVAV tWC 20 Chip Select to End of Write tELWH tELEH tCW tCW Address Setup Time tAVWL tAVEL Address Valid to End of Write 35ns Min Max 45ns Min Max 55ns Min Max 25 35 45 45 ns 15 15 17 17 25 25 30 30 30 30 ns ns tAS tAS 0 0 0 0 0 0 0 0 0 0 ns ns tAVWH tAVEH tAW tAW 15 15 17 17 25 25 30 30 30 30 ns ns Write Pulse Width tWLWH tWLEH tWP tWP 15 15 17 17 25 25 30 30 30 30 ns ns Write Recovery Time tWHAX tEHAX tWR tWR 0 0 0 0 0 0 0 0 0 0 ns ns Data Hold Time tWHDX tEHDX tDH tDH 0 0 0 0 0 0 0 0 0 0 ns ns Write to Output in High Z (1) tWLQZ tWHZ 0 Data to Write Time tDVWH tDVEH tDW tDW 10 10 12 12 20 20 25 25 25 25 ns ns Output Active from End of Write (1) tWHQX tWLZ 0 0 0 0 0 ns 8 0 25ns Max 10 0 25 0 30 0 Units 30 ns 1. This parameter is guaranteed by design but not tested. AC TEST CONDITIONS Figure 1 Figure 2 Vcc 480Ω Input Pulse Levels Input Rise and Fall Times Input and Output Timing Levels Output Load Vcc 480Ω VSS to 3.0V 5ns 1.5V Figure 1 NOTE: For tEHQZ, tGHQZ and tWLQZ, CL = 5pF Figure 2) Q Q 255Ω 30pF 255Ω 5pF 3 White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com EDI88257CA FIG. 2 TIMING WAVEFORM - READ CYCLE tAVAV ADDRESS tAVQV CS tAVAV ADDRESS ADDRESS 1 ADDRESS 2 tAVQV tAVQX tELQV tELQX tEHQZ tGLQV tGLQX tGHQZ OE DATA I/O DATA 1 DATA OUT DATA 2 READ CYCLE 2 (WE HIGH) READ CYCLE 1 (WE HIGH; OE, CS LOW) FIG. 3 WRITE CYCLE - WE CONTROLLED tAVAV ADDRESS tAVWH tELWH tWHAX CS tAVWL tWLWH WE tDVWH DATA IN tWHDX DATA VALID tWLQZ tWHQX HIGH Z DATA OUT WRITE CYCLE 1, WE CONTROLLED FIG. 4 WRITE CYCLE - CS CONTROLLED tAVAV WS32K32-XHX ADDRESS tAVEH tELEH tEHAX CS tAVEL tWLEH WE tDVEH DATA IN DATA VALID HIGH Z DATA OUT WRITE CYCLE 2, CS CONTROLLED White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com tEHDX 4 EDI88257CA DATA RETENTION CHARACTERISTICS (EDI88257LPA ONLY) (TA = -55°C to +125°C) Characteristic Low Power Version only Sym Conditions Min Typ Max Units Data Retention Voltage VDD VDD = 2.0V 2 – – V Data Retention Quiescent Current ICCDR CS ≥ VDD -0.2V – – 2 mA Chip Disable to Data Retention Time TCDR VIN ≥ VDD -0.2V Operation Recovery Time TR or VIN ≤ 0.2V 0 – – ns TAVAV – – ns FIG. 5 DATA RETENTION - CS CONTROLLED Data Retention Mode 4.5V Vcc WS32K32-XHX VDD 4.5V tCDR CS tR CS = VDD -0.2V DATA RETENTION, CS CONTROLLED 5 White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com EDI88257CA PACKAGE 9: 32 PIN SIDEBRAZED CERAMIC DIP (600mils wide) 1.616 1.584 0.175 0.125 0.061 0.017 0.620 0.600 0.060 0.040 Pin 1 Indicator 0.100 TYP 0.020 0.016 0.155 0.115 0.600 NOM 15 x 0.100 = 1.500 ALL DIMENSIONS ARE IN INCHES ORDERING INFORMATION EDI 8 8 257 CA X X X WHITE ELECTRONIC DESIGNS SRAM ORGANIZATION, 256Kx8 TECHNOLOGY: CA = CMOS Standard Power LPA = Low Power ACCESS TIME (ns) PACKAGE TYPE: C = 32 lead Sidebrazed DIP, 600 mil (Package 9) DEVICE GRADE: B = MIL-STD-883 Compliant M = Military Screened -55°C to +125°C I = Industrial -40°C to +85°C C = Commercial 0°C to +70°C White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com 6