WEDC WS128K32N

White Electronic Designs
WS128K32-XG2TXE
ADVANCED*
128Kx32 SRAM MULTICHIP PACKAGE, RADIATION TOLLERANT
FEATURES
Access Times of 35, 45, 55ns
TTL Compatible Inputs and Outputs
Packaging
• 68 lead, 22.4mm CQFP (G2T), 4.57mm (0.180"),
(Package 509)
Built in Decoupling Caps and Multiple Ground Pins
for Low Noise Operation
Weight
Organized as 128Kx32; User Configurable as
256Kx16 or 512Kx8
Low Power Data Retention
Commercial, Industrial and Military Temperature
Ranges
5V Power Supply
Low Power CMOS
WS128K32-XG2TXE – 8 grams typical
Radiation tolerant with epitaxial layer on die.
6T memory cells provide excellent protection
against soft errors
* This product is under development, is not qualified or characterized and is subject to
change or cancellation without notice.
FIGURE 1 – PIN CONFIGURATION FOR WS128K32N-XG2TXE
Top View
Pin Description
NC
A0
A1
A2
A3
A4
A5
CS3#
GND
CS4#
WE1#
A6
A7
A8
A9
A10
VCC
I/O0-31
A0-16
WE1-4#
CS1-4#
OE#
VCC
GND
NC
9 8 7 6 5 4
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
3 2 1 68 67 66 65 64 63 62 61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
I/O16
I/O17
I/O18
I/O19
I/O20
I/O21
I/O22
I/O23
GND
I/O24
I/O25
I/O26
I/O27
I/O28
I/O29
I/O30
I/O31
The White 68 lead G2T CQFP fills
the same fit and function as the
JEDEC 68 lead CQFJ or 68 PLCC.
But the G2T has the TCE and lead
inspection advantage of the CQFP
form.
Block Diagram
WE1# CS1#
128K x 8
8
I/O0-7
December 2000
Rev. 0
WE2# CS2#
WE3# CS3#
WE4# CS4#
OE#
A0-16
VCC
A11
A12
A13
A14
A15
A16
CS1#
OE#
CS2#
NC
WE2#
WE3#
WE4#
NC
NC
NC
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
GND
I/O8
I/O9
I/O10
I/O11
I/O12
I/O13
I/O14
I/O15
Data Inputs/Outputs
Address Inputs
Write Enables
Chip Selects
Output Enable
Power Supply
Ground
Not Connected
1
128K x 8
8
I/O8-15
128K x 8
8
I/O16-23
128K x 8
8
I/O24-31
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
White Electronic Designs
WS128K32-XG2TXE
ADVANCED
ABSOLUTE MAXIMUM RATINGS
Parameter
Operating Temperature
Storage Temperature
Signal Voltage Relative to GND
Junction Temperature
Supply Voltage
Symbol
TA
TSTG
VG
TJ
VCC
Min
-55
-65
-0.5
Max
+125
+150
VCC+0.5
150
7.0
-0.5
TRUTH TABLE
CS#
H
L
L
L
Unit
°C
°C
V
°C
V
OE#
X
L
X
H
RECOMMENDED OPERATING CONDITIONS
Parameter
Supply Voltage
Input High Voltage
Input Low Voltage
Opertating Temp. (MIL)
Symbol
VCC
VIH
VIL
TA
Min
4.5
2.2
-0.3
-55
Max
5.5
VCC + 0.3
+0.8
+125
Functional
Latch-up
Parametric
(Krads)
(Krads)
Typical Iccsb (mA)
30
30
1.2
25°C
SEU LET
Threshold
VCC Max
(VCC MIN)
2
Data I/O
High Z
Data Out
Data In
High Z
Power
Standby
Active
Active
Active
TA = +25°C
Unit
V
V
V
°C
Parameter
OE# capacitance
WE1-4# capacitance
CQFP G2T
CS1-4# capacitance
Data# I/O capacitance
Address input capacitance
Symbol
Conditions
COE
VIN = 0V, f = 1.0 MHz
CWE
VIN = 0V, f = 1.0 MHz
CCS
CI/O
CAD
Max Unit
50 pF
pF
20
VIN = 0V, f = 1.0 MHz 20 pF
VI/O = 0V, f = 1.0 MHz 20 pF
VIN = 0V, f = 1.0 MHz 50 pF
This parameter is guaranteed by design but not tested.
Cross
Section
/BIT
(MeV/mg/cm2) (MeV/mg/cm2)
>100
Mode
Standby
Read
Write
Out Disable
CAPACITANCE
RADIATION CHARACTERISTICS
Total Dose (TM1019.5)
WE#
X
H
L
H
(E-6 cm2)
0.2
DC CHARACTERISTICS
VCC = 5.0V, VSS = 0V, -55°C ≤ TA ≤ +125°C
Parameter
Sym
Conditions
Input Leakage Current
Output Leakage Current
Operating Supply Current
Standby Current
Output Low Voltage
Output High Voltage
ILI
ILO
ICC
ISB
VOL
VOH
VCC = 5.5, VIN = GND to VCC
CS# = VIH, OE# = VIH, VOUT = GND to VCC
CS# = VIL, OE# = VIH, f = 5MHz, VCC = 5.5
CS# = VIH, OE# = VIH, f = 5MHz, VCC = 5.5
IOL = 8mA, VCC = 4.5
IOH = -40mA, VCC = 4.5
Min
Max
Units
10
10
520
8
0.4
µA
µA
mA
mA
V
V
Max
—
1
—
—
Units
V
mA
ns
ns
2.4
NOTE: DC test conditions: VIH = VCC -0.3V, VIL = 0.3V
DATA RETENTION CHARACTERISTICS
-55°C ≤ TA ≤ +125°C
Characteristic
Data Retention Voltage
Data Retention Quiescent Current
Chip Disable to Data Retention Time (1)
Operation Recovery Time (1)
Sym
VCC
ICCDR
TCDR
TR
Conditions
VCC = 2.0V
CS ≥ VCC -0.2V
VIN ≥ VCC -0.2V
or VIN ≤ 0.2V
Min
2
—
0
TRC
NOTE: Parameter guaranteed, but not tested.
December 2000
Rev. 0
2
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
White Electronic Designs
WS128K32-XG2TXE
ADVANCED
AC CHARACTERISTICS
VCC = 5.0V, GND = 0V, -55°C ≤ TA ≤ +125°C
Parameter
Read Cycle
Read Cycle Time
Address Access Time
Output Hold from Address Change
Chip Select Access Time
Output Enable to Output Valid
Chip Select to Output in Low Z
Output Enable to Output in Low Z
Chip Disable to Output in High Z
Output Disable to Output in High Z
Symbol
tRC
tAA
tOH
tACS
tOE
tCLZ1
tOLZ1
tCHZ1
tOHZ1
-35
Min
35
-45
Max
Min
45
35
3
-55
Max
3
Units
Max
45
ns
ns
ns
ns
ns
ns
ns
ns
ns
55
3
35
15
3
0
Min
55
45
20
3
0
55
30
3
0
20
12
20
15
20
20
1. This parameter is guaranteed by design but not tested.
AC CHARACTERISTICS
VCC = 5.0V, GND = 0V, -55°C ≤ TA ≤ +125°C
Parameter
Write Cycle
Write Cycle Time
Chip Select to End of Write
Address Valid to End of Write
Data Valid to End of Write
Write Pulse Width
Address Setup Time
Address Hold Time
Output Active from End of Write
Write Enable to Output in High Z
Data Hold Time
Symbol
tWC
tCW
tAW
tDW
tWP
tAS
tAH
tOW1
tWHZ1
tDH
-35
Min
35
25
25
20
25
0
0
0
-45
Max
Min
45
35
35
25
35
0
0
0
10
0
-55
Max
Min
55
45
45
25
45
0
0
0
15
0
Units
Max
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
20
0
1. This parameter is guaranteed by design but not tested.
FIGURE 2 – AC TEST CIRCUIT
AC Test Conditions
Parameter
Input Pulse Levels
Input Rise and Fall
Input and Output Reference Level
Output Timing Reference Level
I OL
Current Source
VZ
D.U.T.
1.5V
I OH
Current Source
December 2000
Rev. 0
Unit
V
ns
V
V
Notes:
V Z is programmable from -2V to +7V.
IOL & IOH programmable from 0 to 16mA.
Tester Impedance Z0 = 75Ω.
V Z is typically the midpoint of VOH and VOL.
IOL & IOH are adjusted to simulate a typical resistive load circuit.
ATE tester includes jig capacitance.
(Bipolar Supply)
C eff = 50 pf
Typ
VIL = 0, VIH = 3.0
5
1.5
1.5
3
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
White Electronic Designs
WS128K32-XG2TXE
ADVANCED
FIGURE 3 – TIMING WAVEFORM - READ CYCLE
CS#
OE#
READ CYCLE 2 (WE# = VIH)
READ CYCLE 1, (CS# = OE# = VIL, WE# = VIH)
FIGURE 4 – WRITE CYCLE - WE# CONTROLLED
CS#
WE#
WRITE CYCLE 1, WE# CONTROLLED
FIGURE 5 – WRITE CYCLE - CS# CONTROLLED
WS32K32-XHX
CS#
WE#
WRITE CYCLE 2, CS# CONTROLLED
December 2000
Rev. 0
4
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
White Electronic Designs
WS128K32-XG2TXE
ADVANCED
PACKAGE 510: 68 LEAD, CERAMIC QUAD FLAT PACK, CQFP (G2T)
25.15 (0.990) ± 0.26 (0.010) SQ
4.57 (0.180) MAX
22.36 (0.880) ± 0.26 (0.010) SQ
0.27 (0.011) ± 0.04 (0.002)
0.25 (0.010) REF
Pin 1
R 0.25
(0.010)
24.03 (0.946)
± 0.26 (0.010)
0.19 (0.007)
± 0.06 (0.002)
1° / 7°
1.0 (0.040)
± 0.127 (0.005)
23.87
(0.940) REF
DETAIL A
1.27
(0.050)
TYP
SEE DETAIL "A"
0.38 (0.015) ± 0.05 (0.002)
20.3 (0.800) REF
The White 68 lead G2T CQFP
fills the same fit and function
as the JEDEC 68 lead CQFJ
or 68 PLCC. But the G2T has
the TCE and lead inspection
advantage of the CQFP form.
0.940"
TYP
ALL LINEAR DIMENSIONS ARE MILLIMETERS AND PARENTHETICALLY IN INCHES
December 2000
Rev. 0
5
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
White Electronic Designs
WS128K32-XG2TXE
ADVANCED
ORDERING INFORMATION
W S 128K 32 X - XXX X X E X
LEAD FINISH:
Blank = Gold plated leads
A = Solder dip leads
E = Epitaxial Layer on die
DEVICE GRADE:
Q = MIL-STD-883 Compliant
M = Military Screened -55°C to +125°C
I = Industrial -40°C to +85°C
C = Commercial 0°C to +70°C
PACKAGE TYPE:
G2T = 22.4mm Ceramic Quad Flat Pack, Low Profile CQFP (Package 510)
ACCESS TIME (ns)
IMPROVEMENT MARK:
N = No Connect at pin 8, 21, 28 and 39 in HIP for Upgrades
ORGANIZATION, 128Kx32
User configurable as 256Kx16 or 512Kx8
SRAM
WHITE ELECTRONIC DESIGNS CORPORATION
* Low Power Data Retention only available in G2T Package Type
December 2000
Rev. 0
6
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com