LTC1421/LTC1421-2.5 Hot Swap Controller U FEATURES ■ ■ ■ ■ ■ ■ ■ ■ ■ DESCRIPTIO The LTC®1421/LTC1421-2.5 are Hot SwapTM controllers that allow a board to be safely inserted and removed from a live backplane. Using external N-channel pass transistors, the board supply voltages can be ramped up at a programmable rate. Two high side switch drivers control the Nchannel gates for supply voltages ranging from 3V to 12V. Allows Safe Board Insertion and Removal from a Live Backplane System Reset and Power Good Control Outputs Programmable Electronic Circuit Breaker User Programmable Supply Voltage Power-Up Rate High Side Driver for Two External N-Channels Controls Supply Voltages from 3V to 12V Connection Inputs Detect Board Insertion or Removal Undervoltage Lockout Power-On Reset Input A programmable electronic circuit breaker protects against shorts. Warning signals indicate that the circuit breaker has tripped, a power failure has occurred or that the switch drivers are turned off. The reset output can be used to generate a system reset when the power cycles or a fault occurs. The two connect inputs can be used with staggered connector pins to indicate board insertion or removal. The power-on reset input can be used to cycle the board power or clear the circuit breaker. U APPLICATIO S ■ ■ Hot Board Insertion Electronic Circuit Breaker The trip point of the ground sense comparator is set at 0.1V for LTC1421 and 2.5V for LTC1421-2.5. The LTC1421/LTC1421-2.5 are available in 24-pin SO and SSOP packages. , LTC and LT are registered trademarks of Linear Technology Corporation. Hot Swap is a trademark of Linear Technology Corporation. U TYPICAL APPLICATIO Q3 1/2 Si4936DY C3 0.47µF VEE R4 20k 5% Q2 R2 1 0.025Ω 2 1/2 Si4936DY VDD 3 R1 Q1 1 0.005Ω 2 MTB50N06E STAGGERED CONNECTOR VCC 3 23 D1 VCCLO R3 1k LTC1421 GND 12 GND DATA BUS 19 FAULT 3 POR 1 CON1 POR 20 DISABLE 5 1 BEA VCC 13 BEB 12 GND QS3384 QuickSwitch® BACKPLANE 18 VDD 12V 1A + CLOAD 10k 21 CLOAD + 4 SETLO GATELO VOUTLO VCCHI 2 CON2 24 AUXVCC C1 1µF 4 FAULT 4 22 VEE – 12V 1A 17 C2 0.1µF 16 SETHI GATEHI VOUTHI RAMP CPON COMP – COMP + REF FB COMPOUT PWRGD RESET 10 9 14 13 8 11 15 6 7 R5 16k 5% 1µF R6 20k 1% + CLOAD VCC 5V 5A R7 7.15k 1% µP I/O I/O RESET DATA BUS 1421 TA01 QuickSwitch IS A REGISTERED TRADEMARK OF QUALITY SEMICONDUCTOR CORPORATION. PC BOARD 1 LTC1421/LTC1421-2.5 W U U U W W W ABSOLUTE MAXIMUM RATINGS PACKAGE/ORDER I FOR ATIO (Note 1) Supply Voltage (VCCLO, VCCHI, AUXVCC) .............. 13.2V Input Voltage (Analog Pins) ..... – 0.3V to (VCCHI + 0.3V) Input Voltage (Digital Pins) ................... – 0.3V to 13.2V Output Voltage (Digital Pins) .. – 0.3V to (VCCLO + 0.3V) Output Voltage (CPON) ......... – 13.2V to (VCCLO + 0.3V) Output Voltage (VOUTLO, VOUTHI) ........... – 0.3V to 13.2V Output Voltage (GATELO, GATEHI) ........... – 0.3V to 20V Operating Temperature Range LTC1421C ............................................... 0°C to 70°C LTC1421I ........................................... – 40°C to 85°C Storage Temperature Range ................ – 65°C to 150°C Lead Temperature (Soldering, 10 sec)................. 300°C ORDER PART NUMBER TOP VIEW CON1 1 24 AUXVCC CON2 2 23 VCCLO POR 3 22 SETLO FAULT 4 21 GATELO DISABLE 5 20 VOUTLO PWRGD 6 19 VCCHI RESET 7 18 SETHI REF 8 17 GATEHI CPON 9 16 VOUTHI RAMP 10 15 COMPOUT FB 11 14 COMP – GND 12 13 COMP + LTC1421CG LTC1421CSW LTC1421CG-2.5 LTC1421CSW-2.5 LTC1421IG LTC1421ISW LTC1421IG-2.5 LTC1421ISW-2.5 G PACKAGE SW PACKAGE 24-LEAD PLASTIC SSOP 24-LEAD PLASTIC SO TJMAX = 125°C, θJA = 100°C/W (G) TJMAX = 125°C, θJA = 85°C/W (SW) Consult factory for parts specified with wider operating temperature ranges. ELECTRICAL CHARACTERISTICS The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VCCHI = 12V, VCCLO = 5V unless otherwise noted (Note 2). SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS 1.5 3 mA mA DC Characteristics ICCLO VCCLO Supply Current CON1 = CON2 = GND, POR = VCCLO ● ICCHI VCCHI Supply Current CON1 = CON2 = GND, POR = VCCLO ● VLKO Undervoltage Lockout VLKH Undervoltage Lockout Hysteresis VCCLO and VCCHI VCCLO and VCCHI VREF Reference Output Voltage No Load ● ∆VLNR Reference Line Regulation 3V ≤ VCCLO ≤ 12V, No Load ● ∆VLDR Reference Load Regulation IO = 0mA to – 5mA, Sourcing Only ● IRSC Reference Short-Circuit Current VREF = 0V VCOF Comparator Offset Voltage 0V ≤ VCM ≤ (VCCLO − 1.3V) ● VCPSR Comparator Power Supply Rejection 0V ≤ VCM ≤ (VCCLO − 1.3V), 3V ≤ VCCLO ≤ 12V ● VCHST Comparator Hysteresis 0V ≤ VCM ≤ (VCCLO − 1.3V) VRST Reset Voltage Threshold (VOUTLO) FB = VOUTLO FB = Floating FB = GND VRHST Reset Threshold Hysteresis (VOUTLO) FB = VOUTLO FB = Floating FB = GND 7 12 15 mV mV mV RFB FB Pin Input Resistance 0V ≤ VFB ≤ VCCLO 95 kΩ VCB Circuit Breaker Trip Voltage VCB = (VCCLO – VSETLO) or VCB = (VCCHI – VSETHI) VTRIP Output Voltage for Re-Power-Up LTC1421 (Note 3) LTC1421-2.5 (Note 4) 2 0.6 1 2.28 2.45 2.60 1.220 1.232 1.244 4 8 mV 1 3 mV 100 mV – 45 ±10 1 ● 2.80 4.50 5.75 40 2.90 4.65 5.88 50 0.1 2.5 V mA 7 ● ● ● V mV mV/V mV 3.00 4.75 6.01 60 V V V mV V V LTC1421/LTC1421-2.5 ELECTRICAL CHARACTERISTICS The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VCCHI = 12V, VCCLO = 5V unless otherwise noted (Note 2). SYMBOL PARAMETER CONDITIONS MIN IRAMP RAMP Pin Output Current Charge Pump On, VRAMP = 0.4V ICP Charge Pump Output Current Charge Pump On, GATEHI = 0V GATELO = 0V ∆VGATEHI GATEHI N-Channel Gate Drive ● 11 TYP MAX 17 23 UNITS µA µA µA – 600 – 300 VGATEHI − VOUTHI 6 16 V ∆VGATELO GATELO N-Channel Gate Drive VGATELO − VOUTLO 10 16 V VAUXVCC Auxiliary VCC Output Voltage VCCLO = 5V, Unloaded VIL Input Low Voltage CON1, CON2, POR ● VIH Input High Voltage CON1, CON2, POR ● 2 IIN Input Current CON1, CON2, POR = GND ● – 30 VOL Output Low Voltage RESET, COMPOUT, PWRGD, DISABLE, FAULT, IO = 3mA VOH IPU Output High Voltage Logic Output Pull-Up Current 4.5 V 0.8 V V – 90 µA ● 0.4 V CPON, IO = 3mA ● 1.45 V DISABLE, IO = – 3mA ● 4 V CPON, IO = – 1mA ● 3.4 V RESET, PWRGD, FAULT = GND – 60 µA – 15 AC CHARACTERISTICS t1 CON1 or CON2↓ to CPON↑ Figure 1, CL = 15pF t2 PWRGD↑ to RESET↑ Figure 1, RL = 10k to VCCLO, CL = 15pF t3 PWRGD↑ to DISABLE↓ ● 15 20 30 ms ● 160 140 200 200 240 280 ms ms ● 160 140 200 200 240 280 ms ms ● 15 20 30 ms Figure 1, CL = 15pF t4 POR↓ to CPON↓ Figure 1, CL = 15pF t5 PWRGD↓ to RESET↓ Figure 1, RL = 10k to VCCLO, CL = 15pF 32 µs t6 POR↑ to CPON↑ Figure 1, CL = 15pF 50 ns t7 CON1 or CON2↑ to CPON↓ Figure 1, CL = 15pF 50 ns t9 Short-Circuit Detect to FAULT↓ Figure 1, RL = 10k to VCCLO, CL = 15pF VCCLO – SETLO = 0mV to 100mV 20 µs t10 Short-Circuit Detect to CPON↓ Figure 2, CL = 15pF VCCLO – SETLO = 0mV to 100mV 20 µs t11 POR↑ to FAULT↑ Figure 2, RL = 10k to VCCLO, CL = 15pF 20 ns tCHL Comparator High to Low COMP – = 1.232V, 10mV Overdrive RL = 10k to VCCLO, CL = 15pF ● 0.25 0.5 µs tCLH Comparator Low to High COMP – = 1.232V, 10mV Overdrive RL = 10k to VCCLO, CL = 15pF ● 1 1.5 µs Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Note 2: All currents into device pins are positive; all currents out of device pins are negative. All voltages are reference to ground unless otherwise specified. Note 3: After power-on reset, the VOUTLO and VOUTHI have to drop below the VTRIP point before the charge pump is restarted. Note 4: After power-on reset, the VOUTLO has to drop below the VTRIP point before the charge pump is restarted. 3 LTC1421/LTC1421-2.5 U W TYPICAL PERFORMANCE CHARACTERISTICS Reference Voltage vs Temperature 1.238 1.245 24 VCCLO = 5V VCCHI = 12V 23 GATE VOLTAGE (V) 1.234 1.232 1.230 1.228 VCCLO = 5V VCCHI = 12V REFERENCE VOLTAGE (V) VCCLO = 5V VCCHI = 12V 1.236 REFERENCE VOLTAGE (V) Reference Voltage vs Source Current Gate Voltage vs Temperature 22 GATEHI 21 20 19 GATELO 1.226 50 25 75 0 TEMPERATURE (°C) 100 17 – 50 – 25 125 1.220 50 25 75 0 TEMPERATURE (°C) 100 26 26 VCCHI = 12V VCCLO = 5V 18 16 10 14 VCCLO = 5V VCCHI = 12V 1500 ICCLO SUPPLY CURRENT (µA) GATEHI VOLTAGE (V) 20 6 8 4 SOURCE CURRENT (mA) ICCLO Supply Current vs Temperature 24 22 2 0 1421 G03 GATEHI Voltage vs VCCHI Voltage 24 GATELO VOLTAGE (V) 125 1421 G02 GATELO Voltage vs VCCLO Voltage 22 20 18 16 1400 1300 14 12 12 0 2 8 6 10 4 VCCLO VOLTAGE (V) 12 14 0 8 6 10 4 VCCHI VOLTAGE (V) 2 12 1421 G04 14 600 VOLTAGE (mV) 545 535 VCCLO = 5V VCCHI = 12V 2.0 COMPOUT PWRGD RESET 400 300 FAULT 200 530 0 50 25 75 0 TEMPERATURE (°C) 100 125 1421 G07 1.5 1.0 0.5 100 525 125 2.5 VCCLO = 5V VCCHI = 12V 500 100 CPON Voltage vs Sink Current (Charge Pump Off) CPON VOLTAGE (V) VCCLO = 5V VCCHI = 12V 540 50 25 75 0 TEMPERATURE (°C) 1421 G06 VOL vs ISINK 555 520 – 50 – 25 1200 – 50 – 25 1421 G05 ICCHI Supply Current vs Temperature ICCHI SUPPLY CURRENT (µA) 1.230 1.225 1421 G01 4 1.235 18 1.224 – 50 – 25 550 1.240 0 2 4 6 SINK CURRENT (mA) 8 10 1421 G08 0 0 0.5 1.0 1.5 2.0 SINK CURRENT (mA) 2.5 3.0 1421 G09 LTC1421/LTC1421-2.5 U W TYPICAL PERFORMANCE CHARACTERISTICS ICCLO Supply Current vs VCCLO Voltage CPON Voltage vs Source Current (Charge Pump On) 5 7 VCCLO = 5V VCCHI = 12V ICCLO SUPPLY CURRENT (mA) CPON VOLTAGE (V) 4 3 2 1 0 VCCHI = 12V 6 5 4 3 2 1 0 – 0.5 – 1.0 – 1.5 – 2.0 – 2.5 SOURCE CURRENT (mA) – 3.0 1421 G10 0 0 2 8 6 10 4 VCCLO VOLTAGE (V) 12 14 1421 G11 U U U PIN FUNCTIONS CON1 (Pin 1): TTL Level Input with a Pull-Up to VCCLO. Together with CON2, it is used to indicate board connection. The pin must be tied to ground on the host side of the connector. When using staggered connector pins, CON1 and CON2 must be the shortest and must be placed at opposite corners of the connector. Board insertion is assumed after CON1 and CON2 are both held low for 20ms after power-up. CON2 (Pin 2): TTL Level Input with a Pull-Up to VCCLO. Together with CON1 it is used to indicate board connection. POR (Pin 3): TTL Level Input with a Pull-Up to VCCLO. When the pin is pulled low for at least 20ms, a hard reset is generated. Both VOUTLO and VOUTHI will turn off at a controlled rate. A power-up sequence will not start until the POR pin is pulled high. If POR is pulled high before VOUTLO and VOUTHI are fully discharged, a power-up sequence will not begin until the voltage at VOUTLO and VOUTHI are below VTRIP. The electronic circuit breaker will be reset by pulling POR low. FAULT (Pin 4): Open Drain Output to GND with a Weak Pull-Up to VCCLO. The pin is pulled low when an overcurrent fault is detected at VOUTLO or VOUTHI. DISABLE (Pin 5): CMOS Output. The signal is used to disable the board’s data bus during insertion or removal. PWRGD (Pin 6): Open Drain Output to GND with a Weak Pull-Up to VCCLO. The pin is pulled low immediately after VOUTLO falls below its reset threshold voltage. The pin is pulled high immediately after VOUTLO rises above its reset threshold voltage. RESET (Pin 7): Open Drain Output to GND with a Weak Pull-Up to VCCLO. The pin is pulled low when a reset condition is detected. A reset will be generated when any of the following conditions are met: Either CON1 or CON2 is high, POR is pulled low, VCCLO or VCCHI are below their respective undervoltage lockout thresholds, PWRGD goes low or an overcurrent fault is detected at VOUTLO or VOUTHI. RESET will go high 200ms after PWRGD goes high. On power failure, RESET will go low 32µs after PWRGD goes low. REF (Pin 8): The Reference Voltage Output. VOUT = 1.232V ±1%. The reference can source up to 5mA of current. A 1µF bypass capacitor is recommended. CPON (Pin 9): CMOS Output That Can Be Pulled Below Ground. CPON is pulled high when the internal charge pumps for GATELO and GATEHI are turned on. CPON is pulled low when the charge pumps are turned off. The pin can be used to control an external MOSFET for a – 5V to – 12V supply. 5 LTC1421/LTC1421-2.5 U U U PIN FUNCTIONS RAMP (Pin 10): Analog Power-Up Ramp Control Pin. By connecting an external capacitor between the RAMP and GATEHI, a positive linear voltage ramp on GATEHI and GATELO is generated on power-up with a slope equal to 20µA/CRAMP. A 10k resistor in series with the capacitor enhances the ESD performance at the GATEHI pin. FB (Pin 11): Analog Feedback Input. FB is used to set the reset threshold voltage on VCCLO. For a 5V supply leave FB floating. For a 3.3V supply, short FB to VCCLO. GND (Pin 12): Ground COMP + (Pin 13): Noninverting Comparator Input. COMP – (Pin 14): Inverting Comparator Input. COMPOUT (Pin 15): Open Drain Comparator Output. VOUTHI (Pin 16): High Supply Voltage Output. This must be the higher of the two supply voltage outputs. GATEHI (Pin 17): The High Side Gate Drive for the High Supply N-Channel. An internal charge pump guarantees at least 6V of gate drive. The slope of the voltage rise at GATEHI is set by the external capacitor connected between GATEHI and RAMP. When the circuit breaker trips, GATEHI is immediately pulled to GND. SETHI (Pin 18): The Circuit Breaker Set Pin for the High Supply. With a sense resistor placed in the supply path between VCCHI and SETHI, the circuit breaker will trip when the voltage across the resistor exceeds 50mV for more than 20µs. To disable the circuit breaker, VCCHI and SETHI should be shorted together. 6 VCCHI (Pin 19): The Positive Supply Input. This must be the higher of the two input supply voltages. An undervoltage lockout circuit disables the chip until the voltage at VCCHI is greater than 2.45V. VOUTLO (Pin 20): Low Supply Voltage Output. This must be the lower of the two supply voltage outputs. GATELO (Pin 21): The High Side Gate Drive for the Low Supply N-Channel Pass Transistor. An internal charge pump guarantees at least 10V of gate drive. The slope of the voltage rise at GATELO is set by the external capacitor connected between GATEHI and RAMP. When the circuit breaker trips GATELO is immediately pulled to GND. SETLO (Pin 22): The Circuit Breaker Set Pin for the Low Supply. With a sense resistor placed in the supply path between VCCLO and SETLO, the circuit breaker will trip when the voltage across the resistor exceeds 50mV for more than 20µs. To disable the circuit breaker, VCCLO and SETLO should be shorted together. VCCLO (Pin 23): The Positive Supply Input. VCCLO must be equal to or lower voltage than VCCHI. An undervoltage lockout circuit disables the chip until the voltage at VCCLO is greater than 2.45V. AUXVCC (Pin 24): The supply input for the GATELO and GATEHI discharge circuitry. Connect a 1µF capacitor to ground. AUXVCC is powered from VCCLO via an internal Schottky diode and series resistor. LTC1421/LTC1421-2.5 W BLOCK DIAGRAM VCC 24 23 22 19 18 21 10 17 16 20 VCCLO SETLO VCCHI SETHI GATELO RAMP GATEHI VOUTHI VOUTLO AUXVCC 50mV + – 50mV AUXVCC + – CHARGE PUMP N2 CP1 N1 CP3 CP2 + + – VCC UNDERVOLTAGE LOCKOUT 73.5k + – VTRIP CP4 71.5k – 9 CPON FB 11 REF 8 PWRGD 6 RESET 7 26.7k + 1.232V REFERENCE VCC VCC 20µA 4 20µA FAULT VCC DIGITAL CONTROL 1 CON1 2 CON2 20µA 3 RESET TIMING POR + 5 12 DISABLE CP5 COMPOUT 15 COMP – 14 COMP + 13 – GND 1421 BD U W W SWITCHI G TI E WAVEFOR S t1 t2 t5 t9 t7 CON1 VCCLO – SETLO CON2 FAULT CPON CPON PWRGD PWRGD RESET RESET DISABLE POR POR 1421 F01 t3 t4 t5 t11 t2 1421 F02 t10 t6 t6 Figure 1. Nominal Operation Switching Waveforms Figure 2. Fault Detection Switching 7 LTC1421/LTC1421-2.5 U U W U APPLICATIONS INFORMATION Hot Circuit Insertion 12V When circuit boards are inserted into a live backplane, the supply bypass capacitors on the board can draw huge transient currents from the backplane power bus as they charge up. The transient currents can cause permanent damage to the connector pins and cause glitches on the system supply, causing other boards in the system to reset. At the same time, the system data bus can be disrupted when the board’s data pins make or break connection. The LTC1421 is designed to turn a board’s supply voltages on and off in a controlled manner, allowing the board to be safely inserted or removed from a live backplane. The chip also provides a disable signal for the board’s data bus buffer during insertion or removal and provides all the necessary supply supervisory functions for the board. Power Supply Ramping The power supplies on a board are controlled by placing external N-channel pass transistors in the power path (Figure 3). R1 and R2 provide current fault detection. By ramping the gate of the pass transistor up at a controlled rate, the transient surge current (I = C • dV/dt) drawn from the main backplane supply can be limited to a safe value when the board makes connection. 1 12V R2 2 Q2 VOUTHI + 4 3 CLOAD 5V 1 VCCLO 2 Q1 RRAMP 4 3 23 1 R1 2 CON1 22 21 20 19 SETLO GATELO VOUTLO VCCHI LTC1421 18 17 + SLOPE = 20µA/CRAMP VOUTLO 5V t1 t2 SETHI GATEHI VOUTHI RAMP and GATEHI pins. The voltage at the GATEHI pin is clamped one Schottky diode drop below GATELO. The ramp time for each supply is equal to: t = (VCC) (CRAMP)/20µA. During power down the gates are actively pulled down by two internal NFETs. A negative supply voltage can be controlled using the CPON pin as shown in Figure 5. When the board makes connection, the transistor Q3 is turned off because it’s gate is pulled low to –12V by R4. CPON is also pulled to –12V. When the charge pump is turned on, CPON is pulled to VCCLO and the gate of Q3 will ramp up with a time constant determined by R4, R5 and C2. When the charge pump is turned off, CPON goes into a high impedance state, the gate of Q3 is discharged to VEE with a time constant determined by R4 and C2, and Q3 turns off. –12V FROM CONNECTOR CRAMP 10 Q3 1/2 MMDF3N0HD C2 0.047µF CON2 1421 F03 Figure 3: Supply Control Circuitry When power is first applied to the chip, the gates of both N-channels, GATELO and GATEHI are pulled low. After the connection sense pins, CON1 and CON2 are both held low for at least 20ms, a 20µA reference current is connected from the RAMP pin to GND. The voltage at GATEHI begins to rise with a slope equal to 20µA/CRAMP (Figure 4), where CRAMP is an external capacitor connected between the 8 1421 F4a Figure 4. Supplies Turning On CLOAD 16 RAMP VOUTLO VOUTHI R4 20k 5% + CLOAD VEE –12V 1A B R5 16k 5% 9 5V CPON –12V 0V CPON B LTC1421 –12V 0V VEE –12V ~1ms ~1ms Figure 5. Negative Supply Control 1421 F05 LTC1421/LTC1421-2.5 U U W U APPLICATIONS INFORMATION PWRGD and RESET The LTC1421 uses a 1.232V bandgap reference, internal resistive divider and a precision voltage comparator to monitor VOUTLO (Figure 6). The reset threshold voltage for VOUTLO is determined by the FB pin connection as summarized in Table 1. VOUTLO VCCLO 20µA 73.5k 71.5k COMP1 – PWRGD FB VCCLO 26.7k + 20µA When VOUTLO drops below its reset threshold, the comparator output goes high, and PWRGD is immediately pulled low (time point 2). After a 32µs delay, RESET is pulled low. The RESET delay allows the PWRGD signal to be used as an early warning that a reset is about to occur. If the PWRGD signal is used as a interrupt input to a microprocessor, a short power-down routine can be run before the reset occurs. If VOUTLO rises above the reset threshold for less than 200ms, the PWRGD output will trip, but the RESET output is not affected (time point 3). If VOUTLO drops below the reset threshold for less than 32µs, the PWRGD output will trip, but again the RESET output will not be affected (time point 5). Voltage Comparator RESET RESET TIMING REF 1.232V 1421 F06 Figure 6. Supply Monitor Block Diagram Table 1 FEEDBACK PIN VOUTLO RESET VOLTAGE Floating 4.65V VOUTLO 2.90V GND 5.88V When the VOUTLO voltage rises above its reset threshold voltage, the comparator output goes low, and PWRGD is immediately pulled high to VCCLO by a weak pull-up current source or external resistor (Figure 7, time points 1 and 4). After a 200ms delay, RESET is pulled high. The weak pull-up current source to VCCLO on PWRGD and RESET have a series diode so the pins can be pulled above VCCLO by an external pull-up resistor without forcing current back into VCCLO. The uncommitted voltage comparator (COMP2) can be used to monitor output voltages other than VOUTLO. Figure 8a shows how the comparator can be used to monitor a 12V supply (VOUTHI), while the 5V supply (VOUTLO) generates a reset when it dips below 4.65V. When the 12V supply drops below 10.8V, COMPOUT will pull low. The FB pin is left floating. Figure 8b shows how the comparator can be used to monitor the 5V supply (VOUTHI) while the 3.3V supply (VOUTLO) generates a reset when it dips below 2.9V. When the 5V supply drops below 4.65V, COMPOUT will pull low. The FB pin is tied to VOUTLO. 5V 12V 20 LTC1421 VCCLO 16 73.5k 20µA COMP1 6 71.5k – VCCLO 10k 5% 26.7k + 1 2 V2 3 V1 V2 4 V1 5 V2 V2 VOUTLO V1 7 COMP2 PWRGD RESET 200ms <32µs < 200ms 200ms Figure 7. Power Monitor Waveforms 15 20µA RESET TIMING 32µs 11 1.232V 1421 F07 + 13 – 14 107k 1% 13.7k 1% 8 1421 F08a Figure 8a. Monitor 12V, Reset 5V at 4.65V 9 LTC1421/LTC1421-2.5 U U W U APPLICATIONS INFORMATION Figure 8c shows how the comparator can be used to generate a reset when the 12V supply (VOUTHI) drops below 10.8V. The 5V supply (VOUTLO) also generates a reset when it dips below 4.65V. When the 12V supply drops below 10.8V, COMPOUT will pull the FB pin low setting the internal threshold voltage for comparator 1 to 5.88V. Since VOUTLO is less than 5.88V, PWRGD immediately goes low and a reset is generated 32µs later. A 5.1k resistor is tied from the FB pin to VOUTLO, setting the internal threshold to about 2.9V. The new reset threshold voltage is set by the external resistive divider connected to COMP2. When VOUTLO drops below the new threshold, COMPOUT pulls FB to ground, changing the internal threshold at COMP1 to 5.88V and generating a reset. Finally, the comparator may be used to monitor a negative supply as shown in Figure 8e. The external resistor divider Figure 8d shows how the comparator can be used to override the internal reset voltage for a 5V supply on VOUTLO. 3.3V 5V 20 5V 16 73.5k 20 20µA 6 6 16 73.5k COMP1 71.5k 71.5k VCCLO 12V 11 – 26.7k + 11 – 15 102k 1% 20µA VCCLO 26.7k 7 10k 5% + COMP2 RESET TIMING 15 20µA 7 COMP1 20µA LTC1421 VCCLO 5.1k 5% LTC1421 VCCLO COMP2 + RESET TIMING – 13 14 107k 1% – 14 38.3k 1% 8 1.232V 38.3k 1% 1421 F08d 8 1.232V + 13 Figure 8d. Reset 5V at 4.5V 1421 F08b 5V Figure 8b. Monitor 5V, Reset 3.3V at 2.9V 20 LTC1421 VCCLO 5V 12V 16 73.5k 12V 20 20µA LTC1421 VCCLO 20µA COMP1 6 71.5k – VCCLO 6 16 73.5k 26.7k + 11 7 15 20µA COMP2 + – 1.232V 11 15 20µA + RESET TIMING 71.5k – VCCLO 26.7k 7 COMP1 13 14 107k 1% 13.7k 1% COMP2 RESET TIMING + 13 – 14 8 1.232V 13.7k 1% 1421 F08e 8 107k 1% 1421 F08c – 12V Figure 8c. Reset 12V at 10.8V, Reset 5V at 4.65V 10 Figure 8e. Monitor – 12V at – 10.8V, Reset 5V at 4.65V 10k 5% LTC1421/LTC1421-2.5 U U W U APPLICATIONS INFORMATION is connected between REF (Pin 8) and the negative supply and the trip point of Comparator 2 set to GND. Soft Reset Generation A soft reset that doesn’t cycle the supply voltage can be generated externally using Pin 11 (FB) as shown in Figure 9. For a 5V supply the FB pin is left floating to set the internal supply monitor trip voltage to 4.65V. However, if the FB pin is pulled to ground for more than 32µs via a push button or open-collector logic gate, the internal trip point will go to 5.88V and the RESET pin will pull low. RESET will remain low for 200ms after the FB pin is released. The RESET signal will also be pulled low when the voltage at the VOUTLO pin dips below 4.65V for more than 32µs. When using a 3.3V supply, a 1k resistor must be connected from the FB pin to VCCLO to set the internal trip point to 2.90V. 3.3V 1/6 LS7404 OPEN COLLECTOR R1 USED FOR 3.3V R1 SUPPLY ONLY 1k 11 7 FB RESET LTC1421 If more than 20µs of response time is needed to reject supply noise, an external resistor and capacitor can be added to the sense circuit as shown in Figure 10. R 1 SENSE 2 3 Q1 4 CF RF 23 22 VCCLO SETLO 21 20 GATELO VOUTLO LTC1421 5V 1421 F10 RESET LOGIC Figure 10. Short-Circuit Protection Circuit Auxiliary VCC GND 12 32µs sense resistor is greater than 50mV for more than 20µs. When the circuit breaker trips, both N-channel MOSFETs are quickly turned off, FAULT and PWRGD go low and RESET is pulled low 32µs later. FAULT can be connected to a LED or a logic signal back to the host to indicate a faulty board. The chip will remain in the tripped state until a power-on reset is generated, or the power on VCCHI and VCCLO is cycled. If the circuit breaker feature is not used, short VCCLO to SETLO and VCCHI to SETHI. 200ms FB RESET 1421 F09 Figure 9. Generating a Soft Reset Undervoltage Lockout On power-up, an undervoltage lockout circuit prevents the GATELO and GATEHI charge pumps from turning on until VCCLO and VCCHI have both exceeded 2.45V. When a short circuit occurs on the board, it is possible to draw enough current to cause the backplane supply voltage to collapse. If the input supply voltage collapses to a low enough voltage and the LTC1421 gate drive circuitry is unable to shut off the N-channel pass transistors, the system might freeze up in a permanent short condition. To prevent this from occurring, the gate discharge circuitry inside the LTC1421 is powered from AUXVCC, which is in turn powered from VCCLO through an internal Schottky diode and current limiting resistor (Figure 11). VCCLO 23 GATELO GATEHI 21 17 10k Electronic Circuit Breaker The LTC1421 features an electronic circuit breaker function that protects against short circuits or excessive currents on the supplies. By placing a sense resistor between the supply input and set pin of either supply, the circuit breaker will be tripped whenever the voltage across the AUXVCC 24 1µF GATE DRIVE CIRCUITRY LTC1421 1421 F11 Figure 11. AUXVCC Circuitry 11 LTC1421/LTC1421-2.5 U W U U APPLICATIONS INFORMATION When VCCLO collapses, there is enough energy stored on the 1µF capacitor connected to AUXVCC to keep the gate discharge circuitry alive long enough to fully turn off the external N-channels. CONNECTOR VCC DATA BUS Power N-Channel Selection D1 OUT D2 BACKPLANE BOARD 1421 F12 The RDS(ON) of the external pass transistor must be low enough so that the voltage drop across it is about 200mV or less at full current. If the RDS(ON) is too high, the voltage drop across the transistor might cause the output voltage to trip the reset circuit. Table 2 lists the transistors that are recommended for use with the LTC1421. Figure 12. Typical Logic Gate Loading the Data Bus Q1 R1 1 0.005Ω 2 MTB50N06E 5V 3 4 22 23 VCC + 21 20 CLOAD Table 2. N-Channel Selection Guide 0 to 1 1 to 2 LTC1421 PART NUMBER MANUFACTURER DESCRIPTION MMDF2N02E ON Semiconductor Dual N-Channel SO-8 RDS(ON) = 0.1Ω MMDF3NO2HD ON Semiconductor MTB30N06 ON Semiconductor Single 30A N-Channel DD Pak RDS(ON) = 0.05Ω 5 to 10 MTB50N06E ON Semiconductor Single N-Channel DD Pak RDS(ON) = 0.025Ω MTB75N05HD ON Semiconductor Single N-Channel DD Pak RDS(ON) = 0.0095Ω Data Bus When a board is inserted or removed from the host, care must be given to prevent the system data bus from being corrupted when the data pins make or break contact. One problem is that the fully discharged input or output capacitance of the logic gates on the board will draw an inrush current when the data bus pins first make contact. The inrush current can temporarily corrupt the data bus, but usually will not cause long term damage. The problem can be minimized by insuring the input or output data bus capacitance is kept as small as possible. The second, and more serious problem involves the diodes to VCC at the input and output of most logic families (Figure 12). 12 DISABLE GND 12 QS3384 2 Dual N-Channel SO-8 RDS(ON) = 0.09Ω 2 to 5 10 to 20 5 SYSTEM DATA BUS CONNECTOR CURRENT LEVEL (A) VCC 24 3 15 14 5 4 16 17 6 7 19 18 9 8 20 21 10 11 23 22 1 GND BOARD DATA BUS 12 13 1421 F13 Figure 13: Buffering the Data Bus With the board initially unpowered, the VCC input to the logic gate is at ground potential. When the data bus pins make contact, the bus line is clamped to ground through the input diode D1 to VCC. Large amounts of current can flow through the diode and cause the logic gate to latch up and destroy itself when the power is finally applied. This LTC1421/LTC1421-2.5 U U W U APPLICATIONS INFORMATION can usually be prevented by using logic that does not include the clamping diodes such as the QSI 74FCTT family from Quality Semiconductor, or by using a data bus switch such as the 10-bit QS3384 QuickSwitch also from Quality Semiconductor (Tel: 408-450-8000). The QuickSwitch bus switch contains an N-channel placed in series with the data bus. The switch is turned off when the board is inserted and then enabled after the power is stable. The switch inputs and outputs do not have a parasitic diode back to VCC and have very low capacitance. The LTC1421 is designed to work directly with the QuickSwitch bus switch as shown in Figure 13. The DISABLE signal is connected to the enable pins of the QS3384, and each switch is placed in series with a data bus signal. When the board is inserted, the DISABLE 1 2 3 20ms 4 signal is pulled high, turning off the switches. After the board supply voltage ramps up and RESET goes high, DISABLE will pull low enabling the switches. Board Insertion Timing When the board is inserted, GND pin makes contact first, followed by VCCHI and VCCLO (Figure 14, time point 1). DISABLE is immediately pulled high, so the data bus switch is disabled. At the same time CON1 and CON2 make contact and are shorted to ground on the host side (time point 3). Since most boards need to be rocked back and forth to get them in place, there is a period of time when only one side of the connector is making contact. CON1 and CON2 should be located at opposite ends of the connector. 5 6 200ms VCCLO VCCHI DISABLE CON1 CON2 CPON GATEHI VOUTHI GATELO VOUTLO VTH1 PWRGD RESET FAULT POR 1421 F14 Figure 14. Board Insertion Timing 13 LTC1421/LTC1421-2.5 U W U U APPLICATIONS INFORMATION up sequence will begin automatically. The trip point potential for LTC1421 is set at 0.1V and 2.5V for LTC1421-2.5. When CON1 and CON2 are both forced to ground for more than 20ms, the LTC1421 assumes that the board is fully connected to the host and power-up can begin. When VCCLO and VCCHI exceed the 2.45V undervoltage lockout threshold, the 20µA current reference is connected from RAMP to GND, the charge pumps are turned on and CPON is forced high (time point 4). VOUTHI and VOUTLO begin to ramp up. When VOUTLO exceeds the reset threshold voltage, PWRGD will immediately be forced high (time point 5). After a 200ms delay, RESET will be pulled high and DISABLE will be pulled low, enabling the data bus (time point 6). In applications, where either VOUTLO or VOUTHI might be forced above 100mV before power-up, the LTC1421-2.5 should be used. This could occur when leakage through the body diode of the logic chips keeps VOUTLO high or in the case where logic lines are precharged. In other applications, where outputs need to drop to near ground potential before ramping up again to ensure proper initial state for the logic chips, the LTC1421 should be used. Ground Sense Comparator Power-On Reset Timing When POR is pulled low for more than 20ms, GATELO and GATEHI are pulled to ground and VOUTLO and VOUTHI will be discharged. If POR is pulled back high while VOUTLO and VOUTHI are still ramping down, the discharge will continue. When they drop below the VTRIP point, a power- The POR input is used to completely cycle the power supplies on the board or to reset the electronic circuit breaker feature. The POR pin can be connected to a grounded push button, toggle switch or a logic signal from the host. When POR is pulled low for more than 20ms, a power-on reset sequence begins (Figure 15, 1 20ms 2 3 4 32µs 5 6 200ms 7 VCCHI VCCLO DISABLE CON1 CON2 CPON GATEHI VOUTHI GATELO VOUTLO VTH2 VTH1 PWRGD RESET FAULT POR 1421 F15 Figure 15. Power-On Reset Timing 14 LTC1421/LTC1421-2.5 U U W U APPLICATIONS INFORMATION time point 2). Pulses less than 20ms on POR are ignored. CPON goes low. Both GATEHI and GATELO will be actively pulled down to GND. When VOUTLO drops below its reset threshold voltage, PWRGD will immediately pull low (time point 3) followed by RESET and DISABLE 32µs later (time point 4). Both supplies will be discharged to ground and stay there until POR is pulled high. The circuit breaker can be reset by pulling POR low. After POR is low for more than 20ms, the chip will immediately try to power up the supplies once the outputs are below the VTRIP point. Circuit Breaker Timing The waveforms for the circuit when a short occurs on either supply during board insertion are shown in 1 2 3 20ms 4 5 Figure 16. Time points 1 to 4 are the same as the board insertion example, but at time point 5, a short circuit is detected on one of the supplies. The charge pumps are immediately turned off, the outputs VOUTHI and VOUTLO are actively pulled to GND and the CPON and FAULT pins are pulled low. At time point 6, the circuit breaker is reset by pulling POR low. After POR has been low for 20ms (time point 7), CPON and FAULT are pulled high, the 20µA reference current is connected to RAMP and the charge pumps are enabled. VOUTHI and VOUTLO ramp up at a controlled rate. When VOUTLO has exceeded its reset threshold, the PWRGD signal is pulled high (time point 8). After a 200ms delay, RESET is pulled high and DISABLE goes low. 6 20ms 7 8 200ms 9 VCCLO VCCHI DISABLE CON1 CON2 CPON GATEHI VOUTHI GATELO VOUTLO VTH1 PWRGD RESET FAULT POR 1421 F16 Figure 16. Circuit Breaker Timing 15 LTC1421/LTC1421-2.5 U U W U APPLICATIONS INFORMATION Board Removal Timing time for power fail information to be stored in nonvolatile memory, the falling edge of RESET (time point 3) is delayed by 32µs from the falling edged of PWRGD. When the board is removed from the host, the sequence happens in reverse (Figure 17). Since CON1 and CON2 are the shortest pins, they break connection first and are internally pulled high (time point 1). The charge pumps are turned off, CPON is pulled low. VOUTLO and VOUTHI are actively pulled down. When VOUTLO falls below its reset threshold (time point 2) PWRGD is pulled low. To allow 1 2 3 Finally, the input supply pins VCCHI and VCCLO break contact (time point 4). If staggered pins are not used, the board may be powered down prior to removal by switching the POR pin to ground with a toggle switch. 4 32µs VCCLO VCCHI DISABLE CON1 CON2 CPON GATEHI VOUTHI GATELO VOUTLO VTH2 PWRGD RESET FAULT POR 1421 F17 Figure 17. Board Removal Timing 16 LTC1421/LTC1421-2.5 U U W U APPLICATIONS INFORMATION 5V Only Applications will pull the POWERGOOD signal low as long as the supply remains above 4.65V. Note that a soft reset will not affect the POWERGOOD signal. The FAULT signal is also monitored to determine that the circuit breaker has tripped. The LTC1421 may be used in 5V only applications as shown in Figure 18. A soft reset can be generated from the backplane via an open-collector inverter driving the FB (Pin 11) or by a push button to ground. A hard power reset is generated from the backplane via an open-collector inverter driving the POR (Pin 3). A hard reset cycles the power on the board or resets the electronic circuit breaker. The comparator is used to monitor the board supply voltage and – 48V and 24V Applications The LTC1421 may be used in – 48V applications as shown in Figure 19. The LTC1421 provides the hot insertion protection, while the 5V supply is generated by a power R1 0.005Ω 1W 1 2 5V Q1 MTB50N06E 3 22 23 5V R4 10k 4 21 20 19 18 17 16 CLOAD C2 1µF 10 5V C1 1µF 15 10k POWERGOOD 7 14 13 8 LTC1421 5V R2 28k 1% LOGIC RESET R3 10.2k 1% 1µF 10k 11 FAULT 1 SOFT RESET 1/6 LS7004 5 12 9 6 3 S1 HARD RESET 1421 F18 BACKPLANE PC BOARD Figure 18. 5V Only Application with Soft Reset Q1 IRFR9110 – 48V STAGGERED CONNECTOR R1 5.1k 1W + D1 5.1V – 48V C3 2.2µF 25V C2 2.2µF 25V 23 22 21 + 10 9 C1 1µF R2 15k 1/8W 20 19 18 17 16 2 24 LTC1421 4 3 1 13 14 8 11 15 6 7 1 2 R3 56k 1/2W R4 300Ω 1/8W +OUT ASTRODYNE ASD 10-48S5 –IN – OUT CONTROL 3 + 5 5V 2A C4 100µF 16V 6 R5 10k 1/2W Q2 MPSA06 1µF +IN + C4 100µF 100V R6 402Ω 1/8W S1 12 5 1421 F19 – 48V – 48V BACKPLANE PC BOARD Figure 19. – 48V to 5V Hot Swappable Supply 17 LTC1421/LTC1421-2.5 U W U U APPLICATIONS INFORMATION module. The ground pin for the LTC1421 is connected to – 48V; Zener diode D1 and resistor R1 provide the positive supply for the chip. Bypass capacitor C4 is protected against inrush current by P-channel Q1. When the board is inserted into the backplane, transistor Q1 is turned off by resistor R2. When the connection sense pins, CON1 and CON2 have been connected to – 48V for more than 20ms, CPON pulls high turning on Q2 and the gate of Q1 starts to pull low with a time constant determined by R2, R3 and C3. At the same time, the voltage at the input to the power module starts to ramp up. When the voltage across the inputs to the power module reaches the comparator trip level set by R5 and R6, in this case – 32V, the comparator output pulls high and turns on the 5V supply. A cheaper solution is shown in Figure 20 using the LT®1170HV switcher. Again P-channel transistor Q1 protects the bypass capacitors against inrush current and resistors R5 and R6 set the comparator trip voltage. The LT1170HV is turned on via the VC pin. Resistors R11, R14 and transistor Q4 provide a monitoring path for the RESET signal which is level shifted up to 5V through an optoisolator. The P-channel power FET is being replaced by an N-channel FET in Figure 21 for the – 48V application. Again, Zener Diode D1 and resistor R1 provide the positive supply for the chip. Capacitor C1 is to insure Q1 stays off when the board is being hot inserted into the backplane. The resistor divider R2 and R3, along with the internal comparator, perform the undervoltage lock out function. Q1 would only be turned on when the input supply voltage is lower than – 42V. The power module would then be turned on by the optoisolator, 4N25, when the module’s input voltage reaches 47V. Figure 22 shows how to use the LTC1421 with a 24V supply and a LT1074CT step-down switcher. Resistors R5 and R6 set the turn-on threshold to 22V. All of the supervisory signals can be used without level shifting. 18 Figure 23 shows how to use the LTC1421 with a 5V supply and an LTC1430CS8 synchronous step-down switching regulator to generate 3.3V output at up to 10A for microprocessors. Resistors R4, R8 and R9 set the turn-on voltage at 4.8V and the turn-off at 4.25V. Pushbutton switch S1 provides users a way to reset the output while S2 is used to soft-reset the microprocessor only. Figure 24 shows how to use the LTC1421 with a 5V supply and a – 48V supply that is used to generate a ±12V supply using a supply module. Resistors R3 and R4 are used to monitor the input voltage to the supply module. The module is prevented from turning on via the optoisolator until the input voltage reaches – 36V. Zener diode D2 prevents the CPON pin of the LTC1421 from being damaged by excessive voltage. Figure 25 shows how to use the LTC1421 to do overvoltage protection. Resistors R3 and R4 set the trip point at 7V. When the input supply voltage rises above 7V, Q2 is turned on and Q1 turned off while Q3 helps to discharge the output voltage. Figure 26 shows how to use the LTC1421 to control both the power-up and power-down sequence of the outputs. The 5V output would be powered up first followed by the 3V output. At power-down sequence, the 3V output would go down first followed by the 5V supply. Figure 27 shows how to use the LTC1421 to switch 3.3V, 5V, 12V and –12V supplies for PCI application. The rampup rate for 3.3V, 5V and 12V is determined by the ramp capacitor C2 while the –12V supply is controlled by R7 and C3. The internal comparator is being used to do the overcurrent protection for Q4 with the trip point set by resistors R6 and R8. The –12V supply does not have overcurrent protection. R10 is used to set the power good signal trip point at 10V. When the 12V output rises above 10V, the PCI controller gets a power good signal followed by RESET after 200ms. BACKPLANE – 48V – 48V STAGGERED CONNECTOR PC BOARD D1 5.1V S1 – 48V + R1 5.1k 1W C1 1µF 3 1 4 2 24 C2 2.2µF 25V + 12 13 14 8 11 15 6 7 10 9 R4 300Ω 1/8W 1µF R2 15k 1/8W Q2 MPSA06 R3 56k 1/2W R6 402Ω 1/8W R5 10k 1/2W + + C5 4.7µF 50V C4 4.7µF 50V + R8 1k 1/8W 3 C6 100µF 100V SW GND 4 R10 4.32k 1/8W R13 1.24k 1/8W D4 Q3 Q4 MBR3100 2N5401 2N5401 D3 MBR3100 C9 0.33µF 50V R9 1k 1/8W 1 FB VC LT1170HVCT VCC 5 D2 7.5V L1 100µH Figure 20. – 48V to 5V Hot Swappable Supply Using the LT1170HVCT 5 LTC1421 23 22 21 20 19 18 17 16 C3 2.2µF 25V Q1 IRFR9110 1421 F20 R14 4.64k 1/8W R11 4.32k 1/8W + C7 1000µF 25V + C8 1000µF 25V RESET R12 10k 1/8W VCC 5V 3A APPLICATIONS INFORMATION U U W U – 48V LTC1421/LTC1421-2.5 19 LTC1421/LTC1421-2.5 U U W U APPLICATIONS INFORMATION – 48V R1 5.1k 23 D1 4.3V STAGGERED CONNECTOR 22 19 5V 10A 17 18 11 R3 10k + 4.7k 1 + VICOR VI-J30-CY 100µF 100µF 0.1µF LTC1421 12 0.1µF – 8 24 3 13 2 15 GATE IN – 1µF 14 R2 300Ω 1N4148 C1 0.1µF – 48V 4N25 100Ω Q1 BACKPLANE 1421 F21 PC BOARD Figure 21. – 48V to 5V Hot Swappable Supply Q1 IRFR9110 24V C3 2.2µF 25V STAGGERED CONNECTOR R1 5.1k 1/4W + D1 5.1V 23 22 21 20 19 18 17 16 R3 56k 1/8W R4 10 300Ω 1/8W 9 LTC1421 4 3 1 S1 12 BACKPLANE C4 200µF 50V 2 VSW VIN 5 13 14 8 11 15 6 7 VC FB R5 10k 1/2W Q2 MPSA06 1µF R6 620Ω 1/8W R9 2.7k C6 0.01µF PC BOARD Figure 22. 24V to 5V Hot Swappable Supply Using the LT1074CT 20 4 LT1074CT 3 C1 1µF POR + R2 15k 1/8W GND C2 2.2µF 25V 2 24 FAULT + 5 1421 F22 1 L1 50µH D4 MBR745 R7 2.8k 1% R8 2.21k 1% 5V 5A + C5 500µF 25V BACKPLANE 5V STAGGERED CONNECTOR PC BOARD 12 LTC1421 6 7 8 14 13 15 9 10 11 10k S2 1µF C2 0.1µF R5 16V 510Ω 5% R4 10k 1% R8 100k 1% R9 26.7k 1% C10 1µF 16V R10 10k 5% + C4 0.1µF 16V C8 220pF CERAMIC C7 4700pF CERAMIC C3 220µF 16V ×4 6 5 7 2 SHDN G1 VCC PVCC1 C5 10µF 16V 4 1 C6 0.1µF 16V Q2 MTD20N03HL D1 1N4148 FB COMP R7 3 8 GND G2 7.5k 5% LTC1430CS8 + R6 22Ω 5% Figure 23. 5V to 3.3V Hot Swappable Supply Using the LTC1430CS8 S1: HARD POWER/CIRCUIT BREAKER RESET S2: SOFT RESET LTC1430 POWER-UP THRESHOLD: 4.8V ON 4.25V OFF S1 C1 1µF 16V 2 3 5 4 24 1 4 23 22 21 20 19 18 17 16 3 C9 330µF 10V ×6 Q4 MTD20N03HL 2.7µH 15A + Q3 MTD20N03HL 1421 F23 GND RESET µP VCC 3.3V 10A IMAX = 15A APPLICATIONS INFORMATION U U W U R1 0.003Ω Q1 1 3W, 5% 2 MTD20N03HL LTC1421/LTC1421-2.5 21 LTC1421/LTC1421-2.5 U U W U APPLICATIONS INFORMATION R1 0.005Ω 1 1W 2 5V 3 Q1 MTB50N06E STAGGERED CONNECTOR 22 21 20 19 18 17 16 + C2 1µF C1 1µF 13 14 8 11 15 6 LTC1421 4 3 1 5 7 C3 0.47µF – 48V 2 +IN +OUT ASTRODYNE ASD10-48D12 –IN – OUT CONTROL 6 1µF R3 340Ω 1/8W R5 4.3k 1/8W Q3 2N5401 S1 12 1 C5 220µF 100V 10 9 2 24 CLOAD R7 1k 1/8W 10k 23 5V 8A + 4 R4 10k 1/8W R6 15k 1/8W 1421 F24 IRF530 BACKPLANE PC BOARD Figure 24. 5V and – 48V to ±12V Hot Swappable Supply R1 0.005Ω Q1 1 1/2W 2 MTB50N06E 5V 3 1k 4 12Ω Q2 VN2222 Q3 VN2222 100Ω STAGGERED CONNECTOR 23 22 21 20 19 18 17 16 1 CLOAD R3 47.5k 10k C2 0.1µF 10 VCC 24 µP C1 1µF 3 2 12 S1 LTC1421 7 8 14 13 15 RESET GND 1µF R4 10k 1421 F25 BACKPLANE PC BOARD Figure 25. Hot Swappable 5V Supply with Overvoltage Protection 22 5V 8A + 3 + 5 + 12V 0.42A C7 100µF 16V –12V 0.42A C6 100µF 16V LTC1421/LTC1421-2.5 U U W U APPLICATIONS INFORMATION R2 0.005Ω 1W 1 2 5V 3 3 CLOAD STAGGERED CONNECTOR 10k 4 LTC1421 2 S1 C2 0.1µF 24V 10 11 6 7 8 14 13 15 9 24 3 C5 0.1µF 25V 21 20 19 18 17 16 1 5 3.3V 8A + 1k C1 1µF 16V CLOAD R3 1M 5%,1/8W 0.047µF 4 23 22 5V 8A + 4 R1 0.005Ω Q1 1 1W 2 MTB50N06E 3.3V Q2 MTB50N06E 12 R5 330k 1% 1/16W R4 1k 5% 1/16W VCC µP RESET GND 1µF R6 200k 1% 1/16W 1421 F26 BACKPLANE PC BOARD Figure 26. Power-Up and Power-Down Sequence Controller U PACKAGE DESCRIPTION Dimensions in inches (millimeters) unless otherwise noted. G Package 24-Lead Plastic SSOP (0.209) (LTC DWG # 05-08-1640) 5.20 – 5.38** (0.205 – 0.212) 8.07 – 8.33* (0.318 – 0.328) 24 23 22 21 20 19 18 17 16 15 14 13 1.73 – 1.99 (0.068 – 0.078) 0° – 8° 0.13 – 0.22 (0.005 – 0.009) 0.65 (0.0256) BSC 0.55 – 0.95 (0.022 – 0.037) NOTE: DIMENSIONS ARE IN MILLIMETERS *DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.152mm (0.006") PER SIDE **DIMENSIONS DO NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.254mm (0.010") PER SIDE 7.65 – 7.90 (0.301 – 0.311) 0.05 – 0.21 (0.002 – 0.008) 0.25 – 0.38 (0.010 – 0.015) 1 2 3 4 5 6 7 8 9 10 11 12 G24 SSOP 1098 SW Package 24-Lead Plastic Small Outline (Wide 0.300) (LTC DWG # 05-08-1620) 0.598 – 0.614* (15.190 – 15.600) 0.291 – 0.299** (7.391 – 7.595) 0.010 – 0.029 × 45° (0.254 – 0.737) 0.093 – 0.104 (2.362 – 2.642) 0.037 – 0.045 (0.940 – 1.143) 24 23 22 21 20 19 18 17 16 15 14 13 0° – 8° TYP 0.009 – 0.013 (0.229 – 0.330) NOTE 1 0.016 – 0.050 (0.406 – 1.270) 0.050 (1.270) BSC 0.014 – 0.019 (0.356 – 0.482) TYP 0.394 – 0.419 (10.007 – 10.643) NOTE 1 0.004 – 0.012 (0.102 – 0.305) NOTE: 1. PIN 1 IDENT, NOTCH ON TOP AND CAVITIES ON THE BOTTOM OF PACKAGES ARE THE MANUFACTURING OPTIONS. THE PART MAY BE SUPPLIED WITH OR WITHOUT ANY OF THE OPTIONS *DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE **DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE 1 2 3 4 5 Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 6 7 8 9 10 11 12 S24 (WIDE) 1098 23 LTC1421/LTC1421-2.5 U TYPICAL APPLICATION 1 12V 500mA 3 3.3V 7.5A PCI CONNECTOR Q3 2 1/2 IRF7101 R2 0.015Ω 5% 1W 4 R4 30Ω R10 100k R11 10Ω 1 2 4 R1 0.005Ω 5% 1/2W 3 23 R14 5.1k 22 R12 10Ω 21 10k 20 19 18 17 16 10 1 7 LTC1421 PCI POWER CONTROLLER C1 1µF 16V R6 100Ω 1% 1/16W R13 5.1k 6 1µF 8 14 3 ON/OFF C2 0.22µF 25V 11 24 5 3.3V 11.5A CIRCUIT BREAKER 5V 10A CIRCUIT BREAKER Q1 IRF7413 4 FAULT Q4 IRF7413 4 3 5V 5A 12V 3.3A CIRCUIT BREAKER R3 0.005Ω 5% 1 1W 2 13 2 15 12 9 R8 5.62k 1% 1/16W GND LOGIC POWER GOOD RST # RST # SELECT BITS BUS ENABLE DATA BUS QuickSwitch R7 130k Q5 TP0610T ALL RESISTORS 5%, 1/16W EXCEPT WHERE NOTED R5 20k –12V 100mA C3 1µF 25V R9 10Ω Q2 1/2 IRF7101 1421 F27 – 12V NO CIRCUIT BREAKER MOTHERBOARD OR BACKPLANE PCI PERIPHERAL Figure 27. PCI Power Controller RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LTC1155 Dual High Side Switch Driver Short-Circuit Protection and Micropower Standby Operation LTC1422 Hot Swap Controller in SO-8 System Reset Output with Programmable Delay LTC1477/LTC1478 Single and Dual Protected High Side Switches Inrush Current Limited, Built-In 2A Short-Circuit Protection LT1640L/LT1640H Negative Voltage Hot Swap Controller in SO-8 Operates from –10V to –80V LT1641 High Voltage Hot Swap Controller in SO-8 Operates from 9V to 80V LTC1642 Fault Protected Hot Swap Controller Operates Up to 16.5V, Protected to 33V LTC1643L/LTC1643H PCI-Bus Hot Swap Controller 3.3V, 5V and ±12V in Narrow 16-Pin SSOP LTC1645 2-Channel Hot Swap Controller Operates from 1.2V to 12V, Power Sequencing LTC1647 Dual Hot Swap Controller Dual ON Pins for Supplies from 3V to 15V 24 Linear Technology Corporation 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408)432-1900 ● FAX: (408) 434-0507 ● www.linear-tech.com 1421fc LT/LCG 0301 2K REV C • PRINTED IN USA LINEAR TECHNOLOGY CORPORATION 1996