NB100EP223 3.3V1:22 Differential HSTL/PECL to HSTL Clock Driver with LVTTL Clock Select and Output Enable The NB100EP223 is a low skew 1-to-22 differential clock driver, designed with clock distribution in mind, accepting two clock sources into an input multiplexer. The part is designed for use in low voltage applications which require a large number of outputs to drive precisely aligned low skew signals to their destination. The two clock inputs are differential HSTL or LVPECL and they are selected by the CLK_SEL pin which is LVTTL. To avoid generation of a runt clock pulse when the device is enabled/disabled, the Output Enable (OE), which is LVTTL, is synchronous ensuring the outputs will only be enabled/disabled when they are already in LOW state (See Figure 7). The NB100EP223 guarantees low output-to-output skew. The optimal design, layout, and processing minimize skew within a device and from lot to lot. In any differential output pair, the same bias and termination scheme is required. Unused output pairs should be left unterminated (open) to “reduce power and switching noise as much as possible.” Any unused single line of a differential pair should be terminated the same as the used line to maintain balanced loads on the differential driver outputs. The output structure uses an open emitter architecture and will be terminated with 50 to ground instead of a standard HSTL configuration (See Figure 6). The wide VIHCMR specification allows both pair of CLOCK inputs to accept LVDS levels. • 100 ps Typical Device-to- Device Skew • 25 ps Typical Within Device Skew • HSTL Compatible Outputs Drive 50 to Ground With No http://onsemi.com MARKING DIAGRAM* 64 NB100 EP223 AWLYYWW 1 64-LEAD LQFP CASE 848G THERMALLY ENHANCED FA SUFFIX A WL YY WW 64 1 = Assembly Location = Wafer Lot = Year = Work Week *For additional information, see Application Note AND8002/D ORDERING INFORMATION Offset Voltage Maximum Frequency >500 MHz • • 1 ns Typical Propagation Delay • LVPECL and HSTL Mode Operating Range: VCC = 3 V to 3.6 V Device Package Shipping NB100EP223FA LQFP-64 160 Units/Tray NB100EP223FAR2 LQFP-64 1500/Tape & Reel with GND = 0 V, VCCO = 1.6 V to 2.0 V Q Output will Default Low with Inputs Open • • Thermally Enhanced 64-Lead LQFP • CLOCK Inputs are LVDS-Compatible; Requires External 100 LVDS Termination Resistor Semiconductor Components Industries, LLC, 2003 June, 2003 - Rev. 5 1 Publication Order Number: NB100EP223/D VCC0 Q7 Q8 Q8 Q9 Q9 Q10 Q10 Q11 Q11 Q12 Q12 Q13 Q13 VCCO 48 49 Q7 VCCO NB100EP223 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 VCC0 Q6 50 31 Q14 Q6 51 30 Q14 Q5 52 29 Q15 Q5 53 28 Q15 Q4 54 27 Q16 Q4 55 26 Q16 Q3 56 25 Q17 Q3 57 24 Q17 Q2 58 23 Q18 Q2 59 22 Q18 Q1 60 21 Q19 Q1 61 20 Q19 Q0 62 19 Q20 Q0 63 18 Q20 VCC0 64 17 VCC0 12 13 14 15 16 Q21 VCC0 11 Q21 10 NC 9 NC 8 OE VCC 7 GND NC 6 LVPECL_CLK NC 5 LVPECL_CLK 4 CLK_SEL 3 HSTL_CLK 2 HSTL_CLK 1 VCC0 NB100EP223 All VCC, VCCO, and GND pins must be externally connected to appropriate Power Supply to guarantee proper operation (VCC VCCO). The thermally conductive exposed pad on package bottom (see package case drawing) is electrically connected to GND internally. Figure 1. 64-Lead LQFP Pinout (Top View) PIN DESCRIPTION FUNCTION TABLE PIN FUNCTION HSTL_CLK*, HSTL_CLK** LVPECL_CLK*, LVPECL_CLK** CLK_SEL** OE** Q0-Q21, Q0-Q21 VCC VCCO GND*** HSTL, LVPECL or LVDS Differential Inputs L L L H LVPECL Differential Inputs L H L H LVCMOS/LVTTL Input CLK Select H L HSTL_CLK HSTL_CLK LVCMOS/LVTTL Output Enable H H LVPECL_CLK LVPECL_CLK HSTL Differential Outputs Positive Supply_Core (3.0 V - 3.6 V) * The OE (Output Enable) signal is synchronized with the Positive Supply_HSTL Outputs(1.6V-2.0V) rising edge of the HSTL_CLK and LVPECL_CLK signal. Ground OE* CLK_SEL Q0-Q21 * Pins will default LOW when left open. ** Pins will default HIGH when left open. *** The thermally conductive exposed pad on the bottom of the package is electrically connected to GND internally. http://onsemi.com 2 Q0-Q21 NB100EP223 CLK_SEL HSTL_CLK 0 22 HSTL_CLK 22 LVPECL_CLK Q0-Q21 (HSTL) Q0-Q21 (HSTL) 1 LVPECL_CLK VCC GND Q VCCO D OE Figure 2. Logic Diagram ATTRIBUTES Characteristics Value Internal Input Pulldown Resistor 75 k Internal Input Pullup Resistor ESD Protection 37.5 k Human Body Model Machine Model Charged Device Model > 2 kV > 150 V > 2 kV Moisture Sensitivity (Note 1) Flammability Rating Level 3 Oxygen Index: 28 to 34 UL 94 V-0 @ 0.125 in Transistor Count 693 Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 1. For additional information, refer to Application Note AND8003/D. MAXIMUM RATINGS (Note 2) Parameter Symbol Condition 1 Condition 2 Rating Units VCC Core Power Supply GND = 0 V VCCO = 1.8 V 4 V VCCO HSTL Output Power Supply GND = 0 V VCC = 3.3 V 4 V VI PECL Mode Input Voltage GND = 0 V VI ≤ VCC 4 V Iout Output Current Continuous Surge 50 100 mA mA TA Operating Temperature Range 0 to +85 °C Tstg Storage Temperature Range -65 to +150 °C JA Thermal Resistance (Junction-to-Ambient) (See Application Information) 0 LFPM 500 LFPM 64 LQFP 64 LQFP 35.6 30 °C/W °C/W JC Thermal Resistance (Junction-to-Case) (See Application Information) 0 LFPM 500 LFPM 64 LQFP 64 LQFP 3.2 6.4 °C/W °C/W Tsol Wave Solder < 2 to 3 sec @ 248°C 265 °C 2. Maximum Ratings are those values beyond which device damage may occur. http://onsemi.com 3 NB100EP223 LVPECL DC CHARACTERISTICS VCC = 3.3 V; VCCO = 1.8 V; GND = 0 V 0°C Symbol Characteristic 85°C Min Typ Max Min Typ Max Min Typ Max Unit 82 100 130 82 100 130 82 100 130 mA ICC Power Supply Current VIH Input HIGH Voltage (Single-Ended) 2135 2420 2135 2420 2135 2420 mV VIL Input LOW Voltage (Single-Ended) 1490 1675 1490 1675 1490 1675 mV VIHCMR Input HIGH Voltage Common Mode Range (Differential) (Note 3) (Figure 4) LVPECL_CLK/LVPECL_CLK HSTL_CLK/HSTL_CLK 1.2 0.3 3.3 1.6 1.2 0.3 3.3 1.6 1.2 0.3 3.3 1.6 V V 150 A IIH Input HIGH Current IIL Input LOW Current VCC 25°C 150 CLK CLK 150 0.5 -150 0.5 -150 A 0.5 -150 NOTE: 100EP circuits are designed to meet the DC specifications shown in the above table, after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 lfpm is maintained. 3. VIHCMR min varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal. LVTTL/LVCMOS DC CHARACTERISTICS VCC = 3.3 V; VCCO = 1.8 V; GND = 0 V 0°C Symbol Min Characteristic 25°C Typ Max Min Typ Max VIH Input HIGH Voltage VIL Input LOW Voltage IIH Input HIGH Current -150 150 -150 150 Input LOW Current -300 300 -300 300 IIL NOTE: 2.0 85°C Min 2.0 Typ Max Unit 2.0 0.8 V 0.8 0.8 V -150 150 A -300 300 A 100EP circuits are designed to meet the DC specifications shown in the above table, after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 lfpm is maintained. HSTL DC CHARACTERISTICS VCC = 3.3 V; VCCO = 1.6-2.0 V; GND = 0 V 0°C Symbol Characteristic Min Typ 25°C Max Min Typ 85°C Max Min Typ Max Unit VOH Output HIGH Voltage (Note 4) 1000 1200 1000 1200 1000 1200 mV VOL Output LOW Voltage (Note 4) 0 400 0 400 0 400 mV VIH Input HIGH Voltage (Differential) HSTL_CLK/HSTL_CLK VX+100 1600 VX+100 1600 VX+100 1600 mV Input LOW Voltage (Differential) HSTL_CLK/HSTL_CLK -300 VX-100 -300 VX-100 -300 VX-100 mV VX Differential Cross Point Voltage 680 900 680 900 680 900 mV IIH Input HIGH Current -150 150 -150 150 -150 150 A IIL Input LOW Current -300 300 -300 300 -300 300 A VIL NOTE: 100EP circuits are designed to meet the DC specifications shown in the above table, after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 lfpm is maintained. 4. All outputs loaded with 50 to GND (See Figure 6). http://onsemi.com 4 NB100EP223 AC CHARACTERISTICS VCC = 3.0 V to 3.6 V; VCCO = 1.6 V to 2.0 V; GND = 0 V (Note 5) 0°C 25°C Min Typ fout < 500 MHz 600 750 tPLH tPHL Propagation Delay (Differential) LVPECL_CLK to Q HSTL_CLK to Q 700 800 900 900 1000 1100 tskew Within-Device Skew (Note 6) Device-to-Device Skew (Note 7) 25 100 tJITTER Random Clock Jitter (Figure 3) (RMS) VPP Input Swing (Differential Mode) (Note 9) (Figure 4) LVPECL, HSTL 150 tS OE Set Up Time (Note 8) 1.0 1.0 1.0 ns tH OE Hold Time 0.5 0.5 0.5 ns tr/tf Output Rise/Fall Time (20%-80%) 300 Symbol VOpp Characteristic Differential Output Voltage (Figure 3) Max 85°C Min Typ Max Min Typ 600 750 750 850 900 950 1100 1200 50 250 30 200 0.5 2 800 1200 Max 600 700 800 850 1000 1050 1300 1350 ps ps 65 450 50 250 115 450 ps ps 0.5 2 0.5 2 ps 800 1200 800 1200 Unit mV mV 450 700 150 275 450 700 150 350 500 750 ps 5. Measured with 750 mV (LVPECL) source or 1 V (HSTL) source, 50% duty cycle clock source. All outputs loaded with 50 to ground (See Figure 6). 6. Skew is measured between outputs under identical transitions and conditions on any one device. 7. Device-to-Device skew for identical transitions at identical VCC levels. 8. OE Set Up Time is defined with respect to the rising edge of the clock. OE High-to-Low transition ensures outputs remain disabled during the next clock cycle. OE Low-to-High transition enables normal operation of the next input clock (See Figure 7). 9. VPP is the differential input voltage swing required to maintain AC characteristics including tPD and device-to-device skew. 10 9.0 800 8.0 700 7.0 Q AMP (mV) 6.0 600 5.0 500 4.0 3.0 400 RMS JITTER (ps) OUTPUT AMPLITUDE (mV) 900 2.0 300 1.0 0 RMS JITTER (ps) 200 0.5 0.6 0.7 0.8 0.9 1.0 FREQUENCY (GHz) Figure 3. Output Frequency (FOUT) versus Output Voltage (VOPP) and Random Clock Jitter (tJITTER) http://onsemi.com 5 NB100EP223 VCC(LVPECL) VCCO(HSTL) VIH(DIFF) VIH(DIFF) VX VIHCMR VPP VPP VIL(DIFF) GND Figure 4. LVPECL Differential Input Levels VIL(DIFF) GND Figure 5. HSTL Differential Input Levels Z = 50 Q HSTL OUTPUT Q 50 50 GROUND Figure 6. HSTL Output Termination and AC Test Reference CLK CLK OE Q Q Figure 7. Output Enable (OE) Timing Diagram Resource Reference of Application Notes AN1405 - ECL Clock Distribution Techniques AND8002 - Marking and Date Codes AND8009 - ECLinPS Plus Spice I/O Model Kit AND8020 - Termination of ECL Logic Devices For an updated list of Application Notes, please see our website at http://onsemi.com. http://onsemi.com 6 NB100EP223 APPLICATIONS INFORMATION Using the thermally enhanced package of the NB100EP223 The NB100EP223 uses a thermally enhanced 64-lead LQFP package. The package is molded so that a portion of the leadframe is exposed at the surface of the package bottom side. This exposed metal pad will provide the low thermal impedance that supports the power consumption of the NB100EP223 high-speed bipolar integrated circuit and will ease the power management task for the system design. In multilayer board designs, a thermal land pattern on the printed circuit board and thermal vias are recommended to maximize both the removal of heat from the package and electrical performance of the NB100EP223. The size of the land pattern can be larger, smaller, or even take on a different shape than the exposed pad on the package. However, the solderable area should be at least the same size and shape as the exposed pad on the package. Direct soldering of the exposed pad to the thermal land will provide an efficient thermal conduit. The thermal vias will connect the exposed pad of the package to internal copper planes of the board. The number of vias, spacing, via diameters and land pattern design depend on the application and the amount of heat to be removed from the package. Maximum thermal and electrical performance is achieved when an array of vias is incorporated in the land pattern. The recommended thermal land design for NB100EP223 applications on multi-layer boards comprises a 4 X 4 thermal via array using a 1.2 mm pitch as shown in Figure 8 providing an efficient heat removal path. supply enough solder paste to fill those vias and not starve the solder joints. The attachment process for the exposed pad package is equivalent to standard surface mount packages. Figure 9, “Recommended solder mask openings”, shows a recommended solder mask opening with respect to a 4 X 4 thermal via array. Because a large solder mask opening may result in a poor rework release, the opening should be subdivided as shown in Figure 9. For the nominal package standoff of 0.1 mm, a stencil thickness of 5 to 8 mils should be considered. All Units mm 0.2 1.0 1.0 4.6 0.2 4.6 Thermal Via Array (4 X 4) 1.2 mm Pitch 0.3 mm Diameter Exposed Pad Land Pattern Figure 9. Recommended Solder Mask Openings All Units mm Proper thermal management is critical for reliable system operation. This is especially true for high-fanout and high output drive capability products. For thermal system analysis and junction temperature calculation the thermal resistance parameters of the package is provided: 4.6 Table 1. Thermal Resistance * 4.6 Thermal Via Array (4 X 4) 1.2 mm Pitch 0.3 mm Diameter LFPM JA C/W JC C/W 0 35.6 3.2 100 32.8 4.9 500 30.0 6.4 * Junction to ambient and Junction to board, four-conductor layer test board (2S2P) per JESD 51-8 These recommendations are to be used as a guideline, only. It is therefore recommended that users employ sufficient thermal modeling analysis to assist in applying the general recommendations to their particular application to assure adequate thermal performance. The exposed pad of the NB100EP223 package is electrically shorted to the substrate of the integrated circuit and GND. The thermal land should be electrically connected to GND. Exposed Pad Land Pattern Figure 8. Recommended Thermal Land Pattern The via diameter should be approximately 0.3 mm with 1 oz. copper via barrel plating. Solder wicking inside the via may result in voiding during the solder process and must be avoided. If the copper plating does not plug the vias, stencil print solder paste onto the printed circuit pad. This will http://onsemi.com 7 NB100EP223 PACKAGE DIMENSIONS LQFP FA SUFFIX 64-LEAD PACKAGE CASE 848G-02 ISSUE A 4 PL M M/2 -Z- 0.20 (0.008) T X−Y Z AJ AJ 64 49 1 48 PLATING -X- ÇÇÇÇ ÉÉÉÉ ÉÉÉÉ ÇÇÇÇ ÉÉÉÉ AA -Y- L B J AB B/2 L/2 D REF 16 33 0.08 (0.003) 32 17 M Y T−U NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MM. 3. DATUM PLANE E" IS LOCATED AT BOTTOM OF LEAD AND IS COINCIDENT WITH THE LEAD WHERE THE LEAD EXITS THE PLASTIC BODY AT THE BOTTOM OF THE PARTING PLANE. 4. DATUM X", Y" AND Z" TO BE DETERMINED AT DATUM PLANE DATUM E". 5. DIMENSIONS M AND L TO BE DETERMINED AT SEATING PLANE DATUM T". 6. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.25 (0.010) PER SIDE. DIMENSIONS A AND B DO INCLUDE MOLD MISMATCH AND ARE BASE DETERMINED AT DATUM PLAND E". METAL 7. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL NOT CAUSE THE LEAD WIDTH TO EXCEED THE MAXIMUM D DIMENSION BY MORE THAN 0.08 (0.003). DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT. MINIMUM SPACE BETWEEN PROTRUSION AND ADJACENT LEAD OR PROTRUSION 0.07 (0.003). 8. EXACT SHAPE OF EACH CORNER IS OPTIONAL. Z DIM A B C D F G H J K L M N P R S V W AA AB AC AD AE AF DETAIL AJ-AJ A/2 0.20 (0.008) E X−Y Z A DETAIL AH -E-T- AG AG G/2 SEATING PLANE G 0.08 (0.003) T 4 PL 60 PL D 64 PL 0.08 (0.003) M T X−Y V Z 0.05 (0.002) R S AC AE EXPOSED PAD 17 AD 32 S C 33 16 W N K P F AF H DETAIL AH 1 48 64 49 VIEW AG-AG http://onsemi.com 8 0.25 GAGE PLANE MILLIMETERS MIN MAX 10.00 BSC 10.00 BSC 1.35 1.45 0.17 0.27 0.45 0.75 0.50 BSC 1.00 REF 0.09 0.20 0.05 0.15 12.00 BSC 12.00 BSC 0.20 −−− 0 7 0 −−− −−− 1.60 11 13 11 13 0.17 0.23 0.09 0.16 0.08 −−− 0.08 −−− 4.50 4.78 4.50 4.78 INCHES MIN MAX 0.394 BSC 0.394 BSC 0.053 0.057 0.007 0.011 0.018 0.030 0.020 BSC 0.039 BSC 0.004 0.008 0.002 0.006 0.472 BSC 0.472 BSC 0.008 −−− 0 7 0 −−− −−− 0.063 11 13 11 13 0.007 0.009 0.004 0.006 0.003 −−− 0.003 −−− 0.180 0.188 0.180 0.188 NB100EP223 Notes http://onsemi.com 9 NB100EP223 ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). 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