NCP5209 Product Preview 4−In−1 PWM Buck and Tri−Linear DDR Power Controller The NCP5209 4−In−1 PWM Buck and Tri−Linear Power Controller is a complete ACPI compliant power solution for MCH and DDR memory. This IC combines the high efficiency of a PWM controller for the VDDQ supply with the simplicity of linear regulator for the VTT termination voltage as well as the MCH core supply voltage. This IC contains a synchronous PWM buck controller for driving two external NFETs to form the DDR memory supply voltage (VDDQ). The DDR memory termination regulator (VTT) is designed to track at the half of reference voltage while sourcing and sinking current. The two linear regulator controllers driving two external NFETs are cascaded to produce the MCH core voltage (VMCH). Protective features include, soft−start circuitry, under−voltage monitoring of 5VDUAL, 5VATX and 12VATX, and thermal shutdown. The IC is packaged in a QFN−20. http://onsemi.com MARKING DIAGRAM 20 NCP5209 AWLYYWW 1 20−LEAD QFN MN SUFFIX CASE 505AB 1 NCP5209 = Specific Device Code A = Assembly Location WL = Wafer Lot YY = Year WW = Work Week Features • • • • • • • • • • • • • • Synchronous PWM Buck Controller for VDDQ Integrated Power FETs with VTT Regulator Source/Sink up to 2.0 A Two Linear Regulator Drivers for VMCH All External Power MOSFETs are N−Channel Adjustable VDDQ and VMCH by External Dividers VTT Tracks at Half the Reference Voltage or can be Adjusted Externally Fixed Switching Frequency of 250 kHz for DDQ Regulator in Normal Mode Doubled switching frequency (500 kHz) for DDQ Regulator in Standby Mode Soft−Start Protection for all Regulators Under−Voltage Monitoring of Supply Voltages Over−Current Protection for DDQ and VTT Regulators Fully Complies with ACPI Power Sequencing Specifications Protects against Reverse DIMM Insertion Thermal Shutdown Housed in QFN−20 Applications PIN CONNECTIONS COMP FBDDQ SW_DDQ BG_DDQ TG_TDQ BOOT SS PGND VTT VDDQ 5VDUAL OCDDQ BUF_Cut DRV_2P4 FB2P4 DRV_1P5 AGND FBVTT DDQ_REF FB1P5 NOTE: Pin 21 is the thermal pad on the bottom of the device. ORDERING INFORMATION Device NCP5209MN Package Shipping† 20−Lead QFN* Rail NCP5209MNR2 20−Lead QFN* • DDR I and DDR II Memory and MCH Power Supply Tape and Reel *5 x 6 mm †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D. This document contains information on a product under development. ON Semiconductor reserves the right to change or discontinue this product without notice. Semiconductor Components Industries, LLC, 2003 December, 2003 − Rev. P1 1 Publication Order Number: NCP5209/D NCP5209 CL1 5VATX BUF_Cut RL1 BUF_Cut BOOT SCHOTTKY CSS VTT 1.25 V, 12VATX 13 V Zener 5VDUAL VTT 1.8 Apk SCHOTTKY OCDDQ SS 5VDUAL R3 COUT2 FBVTT R4 TGDDQ M1 REF_SNS L DDQ_REF AGND NCP5209 M2 BGDDQ PGND DRV_2P4 COMP_DDQ 2P4V R5 FB2P4 CZ2 CZ1 COUT3 RZ1 R6 CP1 RZ2 R1 FBDDQ DRV_1P5 M4 R2 1P5V R7 FB1P5 VDDQ 1.5 V, 7 A COUT4 R8 Figure 1. Application Diagram http://onsemi.com 2 2.5 V, 20 A COUT1 SWDDQ 3.3VATX M3 VDDQ NCP5209 VREF1 VOLTAGE and CURRENT REFERENCE CL1 RL1 5VATX VREF2 _VREFQD OCDDQ THERMAL SHUTDOWN TSD BOOT 12VATX BUF_CUT BOOT BOOT CONTROL _BOOTGD R10 VREF1 R11 + LOGIC S0 BOOT− UVLO Schottky 13 V Zener Schottky S3 5VDUAL − 5VDUAL _INREGDDQ 5VDUAL R12 + VREF1 R13 − ILIM 5VDUAL− UVLO 5VDLGD + IREF BOOT − TGDDQ M1 VDDQ OCDDQ L R14 + VREF1 − R15 PGND VDDQ PWM LOGIC 5VATX− UVLO _5VDLGD SDDQ BOOT SS CSS M2 PGND PGND OSC COUT1 RSWDDQ BGDDQ S0 COMP_DDQ S3 VREF1 AMP + + A1 CZ2 CP1 CZ1 R1 RZ2 RZ1 − − FBDDQ R2 DDQ_REF 5VDUAL S0 R16 VTT Regulation Control − M2 VTT R17 AGND 5VDUAL VTT R18 R3 − R19 COUT2 M3 + R4 AGND PGND VREF2 VDDQ + FBVTT 5VDUAL BOOT DRV_2P4 + M3 2P4V − R5 AGND S0 VREF2 PGND 5VDUAL FB2P4 BOOT R6 COUT3 + M4 − DRV_IP5 R7 PGND 1P5V AGND FB1P5 R8 AGND Figure 2. Internal Block Diagram. http://onsemi.com 3 COUT4 NCP5209 PIN DESCRIPTION Pin Symbol Descriptions 1 COMP VDDQ Error Amplifier Compensation Node. 2 FBDDQ VDDQ Regulator Feedback Pin for Closed Loop Regulation. 3 SS 4 PGND Soft Start Capacitor Connection to Ground. Power Ground 5 VTT 6 VDDQ VTT Regulator Output Power Input for VTT Linear Regulator 7 AGND Analog Ground Connection and Remote Ground Sense. 8 FBVTT VTT Linear Regulator Feedback pin for Closed Loop Regulation. 9 DDQ_REF 10 FB1P5 11 DRV_1P5 VDDQ Reference Voltage Input of VTT Regulator. 2nd Linear Regulator Feedback Pin for Closed Loop Regulation. 2nd Linear Regulator Gate Driver Output for N−Channel Power FET. 12 FB2P4 13 DRV_2P4 1st Linear Regulator Feedback Pin for Closed Loop Regulation. 1st Linear Regulator Gate Driver Output for N−Channel Power FET. 14 BUF_CUT Active High Control Signal to Activate S3 Sleep State. 15 OCDDQ Over−current Sense and Program Input for the VDDQ High Side FET. 16 5VDUAL 5 V Dual Supply Input 17 BOOT Gate Driver Input Supply. A Boost Capacitor is Connected between SWDDQ and BOOT. 18 TGDDQ Gate Driver Output for VDDQ Regulator High Side N−Channel Power FET. 19 BGDDQ Gate Driver Output for VDDQ Regulator Low Side N−Channel Power FET. 20 SWDDQ DDQ Regulator Current Limit Sense Input. A Protection Resistor Should be Connected between the Inductor Driven Node and SWDDQ. 21 TH_PAD Copper pad on bottom of IC used for heatsinking. This pin should be connected to the ground plane under the IC. MAXIMUM RATINGS Rating Symbol Value Unit 5VDUAL −0.3, 6.0 V Gate Drive (Pin 11, 13, 17) to AGND (Pin 7) Vg −0.3, 14 V Gate Drive (Pin 18, 19) to AGND (Pin 7) Vg −0.3 DC, −4.0 for 100 ns; 14 V Input / Output Pins to AGND (Pin 7) Pin 1−6, 8−10, 12, 14−15, 20 VIO −0.3, 6.0 V Thermal Characteristics QFN−20 Plastic Package Thermal Resistance Junction−to−Air RJA_Q 68 °C/W Operating Junction Temperature Range TJ 0 to + 150 °C Operating Ambient Temperature Range TA 0 to + 70 °C Storage Temperature Range Tstg − 55 to +150 °C Moisture Sensitivity Level MSL Power Supply Voltage (Pin 16) to AGND (Pin 7) 1. This device series contains ESD protection and exceeds the following tests: Human Body Model (HBM) ≤ 2.0 kV per JEDEC standard: JESD22–A114. Machine Model (MM) ≤ 200 V per JEDEC standard: JESD22–A115. 2. Latch–up Current Maximum Rating: ≤ 150 mA per JEDEC standard: JESD78. http://onsemi.com 4 NCP5209 ELECTRICAL CHARACTERISTICS (5VDUAL = 5 V, BOOT = 12 V, 5VATX = 5 V, DDQ_REF = 2.5 V, TA = 0 to 70°C, L = 1.7 H, COUT1 = 3770 F, COUT2 = 470 F, COUT3 = 680 F, COUT4 = 3300 F, CSS = 33 nF, RL1 = 50 k, R1 = 2.2 k, R2 = 2 k, R3 = 0 , R4 = 1 k, R5 = 10 k, R6 = 5 k, R7 = 6.8 , R8 = 7.5 k, RSWDDQ = 1 k, RZ1 = 20 k, RZ2 = 8 , CP1 = 10 nF, CZ1 = 6.8 nF, CZ2 = 100 nF, for min/max values unless otherwise noted.) Characteristic Test Conditions Symbol Min Typ Max Unit 5VDUAL Operating Voltage V5VDUAL 4.5 5.0 5.5 V OCDDQ Operating Voltage VOCDDQ 4.5 5.0 5.5 V 12.0 13.2 V SUPPLY VOLTAGE BOOT Operating Voltage VBOOT Supply Current S0 mode Supply Current from 5VDUAL BUF_CUT = LOW, BOOT = 12 V, 5VATX = 5 V I5VDL_S0 7.0 mA S3 mode Supply Current from 5VDUAL BUF_CUT = HIGH, 5VATX = 0 V I5VDL_S3 5.0 mA S5 mode Supply Current from 5VDUAL BUF_CUT = LOW, 5VATX = 0 V I5VDL_S5 1.0 mA S0 mode Supply Current from BOOT BUF_CUT = LOW, BOOT=12 V, 5VATX = 5 V, TGDDQ, BGDDQ, DRV_2P4 and DRV_1P5 Open IBOOT_S0 40 mA S3 mode Supply Current from BOOT BUF_CUT = HIGH, 5VATX=0 V, TGDDQ, BGDDQ, DRV_2P4 and DRV_1P5 Open IBOOT_S3 10 mA 5VDUAL UVLO Upper Threshold V5VDLUV+ 4.4 V 5VDUAL UVLO Hysteresis V5VDLhys Under−Voltage−Monitor BOOT UVLO Upper Threshold 300 VBOOTUV+ BOOT UVLO Hysteresis mV 10.2 VBOOThys 1.0 V V OCDDQ UVLO Upper Threshold OCDDQUV+ 1.25 V OCDDQ UVLO Hysteresis OCDDQhys 200 mV Tsd 140 °C Tsdhys 25 °C Thermal Shutdown Thermal Shutdown Thermal Shutdown Hysteresis DDQ Switching Regulator FBDDQ Feedback Voltage, Control Loop in Regulation Feedback Input Current TA = 25°C TA = 0 to 70°C VFBQ V(FBDDQ) = 1.190 V IDDQfb 1.178 1.166 1.190 1.190 1.202 1.214 V 1.0 A Oscillator Frequency in S0 Mode FDDQS0 225 250 275 kHz Oscillator Frequency in S3 Mode FDDQS3 450 500 550 kHz IOCDDQ 28 40 52 A Current Limit Blanking Time in S0 Mode TDDQbk 400 ns Minimum Duty Cycle in S0 Mode DS0min 0 % Maximum Duty Cycle in S0 Mode DS0max OCDDQ pin Current Sink V(OCDDQ) = 3 V 100 % DDQ Switching Regulator Minimum Duty Cycle in S3 Mode DS3min Maximum Duty Cycle in S3 Mode DS3max Soft−Start Timing 0 % 90 % Tss1 10 ms GAINDDQ 70 dB DDQ ERROR AMPLIFIER DC Gain http://onsemi.com 5 NCP5209 ELECTRICAL CHARACTERISTICS (5VDUAL = 5 V, BOOT = 12 V, 5VATX = 5 V, DDQ_REF = 2.5 V, TA = 0 to 70°C, L = 1.7 H, COUT1 = 3770 F, COUT2 = 470 F, COUT3 = 680 F, COUT4 = 3300 F, CSS = 33 nF, RL1 = 50 k, R1 = 2.2 k, R2 = 2 k, R3 = 0 , R4 = 1 k, R5 = 10 k, R6 = 5 k, R7 = 6.8 , R8 = 7.5 k, RSWDDQ = 1 k, RZ1 = 20 k, RZ2 = 8 , CP1 = 10 nF, CZ1 = 6.8 nF, CZ2 = 100 nF, for min/max values unless otherwise noted.) Characteristic Test Conditions Symbol Min Typ Max Unit COMP_DDQ = 220 nF, 1 in Series GBWDDQ TBD MHz COMP_DDQ = 10 pF SRDDQ 8.0 V/s IOUT= 0 to 2.0 A (Sink Current) IOUT= 0 to –2.0 A (Source Current) adVTTS0 DDQ ERROR AMPLIFIER Gain−Bandwidth Product Slew Rate VTT Active Termination Regulator VTT tracking REF_SNS/2 at S0 mode −30 30 mV VTT Source Current Limit ILIMVTsrc 2.4 A VTT Sink Current Limit ILIMVTsnk 2.4 A RDDQ_REF 50 k DDQ_REF Input Resistance Dual Linear Regulator Controller 1st Regulator Feedback Voltage, Control Loop in Regulation TA = 0°C to 70°C 1st Regulator Feedback Input Current 0.784 0.800 IFB2P4 1st Regulator DC Gain 2nd Regulator Feedback Voltage, Control Loop in Regulation VFB2P4 1.0 GAIN2P4 TA = 0°C to 70°C 2nd Regulator Feedback Input Current VFB1P5 66 0.784 0.800 IFB1P5 2nd Regulator DC Gain Internal Soft−Start Timing 0.816 V A dB 0.816 V 1.0 A GAIN1P5 66 dB Tss2 1.5 ms Control Section BUF_CUT Input Logic HIGH Logic_H BUF_CUT Input Logic LOW Logic_L 0.8 V ILogic 1.0 A BUF_CUT Input Current 2.0 V Gate Drivers TGDDQ Gate Pull−HIGH Resistance BOOT = 12 V, V(TGDDQ) = 11.9 V RH_TG 3.5 TGDDQ Gate Pull−LOW Resistance BOOT = 12 V, V(TGDDQ) = 0.1 V RL_TG 2.5 BGDDQ Gate Pull−HIGH Resistance BOOT = 12 V, V(BGDDQ) = 11.9 V RH_BG 3.5 BGDDQ Gate Pull−LOW Resistance BOOT = 12 V, V(BGDDQ) = 0.1 V RL_BG 1.3 DRV_2P4 Gate Pull−HIGH Voltage BOOT = 12 V VH2P4 9.0 V DRV_2P4 Gate Pull−LOW Voltage BOOT = 12 V VL2P4 0.8 V DRV_2P4 Gate Source Current BOOT = 12 V IH2P4 10 mA DRV_2P4 Gate Sink Current BOOT = 12 V IL2P4 10 mA DRV_1P5 Gate Pull−HIGH Voltage BOOT = 12 V VH1P5 9.0 V DRV_1P5 Gate Pull−LOW Voltage BOOT = 12 V VL1P5 0.8 V DRV_1P5 Gate Source Current BOOT = 12 V IH1P5 10 mA DRV_1P5 Gate Sink Current BOOT = 12 V IL1P5 10 mA http://onsemi.com 6 NCP5209 DETAILED OPERATION DESCRIPTIONS S0 normal operating mode, in which, all regulators are running. The transition of BUF_CUT from LOW to HIGH in S0 mode triggers the device into the S3 sleep mode. In S3 mode, the external 12VATX and 5VATX supplies collapse and only the VDDQ regulator is working. General The NCP5209 4−In−1 PWM Buck and Tri−Linear DDR Power Controller contains a high efficiency PWM controller, an integrated two−quadrant linear regulator and two linear regulator controllers. The VDDQ supply is generated by a PWM controller driving two external NFETs. The VTT termination voltage is tracked by an integrated linear regulator with sourcing and sinking current capability. The dual linear controllers driving two external NFETs can either be cascaded to create the MCH core voltage or work independently to produced two regulated output voltages. All regulator outputs are adjustable. The inclusion of soft−start, supply under−voltage monitors, over−current protection and thermal shutdown, makes this device a complete power solution for the MCH and DDR memory system. This device is packaged in QFN−20. During S3 mode, the transition of BUF_CUT from HIGH to LOW triggers the device back to S0 mode providing 12ATX and 5VATX are good. The IC can re−enter S5 mode from S0 mode by removing one of the supplies. Transitions from S3 to S5 or vice versa are not allowed. A timing diagram is shown in Figure 4. Table 1 summarizes the operating states of all regulators and the conditions of the output pins. S5−To−S0 Mode Power Up Sequence An internal bandgap reference is generated whenever 5VDUAL exceeds 2.7 V. Once this bandgap reference is in regulation, an internal signal _VREFGD is asserted to wake up the ACPI logic. The assertion of VREFGD enables the ACPI control logic. Once the ACPI control is activated, the power up sequence starts by waking up the 5VDUAL voltage monitor block and reference current generator first. After 5VDUAL is within the preset level, the BOOT and OCDDQ under voltage monitor blocks are enabled to detect the presence of the 12VATX and 5VATX supplies. When the three supplies are in regulation and BUFCUT is LOW the device enters S0 mode by activating the soft−start of VDDQ switching regulator. After the VDDQ regulator is in regulation and the soft−start interval is completed, the _INREGDDQ signal is asserted to wake up the VTT regulator and the dual linear controllers. ACPI Control Logic The ACPI control logic is powered by the 5VDUAL supply input. The BUF_CUT input and the three supply voltage monitoring signals from the internal UVLOs are used to decode the operating mode in accordance with the state transition diagram shown in Figure 5. The 5VDUAL supply must come up before the other supplies. The UVLOs monitor the motherboard supplies 5VDUAL, 12VATX and 5VATX through the 5VDUAL, BOOT and OCDDQ pins respectively. Three control signals, _5VDUALGD, _BOOTGD and _OCDDQGD, are asserted when the supply voltages are in good condition. When the device is first powered up, it is in S5 shutdown mode to minimize the power consumption. When all three supplies are good and BUF_CUT is LOW the device enters Table 1. Mode, Operation and Output Pin Condition OPERATING CONDITIONS OUTPUT PIN CONDITIONS MODE DDQ VTT Dual Linear TGDDQ BGDDQ DRV_2P4 DRV_1P5 S0 Normal Normal Normal Normal Normal Normal Normal S3 Standby H−Z H−Z Standby Standby Low Low S5 H−Z H−Z H−Z Low Low Low Low http://onsemi.com 7 NCP5209 VDDQ Switching Regulator Since the OCDDQ pin is also used for detecting the 5VATX power supply, the upper threshold of the 5VATX UVLO is set to 1.25 V. Therefore, RL1 must be selected in such a way that the voltage at the OCDDQ pin must be higher than this threshold to avoid false triggering of the UVLO. In S3 mode, this over−current protection feature is disabled. The VDDQ regulator in S0 mode is a synchronous buck controller that drives two external power NFETs to supply up to 25 A. It employs the voltage mode fixed frequency PWM control scheme with external compensation switching at 250 kHz ± 10%. As shown in Figure 2, the VDDQ output voltage is divided down and fed back to the inverting input of an amplifier through the FBDDQ pin to close the loop at VDDQ = VFBQ × (1 + R2/R1). This amplifier compares the feedback voltage with an internal VREF1 (=1.190 V) to generate an error signal for the PWM comparator. This error signal is further compared with a fixed frequency RAMP waveform to generate a PWM signal. This PWM signal drives the external NFETs via the TG_DDQ and BG_DDQ pins. External inductor L and capacitor COUT1 filter the output voltage. When the NCP5209 leaves S5 mode, the VDDQ output voltage ramps up at a rate controlled by the capacitor at the SS pin. When VDDQ is regulating in S0 mode, a signal _INREGDDQ goes HIGH. In S3 standby mode, the switching frequency is doubled to reduce the conduction loss in the external NFETs. Feedback Compensation of VDDQ Regulator The compensation network is shown in Figure 2. VTT Active Terminator The VTT active terminator is a two quadrant linear regulator with two internal NFETs to provide current sink and source capability up to 2.0 A. It is active only when the VDDQ regulator is in regulation in S0 mode. It draws power from VDDQ with the internal gate drive power derived from 5VDUAL. While the VTT output is directly connected to the FBVTT pin, the VTT voltage is designed to automatically track at the half of the DDQ_REF voltage. This VTT voltage can be adjusted by using an external resistor divider in the feedback loop. This regulator is stable with any value of output capacitor greater than 470 F, and is insensitive to ESR ranging from 1 m to 400 m. Tolerance of VDDQ Both the tolerance of VFBDDQ and the ratio of external resistor divider R2/R1 impact the precision of VDDQ. When the control loop is in regulation, VDDQ = VFBQ × (1 + R2/R1). With a worst case (for all valid operating conditions) VFBDDQ tolerance of ±2.0%, a worst case range of ±2.5% for VDDQ can be assured if the ratio R2/R1 is specified as 1.10 ±1%. Fault Protection of VTT Active Terminator To provide protection for the internal FETs, a bi−directional current limit set to 2.4 A is implemented. This current limit is also used as a constant current source during VTT startup. Dual Linear Regulators Fault Protection of VDDQ Regulator The dual linear regulators are formed by two high−gain controllers driving external NFETs. They are activated after the DDQ regulator is in regulation in S0 mode. The output voltage of each regulator is fed back through an external resistor divider. The feedback voltage is compared to an internal reference voltage VREF2 (=0.800 V) to achieve voltage regulation. Both linear regulators use a common soft−start ramp voltage set to 1.5 ms. Once they are activated, hiccup mode is employed during the soft−start period to protect them against short circuit or power failure conditions. In the soft−start interval, the feedback voltages of both regulators are compared with the soft−start ramping voltage. If either one of feedback voltages is 100 mV below the SS ramping voltage, a short circuit or power failure condition is detected, In S0 mode, an external resistor (RL1) connecting the 5VATX supply to the OCDDQ pin sets the current limit for the high−side switch. An internal 40 A current sink at the OCDDQ pin establishes a voltage drop across this resistor. The inductor node voltage is sensed at the SWDDQ pin through a resistor (RSWDDQ). The voltage at the OCDDQ pin is compared to the voltage at the SWDDQ pin when the high−side FET is turned on after a fixed period of blanking time thus avoiding false current limit triggering. If the voltage at SW_DDQ is lower than that at OCDDQ, an over−current condition occurs, during which, all regulators are latched off to protect against over−current. The IC can be powered up again only if any one of supply voltages (5VDUAL, 12VATX or 5VATX) is recycled or the SS pin is discharged to ground externally. http://onsemi.com 8 NCP5209 reduce the internal power consumption as well as to avoid soft−start issues. causing both regulators to be reset and initiate the soft start sequence again, as depicted in Figure 3. This hiccup mode feature is disabled once after both outputs are in regulation. Fault Protection of Dual Linear Regulators Internal soft−start is built−in to limit the in−rush current. 3.3VATX BOOT Pin Supply Voltage In a typical application, a flying capacitor is connected between the inductor LX node and the BOOT pin. In S0 mode, the 12VATX supply is tied to the BOOT pin through a Schottky diode. A 13 V zener diode must be put as close to the BOOT pin as possible to clamp the boot strapping voltage produced by the flying capacitor. In S3 mode the 12VATX supply is collapsed. The BOOT voltage is created by the Schottky diode between 5VDUAL and BOOT pins and the flying capacitor. _INREGDDQ DRV_1P5 V1P5 Thermal Consideration Assuming an ambient temperature of 50°C, the maximum allowed dissipated power of the QFN−20 package is 1.45 W. Thus a maximum of 0.8 A of DC current can be handled by the VTT regulator in S0 mode. To take full advantage of the thermal capability of this package, the exposed pad underneath must be soldered directly onto a PCB metal substrate to allow good thermal contact. V1P5 Loading Figure 3. Hiccup Mode Soft−start of Dual Linear Regulators Thermal Shutdown The device will enter S5 mode from any operating mode if the junction temperature of the NCP5209 exceeds 140°C. It will resume normal operation (from S5 to S0 mode) when the junction temperature falls below 115°C. These two linear regulators can be cascaded to generate the 1.5 V MCH core voltage with 2.4 V as the intermediate voltage. By using the 3.3 V ATX as the power supply for the external NFETs, up to 7 A can be delivered. If only one linear regulator is used, it is recommended to pull the feedback pin of the unused regulator to 5VDUAL to http://onsemi.com 9 NCP5209 Power Up and Power Down Timing 5VSTBY or 5VDUAL 12 V 5V BUF_CUT PWRGD DDQ−S0 VTT Dual Lin State 1 2 3 4 5 6 7 8 9 10 SO 1 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 11 12 13 14 15 S3 16 SO 17 18 19 S5 5VSTBY or 5VSTB is ultimate chip enable. This supply has to be up first to ensure gates are in known state. 12 V and 5 V Supplies can Ramp in Either Order PWRGD asserts to indicate 5VDUAL has switched to 5VCC DDQ ramps up with timing set by the SS pin MCH and VTT both ramp once DDQ SS is completed and DDQ is within 90% of regulated voltage SO Operation Prepare S3 Mode −− BUF_CUT = H VTT and MCH will be turned off 12V and 5V ramp down to 0 volts, so as PWRGD Standard S3 State 12V and 5V ramp back to regulation PWRGD PWRGD ramps up to indicate that 5VDUAL has switched to 5VCC DDQ switches back to 250kHz and MCH ramps up VTT ramps up after BUF_CUT goes LOW SO Operation S5 mode −− BUF_CUT = L and (12VUVLO = L or 5VUVLO = L ) DDQ, VTT and MCH turned off S5 Mode Figure 4. Timing Diagram http://onsemi.com 10 5VDUAL OCDDQ NCP5209 State Transition Diagram S5 BUF_CUT=0 AND _BOOTGD=1 AND _OCDDQGD=1 BUF_CUT=0 AND (_BOOTGD=0 OR _OCDDQGD=0) S0 BUF_CUT=1 BUF_CUT=0 AND _BOOTGD=1 AND _OCDDQGD=1 S3 NOTES: Note: 5VDUAL is assumed to be in good conditions in any mode. All possible state transitions are shown. All unspecified inputs do not cause any state change. Figure 5. State Transition Diagram. Applications Information In some systems, the switching of 5VDUAL from 5VSTBY to 5VATX or vice versa does not automatically occur during mode transitions. To avoid overloading the 5VSTBY supply, a PWRGD signal, which is asserted only when 5VDUAL has been switched over to 5VATX, is created. This PWRGD signal is then used for controlling one of the UVLOs of this device so that the device can only enter S0 after the 5VDUAL has been switched over to 5VATX. http://onsemi.com 11 NCP5209 PACKAGE DIMENSIONS 20 PIN QFN, DUAL−SIDED, 6x5 mm MN SUFFIX CASE 505AB−01 ISSUE O A D NOTES: 1. DIMENSIONS AND TOLERANCING PER ASME Y14.5M, 1994. 2. DIMENSIONS IN MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINALS AND IS MEASURED BETWEEN 0.25 AND 0.30 MM FROM TERMINAL 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. B PIN 1 LOCATION E 2X 0.15 C DIM A A1 A2 A3 b D D2 E E2 e K L 2X 0.15 C 0.10 C A2 A 0.08 C A1 (A3) C MILLIMETERS MIN MAX 0.80 1.00 0.00 0.05 0.65 0.75 0.20 REF 0.23 0.28 6.00 BSC 3.98 4.28 5.00 BSC 2.98 3.28 0.50 BSC 0.20 −−− 0.50 0.60 SEATING PLANE D2 20 X L 20 X e 1 10 E2 K 20 11 20 X b 0.10 C A B 0.05 C NOTE 3 ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada Email: [email protected] N. American Technical Support: 800−282−9855 Toll Free USA/Canada ON Semiconductor Website: http://onsemi.com Order Literature: http://www.onsemi.com/litorder Japan: ON Semiconductor, Japan Customer Focus Center 2−9−1 Kamimeguro, Meguro−ku, Tokyo, Japan 153−0051 Phone: 81−3−5773−3850 http://onsemi.com 12 For additional information, please contact your local Sales Representative. NCP5209/D