NCP5210 Product Preview 3−In−1 PWM Dual Buck and Linear DDR Power Controller The NCP5210, 3−In−1 PWM Dual Buck and Linear DDR Power Controller, is a complete power solution for MCH and DDR memory. This IC combines the efficiency of PWM controllers for the VDDQ supply and the MCH core supply voltage with the simplicity of linear regulator for the VTT termination voltage. This IC contains two synchronous PWM buck controller for driving four external NFETs to form the DDR memory supply voltage (VDDQ) and the MCH regulator. The DDR memory termination regulator (VTT) is designed to track at the half of the reference voltage with sourcing and sinking current. Protective features include, soft−start circuitry, under−voltage monitoring of 5VDUAL, and BOOT voltage, and thermal shutdown. The IC is packaged in a QFN−20. Features • Incorporates Synchronous PWM Buck Controllers for VDDQ and • • • • • • • • • • • • • VMCH Integrated Power FETs with VTT Regulator Source/Sink up to 2.0 A All External Power MOSFETs are N−channel Adjustable VDDQ and VMCH by External Dividers VTT Tracks at Half the Reference Voltage Fixed Switching Frequency of 250 kHz for VDDQ and VMCH Doubled Switching Frequency (500 kHz) for VDDQ Controller in Standby Mode to Optimize Inductor Current Ripple and Efficiency Soft−start Protection for all Controllers Under−Voltage Monitor of Supply Voltages Over−Current Protections for DDQ and VTT Regulators Fully Complies with ACPI Power Sequencing Specifications Short Circuit Protection Prevents Damage to Power Supply Due to Reverse DIMM Insertion Thermal Shutdown 20−Lead 5x6 QFN Package http://onsemi.com • DDR I and DDR II Memory and MCH Power Supply NCP5210 AWLYYWW 1 20−LEAD QFN MN SUFFIX CASE 505AB 1 NCP5210 = Specific Device Code A = Assembly Location WL = Wafer Lot YY = Year WW = Work Week PIN CONNECTIONS COMP FBDDQ SW_DDQ BG_DDQ TG_TDQ BOOT SS PGND VTT VDDQ 5VDUAL COMP_1P5 BUF_Cut TG_1P5 BG_1P5 GND_1P5 AGND FBVTT DDQ_REF FB1P5 NOTE: Pin 21 is the thermal pad on the bottom of the device. ORDERING INFORMATION Device NCP5210MN Typical Applications MARKING DIAGRAM 20 Package Shipping† 20−Lead QFN* Rail NCP5210MNR2 20−Lead QFN* Tape and Reel *5 x 6 mm †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D. This document contains information on a product under development. ON Semiconductor reserves the right to change or discontinue this product without notice. Semiconductor Components Industries, LLC, 2003 December, 2003 − Rev. P3 1 Publication Order Number: NCP5210/D NCP5210 BUF_Cut BUF_Cut SS 12 V CSS BOOT VTT 1.25 V, 13 V Zener VTT 5VDUAL 5VDUAL 1.8 Apk COUT2 FBVTT M1 AGND DDQ_REF R5 COUT1 SWDDQ CPM1 RZM2 RZM1 M2 COMP_1P5 BGDDQ FB_1P5 PGND 5VDUAL R6 CZ2 COMP M3 VMCH 2.5 V, 20 A L NCP5210 CZM1 CZM2 VDDQ TGDDQ VDDQ TG_1P5 CZ1 RZ1 L CP1 RZ2 R1 FBDDQ R2 1.5 V, 10 A COUT3 M4 BG_1P5 VDDQ GND_1P5 Figure 1. Application Diagram http://onsemi.com 2 NCP5210 VREF VOLTAGE and CURRENT REFERENCE VCC THERMAL SHUTDOWN _VREFGD TSD 12 V BOOT 13 V Zener BUF_CUT VCC _BOOTGD 5VDUAL S0 CONTROL LOGIC BOOT_ R10 5VDUAL S3 UVLO VREF R11 INREGMCH 5VDUAL INREGDDQ ILIM RL1 5VDUAL + 5VDUAL_ UVLO R13 IREF VCC − R12 VDDQ M1 and _5VDLGD VREF V1P5 PGND PWM LOGIC L TG_DDQ SW_DDQ VDDQ COUT1 VCC BG_DDQ M2 PGND PGND CSS OSC S0 S3 COMP VREF AMP CZ2 CP1 CZ1 RZ1 A1 5VDUAL FBDDQ VCC R1 RZ2 R2 M3 180 Phase Shift VCC L2 TP_1P5 PGND BG_1P5 VMCH COUT2 M4 GND_1P5 PGND PGND AMP_MCH COMP_1P5 VREF CZM1 RZM1 A1 CZM2 CPM1 RM1 RZM2 RM2 FBDDQ DDQ_REF 5VDUAL S0 VDDQ R16 M2 VTT VTT Regulation Control R17 R18 VTT AGND 5VDUAL COUT2 M3 R19 AGND AGND PGND Figure 2. Internal Block Diagram http://onsemi.com 3 FBVTT NCP5210 PIN DESCRIPTION Pin Symbol Description 1 COMP VDDQ error amplifier compensation node 2 FBDDQ DDQ regulator feedback pin for closed loop regulation 3 SS Soft−start pin of DDQ regulator connecting a capacitor 4 PGND Power ground 5 VTT 6 VDDQ VTT regulator output Power input for VTT linear regulator 7 AGND Analog ground connection and remote ground sense 8 FBVTT VTT regulator feedback pin for closed loop regulation 9 DDQ_REF 10 FB1P5 11 GND_1P5 12 BG_1P5 Gate driver output for V1P5 regulator low side N−Channel Power FET 13 TG_1P5 Gate driver output for V1P5 regulator high side N−Channel Power FET 14 BUF_Cut Active High control signal to activate S3 Sleep State 15 COMP_1P5 16 5VDUAL 17 BOOT 18 TG_DDQ Gate driver output for DDQ regulator high side N−Channel Power FET 19 BG_DDQ Gate driver output for DDQ regulator low side N−Channel Power FET 20 SW_DDQ DDQ regulator inductor driven node and current limit sense input 21 TH_PAD Copper pad on bottom of IC used for heatsinking. This pin should be connected to the ground plane under the IC. Reference voltage input of VTT regulator V1P5 Switching Regulator feedback pin for closed loop regulation Power ground for V1P5 regulator V1P5 error amplifier compensation node 5V Dual supply input, which is monitored by under−voltage lock out circuitry Gate driver input supply, which is monitored by under−voltage lock out circuitry, and a boost capacitor connection between SWDDQ and this pin MAXIMUM RATINGS Rating Symbol Value Unit 5VDUAL −0.3, 6.0 V Boot −0.3, 14 V Gate Drive (Pin 12, 13, 18, 19) to AGND (Pin 7) Vg −0.3 DC, −4.0 for 1.0 s; 14 V Input / Output Pins to AGND (Pin 7) Pin 1−6, 8−11, 14−16, 20 VIO −0.3, 6.0 V RJA 35(TBD) °C/W Operating Junction Temperature Range TJ 0 to + 150 °C Operating Ambient Temperature Range TA 0 to + 70 °C Storage Temperature Range Tstg − 55 to +150 °C Moisture Sensitivity Level MSL 2 Power Supply Voltage (Pin 16) to AGND (Pin 7) Boot (Pin 17) to AGND (Pin 7) Thermal Characteristics QFN−20 Plastic Package Thermal Resistance Junction to Air 1. This device series contains ESD protection and exceeds the following tests: Human Body Model (HBM) ≤ 2.0 kV per JEDEC standard: JESD22–A114. Machine Model (MM) ≤ 200 V per JEDEC standard: JESD22–A115. 2. Latch–up Current Maximum Rating: ≤ 150 mA per JEDEC standard: JESD78. http://onsemi.com 4 NCP5210 ELECTRICAL CHARACTERISTICS (5VDUAL = 5 V, BOOT = 12 V, 5VATX = 5 V, DDQ_REF = 2.5 V, TA = 0°C to 70°C, L = 1.7 H, COUT1 = 3770 F, COUT2 = 470 F, COUT3 = NA, CSS = 33 nF, RL1 = 200 k, R1 = 2.166 k, R2 = 2 k, RZ1 = 20 k, RZ2 = 8 , CP1 = 10 nF, CZ1 = 6.8 nF, CZ2 = 100 nF, RM1 = 2.166 k, RM2 = 2 k, RZM1 = 20 k, RZM2 = 8 , CPM1 = 10 nF, CZM1 = 6.8 nF, CZM2 = 100 nf for min/max values unless otherwise noted.) duplicate component values of MCH regulator from DDQ. Characteristic Test Conditions Symbol Min Typ Max Unit V5VDUAL 4.5 5.0 5.5 V VBOOT 8.0 12.0 13.2 V SUPPLY VOLTAGE 5VDUAL Operating Voltage BOOT Operating Voltage SUPPLY CURRENT S0 mode Supply Current from 5VDUAL BUF_Cut = LOW, BOOT = 12 V I5VDL_S0 10 mA S3 mode Supply Current from 5VDUAL BUF_Cut = HIGH I5VDL_S3 5.0 mA S5 mode Supply Current from 5VDUAL BUF_Cut = LOW, I5VDL_S5 1.0 mA S0 mode Supply Current from BOOT BUF_Cut = LOW, BOOT = 12 V, TGDDQ, BGDDQ , TG_1P5 and BG_1P5 Open IBOOT_S0 20 mA S3 mode Supply Current from BOOT BUF_Cut=HIGH, TGDDQ, BGDDQ, TG_1P5 and BG_1P5 Open IBOOT_S3 20 mA 5VDUAL UVLO Upper Threshold V5VDLUV+ 4.4 V 5VDUAL UVLO Hysteresis V5VDLhys UNDER−VOLTAGE−MONITOR 300 mV BOOT UVLO Upper Threshold VBOOTUV+ 10.2 V BOOT UVLO Hysteresis VBOOThys 1.0 V Tsd 150 °C Tsdhys 25 °C THERMAL SHUTDOWN Thermal Shutdown Thermal Shutdown Hysteresis DDQ SWITCHING REGULATOR FBDDQ Feedback Voltage, Control Loop in Regulation Feedback Input Current Ta = 25°C Ta = 0°C to 70°C VFBQ V(FBDDQ) = 1.3 V IDDQfb 1.188 1.176 1.200 1.212 1.224 V 1.0 A Oscillator Frequency in S0 Mode FDDQS0 225 250 275 KHz Oscillator Frequency in S3 Mode FDDQS3 450 500 550 KHz Current Limit Blanking Time in S0 Mode TDDQbk 400 nS Minimum Duty Cycle Dmin 0 % Maximum Duty Cycle Dmax Soft−Start Pin Current for DDQ V(SS) = 0.5 V 100 % Iss1 4.0 A GAINDDQ 70 dB DDQ ERROR AMPLIFIER DC Gain Gain−Bandwidth Product COMP PIN to GND = 220nF, 1 in Series GBWDDQ TBD MHz Slew Rate COMP PIN TO GND = 10 pF SRDDQ 8.0 V/uS IOUT= 0 to 2.0 A (sink current) IOUT= 0 to –2.0 A (source current) dVTTS0 VTT ACTIVE TERMINATION REGULATOR VTT tracking DDQ_REF/2 at S0 mode −30 30 mV VTT Source Current Limit ILIMVTsrc 2.4 A VTT Sink Current Limit ILIMVTsnk 2.4 A DDQ_REF Input Resistance DDQREF 50 k http://onsemi.com 5 NCP5210 ELECTRICAL CHARACTERISTICS (5VDUAL = 5 V, BOOT = 12 V, 5VATX = 5 V, DDQ_REF = 2.5 V, TA = 0°C to 70°C, L = 1.7 H, COUT1 = 3770 F, COUT2 = 470 F, COUT3 = NA, CSS = 33 nF, RL1 = 200 k, R1 = 2.166 k, R2 = 2 k, RZ1 = 20 k, RZ2 = 8 , CP1 = 10 nF, CZ1 = 6.8 nF, CZ2 = 100 nF, RM1 = 2.166 k, RM2 = 2 k, RZM1 = 20 k, RZM2 = 8 , CPM1 = 10 nF, CZM1 = 6.8 nF, CZM2 = 100 nf for min/max values unless otherwise noted.) duplicate component values of MCH regulator from DDQ. Characteristic Test Conditions Symbol Min Typ Max Unit BUF_Cut Input Logic HIGH Logic_H 2.0 BUF_Cut Input Logic LOW Logic_L 0.8 V Ilogic 1.0 A CONTROL SECTION BUF_Cut Input Current V GATE DRIVERS TGDDQ Gate Pull−HIGH Resistance VCC = 12 V, V(TGDDQ) = 11.9 V RH_TG 3.0 TGDDQ Gate Pull−LOW Resistance VCC = 12 V, V(TGDDQ) = 0.1 V RL_TG 2.5 BGDDQ Gate Pull−HIGH Resistance VCC = 12 V, V(BGDDQ) = 11.9 V RH_BG 3.0 BGDDQ Gate Pull−LOW Resistance VCC = 12 V, V(BGDDQ) = 0.1 V RL_BG 1.3 TG1P5 Gate Pull−HIGH Resistance VCC = 12 V, V(TG1P5) = 11.9 V RH_TPG 3.0 TG1P5 Gate Pull−LOW Resistance VCC = 12 V, V(TG1P5) = 0.1 V RL_TPG 2.5 BG1P5 Gate Pull−HIGH Resistance VCC = 12 V, V(BG1P5) = 11.9 V RH_BPG 3.0 BG1P5 Gate Pull−LOW Resistance VCC = 12 V, V(BG1P5) = 0.1 V RL_BPG 1.3 Ta = 0°C to 70°C VFB1P5 MCH SWITCHING REGULATOR VFB1P5 Feedback Voltage, Control Loop in Regulation Feedback Input Current 0.784 0.8 I1P5FB Oscillator Frequency F1P5 225 Minimum Duty Cycle Dmin_1P5 0 Maximum Duty Cycle Dmax_1P5 Soft−start Pin Current for V1P5 regulator ISS2 http://onsemi.com 6 250 0.816 V 1.0 A 275 KHz % 100 8.0 % A NCP5210 DETAILED OPERATION DESCRIPTIONS General The ACPI control logic is enabled by the assertion of _VREFGD. Once the ACPI control is activated, the power up sequence starts by waking up the 5VDUAL voltage monitor block. If the 5VDUAL supply is within the preset levels, the BOOT under voltage monitor block is then enabled. After the BOOT UVLO is asserted HIGH, the ACPI control triggers this device from S5 shutdown mode into S0 normal operating mode by activating the soft−start of DDQ switching regulator, providing BUF_CUT remaining LOW. Once the DDQ regulator is in regulation and the soft−start interval is completed, the _InRegDDQ signal is asserted HIGH to enable the VTT regulator as well as the V1P5 switching regulator. The NCP5210 3−In−1 PWM Dual Buck Linear DDR Power Controller contains two high efficiency PWM controllers and an integrated two−quadrant linear regulator. The VDDQ supply is produced by a PWM switching controller with two external NFETs. The VTT termination voltage is an integrated linear regulator with sourcing and sinking current capability which tracks at 1/2 VDDQ. The MCH core voltage is created by the secondary switching controller. The inclusion of soft−start, supply under−voltage monitors, short circuit protection and thermal shutdown, makes this device a total power solution for the MCH and DDR memory system. This device is packaged in a QFN−20. DDQ Switching Regulator ACPI Control Logic In S0 mode the DDQ regulator is a switching synchronous rectification buck controller driving two external power NFETs to supply up to 20 A. It employs voltage mode fixed frequency PWM control with external compensation switching at 250kHz ± 10%. As shown in Figure 2, the VDDQ output voltage is divided down and fed back to the inverting input of an internal amplifier through the FBDDQ pin to close the loop at VDDQ = VFBQ × (1 + R2/R1). This amplifier compares the feedback voltage with an internal reference voltage of 1.200 V to generate an error signal for the PWM comparator. This error signal is compared with a fixed frequency RAMP waveform derived from the internal oscillator to generate a pulse−width−modulated signal. The PWM signal drives the external NFETs via the TG_DDQ and BG_DDQ pins. External inductor L and capacitor COUT1 filter the output waveform. When the IC leaves the S5 state, the VDDQ output voltage ramps up at a soft−start rate controlled by the capacitor at the SS pin. When the regulation of VDDQ is detected in S0 mode, _INREGDDQ goes HIGH to notify the control block. In S3 standby mode, the switching frequency is doubled to reduce the conduction loss in the external NFETs. The ACPI control logic is powered by the 5VDUAL supply. It accepts external control at the BUF_CUT input, and internal supply voltage monitoring signals from two UVLOs to decode the operating mode in accordance with state transition diagram in Figure 3. These UVLOs monitor the external supplies, 5VDUAL and 12VATX, through 5VDUAL and BOOT pins respectively. Two control signals, _5VDUALGD and _BOOTGD, are asserted when the supply voltages are good. The device powers up initially in the S5 shutdown mode to minimize the power consumption. When all three supply voltages are good and BUF_CUT is LOW, the device enters the S0 normal operating mode. When BUF_CUT transitions from LOW to HIGH in S0 mode the device goes into the S3 sleep mode. In S3 mode the 12VATX supply collapses. On transition of BUF_CUT from HIGH to LOW, the device returns to S0 mode. The IC re−enters S5 mode if one of the supplies is removed during S0 mode. Transitions from S3 to S5 or vice versa are not allowed. A timing diagram is shown in Figure 3. Table 1 summarizes the operating states of all the regulators, as well as the conditions of output pins. S5 To S0 Mode Power Up Sequence An internal bandgap reference is generated whenever 5VDUAL exceeds 2.7 V. Once this bandgap reference is in regulation, an internal signal _VREFGD is asserted. Table 1. Mode, Operation and Output Pin Condition OPERATING CONDITIONS OUTPUT PIN CONDITIONS MODE DDQ VTT TGDDQ BGDDQ TP_1P5 BG_1P5 S0 Normal Normal Normal Normal Normal Normal S3 Standby H−Z Standby Standby Low Low S5 H−Z H−Z Low Low Low Low http://onsemi.com 7 NCP5210 at the half of DDQ_REF. This regulator is stable with any value of output capacitor greater than 470 F, and is insensitive to ESR ranging from 1−m to 400 m. For enhanced efficiency, an active synchronous switch is used to eliminate the conduction loss contributed by the forward voltage of a diode or Schottky diode rectifier. Adaptive non−overlap timing control of the complementary gate drive output signals is provided to reduce shoot−through current that degrades efficiency. Fault Protection of VTT Active Terminator To provide protection for the internal FETs, bi−directional current limit preset at 2.4 A magnitude is implemented. This current limit is also used as constant current source during VTT startup. Tolerance of VDDQ Both the tolerance of VFBQ and the ratio of the external resistor divider R2/R1 impact the precision of VDDQ. With the control loop in regulation, VDDQ = VFBQ × (1 + R2/R1). With a worst case (for all valid operating conditions) VFBQ tolerance of ±1.5%, a worst case range of ±2% for VDDQ will be assured if the ratio R2/R1 is specified as 0.9455 ±1%. MCH Switching Regulator The secondary switching regulator is identical to the DDQ regulator except the output is 10 A, no fault protection is implemented and the soft−start timing is twice as fast with respect to CSS. BOOT Pin Supply Voltage Fault Protection of VDDQ Regulator In typical application, a flying capacitor is connected between SWDDQ and BOOT pins. In S0 mode, 12VATX is tied to BOOT pin through a Schottky diode as well. A 13−V Zener clamp circuit must clamp this boot strapping voltage produced by the flying capacitor in S0 mode. In S3 mode the 12VATX is collapsed and the BOOT voltage is created by the Schottky diode between 5VDUAL and BOOT pins as well as the flying capacitor. In S0 mode, an internal voltage (VOCP) = 5VDUAL – 0.8 sets the current limit for the high−side switch. The voltage VOCP pin is compared to the voltage at SWDDQ pin when the high−side gate drive is turned on after a fixed period of blanking time to avoid false current limit triggering. When the voltage at SWDDQ is lower than VOCP, an over−current condition occurs and all regulators are latched off to protect against over−current. The IC can be powered up again if one of the supply voltages, 5VDUAL or 12VATX, is recycled. In S3 mode, this over−current protection feature is disabled. Thermal Consideration Assuming an ambient temperature of 50°C, the maximum allowed dissipated power of QFN−20 is 2.8 W, which is enough to handle the internal power dissipation in S0 mode. To take full advantage of the thermal capability of this package, the exposed pad underneath must be soldered directly onto a PCB metal substrate to allow good thermal contact. Feedback Compensation of VDDQ Regulator The compensation network is shown in Figure 2. VTT Active Terminator The VTT active terminator is a 2 quadrant linear regulator with two internal NFETs to provide current sink and source capability up to 2.0 A. It is activated only when the DDQ regulator is in regulation in S0 mode. It draws power from VDDQ with the internal gate drive power derived from 5VDUAL. While VTT output is connecting to the FBVTT pin directly, VTT voltage is designed to automatically track Thermal Shutdown When the junction temperature of the IC exceeds 150°C, the entire IC is shutdown. When the junction temperature drops below 115°C, the chip resumes normal operation. http://onsemi.com 8 NCP5210 5VSTBY or 5VDUAL 12 V 5V BUF_CUT Switching Frequency Doubles SS pin DDQ−S0 VTT MCH State 1 2 3 4 5 6 7 8 9 10 SO 11 12 13 S3 14 15 16 SO Figure 3. NCP5210 Power−up and Power−down 2. 5VSTBY or 5VSTB is the Ultimate Chip Enable. This supply has to be up first to ensure gates are in known state. 3. 12 V and 5 V supplies can ramp in either order. 4. DDQ will ramp with the tracking of SS pin, timing is 1.2 * CSS / 4 (sec). 5. DDQ SS is completed, then SS pin is released from DDQ. SS pin is shorted to ground. 5. MCH ramps with the tracking of SS pin ramp, timing is 1.2 * CSS / 8 (sec). VTT rises. 6. MCH SS is completed, then SS pin is released from MCH. SS pin is shorted to ground. S0 Mode. 7. S3 MODE − BUF_CUT = H 8. VTT and MCH will be turned off. 9. 12 V and 5 V ramps to 0 V. 10. Standard S3 State 11. 12 V and 5 V ramps back to regulation. 12. BUF_CUT goes LOW 13. 12 V UVLO = L and BUF_CUT = L. MCH ramps with SS pin, timing is 1.2 * CSS / 8 (sec). VTT rises. 14. S0 Mode 15. S5 Mode − BUF_CUT = L, and 12VUVLO = H or 5VUVLO = H 16. DDQ, VTT, and MCH Turned OFF 17. S5 Mode http://onsemi.com 9 17 S5 NCP5210 S5 BUF_CUT = 0 AND _BOOTGD = 1 AND BUF_CUT = 0 AND (_BOOTGD = 0) S0 BUF_CUT = 0 AND _BOOTGD = 1 AND BUF_CUT = 1 NOTE: All possible state transitions are shown. All unspecified inputs do not cause any state change. S3 Figure 4. Transitions State Diagram of NCP5210 http://onsemi.com 10 NCP5210 PACKAGE DIMENSIONS 20 PIN QFN, DUAL−SIDED, 6x5 mm MN SUFFIX CASE 505AB−01 ISSUE O A D NOTES: 1. DIMENSIONS AND TOLERANCING PER ASME Y14.5M, 1994. 2. DIMENSIONS IN MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINALS AND IS MEASURED BETWEEN 0.25 AND 0.30 MM FROM TERMINAL 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. B PIN 1 LOCATION E 2X 0.15 C DIM A A1 A2 A3 b D D2 E E2 e K L 2X 0.15 C 0.10 C A2 A 0.08 C A1 (A3) C SEATING PLANE D2 20 X L 20 X e 1 10 E2 K 20 11 20 X b 0.10 C A B 0.05 C NOTE 3 http://onsemi.com 11 MILLIMETERS MIN MAX 0.80 1.00 0.00 0.05 0.65 0.75 0.20 REF 0.23 0.28 6.00 BSC 3.98 4.28 5.00 BSC 2.98 3.28 0.50 BSC 0.20 −−− 0.50 0.60 NCP5210 ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. 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This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada Email: [email protected] N. American Technical Support: 800−282−9855 Toll Free USA/Canada ON Semiconductor Website: http://onsemi.com Order Literature: http://www.onsemi.com/litorder Japan: ON Semiconductor, Japan Customer Focus Center 2−9−1 Kamimeguro, Meguro−ku, Tokyo, Japan 153−0051 Phone: 81−3−5773−3850 http://onsemi.com 12 For additional information, please contact your local Sales Representative. NCP5210/D