ETC PI74ALVTC16646

PI74ALVTC16646
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2.5V 16-Bit Bus Transceiver and
Register with 3-State Outputs
Product Features
Product Description
• PI74ALVTC16646 is designed for low voltage operation,
VDD = 1.65V to 3.6V
• Supports Live Insertion
• 3.6V I/O Tolerant Inputs and Outputs
• Bus Hold
• High Drive, –32/64mA @ 3.3V
• Uses patented noise reduction circuitry
• Power-off high impedance inputs and outputs
• Industrial operation at –40°C to +85°C
• Packages available:
– 56-pin 240-mil wide plastic TSSOP (A56)
– 56-pin 173-mil wide plastic TVSOP (K56)
Pericom Semiconductor’s PI74ALVTC series of logic circuits are
produced using the Company’s advanced 0.35 micron CMOS
technology, achieving industry leading speed.
The PI74ALVTC16646 is a 16-bit bus transceiver and register
designed for 1.65V to 3.6V VCC operation. It can be used as two 8bit transceivers or one 16-bit transceiver. Data on the A or B bus is
clocked into the registers on the low-to-high transition of the
appropriate Clock (CLKAB or CLKBA) input. Four fundamental
bus-management functions can be performed.
Output Enable (OE) and Direction Control (DIR) inputs are provided
to control the transceiver functions. In the transceiver mode, data
present at the high-impedance port may be stored in either register
or in both. The Select Control (SAB and SBA) inputs can multiplex
stored and real-time (transparent mode) data. Circuitry used for
Select Control eliminates the typical decoding glitch that occurs in
a multiplexer during the transition between stored and real-time
data. DIR determines which bus receives data when OE is LOW. In
the isolation mode (OE HIGH), A data may be stored in one register
and/or B data may be stored in the other register.
Logic Block Diagrams
1OE 56
1
1DIR
1CLKBA
When an output function is disabled, the input function is still
enabled and may be used to store and transmit data. Only one of the
two buses, A or B, can be driven at a time.
55
1SBA 54
1CLKAB
2
1SAB
3
One of Eight Channels
To ensure the high-impedance state during power up or power
down, OE should be tied to VCC through a pullup resistor; the
minimum value of the resistor is determined by the current-sinking
capability of the driver.
1D
C1
1A1
5
52
Active bus-hold circuitry is provided to hold unused or floating
data inputs at a valid logic level.
1B1
1D
C1
The family offers both I/O Tolerant, which allows it to operate in
mixed 1.65/3.6V systems, and “Bus Hold,” which retains the data
input’s last state preventing “floating” inputs and eliminating the
need for pullup/down resistors.
TO SEVEN OTHER CHANNELS
2OE
29
2DIR
2CLKBA
28
30
2SBA
2CLKAB
2SAB
31
27
26
One of Eight Channels
1D
C1
2A115
42
1D
C1
2B1
TO SEVEN OTHER CHANNELS
1
PS8596
01/22/02
PI74ALVTC16646
2.5V 16-Bit Bus Transceiver and
Register with 3-State Outputs
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Product Pin Description
Pin Configuration
Pin Name
1DIR
56
55
54
1OE
1SAB
1
2
3
GND
4
53
GND
5
6
7
8
9
10
11
52
51
50
49
48
47
46
1B1
12 56-Pin 45
13 A, K 44
14
43
15
42
16
41
17
40
1B6
1CLKAB
1A1
1A2
VCC
1A3
1A4
1A5
GND
1A6
1A7
1A8
2A1
2A2
2A3
GND
2A4
18
19
39
38
2A5
20
21
22
23
24
25
26
27
28
37
36
35
34
33
32
2A6
VCC
2A7
2A8
GND
2SAB
2CLKAB
2DIR
31
30
29
1CLKBA
1SBA
D e s cription
xO E
O utput Enable Inputs (Active LO W)
xDIR
Direction Control
xCLK AB, xCLK BA Clock Pulse Inputs
1B2
VCC
1B3
1B4
1B5
GND
1B7
1B8
2B1
xSAB, xSBA
Select Control Inputs
xAx
Data Register A Inputs
Data Register B O utputs
xBx
Data Register B Inputs
Data Register A O utputs
GND
Ground
VCC
Power
2B2
2B3
GND
2B4
2B5
2B6
VCC
2B7
2B8
GND
2SBA
2CLKBA
2OE
Truth Table
Inputs
D ata I/O
xOE
xD IR
xCLKAB
xCLKBA
xSAB
xSBA
xAx
xBx
Store A, B Unspecified(1)
Store B, A Unspecified(1)
X
X
X
X
↑
X
X
↑
X
X
X
X
Input
Unspecified(1)
Unspecified(1)
Input
Isolation, Hold Storage
Store A and B Data
H
H
X
X
H or L
↑
H or L
↑
X
X
X
X
Input Disable
Input
Input Disable
Input
Real Time A Data to B Bus
Stored A Data to B Bus
L
L
H
H
X
H or L
X
X
L
H
X
X
Input
Input
O utput
O utput
Real Time B Data to A Bus
Stored B Data toA Bus
L
L
L
L
X
X
X
H or L
X
X
L
H
O utput
O utput
Input
Input
Function
Notes:
1. The data output functions may be enabled or disabled by various signals at the xOE or xDIR inputs. Data input
functions are always enabled, i.e., data at the bus pins will be stored on every LOW-to-HIGH transition on the clock inputs.
2. H = High Voltage Level
X = Don’t Care
L = Low Voltage Level
↑ = LOW-to-HIGH transition
2
PS8596
01/22/02
PI74ALVTC16646
2.5V 16-Bit Bus Transceiver and
Register with 3-State Outputs
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Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.)
Supply Voltage Range, VDD ........................................................ –0.5V to 4.6V
Input Voltage Range, VI ................................................................ –0.5V to 4.6V
Output Voltage Range, VO (3-Stated) .............................. –0.5V to 4.6V
Output Voltage Range, VO(1) (Active) .................. –0.5V to VDD +0.5V
DC Input Diode Current (IIK) VI < 0V ........................................ –50mA
DC Output Diode Current (IOK)
VO < 0V ................................................................................... –50mA
VO > VDD .................................................................................................... ±50mA
DC Output Source/Sink Current (IOH/IOL) ......................... –64/128mA
DC VDD or GND Current per Supply Pin (ICC or GND) ............ ±100mA
Storage Temperature Range, Tstg .................................. –65°C to150°C
Note:
Stresses greater than those listed under MAXIMUM
RATINGS may cause permanent damage to the device. This
is a stress rating only and functional operation of the device
at these or any other conditions above those indicated in the
operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for
extended periods may affect reliability.
Recommended Operating Conditions(2)
M in.
M ax.
O perating
1.65
3.6
Data Retention O nly
1.2
3.6
2.0
VDD
Supply voltage
VIH
High- level input voltage
VDD = 2.7V to 3.6V
VIL
Low- level input voltage
VDD = 2.7V to 3.6V
VI
Input voltage
VO
O utput voltage
O utput current in IOH/IOL
∆t/∆v
TA
0.8
–0.3
3.6
Active State
0
VDD
O ff State
0
3.6
VDD =
VDD =
VDD =
VDD =
3.0V to 3.6V
3.0V to 3.6V
2.3V to 2.7V
1.65V to 1.95V
Input transistion rise or fall rate(3)
O perating free- air temperature
Units
V
–32/64
±24
±18
±6
mA
0
10
ns/V
−40
85
C
Notes:
1. Absolute maximum of IO must be observed.
2. Unused control inputs must be held HIGH or LOW to prevent them from floating.
3 As measured between 0.8V and 2.0V, VDD = 3.0V.
3
PS8596
01/22/02
PI74ALVTC16646
2.5V 16-Bit Bus Transceiver and
Register with 3-State Outputs
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Electrical Characteristics over Recommended Operating Free-Air Temperature Range
(unless otherwise noted)
DC Characteristics (2.7V<VDD ≤ 3.6V)
Parame te r
VIK
VO H
Input Clamp Diode
HIGH Level Output Voltage
Conditions
VD D
IIK = −18mA
3.0
2.7 - 3.6
VD D – 0.2
IO H = −12mA
2.7
2.2
IO H = −18mA
M ax.
3.0
2.2
2.0
IO L = 100µA
2.7 - 3.6
0.2
IO L = 12mA
2.7
0.4
IO L = 18mA
IO L = 24mA
0.45
3.0
0.5
IO L = 64mA
0.75
II
Input Leakage Current
VI = VD D , or GND
3.6
±5.0
IO Z
3- State Output Leakage
VO = 3.6V
2.7
±10
IO F F
Power- OFF Leakage Current
VI or VO ≤ 3.6V
0
10
Bus Hold Current
A or B Outputs
VI = 0.8V
3.0
VI = 2.0V
VI = 0 to 3.6V
ID D
∆ID D
Quiescent Supply Current
Increase in ID D per input
V
0.4
IO L = 32mA
IH O LD
Units
2.4
IO H = −32mA
LOW Level Output Voltage
Typ.
–1.2
IO H = −100µA
IO H = −24mA
VO L
M in.
3.6
VI = VD D or GND
75
–75
µA
±500
50
VD D ≤ (VI,VO ) ≤ 3.6V
2.7 - 3.6
VIH = VD D –0.6V,
Other inputs at VD D or Gnd
±50
400
Notes:
1. All unused inputs must be held at VCC or GND to ensure proper device operation.
4
PS8596
01/22/02
PI74ALVTC16646
2.5V 16-Bit Bus Transceiver and
Register with 3-State Outputs
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Electrical Characteristics over Recommended Operating Free-Air Temperature Range
(unless otherwise noted; continued from previous page)
DC Characteristics (2.3V ≤VDD ≤ 2.7V)
De s cription
VIK
Parame te rs
Input Clamp Diode
Conditions
IIK = –18mA
HIGH Level Output Voltage
2.3 - 2.7
IOH = –12mA
2.3
IOH = –18mA
IOL = 100µA
VOL
LOW Level Output Voltage
M in.
Typ.
2.3
IOH = –100µA
VOH
VDD
M ax.
–1.2
VDD– 0.2
1.8
1.7
2.3 - 2.7
0.2
IOL = 12mA
IOL = 18mA
0.5
2.3
0.55
II
Input Leakage Current
VI = VDD or GND
2.7
±5.0
IOZ
3- State Output Leakage
VO = 3.6V
2.3
±10
IOFF
Power- OFF Leakage Current
VI or VO ≤ 3.6V
0
10
Bus Hold Current
A or B Outputs
VI = 0.7V
IDD
∆ΙDD
Quiescent Supply Current
Increase in IDD per input
V
0.4
IOL = 24mA
IHOLD(1)
Units
2.5
VI = 1.7V
90
–90
VI = VDD or GND
40
VDD ≤ (VI,VO) ≤ 3.6V
±40
VIH = VDD –0.6V,
Inputs at VDD or Gnd
2.3 - 2.7
µA
µA
400
Note:
1. Not Guaranteed
5
PS8596
01/22/02
PI74ALVTC16646
2.5V 16-Bit Bus Transceiver and
Register with 3-State Outputs
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Electrical Characteristics over Recommended Operating Free-Air Temperature Range
(unless otherwise noted; continued from previous page)
DC Characteristics (1.65V ≤ VDD ≤ 1.95V)
De s cription
Parame te rs
VIK
Input Clamp Diode
VOH
HIGH Level Output Voltage
VOL
LOW Level Output Voltage
Conditions
IIK = –18mA
VDD
M in.
Typ.
1.65
IOH = –100µA
1.65- 1.95
IOH = –6mA
M ax.
–1.2
VDD –0.2
V
1.4
IOL = 100µA
1.65
0.2
IOL = 6mA
0.3
II
Input Leakage Current
VI = VDD or GND
1.95
±5.0
IOZ
3- State Output Leakage
VO = 3.6V
1.65
±10
IOFF
Power- OFF Leakage Current
VI = VO ≤ 3.6V
0
10
Bus Hold Current
A or B Outputs
VI = 0.4
IHOLD(1)
IDD
∆ΙDD
Quiescent Supply Current
Increase in IDD per input
Units
1.65
VI = 1.3
VI = VDD or GND
50
µA
–50
20
VDD ≤ (VI,VO) ≤ 3.6V
VI = VDD –06V,
Other inputs at VDD or Gnd
1.65- 1.95
±20
400
Note:
1. Not Guaranteed
6
PS8596
01/22/02
PI74ALVTC16646
2.5V 16-Bit Bus Transceiver and
Register with 3-State Outputs
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Timing Requirements (Over recommended operating free-air temperature range,
unless otherwise noted, see Figures 1 thru 4)
VCC = 1.8V ±0.15V
M in.
fclock Clock Frequency
VCC = 2.5V ±0.2V
VCC = 3.3V ±0.3V
M in.
M in.
M ax.
M ax.
150
180
M ax.
180
tw Pulse duration,
CLKAB or
CLKBA high or low
2.0
1.5
1.5
tsu Setup time,
A before CLKAB↑, or
B before CLKBA↑
1.8
1.4
1.2
th Hold time,
A after CLKAB↑, or
B after CLKBA↑
1.0
0.7
0.5
Units
MHz
ns
Switching Characteristics (Over recommended operating free-air temperature range,
unless otherwise noted, see Figures 1 thru 4)
Parame te rs
From
(Input)
To
(Output)
fmax
tpd
ten
tdis
ten
tdis
A or B
CLK AB
or
CLK BA
SAB or
SBA
OE
DIR
B or A
A or B
VCC = 1.8V ±0.15V
M in.
VCC = 2.5V ±0.2V
M ax.
M in.
150
1.0
VCC = 3.3V ±0.3V
M ax.
M in.
5.0
180
1.0
4.0
180
1.0
3.4
1.1
5.5
1.0
4.5
1.0
3.3
1.3
6.0
1.1
5.3
1.0
3.8
1.2
5.8
1.0
5.0
1.0
4.0
1.3
6.1
1.0
4.7
1.2
5.0
MHz
1.0
5.2
4.7
1.0
4.0
1.7
6.4
4.4
1.0
4.2
7
Units
M ax.
ns
PS8596
01/22/02
PI74ALVTC16646
2.5V 16-Bit Bus Transceiver and
Register with 3-State Outputs
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Test Circuits and Switching Waveforms
Switch Position
Parameter Measurement Information (VDD = 1.65V - 3.6V)
3.3V/2.5V VDD
2 x VDD
R1
500Ω
From Output
Under Test
Te s t
S1
tPD
Open
tPLZ/tPZL
2 x VDD
tPHZ/tPZH
GND
Open
GND
RL
500Ω
50pF
CL
Pulse Width
(See Note A)
VDD
Low-High-Low
Pulse
VDD/2
0V
tW
1.8V VDD
2 x VDD
VDD
High-Low-High
Pulse
R1
1kΩ
From Output
Under Test
VDD/2
0V
Open
30pF
CL
RL
1kΩ
GND
Propagation Delay
(See Note A)
VDD
VDD/2
0V
Input
tPLH
Setup, Hold, and Release Timing
Data
Input
tSU
Timing
Input
tH
tPHL
VDD
VDD/2
VOL
Output
tPHL
VDD
VDD/2
0V
tPLH
VDD
VDD/2
0V
Opposite Phase
Input Transition
VDD
VDD/2
0V
Enable Disable Timing
Notes:
A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions
such that the output is LOW except when disabled by
the output control.
Waveform 2 is for an output with internal conditions
such that the output is HIGH except when disabled by
the output control.
C. All input pulses are supplied by generators having the
following characteristics: PRR ≤ 10 MHz, ZO = 50Ω,
tr ≤ 2ns, tf ≤ 2ns, measured from 10% to 90%, unless
otherwise specified.
D. The outputs are measured one at a time with one
transition per measurement.
VDD
Output
Control
(Active LOW)
VDD/2
0V
tPLZ
tPZL
VDD
Output
Waveform 1
S1 at 2xVDD
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
VDD
VDD/2
+0.15V
tPZH
VOL
tPHZ
-0.15V
VOH
VDD/2
0V
Pericom Semiconductor Corporation
2380 Bering Drive • San Jose, CA 95131 • 1-800-435-2336 • Fax (408) 435-1100 • http://www.pericom.com
8
PS8596
01/22/02
PI74ALVTC16646
2.5V 16-Bit Bus Transceiver and
Register with 3-State Outputs
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Packaging Mechanical: 56-pin TSSOP (A)
56
.236
.244
1
.547
.555
6.0
6.2
13.9
14.1
1.20
SEATING PLANE
.047
Max.
.004 0.09
.008 0.20
.0197
BSC
0.50
.007
.011
0.17
0.27
X.XX DENOTES DIMENSIONS
X.XX IN MILLIMETERS
0.45 .018
0.75 .030
.002
.006
0.05
0.15
.319 BSC
8.1
Packaging Mechanical: 56-pin TVSOP (K)
56
.169
.177
4.30
4.50
1
.441
.449
0.45 .018
0.75 .030
.031
.041
0.80
1.05
11.20
11.40
0.09
0.20
.0035
.008
.252
BSC
6.4
SEATING
PLANE
.016
BSC
0.40
X.XX
X.XX
.002
.006
0.05
0.15
.005
.009
0.13
0.23
.047
1.20
Max.
DENOTES DIMENSIONS
IN MILLIMETERS
Orde ring Information
Package - Pins
PI74ALVTC16646A
TSSOP - 56
PI74ALVTC16646K
TVSOP - 56
Pericom Semiconductor Corporation
2380 Bering Drive • San Jose, CA 95131 • 1-800-435-2336 • Fax (408) 435-1100 • http://www.pericom.com
9
PS8596
01/22/02