ETC PI74ALVTC16501

PI74ALVTC16501
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2.5V 18-Bit Universal Bus Transceiver
With 3-State Outputs
Product Features
Product Description
• PI74ALVTC16501 is designed for low voltage operation,
VDD = 1.65V to 3.6V
• Supports Live Insertion
• 3.6V I/O Tolerant Inputs and Outputs
• Bus Hold
• High Drive, –32/64mA @ 3.3V
• Uses patented noise reduction circuitry
• Power-off high impedance inputs and outputs
• Industrial operation at –40°C to +85°C
• Packages available:
– 56-pin 240-mil wide plastic TSSOP (A)
– 56-pin 173-mil wide plastic TVSOP (K)
Pericom Semiconductor’s PI74ALVTC series of logic
circuits are produced using the Company’s advanced
0.35 micron CMOS technology, achieving industry
leading speed.
The 18-bit PI74ALVTC16501 univeral bus transceiver
is designed for 1.65V to 3.6V VDD operation.
Data flow in each direction is controlled by Output
Enable (OEAB and OEBA), Latch Enable (LEAB and
LEBA), and CLOCK (CLKAB and CLKBA) inputs. For
A-to-B data flow, the device operates in the transparent
mode when LEAB is HIGH. When LEAB is LOW, the
A data is latched if CLKAB is held at a high or low logic
level. If LEAB is LOW, the A-bus data is stored in the
latch/flip-flop on the low-to-high transition of CLKAB.
When OEAB is HIGH, the outputs are active. When
OEAB is LOW, the outputs are in the high-impedance
state.
Data flow for B to A is similar to that of A to B but uses
OEBA, LEBA, and CLKBA. The Output Enables are
complementary (OEAB is active HIGH and OEBA is
active LOW)
To ensure the high-impedance state during power up
or power down, OEBA should be tied to VDD through
a pull-up resistor and OEAB should be tied to GND
through a pulldown resistor; the minimum value of the
resistor is determined by the current-sinking capability
of the driver.
Logic Block Diagram
1
PS8594
01/22/02
PI74ALVTC16501
2.5V 18-Bit Universal Bus Transceiver
with 3-State Outputs
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Product Pin Description
Pin Name
OE
LE
CLK
Ax
Bx
GND
VDD
Truth Table(1)†
Description
Output Enable Input (Active HIGH)
Latch Enable (Active HIGH)
Clock Input (Active HIGH)
Data I/O
Data I/O
Ground
Power
Inputs
Product Pin Configuration
OEAB
LEAB
1
2
56
55
GND
CLKAB
A1
GND
A2
3
4
5
54
53
52
B1
GND
B2
A3
6
7
8
51
50
49
B3
VDD
B4
A5
A6
9
10
48
47
B5
B6
GND
A7
A8
11
12
13
46
56-Pin
A, K 45
44
A9
A10
A11
14
15
16
43
42
41
B9
B10
B11
A12
GND
17
18
40
39
B12
GND
A13
A14
A15
19
20
21
38
37
36
B13
B14
B15
VDD
A16
A17
22
23
24
35
34
33
VDD
B16
B17
GND
A18
25
26
32
31
GND
B18
OEBA
LEBA
27
28
30
29
CLKBA
GND
VDD
A4
Output B
OEAB
LEAB
CLKAB
A
L
X
X
X
Z
H
H
X
L
L
H
H
X
H
H
H
L
­
L
L
H
L
­
H
H
H
L
H
X
B0‡
H
L
L
X
B0§
Notes:
1. H = High Signal Level
L = Low Signal Level
Z = High Impedance
↑ = LOW-to-HIGH Transition
† A-to-B data flow is shown: B-to-A flow is similar but
uses OEBA, LEBA, CLKBA.
‡ Output level before the indicated steady-state input
conditions were established, provided that CLKAB is
HIGH before LEAB goes LOW.
§ Output level before the indicated steady-state input
conditions were established.
GND
B7
B8
2
PS8594
01/22/02
PI74ALVTC16501
2.5V 18-Bit Universal Bus Transceiver
with 3-State Outputs
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Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.)
Supply Voltage Range, VDD ........................................................ –0.5V to 4.6V
Input Voltage Range, VI ................................................................. -0.5V to 4.6V
Output Voltage Range, VO (3-Stated) ............................... -0.5V to 4.6V
Output Voltage Range, VO(1) (Active) .................. –0.5V to VDD +0.5V
DC Input Diode Current (IIK) VI < 0V ......................................... -50mA
DC Output Diode Current (IOK)
VO < 0V .................................................................................... -50mA
VO > VDD .................................................................................................... ±50mA
DC Output Source/Sink Current (IOH/IOL) .......................... -64/128mA
DC VDD or GND Current per Supply Pin (ICC or GND) ............ ±100mA
Storage Temperature Range, Tstg .................................. –65°C to150°C
Note:
Stresses greater than those listed under MAXIMUM
RATINGS may cause permanent damage to the device. This
is a stress rating only and functional operation of the device
at these or any other conditions above those indicated in the
operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for
extended periods may affect reliability.
Recommended Operating Conditions(2)
M in.
M ax.
O perating
1.65
3.6
Data Retention O nly
1.2
3.6
2.0
VDD
Supply voltage
VIH
High- level input voltage
VDD = 2.7V to 3.6V
VIL
Low- level input voltage
VDD = 2.7V to 3.6V
VI
Input voltage
VO
O utput voltage
O utput current in IOH/IOL
∆t/∆v
TA
0.8
–0.3
3.6
Active State
0
VDD
O ff State
0
3.6
VDD =
VDD =
VDD =
VDD =
O perating free- air temperature
V
–32/64
±24
±18
±6
mA
0
10
ns/V
−40
85
C
3.0V to 3.6V
3.0V to 3.6V
2.3V to 2.7V
1.65V to 1.95V
Input transistion rise or fall rate(3)
Units
Notes:
1. Absolute maximum of IO must be observed.
2. Unused control inputs must be held HIGH or LOW to prevent them from floating.
3 As measured between 0.8V and 2.0V, VDD = 3.0V.
3
PS8594
01/22/02
PI74ALVTC16501
2.5V 18-Bit Universal Bus Transceiver
with 3-State Outputs
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Electrical Characteristics over Recommended Operating Free-Air Temperature Range
(unless otherwise noted)
DC Characteristics (2.7V<VDD ≤ 3.6V)
Parame te r
VIK
VO H
Input Clamp Diode
HIGH Level Output Voltage
Conditions
VD D
IIK = −18mA
3.0
2.7 - 3.6
VD D – 0.2
IO H = −12mA
2.7
2.2
IO H = −18mA
M ax.
3.0
2.2
2.0
IO L = 100µA
2.7 - 3.6
0.2
IO L = 12mA
2.7
0.4
IO L = 18mA
IO L = 24mA
0.45
3.0
0.5
IO L = 64mA
0.75
II
Input Leakage Current
VI = VD D , or GND
3.6
±5.0
IO Z
3- State Output Leakage
VO = 3.6V
2.7
±10
IO F F
Power- OFF Leakage Current
VI or VO ≤ 3.6V
0
10
Bus Hold Current
A or B Outputs
VI = 0.8V
3.0
VI = 2.0V
VI = 0 to 3.6V
ID D
∆ID D
Quiescent Supply Current
Increase in ID D per input
V
0.4
IO L = 32mA
IH O LD
Units
2.4
IO H = −32mA
LOW Level Output Voltage
Typ.
–1.2
IO H = −100µA
IO H = −24mA
VO L
M in.
3.6
VI = VD D or GND
75
–75
µA
±500
50
VD D ≤ (VI,VO ) ≤ 3.6V
VIH = VD D –0.6V,
Other inputs at VD D or Gnd
4
2.7 - 3.6
±50
400
PS8594
01/22/02
PI74ALVTC16501
2.5V 18-Bit Universal Bus Transceiver
with 3-State Outputs
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Electrical Characteristics over Recommended Operating Free-Air Temperature Range (unless otherwise noted)
(continued from previous page)
DC Characteristics (2.3V ≤VDD ≤ 2.7V)
De s cription
VIK
Parame te rs
Input Clamp Diode
Conditions
IIK = –18mA
HIGH Level Output Voltage
2.3 - 2.7
IOH = –12mA
2.3
IOH = –18mA
IOL = 100µA
VOL
LOW Level Output Voltage
M in.
Typ.
2.3
IOH = –100µA
VOH
VDD
M ax.
–1.2
VDD– 0.2
1.8
1.7
2.3 - 2.7
0.2
IOL = 12mA
IOL = 18mA
2.3
0.5
0.55
II
Input Leakage Current
VI = VDD or GND
2.7
±5.0
IOZ
3- State Output Leakage
VO = 3.6V
2.3
±10
IOFF
Power- OFF Leakage Current
VI or VO ≤ 3.6V
0
10
Bus Hold Current
A or B Outputs
VI = 0.7V
IDD
∆ΙDD
Quiescent Supply Current
Increase in IDD per input
V
0.4
IOL = 24mA
IHOLD(1)
Units
2.5
VI = 1.7V
90
–90
VI = VDD or GND
40
VDD ≤ (VI,VO) ≤ 3.6V
±40
VIH = VDD –0.6V,
Inputs at VDD or Gnd
2.3 - 2.7
µA
µA
400
Note:
1. Not Guaranteed
5
PS8594
01/22/02
PI74ALVTC16501
2.5V 18-Bit Universal Bus Transceiver
with 3-State Outputs
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Electrical Characteristics over Recommended Operating Free-Air Temperature Range (unless otherwise noted)
(continued from previous page)
DC Characteristics (1.65V ≤ VDD ≤ 1.95V)
De s cription
Parame te rs
VIK
Input Clamp Diode
VOH
HIGH Level Output Voltage
VOL
LOW Level Output Voltage
Conditions
IIK = –18mA
VDD
M in.
Typ.
1.65
IOH = –100µA
1.65- 1.95
IOH = –6mA
M ax.
–1.2
VDD –0.2
V
1.4
IOL = 100µA
0.2
1.65
IOL = 6mA
0.3
II
Input Leakage Current
VI = VDD or GND
1.95
±5.0
IOZ
3- State Output Leakage
VO = 3.6V
1.65
±10
IOFF
Power- OFF Leakage Current
VI = VO ≤ 3.6V
0
10
Bus Hold Current
A or B Outputs
VI = 0.4
IHOLD(1)
IDD
∆ΙDD
Quiescent Supply Current
Increase in IDD per input
Units
1.65
VI = 1.3
VI = VDD or GND
50
µA
–50
20
VDD ≤ (VI,VO) ≤ 3.6V
VI = VDD –06V,
Other inputs at VDD or Gnd
1.65- 1.95
±20
400
Note:
1. Not Guaranteed
6
PS8594
01/22/02
PI74ALVTC16501
2.5V 18-Bit Universal Bus Transceiver
with 3-State Outputs
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Timing Requirements over recommended operating free-air temperature range
(unless otherwise noted, see Figures 1 thru 4)
VDD = 1.8V
±0.15V
M in.
M ax.
fclock Clock Frequency
tw Pulse duration
VDD = 2.5V
±0.2V
VDD = 3.3V
±0.3V
M in
M in. M ax.
M ax.
150
LE High
1.5
1.5
3.5
3.0
2.0
2.5
2.0
2.0
CLK High
1.2
1.0
1.0
1.5
1.0
1.0
1.0
1.0
1.0
1.0
1.5
1.5
1.5
Data before CLK↑
Data after LE ↓
180
2.0
Data before CLK↑
1.5
180
CLK High
or Low
Units
MHz
ns
Switching Characteristics over recommended operating free-air temperature range
(unless otherwise noted, see Figures 1 thru 4)
Parame te rs
From
(Input)
To
(Output)
M in.
VDD = 2.5V
±0.2V
M ax.
M in.
150
fmax
A or B
tpd
VDD = 1.8V
±0.15V
LE
CLK
B or A
A or B
M ax.
180
VDD = 3.3V
±0.3V
M in.
M ax.
180
MHz
1.1
4.5
1.0
3.4
1.0
3.0
2.1
5.0
2.0
4.0
1.5
3.4
1.3
5.0
1.0
4.5
1.0
3.2
ten
OEAB
B
1.2
4.5
1.0
4.0
1.0
3.1
tdis
OEAB
B
1.7
5.5
1.5
4.2
2.0
3.5
ten
OEBA
A
1.7
5.0
1.5
4.5
1.0
3.1
tdis
OEBA
A
1.7
5.5
1.5
4.2
2.0
4.0
7
Units
ns
PS8594
01/22/02
PI74ALVTC16501
2.5V 18-Bit Universal Bus Transceiver
with 3-State Outputs
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Test Circuits and Switching Waveforms
Switch Position
Parameter Measurement Information (VDD = 1.65V - 3.6V)
3.3V/2.5V VDD
2 x VDD
R1
500Ω
From Output
Under Test
Open
S1
tPD
Open
tPLZ/tPZL
2 x VDD
tPHZ/tPZH
GND
GND
RL
500Ω
50pF
CL
Te s t
Pulse Width
(See Note A)
VDD
Low-High-Low
Pulse
VDD/2
0V
tW
1.8V VDD
VDD
2 x VDD
High-Low-High
Pulse
R1
1kΩ
From Output
Under Test
VDD/2
0V
Open
30pF
CL
RL
1kΩ
GND
Propagation Delay
(See Note A)
VDD
VDD/2
0V
Input
tPLH
Setup, Hold, and Release Timing
Data
Input
tSU
Timing
Input
tH
tPHL
VDD
VDD/2
VOL
Output
VDD
VDD/2
0V
tPHL
tPLH
VDD
VDD/2
0V
Opposite Phase
Input Transition
VDD
VDD/2
0V
Enable Disable Timing
VDD
Notes:
A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that
the output is LOW except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that
the output is HIGH except when disabled by the output control.
C. All input pulses are supplied by generators having the following
characteristics: PRR ≤ 10 MHz, ZO = 50Ω,
tr ≤ 2ns, tf ≤ 2ns, measured from 10% to 90%, unless
otherwise specified.
D. The outputs are measured one at a time with one transition per
measurement.
Output
Control
(Active LOW)
VDD/2
tPLZ
tPZL
VDD
Output
Waveform 1
S1 at 2xVDD
(see Note B)
Output
Waveform 2
S1 at GND
VDD
VDD/2
+0.15V
tPZH
VOL
tPHZ
–0.15V
VOH
VDD/2
0V
(see Note B)
8
0V
PS8594
01/22/02
PI74ALVTC16501
2.5V 18-Bit Universal Bus Transceiver
with 3-State Outputs
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Packaging Mechanical: 56-pin TSSOP (A)
56
.236
.244
1
.547
.555
6.0
6.2
13.9
14.1
1.20
SEATING PLANE
.047
Max.
.004 0.09
.008 0.20
.0197
BSC
0.50
.007
.011
0.17
0.27
X.XX DENOTES DIMENSIONS
X.XX IN MILLIMETERS
0.45 .018
0.75 .030
.002
.006
0.05
0.15
.319 BSC
8.1
Packaging Mechanical: 56-pin TVSOP (K)
56
.169
.177
4.30
4.50
1
.441
.449
0.45 .018
0.75 .030
.031
.041
0.80
1.05
11.20
11.40
0.09
0.20
.0035
.008
.252
BSC
6.4
SEATING
PLANE
.016
BSC
0.40
X.XX
X.XX
.002
.006
0.05
0.15
.005
.009
0.13
0.23
.047
1.20
Max.
DENOTES DIMENSIONS
IN MILLIMETERS
Orde ring Information
Package - Pins
PI74ALVTC16501A
TSSOP - 56
PI74ALVTC16501K
TVSOP - 56
Pericom Semiconductor Corporation
2380 Bering Drive • San Jose, CA 95131 • 1-800-435-2336 • Fax (408) 435-1100 • http://www.pericom.com
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PS8594
01/22/02