TPS5300 IMVP MOBILE POWER SUPPLY CONTROLLER SLVS334 – DECEMBER 2000 Single-Chip Speed Step Solution Hysteretic Controller Provides Fast DRV_CLK VSENSE_CLK DT_SET ANAGND VSENSE_CORE SLOWST VREFB VHYST OCP DROOP IOUT PSM/LATCH IS– IS+ VGATE DRVGND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 DRV_IO VSENSE_IO VBIAS ENABLE_EXT RAMP VID0 VID1 VID2 VID3 VID4 VR_ON BOOT TG PH VCC BG description The TPS5300 is a hysteretic synchronous-buck controller, with two on-chip linear regulator controllers, incorporating speed-step output voltage positioning technology. The TPS5300 provides a precise, programmable supply voltage to a mobile processor. A ripple regulator provides the core voltage, while two linear regulator drivers regulate external NPN power transistors for the I/O and CLK voltages. A 5-bit voltage identification (VID) DAC allows programming for the ripple regulator voltage to values between 0.925 V to 1.275 V in 25 mV steps and 1.30 V to 2 V in 50 mV. The fast transient response time and active voltage DROOP positioning reduce the number of output capacitors required to keep the output voltage within tight dynamic voltage regulation limits. The power saving mode (PSM) allows the user to select a single operating ramp or allows the controller to automatically switch to lower frequencies at low loads. The high-gain current sense differential amplifier allows the use of small-value sense resistors that minimize conduction losses. The TPS5300 includes high-side and low-side gate drivers rated at 2 A typical, that enable efficient operation at higher frequencies and drive larger or multiple power MOSFETs. An adaptive dead-time circuit minimizes dead-time losses while preventing cross-conduction of high-side and low-side switches. All three outputs power up together as they track the same user programmable slowstart voltage. The enable external (ENABLE_EXT) terminal allows the TPS5300 to activate external switching controllers for additional system power requirements. The TPS5300 features undervoltage lockout, overvoltage, undervoltage, and user-programmable overcurrent protection, and is packaged in a small 32-pin TSSOP PowerPAD package. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PowerPAD is a trademark of Texas Instruments. Copyright 2000, Texas Instruments Incorporated PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 PRODUCT PREVIEW Transient Response Time and Reduced Output Capacitance Two Linear Regulator Controllers Regulating Clock and I/O Voltages Internal 2-A (Typ) Gate Drivers With Bootstrap Diode Which Increase Efficiency 5-Bit Dynamic VID Active Droop Compensation Enables Tight Dynamic Regulation for Reduced Output Capacitance Power Saving Mode (PSM) Promotes Long Battery Life High Bandwidth Current Sense Amplifier Adaptive Dead-Time Control Circuit Prevents Cross Conduction OVP, OCP, UVLO, UVP, and Thermal System Protection VGATE Terminal Provides Power-Good Signal for All Three Outputs Enable External Terminal (ENABLE_EXT) 32-Pin TSSOP PowerPAD Enhances Thermal Performance 1% Reference Voltage Accuracy DAP PACKAGE (TOP VIEW) TPS5300 IMVP MOBILE POWER SUPPLY CONTROLLER SLVS334 – DECEMBER 2000 1 2 32 31 29 15 Vref CLK Shutdown VSS Q S ShutdownB Q R Clock and IO Regulator Drivers Latch disabled DROOP IS– IS+ VBIAS 30 BIAS Vref VSS and DAC 17 BOOT TG PH BG 16 DRVGND Hyst. Set DT_SET VREFB 8 POST OFFICE BOX 655303 6 5 SLOWST 7 VSENSE_CORE 23 • DALLAS, TEXAS 75265 Power Save Mode Control 12 4 28 RAMP Vref 24 21 PSM/LATCH 25 18 VCC (+5 V)1 VSS is dominant if VSS < Vref _ VCC Bandgap UVP is Enabled When VSS > Vref CLK, and Vsense Core or Vsense IO or Vsense CLK < 0.75 of their Vref 19 + 26 3 2 14 20 Core Voltage Regulator Controller 27 UVP VHYST PRODUCT PREVIEW Shutdown VID4 13 x 25 VR_ON VCC Vref IO VID3 22 OCP_OVP Enables Device When OCP_OVP OCP Core > 200 mV or Vsense Core or Vsense IO or Vsense CLK > 1.15 of their Vref PWRGD is LOW if PWRGD Vsense Core or Vsense IO or Vsense CLK > 0.93 of their Vref Vss is dominant if Vss < Vref IO VID2 10 UVLO Enables IC When VR_ON > 2.5 V and VBIAS > 4.46 V UVLO VSS VID1 11 9 Protection Circuitry VSS is dominant if VSS < Vref CLK VID0 IOUT OCP VGATE ENABLE_EXT VSENSE_IO DRV_IO DRV_CLK VSENSE_CLK functional schematic ANAGND TPS5300 IMVP MOBILE POWER SUPPLY CONTROLLER SLVS334 – DECEMBER 2000 Terminal Functions TERMINAL NO. I/O DESCRIPTION ANAGND 4 Analog ground BG 17 O Bottom gate drive. BG is an output drive to the low-side synchronous rectifier FET. BOOT 21 I Bootstrap. Connect a 1-µF low ESR ceramic capacitor to PH to generate a floating drive for the high-side FET driver. DROOP 10 I DRV_CLK 1 O Active voltage droop position voltage. DROOP is a voltage input used to set the amount of output-voltage, set-point droop as a function of load current. The amount of droop compensation is set with a resistor divider between IOUT and ANAGND. A voltage divider from VO to VSENSE_CORE sets the no load offset. CLK voltage regulator. DRV_CLK drives an external NPN bipolar power transistor for regulating CLK voltage to VREF_CLK. DRVGND 16 DRV_IO 32 O Drives an external NPN bipolar power transistor for regulating IO voltage to VREF_IO. DT_SET 3 I DT_SET sets the transition time for speed step output voltage positioning. Attach a capacitor from DT_SET to ground to program time. ENABLE_EXT 29 O Open drain output. ENABLE_EXT enables external converters when the internal enable signal is high (good), and disables when there is a fault with any regulator (OVP, UVP, OCPrr), VR_ON UVLO is low, or the VBIAS UVLO is low. Can be connected to the enable terminal of an external linear regulator or switching controller. A pullup resistor is required to set the desired voltage rail. IS– 13 I Current sense negative Kelvin connection. Connect to the node between the current sense resistor and the output capacitors. Keep the PCB trace short and route trace next to the IS+ trace to help reduce loop inductance noise pickup and cancel common mode noise through mutual coupling. IS+ 14 I Current sense positive Kelvin connection. Connect to the node between the output inductor and the current sense resistor. Keep the PCB trace short and route trace next to the IS-trace to help reduce loop inductance noise and cancel common mode noise through mutual coupling. IOUT 11 O Current sense differential amplifier output. The voltage on IOUT equals 25 x (VI(+) – VI(–)) = 25 x (R(sense) x IL). OCP 9 I Over current protection. Current limit trip point is set with a resistor divider between IOUT and ANAGND. The typical OCP trip point should be set at 1.30 × I(max). The OCP voltage also sets the PSM automatic trip points. PH 19 I/O Phase voltage node. PH is used for bootstrap low reference. PH connects to the junction of the high-side and low-side FET’s. PSM/LATCH 12 I PSM. Power saving mode boosts efficiency at low load current by automatically decreasing the switching frequency toward the natural converter operating frequency. A logic low (<1.8) disables PSM, maintaining the higher switching frequency range set by CT. RAMP 28 I Sets a ramp on the feedback signal to increase the switching frequency. Add a resistor from PH to RAMP and connect RAMP to VSENSE_CORE for a dc-coupled ramp. Add a capacitor from RAMP to VSENSE_CORE to set an ac-coupled ramp. SLOWST 6 I Slow start (soft start). A capacitor from SLOWST to GND sets the slowstart time for the ripple regulator and the two linear regulators. The three converters will ramp up together while tracking the output voltage. A current equal to IVrefb/5 charges the capacitor. TG 20 O Top gate drive. TG is an output drive to the high-side power switching FET’s. It is also used in the anticross-conduction circuit to eliminate shoot-through current. VBIAS 30 I Analog VBIAS. It is recommended that at least a 1-µF capacitor be connected to ANAGND. Supply from VCB through RC filter VCC 18 VGATE 15 Drive ground. Ground for FET drivers. Connect to FET PWRGND PRODUCT PREVIEW NAME LATCH. Allows disabling fault latch. Recommend enabling fault latch protection Supply voltage. VCC is the supply voltage for the FET drivers. Add an external resistor/capacitor filter from VCC to VBIAS. It is recommended that a 1-µF capacitor be connected to the DRVGND terminal. O Logical and output of the combined core, IO, and CLK powergoods. VGATE outputs a logic high when all (core, IO, CLK) output voltages are within 7% of the reference voltage. An open drain output allows setting to desired voltage level through a pullup resistor. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 TPS5300 IMVP MOBILE POWER SUPPLY CONTROLLER SLVS334 – DECEMBER 2000 Terminal Functions (Continued) TERMINAL PRODUCT PREVIEW NAME NO. I/O DESCRIPTION Ripple regulator hysteresis set terminal. The hysteresis is set with a resistor divider from VREFB to GRD. The hysteresis voltage window will be ± the voltage between VREFBand VHYST. VHYST 8 I VID0 27 I VID1 26 I VID2 25 I VID3 24 I VID4 23 I VREFB 7 O Buffered ripple regulator reference voltage from VID network VR_ON 22 I Enables the drive signals to the MOSFET drivers. It is recommended that an external pullup resistor be connected to 5 V. VSENSE_CLK 2 I CLK feedback voltage sense. Connect to CLK linear regulator output voltage to regulate VSENSE_CORE 5 I Feedback voltage sense input for the core. Connect to ripple regulator output voltage to sense and regulate output voltage. It is recommended that an RC low-pass filter be connected at this pin to filter high frequency noise. VSENSE_IO 31 I I/O feedback voltage sense. Connect to I/O linear regulator output voltage to regulate Voltage identification inputs 0, 1, 2, 3, and 4. These terminals are digital inputs that set the output voltage of the converter. The code pattern attern for setting the out output ut voltage is located in the terminal functions table. These terminals are internally pulled up to VBIAS. absolute maximum ratings over operating free-air temperature (unless otherwise noted)† Supply voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Input voltage, VI: VBIAS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V VR_ON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 V VID0, VID1, VID2, VID3, VID4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 V PSM/LATCH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 V IS–, IS+ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 V RAMP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 V VSENSE_CORE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 V VSENSE_IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 V VSENSE_CLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 V All other input terminals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V BOOT to DRVGND voltage (high-side driver on) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 V BOOT to PH voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V BOOT to TG voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V PH to DRVGND voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –1 V to 35 V ANAGND to DRVGND voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±1 V Output voltage, VO: VGATE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 V ENABLE_EXT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 V Continuous power dissipation, PD: Without PowerPad soldered, TA = 25°C, TJ = 125°C . . . . . . . . . . . 1.2 W With PowerPad soldered, TC = 25°C, TJ = 125°C . . . . . . . . . . . . . 6.25 W Operating junction temperature, TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 125°C Storage temperature, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C Lead temperature, T(lead) (soldering, 10 seconds) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TPS5300 IMVP MOBILE POWER SUPPLY CONTROLLER SLVS334 – DECEMBER 2000 dc and ac recommended operating conditions, 0 < TJ < 125°C (unless otherwise noted) Supply voltage, Vbatt Linear regulator supply voltage, VI(IO+CLK) Supply voltage range, VCC, VBIAS MIN NOM MAX 3 12.5 28 UNIT V 3 3.3 6 V 4.5 5 6 V electrical characteristics over recommended operating free-air temperature range, 0 < TJ < 125°C, VIN = 4.3 V – 28 V (unless otherwise noted) PARAMETER TEST CONDITIONS MIN Current source pullup to VCC 2.25 TYP MAX UNIT Reference/Voltage Identification VIH(VID) High-level input voltage, D0–D4 VIL(VID) Low-level input voltage, D0–D4 V 1 V V(CUM_ACCRR) Initial accuracy ripple regula regulator 0.925 V ≤ Vref(core) ≤ 2 V, Hysteresis window = 30 mV –1.5% 1.5% 0.925 V ≤ Vref(core) ≤ 2 V, TJ = 25°C (see Note 2) Hysteresis window = 30 mV –1% 1% PRODUCT PREVIEW Cumulative Reference (see Note 1) Buffered Reference VO(VREFB) Output voltage, VREFB Hysteretic Comparator (core) I(REFB) = 50 µA VOS(HYSCMPrr) Input offset voltage Vhys(ACCrr) Hysteresis accuracy V(DROOP) pin grounded (see Note 2) V(VREFB) – V(VHYST) = 15 mV (Hysteresis window = 30 mV) Vhys(SETrr) Maximum hysteresis setting tPHL(HC) Propagation delay time from (AC) VSENSE_CORE to TG or BG (excluding deadtime) Vref – 5 mV Vref Vref – 5 mV V –4 4 mV –5 5 mV 60 10-mV overdrive, 0.925 V ≤ Vref ≤ 2 V, (see Note 2) mV 220 250 200 225 ns Overcurrent Protection (core) Normal operation V(OCP) Trip point, point OCP 180 mV 300 During dynamic VID change Overvoltage Protection (core, IO, CLK) V(OVP) Vhys(OVP) Trip point, OVP Upper threshold Hysteresis Upper-lower thresholds (see Note 2) 112 115 120 %Vref mV 80 %Vref mV 10 Undervoltage Protection (IO, CLK) V(UVP) Vhys(UVP) Trip point, UVP Lower threshold Hysteresis Upper-lower thresholds (see Note 2) 70 75 10 NOTES: 1. Cumulative reference accuracy is the combined accuracy of the reference voltage and the input offset voltage of the hysteretic comparator. Cumulative accuracy equals to the average of the low-level and high-level thresholds of the hysteretic comparator. 2. Ensured by design, not production tested. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 TPS5300 IMVP MOBILE POWER SUPPLY CONTROLLER SLVS334 – DECEMBER 2000 electrical characteristics over recommended operating free-air temperature range, 0 < TJ < 125°C, VIN = 4.3 V – 28 V (unless otherwise noted) (continued) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 4.46 V Bias UVLO (Resets fault latch) VIT(startUVLO) VIT(stopUVLO) Start threshold Stop threshold 3.3 VR_ON connected to GND and VI above UVLO start threshold VBIAS quiescent current, I(ving1) V 10 15 µA 2.1 2.5 V VR_ON UVLO (Resets fault latch) VIT(startVRON) VIT(stopVRON) Start threshold Stop threshold 1.3 V Slowstart I(chg) Charge current (I(chg) = (I(REFB)/5) V(SS) = 0.5 V, I(VREFB) = 65 µA VREFB = 1.3 V; I(chg) = (I(VREFB)/5) I(dischg) Discharge current V(SS) = 1.3 V, Design for VIN(min) = 4.5 V 10.4 13 15.6 3 µA mA PRODUCT PREVIEW VGATE (CORE, IO, CLK) (PWRGD of three outputs with open drain output) V(VGATE) Undervoltage trip point (VSENSE_CORE, _IO, & _CLK) VIN and V(drv) above UVLO thresholds 87.5 90 92.5 %Vref V(olVGATE) Output saturation voltage IO = 2.5 mA Enable EXT (SHUTDOWNB of IC with open-drain output. Use pullup resistor to 5 V or 3.3 V) 0.5 0.75 V V(olEN_EXT) Output saturation voltage DROOP Compensation IO = 2.5 mA 0.5 0.75 V V(DROOP_ACC) Initial accuracy tPHL(HC) Propagation delay V(DROOP) = 50 mV 15-mV to 150-mV swing, 1.3 V ≤ Vref ≤ 3.3 V, VCC = 5 V (see Note 2) –4 8 mV 200 500 ns 25 26 V/V 3 mV 500 ns Current Sensing With chopper stabilization (backup disable with metal mask) G(CS) Gain VIO Input offset t(VDSRESP) Response time (measured from 50% of (VIS+ – VIS– ) to 50% of V(IOUT)) VIS– = 1.3 V, VIS+ – VIS– = 10 mV VIS– = 0.925 V – 2 V, VIS+ is pulsed from VIS– to (VIS– + 50 mV), VCC = 5 V (see Note 2) 24 –3 NOTES: 2. Ensured by design, not production tested. 3. The VBIAS voltage is required to be a quiet bias supply for the TPS5300 control logic. External noisy loads should use VCC instead of the VBIAS voltage. 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TPS5300 IMVP MOBILE POWER SUPPLY CONTROLLER SLVS334 – DECEMBER 2000 electrical characteristics over recommended operating free-air temperature range, 0 < TJ < 125°C, VIN = 4.3 V – 28 V (unless otherwise noted) (continued) PARAMETER TEST CONDITIONS MIN TYP MAX 2.1 2.3 54 60 66 39 45 51 24 30 36 9 15 21 UNIT PSM/LATCH Power Saving Mode (PSM Comparator) V(PSMth1) V(PSMth2) V(PSMth3) V(PSMth4) PSM comparator start threshold PSM comparator stop threshold 1.8 Sweep OCP through thresholds OCP voltage trip points for PSM V R(tPSM1) PH to Ct, PSM = GND, V(IS+) – V(IS–) = 60 mV (see Note 3) 5.3 6.67 8 R(tPSM2) PH to Ct, PSM = GND, V(IS+) – V(IS–) = 45 mV (see Note 3) 8 10 12 R(tPSM3) PH to Ct, PSM = GND, V(IS+) – V(IS–) = 30 mV (see Note 3) 16 20 24 R(tPSM4) PH to Ct, PSM = GND, V(IS+) – V(IS–) = 15 mV (see Note 3) 1 PSM ramp timing resistance V mV kΩ MΩ PSM/LATCH Fault Latch Disable V(No_Latch/PSM) Disable latch threshold PSM enabled V(No_Latch) Disable latch threshold PSM disabled VBIAS + 0.3 V(Latch_enabled) Enable latch threshold Thermal Shutdown T(OTP) T(hyst) V ANAGND ANAGND – 0.3 V VBIAS V Over temperature trip point See Note 2 160 °C Hysteresis See Note 2 10 °C Dynamic VID Change (No current limit) Ι∆tSRC Voltage change timing current VCC = 5 V, V(ref1) = 2 V, DT_SET = 0.925 V 13.3 14 14.7 µA NOTES: 2. Ensured by design, not production tested. 3. The BIAS voltage is required to be a quiet bias supply for the TPS5300 control logic. External noisy loads should use VCC instead of the BIAS voltage. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 PRODUCT PREVIEW V(startINH) V(stopINH) TPS5300 IMVP MOBILE POWER SUPPLY CONTROLLER SLVS334 – DECEMBER 2000 electrical characteristics over recommended operating free-air temperature range, 0 < TJ < 125°C, VIN = 4.3 V – 28 V (see test circuits) (unless otherwise noted) (continued) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Output Drivers (see Note 4) IO(srcTG) Duty cycle < 2%, tpw < 100 µs, V(BOOT) – V(PH) = 4.5 V, V(TG) – V(PH) = 0.5 V (src) 1.2 2 A IO(sinkTG) Duty cycle < 2%, tpw < 100 µs, V(BOOT) – V(PH) = 4.5 V, V(TG) – V(PH) = 4 V (sink) 1.2 3.3 A IO(srcBG) Duty cycle < 2%, tpw < 100 µs, VCC = 4.5 V, V(BG) = 0.5 V (src) 1.4 2 A IO(sinkBG) Duty cycle < 2%, tpw < 100 µs, VCC = 4.5 V, V(BG) = 4 V (src) 1.3 3.3 A V(BOOT) – V(PH) = 4.5 V, VTG = 4 V V(BOOT) – V(PH) = 4.5 V, VTG = 0.5 V 2.5 Ω 1.5 Ω VCC = 4.5 V, V(BG) = 4 V VCC = 4.5 V, V(BG) = 0.5 V 2.5 Ω 1.5 Ω Cl = 3.3 nF, V(BOOT) = 4.5 V, V(PH) = GND 10 ns Cl = 3 3.3 3 nF nF, VCC = 4.5 45V 10 ns Peak output current (see Notes 2 and 4) ro(srcTG) ro(sinkTG) ro(srcBG) Output resistance (see Note 4) PRODUCT PREVIEW ro(sinkBG) tf(TG) tr(TG) TG fall time (AC) (see Note 5) tf(BG) tr(BG) BG fall time (AC) (see Note 5) TG rise time (AC) (see Note 5) BG rise time (AC) (see Note 5) High-Side DRIVER Quiescent Current Ihighdrq1 HIGHDRIVE (TG) quiescent current VR_ON grounded, or VCC below UVLO threshold; V(BOOT) = 5 V, PH grounded 10 µA Adaptive Deadtime Circuit VIH(TG) VIL(TG) TG – PH High-level input voltage VIH(BG) VIL(BG) BG High-level input voltage t(NUL) 2.4 TG – PH Low-level input voltage 1.33 0 925 V – 2 V (see Note 2) V(IS–) = 0.925 BG Low-level input voltage Driver nonoverlap time (AC) V 3 1.7 CBG = 9 nF, 10% threshold on BG, VCC = 5 V 50 ns NOTES: 2. Ensured by design, not production tested. 4. The pulldown (sink) circuit of the high-side driver is a MOSFET transistor referenced to DRVGND. The driver circuits are bipolar and MOSFET transistors in parallel. The peak output current rating is the combined current rating from the bipolar and MOSFET transistors. The output resistance is the rds(on) of the MOSFET transistor when the voltage on the driver output is less than the saturation voltage of the bipolar transistor. 5. Rise and fall times are measured from 10% to 90% of pulsed values. 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TPS5300 IMVP MOBILE POWER SUPPLY CONTROLLER SLVS334 – DECEMBER 2000 electrical characteristics over recommended operating free-air temperature range, 0 < TJ < 125°C, VIN = 4.3 V – 28 V (see test circuits) (unless otherwise noted) (continued) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VCC = 5 V, VSENSE_IO = 0.9 × V(REFIO) (see Note 2) 134 mA VCC = 5 V, VSENSE_IO = 1.1 × V(REFIO) (see Note 2) 14 µA Linear Regulator OUTPUT DRIVERs (IO, CLK) (see Note 4) Peak out output ut current linear regulator driver IO IO(sinkLDODR) V(CUM_ACC IO) Initial accuracy IO condition: closed loop; linear regulator VCC = 5 V, Vref = 1.5 V, IO = 1 A VCC = 5 V, Vref = 1.5 V, IO = 1 A, TJ = 25°C (see Note 2) V(Load Reg IO) Load regulation IO VCC = 5 V, βNPN ≥ 15, 0 ≤ ILoad ≤ 2 A, (see Note 2) V(IN Line Reg IO) VIN line regulation IO 5.5 V ≥ VCC ≥ 4.5 V, 3 V ≤ VIN (IO) ≤ 6 V, (see Note 2) IO(srcLDODR) Peak out output ut current regulator, driver CLK IO(sinkLDODR) –1.65% 1.65% –1.5% 1.5% 25 5 mV mV VCC = 5 V, VSENSE_IO = 0.9 × V(REFIO) (see Note 2) 10 mA VCC = 5 V, VSENSE_IO = 1.1 × V(REFIO) (see Note 2) 14 µA Initial accuracy CLK condition: closed loop VCC = 5 V, Vref = 2.5 V, IO = 75 mA –1.55% 1.55% Linear regulator VCC = 5 V, Vref = 2.5 V, IO = 75 mA, TJ = 25°C, (see Note 2) –1.5% 1.5% V(LoadRegCLK) Load regulation CLK VCC = 5 V βNPN ≥ 15, 0 ≤ ILoad ≥ 150 mA, (see Note 2) 5 mV VIN(LineRegCLK) Line regulation CLK 5.5 V ≥ VCC ≥ 4.5 V, 3 V ≤ VIN (CLK) ≤ 6 V, (see Note 2) 5 mV V(CUM_ACCCLK) NOTES: 2. Ensured by design, not production tested. 4. The pulldown (sink) circuit of the high-side driver is a MOSFET transistor referenced to DRVGND. The driver circuits are bipolar and MOSFET transistors in parallel. The peak output current rating is the combined current rating from the bipolar and MOSFET transistors. The output resistance is the rds(on) of the MOSFET transistor when the voltage on the driver output is less than the saturation voltage of the bipolar transistor. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 9 PRODUCT PREVIEW IO(srcLDODR) TPS5300 IMVP MOBILE POWER SUPPLY CONTROLLER SLVS334 – DECEMBER 2000 Table 1. Voltage Programming Code PRODUCT PREVIEW VID PINS 0 = GROUND, 1 = FLOATING, OR PULLUP TO 5 V Vref VID4 VID3 VID2 VID1 VID0 (Vdc) 1 1 1 1 1 No CPU – Off 1 1 1 1 0 0.925 1 1 1 0 1 0.950 1 1 1 0 0 0.975 1 1 0 1 1 1.000 1 1 0 1 0 1.025 1 1 0 0 1 1.050 1 1 0 0 0 1.075 1 0 1 1 1 1.100 1 0 1 1 0 1.125 1 0 1 0 1 1.150 1 0 1 0 0 1.175 1 0 0 1 1 1.200 1 0 0 1 0 1.225 1 0 0 0 1 1.250 1 0 0 0 0 1.275 0 1 1 1 1 No CPU – Off 0 1 1 1 0 1.300 0 1 1 0 1 1.350 0 1 1 0 0 1.400 0 1 0 1 1 1.450 0 1 0 1 0 1.500 0 1 0 0 1 1.550 0 1 0 0 0 1.600 0 0 1 1 1 1.650 0 0 1 1 0 1.700 0 0 1 0 1 1.750 0 0 1 0 0 1.800 0 0 0 1 1 1.850 0 0 0 1 0 1.900 0 0 0 0 1 1.950 0 0 0 0 0 2.000 NOTE: If the VID bits are set to 11111 or 01111, then the high-side and low-side driver outputs will be set low.. Table 2. PSM Program Modes 10 Pin Voltage Function 1 < (ANAGND – 0.3 V) Disable PSM and disable fault latch 2 ANAGND to 1.8 V Disable PSM and enable fault latch 3 2.3 V to VBIAS Enable PSM and enable fault latch 4 > (VBIAS + 0.3 V) Enable PSM and disable fault latch POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TPS5300 IMVP MOBILE POWER SUPPLY CONTROLLER SLVS334 – DECEMBER 2000 detailed description reference/voltage identification The reference /voltage programming (VP) section consists of a temperature-compensated, bandgap reference and a 5-bit voltage selection network. The five VID pins are inputs to the VID selection network and are TTL compatible inputs that are internally pulled up to VCC with pullup resistors. The internal reference voltage can be programmed from 0.925 V to 2 V with the VID pins. The VID codes are listed in Table 1. The output voltage of the VP network, Vref, is within ±1.5% of the nominal setting. The ±1.5% tolerance is over the full VP range of 0.925 V to 2 V, and includes a junction temperature range of 0°C to 125°C, and a VCC range of 4.5 V to 5.5 V. The output of the reference/VP network is indirectly brought out through a buffer to the VREFB pin. The voltage on this pin will be within ±5 mV of Vref. It is not recommended to drive loads with VREFB, other than setting the hysteresis of the hysteretic comparator, because the current drawn from VREFB sets the charging current for the slowstart capacitor. Refer to the slowstart section for additional information. Dynamic VID change controls the rate of change of the programmed VID to allow transitioning within 100 µs, while controlling the dv/dt to avoid large input surge currents. VID could change with any input voltage, output voltage, or output current. A new change is ignored until the current transition is finished. Program the transition by adding a capacitor from DT_SET to ANAGND. I t 14 µA t C DT_SET t V V V REF REF2 REF1 hysteretic comparator The hysteretic comparator regulates the output voltage of the synchronous-buck converter. The hysteresis is set by two external resistors and is centered around VREFB. The two external resistors form a resistor divider from VREFB to ANAGND, and the divided down voltage connects to the VHYST terminal. The hysteresis of the comparator will be equal to twice the voltage that is across the VREFB and VHYST pins. The maximum hysteresis setting is 60 mV. ramp generator The ramp generator circuit is partially composed of the PSM circuit. An external resistor from PH to VSENSE_CORE superimposes a ramp (proportional to VI and VO) onto the feedback voltage. This allows increasing the operating frequency, and reduces frequency dependance on the output filter values. A capacitor can be used to provide ac-coupling. Also, connecting a resistor from VI to VSENSE_CORE allows feed forward to counteract any dc offsets due to the ramp generator or propagation delays limiting duty cycle. power saving mode/latch The power saving mode circuit reduces the operating frequency of the ripple regulator during light load. This helps boost the efficiency during light loads by reducing the switching losses. Care should be taken to not allow rms current losses to exceed the switching losses. A 2-bit binary weighted resistor ramp circuit allows setting four operating frequencies. The PSM/LATCH terminal allows disabling of the fault latch (see Table 2). This allows the user to troubleshoot or implement an external protection circuit. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 11 PRODUCT PREVIEW dynamic VID change TPS5300 IMVP MOBILE POWER SUPPLY CONTROLLER SLVS334 – DECEMBER 2000 detailed description (continued) active voltage DROOP positioning The droop compensation network reduces the load transient overshoot/undershoot on VO, relative to Vref. VO(max) is programmed to a voltage greater than Vref in the mechanical data drawing by an external resistor divider from VO to the VSENSE pin to reduce the undershoot on VOUT during a low to high load transient. The overshoot during a high to low load transient is reduced by subtracting the voltage that is on the DROOP pin from Vref. The voltage on the IOUT pin is divided down with an external resistor divider, and connected to the DROOP pin. Thus, under loaded conditions, VO is regulated to VO(max) – V(DROOP). The continuous sensing of the inductor current allows a fast regulating voltage adjustment allowing higher transient repetition rates. low-side driver The low-side driver is designed to drive low rds(on), N-channel MOSFETs. The current of the driver is typically 2-A source and 3.3-A sink. The supply to the low-side driver is internally connected to VCC. PRODUCT PREVIEW high-side driver The high-side driver is designed to drive low rds(on) N-channel MOSFETs. The current of the driver is typically 2-A source and 3.3-A sink. The high-side driver is configured as a floating bootstrap driver. The internal bootstrap diode, connected between the DRV and BOOT pins, is a Schottky diode for improved drive efficiency. The maximum voltage that can be applied between the BOOT pin and ground is 35 V. deadtime control The deadtime control prevents shoot-through current from flowing through the main power FET’s during the switching transitions by actively controlling the turnon times of the MOSFET drivers. The high-side driver is not allowed to turn on until the gate drive voltage to the low-side FET is below 1.7 V. The low-side driver is not allowed to turn on until the gate drive voltage from high-side FET to PH is below 1.3 V. current sensing Current sensing is achieved by sensing the voltage across a current-sense resistor placed in series between the output inductor and the output capacitors. The sensing network consists of a high bandwidth differential amplifier with a gain of 25x to allow using sense resistors with values as low as 1 mΩ. Sensing occurs at all times to allow having realtime information for quick response during an active voltage droop positioning transition. The voltage on the IOUT pin equals 25 times the sensed voltage. VR_ON The VR_ON terminal is a TTL compatible digital pin that is used to enable the controller. When VR_ON is low, the output drivers are low, the linear regulator drivers are off, and the slowstart capacitor is discharged. When VR_ON goes high, the short across the slowstart capacitor is released and normal converter operation begins. When the system logic supply is connected to the VR_ON pin, the VR_ON pin can control power sequencing by locking out controller operation until the system logic supply exceeds the input threshold voltage of the VR_ON circuit. Thus, VCC and the system logic supply (either 5 V or 3.3 V) must be above UVLO thresholds before the controller is allowed to start up. Likewise, a microprocessor or other external logic can also control the sequencing through VR_ON. VBIAS undervoltage lockout The VBIAS undervoltage-lockout circuit disables the controller, while VBIAS is below the 4.46-V start threshold during power up. The controller is disabled when VBIAS goes below 3.3 V. While the controller is disabled, the output drivers will be low and the slowstart capacitor will be shorted. When VBIAS exceeds the start threshold, the short across the slowstart capacitor is released and normal converter operation begins. 12 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TPS5300 IMVP MOBILE POWER SUPPLY CONTROLLER SLVS334 – DECEMBER 2000 detailed description (continued) IO linear regulator driver The IO linear regulator driver circuit drives a high power NPN external power transistor, allowing external power dissipation. The IO voltage is ramped up with the slowstart with the other two converters. Under voltage protection protects against hard shorts or extreme loading. The VSENSE_IO voltage is monitored by the VGATE (powergood) circuit. A fault or shutdown on any converter will shut down the linear regulator. CLK linear regulator driver The CLK linear regulator driver circuit drives a lower power NPN external power transistor, allowing external power dissipation. The CLK voltage is ramped up with the slowstart with the other two converters. Under voltage protection protects against hard shorts or extreme loading. The VSENSE_CLK voltage is monitored by the VGATE (powergood) circuit. A fault or shutdown on any converter will shut down the linear regulator. The slowstart circuit controls the rate at which VOUT powers up. A capacitor is connected between the SLOWST and ANAGND pins and is charged by an internal current source. The value of the current source is proportional to the reference voltage, so that the charging rate of Cslowst is proportional to the reference voltage. By making the charging current proportional to Vref, the power up time for VO will be independent of Vref. Thus, Cslowst can remain the same value for all VP settings. The slowstart charging current is determined by the following equation: I SLOWSTART I(VREFB) 5 (amps) where I(VREFB) is the current flowing out of the VREFB terminal. It is recommended that no additional loads be connected to VREFB, other than the resistor divider for setting the hysteresis voltage. Thus, these resistor values will determine the slowstart charging current. The maximum current that can be sourced by the VREFB circuit is 500 µA. The equation for setting the slowstart time is: tSLOWSTART = 5 × CSLOWSTART × RVREFB (seconds) where R(VREFB) is the total external resistance from VREFB to ANAGND. VGATE The VGATE circuit monitors for an undervoltage condition on V(out_core), V(out_IO), and V(out_CLK). If any VO is 7% below its reference voltage, or if any UVLO (Vcc, VR_ON) threshold is not reached, then the VGATE pin is pulled low. The VGATE terminal is an open drain output. overvoltage protection The overvoltage protection circuit monitors Vout_core, Vout_IO, and Vout_CLK for an overvoltage condition. If any VO is 15% above its reference voltage, then a fault latch is set, then both the ripple regulator output drivers and the linear regulator drivers are turned off. The latch will remain set until VBIAS goes below the undervoltage lockout value or until VR_ON is pulled low. overcurrent protection The overcurrent protection circuit monitors the current through the current sense resistor. The overcurrent threshold is adjustable with an external resistor divider between IOUT and ANAGND terminals, with the divider voltage connected to the OCP terminal. If the voltage on the OCP terminal exceeds 200 mV, then a fault latch is set and the output drivers (ripple regulator and linear regulators) are turned off. The latch remains set until VBIAS goes below the undervoltage lockout value or until VR_ON is pulled low. thermal shutdown Thermal shutdown disables the controller if the junction temperature exceeds the 165°C thermal shutdown trip point. The hysteresis is 10°C. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 13 PRODUCT PREVIEW slowstart TPS5300 IMVP MOBILE POWER SUPPLY CONTROLLER SLVS334 – DECEMBER 2000 APPLICATION INFORMATION Vout IO Vio 3.3/5V Vclk 3.3/5V Vout CLK DRV_CLK 1 2 VSENSE_CLK ENABLE_EXT DRV_IO VSENSE_IO V_GATE 32 31 29 15 OCP 9 11 IOUT DROOP 10 Protection Circuitry VSS is dominant if VSS < Vref(CLK) VR_ON 22 UVLO Enables IC When UVLO VR_ON > 2.5V and Vcc > 4.46V VSS 13 Vref CLK Shutdown VSS is dominant if VSS < Vref(IO) PWRGD is LOW if PWRGD Vsense Core or Vsense IO or Vsense CLK > 0.93 of their Vref VSS 14 Q S ShutdownB Q R Shutdown Clock and IO UVP Regulator Drivers VBIAS 30 Latch disabled UVP is Enabled When Vss > Vref CLK, and Vsense Core or Vsense IO or Vsense CLK < 0.75 of their Vref BOOT 21 20 Regulator Controller VID0 27 VID1 26 Bandgap VID3 24 _ + Vcc Vss is dominant if Vss<Vref Vref 19 Vss 17 16 Vref and DAC Hyst. Set VID4 23 3 DT_SET 14 VBIAS VCC(+5V) 18 Core Voltage VID2 25 IS– IS+ Vcc Vref IO PRODUCT PREVIEW x 25 OCP_OVP Enables Device When Core > 200mV OCP_OVP OCP or Vsense Core or Vsense IO or Vsense CLK > 1.15 of their Vref 7 VREFB 8 VHYST Power Save Mode Control 6 5 12 28 RAMP SLOWST VSENSE_CORE PSM/LATCH POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 4 Vcc (5V) Vbatt TG PH BG DRVGND ANAGND VO TPS5300 IMVP MOBILE POWER SUPPLY CONTROLLER SLVS334 – DECEMBER 2000 MECHANICAL DATA DAP (R-PDSO-G**) PowerPAD PLASTIC SMALL-OUTLINE PACKAGE 38 PINS SHOWN 0,30 0,19 0,65 38 0,13 M 20 Thermal Pad (see Note D) 6,20 NOM 8,40 7,80 0,15 NOM 1 19 PRODUCT PREVIEW Gage Plane 0,25 A 0°-8° 0,75 0,50 Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,10 28 30 32 38 A MAX 9,80 11,10 11,10 12,60 A MIN 9,60 10,90 10,90 12,40 DIM 4073257/A 07/97 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion. The package thermal performance may be enhanced by bonding the thermal pad to an external thermal plane. This pad is electrically and thermally connected to the backside of the die and possibly selected leads. E. Falls within JEDEC MO-153 PowerPAD is a trademark of Texas Instruments. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 15 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. Customers are responsible for their applications using TI components. In order to minimize risks associated with the customer’s applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance or customer product design. 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