TPS5615, TPS5618, TPS5625, TPS5633 SYNCHRONOUS-BUCK HYSTERETIC REGULATOR CONTROLLER SLVS177B – SEPTEMBER 1998 – REVISED JULY 2000 D D D D D D D D D D ±1% Reference Over Full Operating Temperature Range Synchronous Rectifier Driver for >90% Efficiency Fixed Output Voltage Options of 1.5 V, 1.8 V, 2.5 V, and 3.3 V User-Selectable Hysteretic-Type Control Low Supply Current . . . 3 mA Typ 11.4-V to 13-V Input Voltage Range, VCC Power Good Output Programmable Soft-Start Overvoltage/Overcurrent Protection Active Deadtime Control PWP PACKAGE (TOP VIEW) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 IOUT AGND2 OCP VHYST VREFB VSENSE ANAGND SLOWST BIAS LODRV LOHIB DRVGND LOWDR DRV description 28 27 26 25 24 23 22 21 20 19 18 17 16 15 PWRGD NC NC NC NC NC INHIBIT IOUTLO LOSENSE HISENSE BOOTLO HIGHDR BOOT VCC NC – No internal connection The TPS5615 family of synchronous-buck regulator controllers provides an accurate supply voltage to DSPs. The output voltage is internally set by a resistive divider with an accuracy of 1% over the full operating temperature range. A hysteretic controller with user-selectable hysteresis is used to dramatically reduce overshoot and undershoot caused by load transients. Propagation delay from the comparator inputs to the output drivers is less than 250 ns. Overcurrent shutdown and crossover protection for the output drivers combine to eliminate destructive faults in the output FETs. PWRGD monitors the output voltage and pulls the open-collector output low when the output drops below 93% of the nominal output voltage. An overvoltage circuit disables the output drivers if the output voltage rises 15% above the nominal value. The inhibit pin can be used to control power sequencing. Inhibit and undervoltage lockout assures that the 12-V supply voltage and system supply voltage (5 V or 3.3 V) are within proper operating limits before the controller starts. The output driver circuits include 2-A drivers with internal 8-V gate-voltage regulators that can easily provide sufficient power for today’s high-powered DSPs. The high-side driver can be configured either as a ground-referenced driver or as a floating bootstrap driver. The TPS5615 family is available in a 28-pin TSSOP PowerPad package. It operates over a junction temperature range of 0°C to 125°C. AVAILABLE OPTIONS TJ OUTPUT VOLTAGE PACKAGE TSSOP† (PWP) 1.5 V TPS5615PWP 1.8 V TPS5618PWP 2.5 V TPS5625PWP 0°C to 125°C 3.3 V TPS5633PWP † The PWP package is availble taped and reeled. Add R suffix to device type (e.g., TPS5615PWPR). Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PowerPAD is a trademark of Texas Instruments Incorporated. Copyright 2000, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 TPS5615, TPS5618, TPS5625, TPS5633 SYNCHRONOUS-BUCK HYSTERETIC REGULATOR CONTROLLER SLVS177B – SEPTEMBER 1998 – REVISED JULY 2000 functional block diagram 15 VCC 7 ANAGND 28 20 PWRGD LOSENSE 21 IOUTLO 19 HISENSE VCC 2V + _2X 22 INHIBIT UVLO 10 V 3 OCP _ Shutdown S VCC 1 IOUT Q Fault Deglitch + Rising Edge Delay R HIGHDR 100mV HIGHIN Deglitch VOVP 1.15 VREF VPGD 0.93 VREF Analog Bias VSENSE PREREG Analog Bias IVREFB 8 SLOWST VCC 9 BIAS Slowstart Comparator + _ 5 14 DRV DRV REG Shutdown 16 BOOT 17 HIGHDR _ Bandgap Shutdown CM Filters + VREF 18 BOOTLO + _ Hysteresis Comparator + _ 13 LOWDR 12 DRVGND Hysteresis Setting I VREFB 2 AGND2 2 5 VREFB 4 VHYST 6 VSENSE POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 11 LOHIB 10 LODRV TPS5615, TPS5618, TPS5625, TPS5633 SYNCHRONOUS-BUCK HYSTERETIC REGULATOR CONTROLLER SLVS177B – SEPTEMBER 1998 – REVISED JULY 2000 Terminal Functions TERMINAL NAME NO. I/O DESCRIPTION AGND2 2 Analog ground (must be connected). ANAGND 7 Analog ground BIAS 9 Analog bias pin. A 1-µF capacitor should be connected from BIAS to ANAGND. BOOT 16 Bootstrap. A 1-µF capacitor should be connected from BOOT to BOOTLO. BOOTLO 18 Bootstrap low. Connect to the junction of the high-side and low-side FETs for floating drive configuration. Connect to PGND for ground-reference drive configuration. DRV 14 Drive regulator for the FET drivers. A 1-µF capacitor should be connected from DRV to DRVGND. DRVGND 12 Drive ground. Ground for FET drivers. Connect to FET PWRGND. HIGHDR 17 High drive. Output drive to high-side power switching FETs. HISENSE 19 High current sense. For current sensing across high-side FETs, connect to the drain of the high-side FETs; for optional current sensing scheme, connect to power supply side of current-sense resistor placed in series with high-side FET drain. INHIBIT 22 Disables the drive signals to the MOSFET drivers. Also serves as UVLO for system logic supply (3.3 V or 5 V). An external pullup resistor should be connected to system-logic supply. IOUT 1 Current out. Output voltage on this terminal is proportional to the load current as measured across the Rds(on) of the high side FET. The voltage on this terminal equals 2 × RDS(ON) × IOUT. In applications where very accurate current-sensing is required, a sense resistor should be connected between the input supply and the drain of the high-side FETs. IOUTLO 21 Current sense low output. This is the voltage on the LOSENSE terminal when the high-side FETs are on. A ceramic capacitor (between 0.033 µF and 0.1 µF) should be connected from IOUTLO to HISENSE to hold the sensed voltage. LODRV 10 Low drive enable. Normally tied to 5 V. To configure the low-side FET as a crowbar, pull LODRV low. LOHIB 11 Low side inhibit. Connect to the junction of the high- and low-side FETs to control the anti-crossconduction and eliminate shoot-through current. Disabled when configured in crowbar mode. LOSENSE 20 Low current sense. For current sensing across high-side FETs, connect to the source of the high-side FETs; for optional current sensing scheme, connect to high-side FET drain side of current-sense resistor placed in series with high-side FET drain. 13 Low drive. Output drive to synchronous rectifier FETs. LOWDR NC 23–27 No connect OCP 3 Over current protection. Current limit trip point is set with a resistor divider between IOUT and ANAGND. PWRGD 28 Power good. PWRGD signal goes high when output voltage is within 7% of voltage setpoint. Open-drain output. SLOWST 8 Slow Start (soft start). A capacitor form SLOWST to ANAGND sets the slowstart time. Slowstart current = IVREFB/5 VHYST 4 Hysteresis set input. The hysteresis is set with a resistor divider from VREFB to ANAGND. Hysteresis = 2 × (VREFB – VHYST) VCC VREFB 15 12-V supply. A 1-µF capacitor should be connected from VCC to DRVGND. 5 Buffered reference voltage VSENSE 6 Voltage sense Input. To be connected from converter output voltage bus to sense and control output voltage. It is recommended that a RC low-pass filter be connected at this pin to filter noise. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 TPS5615, TPS5618, TPS5625, TPS5633 SYNCHRONOUS-BUCK HYSTERETIC REGULATOR CONTROLLER SLVS177B – SEPTEMBER 1998 – REVISED JULY 2000 detailed description Vref The reference voltage section consists of a temperature-compensated bandgap reference and a resistive divider that sets the output voltage option. The output voltage, VREF, is within 1% of the nominal setting over the full junction temperature range of 0°C to 125°C, and a VCC supply voltage range of 11.4 V to 12.6 V. The output of the reference network is indirectly brought out through a buffer to the VREFB pin. The voltage on this pin will be within 2% of VREF. It is not recommended to drive loads with VREFB, other than setting the hysteresis of the hysteretic comparator, because the current drawn from VREFB sets the charging current for the slowstart capacitor. Refer to the slowstart section for additional information. hysteretic comparator The hysteretic comparator regulates the output voltage of the synchronous-buck converter. The hysteresis is set by 2 external resistors and is centered on VREF. The 2 external resistors form a resistor divider from VREFB to ANAGND, with the output voltage connecting to the VHYST pin. The hysteresis of the propagation delay from the comparator inputs to the driver outputs is 250 ns (maximum). The maximum hysteresis setting is 60 mV. IO(MAX) = 0.5 µA VREFB R1 VHYST R1 +2 R2 VH VREFB–V H Where VH = desired hysteresis voltage TPS56xx R2 +2 ǒ VREFB * V HǓ Figure 1. Setting the Hysteresis Voltage low-side driver The low-side driver is designed to drive low-Rds(on) n-channel MOSFETs. The current rating of the driver is 2 A, source or sink. The bias to the low-side driver is internally connected to the DRV regulator. high-side driver The high-side driver is designed to drive low-Rds(on) n-channel MOSFETs. The current rating of the driver is 2 A, source or sink. The high-side driver can be configured either as a ground-referenced driver or as a floating bootstrap driver. When configured as a floating driver, the bias voltage to the driver is developed from the DRV regulator. The internal bootstrap diode, connected between the DRV and BOOT pins, is a Schottky for improved drive efficiency. The maximum voltage that can be applied between BOOT and DRVGND is 30 V. The driver can be referenced to ground by connecting BOOTLO to DRVGND, and connecting BOOT to either DRV or VCC. deadtime control Deadtime control prevents shoot-through current from flowing through the main power FETs during switching transitions by actively controlling the turn-on times of the MOSFET drivers. The high-side driver is not allowed to turn on until the gate-drive voltage to the low-side FET is below 2 V; the low-side driver is not allowed to turn on until the voltage at the junction of the 2 FETs (Vphase) is below 2 V. 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TPS5615, TPS5618, TPS5625, TPS5633 SYNCHRONOUS-BUCK HYSTERETIC REGULATOR CONTROLLER SLVS177B – SEPTEMBER 1998 – REVISED JULY 2000 detailed description (continued) current sensing Current sensing is achieved by sampling and holding the voltage across the high-side power FET while the high-side FET is on. The sampling network consists of an internal 60-Ω switch and an external ceramic hold capacitor. Recommended value of the hold capacitor is between 0.033 µF and 0.1 µF. The actual value should give a time constant (60 Ω × CH ) greater than the FET on time. Internal logic controls the turn-on and turn-off of the sample/hold switch such that the switch does not turn on until the Vphase voltage transitions high, and the switch turns off when the input to the high-side driver goes low. Thus sampling will occur only when the high side FET is conducting current. The voltage on the IOUT pin equals 2 times the sensed high-side voltage. In applications where a higher accuracy in current-sensing is required, a sense resistor can be placed in series with the high-side FET and the voltage across the sense resistor can be sampled by the current sensing circuit. See Figures 2 and 3. overcurrent protection The overcurrent protection (OCP) circuit monitors the current through the high-side FET. The overcurrent threshold is adjustable with an external resistor divider between IOUT and ANAGND, with the divider voltage connected to OCP. If the voltage on OCP (VS ) exceeds 100 mV, then a fault latch is set and the output drivers are turned off. The latch will remain set until VCC goes below the undervoltage lockout value. A 3-µs deglitch timer is included for noise immunity. The OCP circuit is also designed to protect the high-side power FET against a short-to-ground fault on the terminal common to both power FETs (Vphase). RS VCC VP VCC CH VP CH VS 2 * VS HIGHDR R1 LOSENSE IOUT HISENSE IOUTLO 2 * VS HIGHDR LOSENSE HISENSE IOUTLO VS IOUT R1 OCP OCP TPS56xx R2 R1 + R2 ǒ V S–0.05 0.05 TPS56xx Ǔ R2 R1 Figure 2. OCP Using FET ON-Resistance + R2 ǒ V S–0.05 Ǔ 0.05 Figure 3. Precision OCP Using External Resistor inhibit INHIBIT is a TTL-compatible digital input used to enable the controller. When INHIBIT is low, the output drivers are low and the slowstart capacitor is discharged. When INHIBIT goes high, the short across the slowstart capacitor is released and normal converter operation begins. When the system-logic supply is connected to INHIBIT, it also controls power sequencing by locking out controller operation until the system-logic supply exceeds the input threshold voltage of the inhibit circuit. Thus the 12-V supply and the system-logic supply (either 5 V or 3.3 V) must be above UVLO thresholds before the controller is allowed to start up. The INHIBIT comparator start threshold is 2.1 V and the hysteresis is 100 mV. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 TPS5615, TPS5618, TPS5625, TPS5633 SYNCHRONOUS-BUCK HYSTERETIC REGULATOR CONTROLLER SLVS177B – SEPTEMBER 1998 – REVISED JULY 2000 detailed description (continued) VCC To Power Stage R1 SHUTDOWN INHIBIT R2 TPS56xx R2 + V2.1 R1 –2.1 TRIP Where VTRIP=desired VSUPPLY trip voltage Figure 4. Input Undervoltage Lockout Circuit Using INHIBIT VCC undervoltage lockout (UVLO) The undervoltage lockout circuit disables the controller while the VCC supply is below the 10-V start threshold during power up. While the controller is disabled, the output drivers will be low and the slowstart capacitor will be shorted. When VCC exceeds the start threshold, the short across the slowstart capacitor is released and normal converter operation begins. There is a 2-V hysteresis in the undervoltage lockout circuit for noise immunity. slowstart The slowstart circuit controls the rate at which VO powers up. A capacitor is connected between SLOWSST and ANAGND and is charged by an internal current source. The slowstart charging current is determined by the following equation: I SLOWSTART + I(VREFB) 5 where I(VREFB) is the current flowing out of VREFB. It is recommended that no additional loads be connected to VREFB, other than the resistor divider for setting the hysteresis voltage. The maximum current that can be sourced by the VREFB circuit is 500 µA. The slowstart time is set by: t SLOWSTART +5 C SLOWST R VREFB where RVREFB is the total external resistance from VREFB to ANAGND. power good The power good circuit monitors for an undervoltage condition on VO. If VO is 7% below VREF, then PWRGD is pulled low. PWRGD is an open-drain output. overvoltage protection The overvoltage protection (OVP) circuit monitors VO for an overvoltage condition. If VO is 15% above VREF, then a fault latch is set and both output drivers are turned off. The latch will remain set until VCC goes below the undervoltage lockout value. A 3-µs deglitch timer is included for noise immunity. Refer to the LODRV section for information on how to protect the load against overvoltages due to a shorted fault across the high-side power FET. 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TPS5615, TPS5618, TPS5625, TPS5633 SYNCHRONOUS-BUCK HYSTERETIC REGULATOR CONTROLLER SLVS177B – SEPTEMBER 1998 – REVISED JULY 2000 detailed description (continued) drive regulator The drive regulator provides drive voltage to the output drivers. The minimum drive voltage is 7 V. The minimum short circuit current is 100 mA. Connect a 1-µF ceramic capacitor from DRV to DRVGND. LODRV The LODRV circuit is designed to protect the load against overvoltages that occur if the high-side FETs become shorted. External components to sense an overvoltage condition are required to use this feature. When an overvoltage fault occurs, LODRV is pulled low and the low-side FET will be turned on, overriding all control signals inside the TPS56xx controller. The crowbar action will short the system-logic supply to ground through the faulted high-side FETs and the low-side FETs. A fuse, in series with VIN, should be added to disconnect the short circuit. absolute maximum ratings over operating free-air temperature (unless otherwise noted)† Supply voltage range, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 to 14 V Input voltage range: BOOT to DRVGND (high-side driver ON) . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 to 30 V BOOT to HIGHDRV . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 to 15 V BOOT to BOOTLO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 to 15 V INHIBIT, LODRV . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 to 7.3 V PWRGD, OCP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 to 7 V LOHIB, LOSENSE, IOUTLO, HISENSE . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 to 14 V VSENSE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 to 5 V Voltage difference between ANAGND and DRVGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±0.5 V Output current, VREFB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 mA Short circuit duration, DRV . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Continuous Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table Operating junction temperature range, TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 125°C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C Lead temperature soldering 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . 260°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: Unless otherwise specified, all voltages are with respect to ANAGND. DISSIPATION RATING TABLE PACKAGE TA ≤ 25°C POWER RATING DERATING FACTOR ABOVE TA = 25°C TA = 70°C POWER RATING TA = 85°C POWER RATING PWP 1150 mW 11.5 mW/°C 630 mW 460 mW POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 TPS5615, TPS5618, TPS5625, TPS5633 SYNCHRONOUS-BUCK HYSTERETIC REGULATOR CONTROLLER SLVS177B – SEPTEMBER 1998 – REVISED JULY 2000 recommended operating conditions MIN MAX 11.4 13 BOOT to DRVGND 0 28 BOOT to BOOTLO 0 13 INHIBIT, LODRV, PWRGD, OCP 0 6 LOHIB, LOSENSE, IOUTLO, HISENSE 0 13 VSENSE 0 4.5 0 ±0.2 V 0 0.4 mA Supply voltage, VCC Input voltage Voltage difference between ANAGND and DRVGND Output current, VREFB† UNIT V V † Not recommended to load VREFB other than to set hysteresis since IVREFB sets slowstart time. electrical characteristics over recommended operating virtual junction temperature range, VCC = 12 V, IDRV = 0 A (unless otherwise noted) reference PARAMETER TEST CONDITIONS MIN TPS5615 TPS5618 VREF Reference voltage VREFB Output voltage VREFB Output regulation TPS5625 4 V to 12.6 12 6 V VCC = 11 11.4 TPS5633 TYP MAX 1.485 1.515 1.782 1.818 2.475 2.525 3.267 IREFB = 50 µA 10 µA ≤ IO ≤ 500 µA VREF–2% UNIT V 3.333 VREF VREF+2% 2 V mV power good PARAMETER TEST CONDITIONS Undervoltage trip threshold MIN 90 Low-level output voltage, PWRGD IO = 5 mA VPWRGD = 6 V High-level input current, PWRGD TYP 93 0.5 Hysteresis MAX UNIT 95 %VREF 0.75 V 1 µA 10 mV overvoltage protection PARAMETER TEST CONDITIONS Overvoltage trip threshold Hysteresis MIN TYP 112 115 See Note 2 MAX UNIT 120 %VREF 10 mV NOTE 2: Ensured by design, not tested. slowstart PARAMETER Charge current Discharge current TEST CONDITIONS VSLOWST = 0.5 V, VSOFTST = 1 V IVREFB = 65 µA MIN TYP MAX UNIT 10.4 13 15.6 µA 3 Comparator input offset voltage Comparator input bias current See Note 2 Hysteresis –7.5 NOTE 2: Ensured by design, not tested. 8 10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 mA 10 mV 100 nA 7.5 mV TPS5615, TPS5618, TPS5625, TPS5633 SYNCHRONOUS-BUCK HYSTERETIC REGULATOR CONTROLLER SLVS177B – SEPTEMBER 1998 – REVISED JULY 2000 electrical characteristics over recommended operating virtual junction temperature range, VCC = 12 V, IDRV = 0 A (unless otherwise noted) (continued) inhibit PARAMETER TEST CONDITIONS Startup threshold MIN TYP MAX UNIT 1.9 2.1 2.35 V Hysteresis 0.08 0.1 0.12 V Stop threshold 1.85 V input undervoltage lockout PARAMETER TEST CONDITIONS Startup threshold MIN TYP MAX UNIT 9.25 10 10.75 V Hysteresis 1.9 2 2.2 V Stop threshold 7.5 V hysteretic comparator PARAMETER TEST CONDITIONS Input offset voltage TYP –2.5 Input bias current See Note 2 Hysteresis accuracy VREFB – VHYST = 15 mV, (hysteresis window = 30 mV) VREFB – VHYST = 30 mV Maximum hysteresis setting MIN – 3.5 MAX UNIT 2.5 mV 500 nA 3.5 mV 60 mV NOTE 2: Ensured by design, not tested. overcurrent protection PARAMETER TEST CONDITIONS OCP trip threshold Input bias current POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MIN TYP 90 100 MAX UNIT 110 mV 100 nA 9 TPS5615, TPS5618, TPS5625, TPS5633 SYNCHRONOUS-BUCK HYSTERETIC REGULATOR CONTROLLER SLVS177B – SEPTEMBER 1998 – REVISED JULY 2000 electrical characteristics over recommended operating virtual junction temperature range, VCC = 12 V, IDRV = 0 A (unless otherwise noted) (continued) high-side VDS sensing PARAMETER TEST CONDITIONS MIN Gain TYP MAX 2 UNIT V/V Initial accuracy VHISENSE = 12 V, VLOSENSE = 11.9 V Differential input to Vds sensing amp = 100 mV IOUTLO sink current 5 V ≤ VIOUTLO ≤ 13 V IOUT source current VIOUT = 0.5 V, VIOUTLO = 11.5 V VHISENSE = 12 V, 500 µA IOUT sink current VIOUT = 0.05 V, VIOUTLO = 12 V VHISENSE = 12 V, 50 µA Output voltage swing VHISENSE = 11 V VHISENSE = 4.5 V VHISENSE = 3 V LOSENSE high-level input voltage LOSENSE low-level input voltage Sample/hold resistance CMRR VHISENSE = 4.5 V, VHISENSE = 4.5 V, RIOUT = 10 kΩ See Note 2 194 mV 250 nA 0 2 0 1.5 0 0.75 2.85 V V See Note 2 11.4 V ≤ VHISENSE ≤ 12.6 V, LOSENSE connected to HISENSE, VHISENSE – VIOUTLO = 0.15 V 4.5 V ≤ VHISENSE ≤ 5.5 V, LOSENSE connected to HISENSE, VHISENSE – VIOUTLO = 0.15 V 206 2.4 50 60 80 62 85 123 3 V ≤ VHISENSE ≤ 3.6 V, LOSENSE connected to HISENSE, VHISENSE – VIOUTLO = 0.15 V 67 95 144 VHISENSE = 12.6 V to 3 V, VHISENSE – VOUTLO = 100 mV 69 75 MIN TYP V Ω dB NOTE 2: Ensured by design, not tested. deadtime PARAMETER LOHIB LODR LOHIB LODR High level input voltage High-level Low level input voltage Low-level TEST CONDITIONS See Note 2 2.4 See Note 2 3 MAX UNIT V See Note 2 1.4 See Note 2 1.7 V NOTE 2: Ensured by design, not tested. LODRV PARAMETER LODRV TEST CONDITIONS High-level input voltage MIN TYP MAX 1.85 UNIT V Low-level input voltage 0.95 V MAX UNIT drive regulator PARAMETER TEST CONDITIONS Output voltage 11.4 V ≤ VCC ≤ 12.6 V, Output regulation 1 mA ≤ IDRV ≤ 500 mA IDRV = 50 mA Short-circuit current 10 MIN • DALLAS, TEXAS 75265 9 100 100 POST OFFICE BOX 655303 TYP 7 V mV mA TPS5615, TPS5618, TPS5625, TPS5633 SYNCHRONOUS-BUCK HYSTERETIC REGULATOR CONTROLLER SLVS177B – SEPTEMBER 1998 – REVISED JULY 2000 electrical characteristics over recommended operating virtual junction temperature range, VCC = 12 V, IDRV = 0 A (unless otherwise noted) (continued) bias regulator PARAMETER TEST CONDITIONS 11.4 V ≤ VCC ≤ 12.6 V, Output voltage See Note 3 MIN TYP MAX 6 UNIT V NOTE 3: The bias regulator is designed to provide a quiet bias supply for the TPS56xx controller. External loads should not be driven by the bias regulator. output drivers PARAMETER (see Note 4) TEST CONDITIONS High-side sink High-side source Peak output current Low-side sink Low-side source High-side sink High-side source Output resistance Low-side sink Low-side source MIN Duty cycle < 2%, tpw < 100 µs, TJ = 125°C, VBOOT – VBOOTLO = 6 6.5 5V V, VHIGHDR = 1.5 V (SRC) or 5 V (sink), See Note 2 2 Duty cycle < 2%, tpw < 100 µs, TJ = 125°C, VDRV = 6 6.5 5 V, V VLOWDR = 1.5 1 5 V (SRC) or 5 V (sink), See Note 2 2 TYP MAX UNIT 2 A 2 3 TJ = 125°C,, VBOOT – VBOOTLO = 6.5 V,, VHIGHDR = 1.5 V (SRC) or 5 V (sink) 45 5.7 TJ = 125°C, VDRV = 6.5 V, VLOWDR = 1.5 V (SRC) or 5 V (sink) Ω 45 NOTES: 2. Ensured by design, not tested. 4. The pull up/down circuits of the drivers are bipolar and MOSFET transistors in parallel. The peak output current rating is the combined current from the bipolar and MOSFET transistors. The output resistance is the RDS(ON) of the MOSFET transistor when the voltage on the driver output is less than the saturation voltage of the bipolar transistor. supply current PARAMETER TEST CONDITIONS VCC supply voltage range VCC quiescent current MIN TYP MAX 11.4 12 13 10 VINHIBIT = 5 V, VBOOTLO = 0 V, VCC > 10.75 V at startup, See Note 2 3 VINHIBIT = 5 V, VBOOTLO = 0 V, CLOWDR = 50 pF, VCC > 10.75 V at startup, CHIGHDR = 50 pF, fswx = 200 kHz 5 VINHIBIT = 5 V, VBOOT = 13 V, CHIGHDR = 50 pF, VCC > 10.75 V at startup, VBOOTLO = 0 V, fswx = 200 kHz V mA VINHIBIT = 0 V or VCC < 9.25 V at startup, VBOOT = 13 V, VBOOTLO = 0 V High-side drive regulator quiescent current UNIT 80 2 µA mA NOTE 2: Ensured by design, not tested. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 11 TPS5615, TPS5618, TPS5625, TPS5633 SYNCHRONOUS-BUCK HYSTERETIC REGULATOR CONTROLLER SLVS177B – SEPTEMBER 1998 – REVISED JULY 2000 switching characteristics over recommended operating virtual junction temperature range, VCC = 12 V, IDRV = 0 V (unless otherwise noted) PARAMETER P Propagation ti d delay l TEST CONDITIONS MAX UNIT 150 250 ns OCP comparator See Note 2 1 OVP comparator See Note 2 1 PWRGD comparator See Note 2 1 SLOWST comparator Overdrive = 10 mV (see Note 2) HIGHDR output CL = 9 nF, VBOOTLO = 0 V, VBOOT = 6.5 V, TJ = 125°C LOWDR output CL = 9 nF, TJ = 125°C VDRV = 6.5 V, HIGHDR output CL = 9 nF, VBOOTLO = 0 V, VBOOT = 6.5 V, TJ = 125°C LOWDR output CL = 9 nF, TJ = 125°C VDRV = 6.5 V, OCP See Note 2 2 5 OVP See Note 2 2 5 Fall time Response time TYP Overdrive = 10 mV (see Note 2) Rise time Deglitch time (includes comparator propagation delay) MIN VSENSE to HIGHDR or LOWDR (excluding deadtime) High-side VDS sensing 560 µs 900 60 ns 60 60 ns 60 VHISENSE = 12 V, VIOUTLO pulsed from 12 V to 11.9 V, 100 ns rise/fall times, See Note 2 2 VHISENSE = 4.5 V, VIOUTLO pulsed from 4.5 V to 4.4 V, 100 ns rise/fall times, See Note 2 3 VHISENSE = 3 V, VIOUTLO pulsed from 3 V to 2.9 V, 100 ns rise/fall times, See Note 2 3 Short-circuit protection risingedge delay SCP LOSENSE = 0 V, Turn-on/turn-off delay VDS sensing sample/hold switch Crossover delay time (see Note 2) ns µs µs 300 500 ns 3 V ≤ VHISENSE ≤ 11 V, VLOSENSE = VHISENSE (see Note 2) 30 100 ns LOWDR to HIGHDRV, and LOHIB to LOWDR See Note 2 30 100 ns Prefilter pole frequency Hysteretic comparator See Note 2 Propagation delay LODRV See Note 2 NOTE 2: Ensured by design, not tested. 12 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 MHz 400 ns TPS5615, TPS5618, TPS5625, TPS5633 SYNCHRONOUS-BUCK HYSTERETIC REGULATOR CONTROLLER SLVS177B – SEPTEMBER 1998 – REVISED JULY 2000 TYPICAL CHARACTERISTICS SLOWSTART TIMING vs CAPACITANCE 1000 10 VREFB = 2 V I(VREFB) = 100µA C(SLOWST) = 0.1 µF TJ = 25°C VREFB = 2 V C(SLOWST) = 0.1µF TJ = 25°C SLOWSTART Timing – ms SLOWSTART Time – ms 100 SLOWSTART TIMING vs VREFB CURRENT 1 0.1 0 0.0001 0.001 0.01 0.1 100 10 1 1 1 Capacitance – µF Figure 5 t f – Output Driver Fall Time – ns t r – Output Driver Rise Time – ns High Side Driver 10 Low Side Driver 1 1 1000 OUTPUT DRIVER FALL TIME vs LOAD CAPACITANCE 1000 0.1 100 Figure 6 OUTPUT DRIVER RISE TIME vs LOAD CAPACITANCE 100 10 I(VREFB) – VREFB Current – µA 10 100 100 High Side Driver 10 Low Side Driver 1 0.1 CL – Load Capacitance – nF 1 10 100 CL – Load Capacitance – nF Figure 7 Figure 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 13 TPS5615, TPS5618, TPS5625, TPS5633 SYNCHRONOUS-BUCK HYSTERETIC REGULATOR CONTROLLER SLVS177B – SEPTEMBER 1998 – REVISED JULY 2000 TYPICAL CHARACTERISTICS OCP THRESHOLD VOLTAGE vs JUNCTION TEMPERATURE OVP THRESHOLD VOLTAGE vs JUNCTION TEMPERATURE 105 118 OCP Threshold Voltage – mV OVP Threshold Voltage – % 117 116 115 114 103 101 99 97 113 95 112 0 25 50 75 100 0 125 25 100 125 Figure 10 Figure 9 INHIBIT HYSTERESIS VOLTAGE vs JUNCTION TEMPERATURE INHIBIT START THRESHOLD VOLTAGE vs JUNCTION TEMPERATURE 150 INHIBIT Hysteresis Voltage – mV 2.1 INHIBIT Start Threshold Voltage – V 75 TJ – Junction Temperature – °C TJ – Junction Temperature – °C 2.05 2 1.95 125 100 75 50 1.90 0 25 50 75 100 125 0 25 50 Figure 12 Figure 11 POST OFFICE BOX 655303 75 100 TJ – Junction Temperature – °C TJ – Junction Temperature – °C 14 50 • DALLAS, TEXAS 75265 125 TPS5615, TPS5618, TPS5625, TPS5633 SYNCHRONOUS-BUCK HYSTERETIC REGULATOR CONTROLLER SLVS177B – SEPTEMBER 1998 – REVISED JULY 2000 TYPICAL CHARACTERISTICS UVLO HYSTERESIS VOLTAGE (VCC) vs JUNCTION TEMPERATURE UVLO START THRESHOLD VOLTAGE VCC vs JUNCTION TEMPERATURE 2.5 UVLO Hysteresis Voltage ( VCC ) – V UVLO Start Threshold Voltage ( VCC ) – V 10.5 10 9.5 2.3 2.1 1.9 1.7 1.5 9 0 25 50 75 100 0 125 25 75 100 125 TJ – Junction Temperature – °C TJ – Junction Temperature – °C Figure 14 Figure 13 PWRGD THRESHOLD VOLTAGE vs JUNCTION TEMPERATURE QUIESCENT CURRENT VCC vs JUNCTION TEMPERATURE 95 PWRGD Threshold Voltage – % Vo 6 Quiescent Current ( VCC ) – mA 50 4 2 94 93 92 91 90 0 0 25 50 75 100 125 0 25 50 75 100 125 TJ – Junction Temperature – °C TJ – Junction Temperature – °C Figure 16 Figure 15 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 15 TPS5615, TPS5618, TPS5625, TPS5633 SYNCHRONOUS-BUCK HYSTERETIC REGULATOR CONTROLLER SLVS177B – SEPTEMBER 1998 – REVISED JULY 2000 TYPICAL CHARACTERISTICS VDS SAMPLE/HOLD RESISTANCE vs JUNCTION TEMPERATURE SLOWSTART CHARGE CURRENT vs JUNCTION TEMPERATURE 100 VDS Sample/Hold Resistance – Ω Slowstart Charge Current – µ A 15 14 13 12 11 75 50 25 0 10 0 25 50 75 100 0 125 25 50 Figure 18 Figure 17 DRIVE REGULATOR LOAD REGULATION vs JUNCTION TEMPERATURE DRIVE REGULATOR OUTPUT VOLTAGE vs JUNCTION TEMPERATURE 175 Drive Regulator Load Regulation – mV 8.5 Vo – Drive Regulator Output Voltage – V 125 TJ – Junction Temperature – °C TJ – Junction Temperature – °C 8.25 8 7.75 150 125 100 7.5 0 25 50 75 100 125 0 25 50 Figure 20 Figure 19 POST OFFICE BOX 655303 75 100 TJ – Junction Temperature – °C TJ – Junction Temperature – °C 16 100 75 • DALLAS, TEXAS 75265 125 TPS5615, TPS5618, TPS5625, TPS5633 SYNCHRONOUS-BUCK HYSTERETIC REGULATOR CONTROLLER SLVS177B – SEPTEMBER 1998 – REVISED JULY 2000 TYPICAL CHARACTERISTICS HIGH–SIDE DRIVER OUTPUT RESISTANCE vs JUNCTION TEMPERATURE DRIVE REGULATOR LINE REGULATION vs JUNCTION TEMPERATURE 5 High–Side Driver Output Resistance – Ω 150 125 4 3 2 1 0 100 0 25 50 75 100 0 125 25 50 75 100 125 TJ – Junction Temperature – °C TJ – Junction Temperature – °C Figure 22 Figure 21 LOW–SIDE DRIVER OUTPUT RESISTANCE vs JUNCTION TEMPERATURE 6 Low–Side Driver Output Resistance –Ω Drive Regulator Line Regulation – mV 175 5 4 3 2 1 0 0 25 50 75 100 125 TJ – Junction Temperature – °C Figure 23 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 17 TPS5615, TPS5618, TPS5625, TPS5633 SYNCHRONOUS-BUCK HYSTERETIC REGULATOR CONTROLLER SLVS177B – SEPTEMBER 1998 – REVISED JULY 2000 APPLICATION INFORMATION Synchronous rectifier buck regulator circuits are used where high efficiency and low dropout voltages are required. The TPS56xx controller is useful in applications with very high transient loads and wide dc load ranges, such as multiple-DSP applications. The circuit below will meet a wide variety of applications with maximum continuous-rated output currents of up to 8 A. Design tradeoffs, such as cost, size, or efficiency may need to be addressed for specific applications. Care should be taken in the proper layout (see last section of this data sheet for specific layout guidelines), especially in the higher-current configurations, to ensure that noise and ripple are kept to a minimum. Basic layout considerations are discussed in the 1996 Power Supply Circuits Databook (Literature no. SLVD002). Design guidelines and equations are discussed in Synchronous Buck Converter Design Using TPS56xx Controllers in SLVP10x EVMs User’s Guide (Literature no. SLVU007). 18 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TPS5615, TPS5618, TPS5625, TPS5633 SYNCHRONOUS-BUCK HYSTERETIC REGULATOR CONTROLLER SLVS177B – SEPTEMBER 1998 – REVISED JULY 2000 J1–6 J1–5 Vin RETURN J1–9 J1–10 J1–7 PG +12 V J1–8 R6 1.3 kΩ C1 22 µF 10 V C14 0.01 µF C12 0.1 µF R12 20.0 kΩ 1% U1 TPS5625 R9 100 Ω 1% C15 1000 pF R13 C16 0.1 µF C17 1 µF Analog GND J1–3 J1–1 R11 750 Ω SD R7 11.0 kΩ 1% PwrGND APPLICATION INFORMATION C11 1 µF R8 100 Ω 1% R1 1.0 kΩ 1 IOUT PWRGD 28 2 3 AGND2 OCP NC NC 27 26 4 VHYST NC 25 5 VREFB NC 24 6 7 VSENSE ANAGND NC INHIBIT 23 22 8 SLOWST 9 BIAS IOUTLO 21 LOSENSE 20 10 LODRV HISENSE 19 11 LOHIB BOOTLO 18 12 DRVGND HIGHDR 17 13 14 LOWDR DRV BOOT VCC 16 15 R2 10 kΩ C3 0.1 µF C2 0.1 µF C4 1 µF R17 1 MΩ C7 1 µF R4 10 Ω C18 0.1 µF R3 10 Ω Q2 Si4410 L1 2.2 µH Q1 Si4410 C5 2.2 µF R16 4.7 Ω Power GND C6 680 µF 6.3 V C8 0.01 µF R5 2.7 Ω L2 2.6 µH See Note A L1 = 10T #22 on T30–18 Core L2 = 12T #20 on T44–8Core C9 820 µF 4V C10 10 µF Not Used: R10, R13, R14 C13 J1–15 J1–16 J1–18 J1–17 2.5 V 8A J1–2 J1–4 VsenseH VsenseL/ AnaGND J1–11 J1–12 J1–14 PwrGND J1–13 R15 4.7 Ω NOTE A: Theses two traces should be physically close to each other for good noise immunity. Figure 24. Typical Design Schematic POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 19 TPS5615, TPS5618, TPS5625, TPS5633 SYNCHRONOUS-BUCK HYSTERETIC REGULATOR CONTROLLER SLVS177B – SEPTEMBER 1998 – REVISED JULY 2000 Table 1. Test Results for 2.5-V, 8-A Converter TEST Output voltage CONDITIONS QTY UNITS VIN = 5.25 V, VIN = 5.25 V, IO = 8 A IO = 0.8 to 8 A IO =6 A, VIN = 5.25 V, VCC = 4.5 V to 6 V IO = 8 A 0.2 % Ripple 50 mVpp Efficiency VIN = 5.25 V, IO = 8 A 89 % Load regulation Line regulation 2.50 V 0.4 % Table 2. 2.5-V, 8-A Converter Bill of Materials REF DES QTY DESCRIPTION MFG 1 10SS22M Capacitor, Os-Con, 22 µF, 10 V, 20% Sanyo C2 4 GRM39X7R104K016A Capacitor, Ceramic, 0.1 µF, 16 V, 10%, X7R muRata GRM39X7R104K016A Capacitor, Ceramic, 0.1 µF, 16 V, 10%, X7R muRata C3 C4 4 GRM42-6Y5V105Z016A Capacitor, Ceramic, 1 µF, 16 V, +80%–20% muRata C5 1 GRM42-6Y5V225Z016A Capacitor, Os-Con, 2.2 µF, 16 V, Y5U muRata C6 1 6SP680M Capacitor, Os-Con, 680 µF, 6.3 V, 20% Sanyo GRM42-6Y5V105Z016A Capacitor, Ceramic, 1 µF, 16 V, +80%–20% muRata C8 2 GRM39X7R103K025A Capacitor, Ceramic, 0.01 µF, 25 V, 10%, X7R muRata C9 1 4SP820M Capacitor, Os-Con, 820 µF, 4 V, 20% Sanyo C10 1 C7 GRM235Y5V106Z016A Capacitor, Ceramic, 10 µF, 16 V, Y5V muRata C11 GRM42-6Y5V105Z016A Capacitor, Ceramic, 1 µF, 16 V, +80%–20% muRata C12 GRM39X7R104K016A Capacitor, Ceramic, 0.1 µF, 16 V, 10%, X7R muRata C14 GRM39X7R103K025A Capacitor, Ceramic, 0.01 µF, 25 V, 10%, X7R muRata GRM39X7R102K050A Capacitor, Ceramic, 1000 pF, 50 V, 10%, X7R muRata C16 GRM39X7R104K016A Capacitor, Ceramic, 0.1 µF, 16 V, 10%, X7R muRata C17 GRM42-6Y5V105Z016A Capacitor, Ceramic, 1 µF, 16 V, +80%–20% muRata GRM39X7R104K016A Capacitor, Ceramic, 0.1 µF, 16 V, 10%, X7R muRata S1122-18-ND Header, RA, 18-pin, 0.23 Posts × 0.20 Tails Sullins C15 1 C18 J1 1 L1 1 L2 1 Q1 2 Q2 Inductor, Filter, 2.2 µH, 8.5 A (10T #22 on T30-18 Core) Inductor, Filter, 2.6 µH, 8.5 A (12T #20 on T44-8 Core) Si4410DY FET, N-ch, 30-V, 10-A, 13-mΩ Siliconix Si4410DY FET, N-ch, 30-V, 10-A, 13-mΩ Siliconix R1 3 Std Resistor, Chip, 1.0 kΩ, 1/16W, 5% R2 1 Std Resistor, Chip, 10 kΩ, 1/16W, 5% R3 2 Std Resistor, Chip, 10 Ω, 1/10W, 5% Std Resistor, Chip, 10 Ω, 1/10W, 5% Std Resistor, Chip, 2.7 Ω, 1/4W, 5% R4 R5 1 R6 Std Resistor, Chip, 1.3 kΩ, 1/16W, 5% R7 1 Std Resistor, Chip, 11.0 kΩ, 1/16W, 1% R8 2 Std Resistor, Chip, 100 Ω, 1/16W, 1% Std Resistor, Chip, 100 Ω, 1/16W, 1% R9 Std Resistor, Chip, 750 Ω, 1/16W, 5% R12 1 Std Resistor, Chip, 20.0 kΩ, 1/16W, 1% R15 2 Std Resistor, Chip, 4.7 Ω, 1/16W, 5% R11 Std Resistor, Chip, 4.7 Ω, 1/16W, 5% R17 1 Std Resistor, Chip, 1 MΩ, 1/16W, 5% U1 1 TPS5625PWP IC, PWM Ripple Controller, FIxed 2.5 V R16 20 PART NUMBER C1 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TI TPS5615, TPS5618, TPS5625, TPS5633 SYNCHRONOUS-BUCK HYSTERETIC REGULATOR CONTROLLER SLVS177B – SEPTEMBER 1998 – REVISED JULY 2000 APPLICATION INFORMATION EFFICIENCY vs OUTPUT CURRENT 100 Efficiency – % 95 90 85 80 0 1 2 3 4 5 6 7 8 Output Current – A Figure 25 Top: Vo 10 mV/div Bottom: VDS Q2 5 V/div 2 µs/div Figure 26. Output Voltage Ripple at 8 A POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 21 TPS5615, TPS5618, TPS5625, TPS5633 SYNCHRONOUS-BUCK HYSTERETIC REGULATOR CONTROLLER SLVS177B – SEPTEMBER 1998 – REVISED JULY 2000 APPLICATION INFORMATION 20 µs/div IO 2.5 A/div VO 20 mV/div Figure 27. Rising Load Transient Response IO 2.5 A/div 20 µs/div VO 20 mV/div Figure 28. Falling Load Transient Response 22 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TPS5615, TPS5618, TPS5625, TPS5633 SYNCHRONOUS-BUCK HYSTERETIC REGULATOR CONTROLLER SLVS177B – SEPTEMBER 1998 – REVISED JULY 2000 APPLICATION INFORMATION layout guidelines Good power supply results will only occur when care is given to proper design and layout. Layout will affect noise pickup and generation and can cause a good design to perform with less than expected results. With a range of currents from milliamps to tens or even hundreds of amps, good power supply layout is much more difficult than most general PCB design. The general design should proceed from the switching node to the output, then back to the driver section and, finally, place the low-level components. Below are several specific points to consider before layout of a TPS56xx design begins. 1. All sensitive analog components should be referenced to ANAGND. These include components connected to SLOWST, IOUT, OCP, VSENSE, VREFB, VHYST, BIAS, and LOHIB. 2. Analog ground and drive ground should be isolated as much as possible. Ideally, analog ground will connect to the ground side of the bulk storage capacitors, on VO, and drive ground will connect to the main ground plane close to the source of the low-side FET. 3. Connections from the drivers to the gate of the power FETs should be as short and wide as possible to reduce stray inductance. This becomes more critical if external gate resistors are not being used. 4. The bypass capacitor for the DRV regulator should be placed close to the TPS56xx and be connected to DRVGND. 5. The bypass capacitor for VCC should be placed close to the TPS56xx and be connected to DRVGND. 6. When configuring the high-side driver as a floating driver, the connection from BOOTLO to the power FETs should be as short and as wide as possible. The other pins that also connect to the power FETs, LOHIB and LOSENSE, should have a separate connection to the FETs, since BOOTLO will have large peak currents flowing through it. 7. When configuring the high-side driver as a floating driver, the bootstrap capacitor (connected from BOOT to BOOTLO) should be placed close to the TPS56xx. 8. When configuring the high-side driver as a ground referenced driver, BOOTLO should be connected to DRVGND. 9. The bulk storage capacitors across VI should be placed close to the power FETs. High-frequency bypass capacitors should be placed in parallel with the bulk capacitors and connected close to the drain of the high-side FET and close to the source of the low-side FET. 10. High-frequency bypass capacitors should be placed across the bulk storage capacitors on VO. 11. HISENSE and LOSENSE should be connected very close to the drain and source, respectively, of the high-side FET. HISENSE and LOSENSE should be routed very close to each other to minimize differential-mode noise coupling to these traces. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 23 MECHANICAL DATA MHTS001D – JANUARY 1995 – REVISED MAY 1999 MECHANICAL DATA PWP (R-PDSO-G**) PowerPAD PLASTIC SMALL-OUTLINE 20 PINS SHOWN 0,30 0,19 0,65 20 0,10 M 11 Thermal Pad (See Note D) 4,50 4,30 0,15 NOM 6,60 6,20 Gage Plane 1 10 0,25 A 0°– 8° 0,75 0,50 Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,10 14 16 20 24 28 A MAX 5,10 5,10 6,60 7,90 9,80 A MIN 4,90 4,90 6,40 7,70 9,60 DIM 4073225/F 10/98 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusions. The package thermal performance may be enhanced by bonding the thermal pad to an external thermal plane. This pad is electrically and thermally connected to the backside of the die and possibly selected leads. E. Falls within JEDEC MO-153 PowerPAD is a trademark of Texas Instruments Incorporated. 24 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PACKAGE OPTION ADDENDUM www.ti.com 30-Mar-2005 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty Lead/Ball Finish MSL Peak Temp (3) TPS5615PWP ACTIVE HTSSOP PWP 28 50 TBD CU NIPDAU Level-1-220C-UNLIM TPS5615PWPR ACTIVE HTSSOP PWP 28 2000 TBD CU NIPDAU Level-1-220C-UNLIM TPS5618PWP ACTIVE HTSSOP PWP 28 50 TBD CU NIPDAU Level-1-220C-UNLIM TPS5618PWPR ACTIVE HTSSOP PWP 28 2000 TBD CU NIPDAU Level-1-220C-UNLIM TPS5625PWP ACTIVE HTSSOP PWP 28 50 TBD CU NIPDAU Level-1-220C-UNLIM TPS5625PWPR ACTIVE HTSSOP PWP 28 2000 TBD CU NIPDAU Level-1-220C-UNLIM TPS5633PWP ACTIVE HTSSOP PWP 28 50 TBD CU NIPDAU Level-1-220C-UNLIM TPS5633PWPR ACTIVE HTSSOP PWP 28 2000 TBD CU NIPDAU Level-1-220C-UNLIM (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. 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