TI TPS5300

TPS5300
8,1 mm x 11 mm
SLVS334A – DECEMBER 2000 – REVISED SEPTEMBER 2001
MOBILE CPU POWER SUPPLY CONTROLLER
FEATURES
D Power Stage Input Voltage Range of 3 V to
D
D
D
D
D
D
D
D
D
D
28 V
Single-Chip Dynamic Output Voltage
Transition Solution
Hysteretic Controller Provides Fast Transient
Response Time and Reduced Output
Capacitance
Two Linear Regulator Controllers Regulating
Clock and I/O Voltages
Internal 2-A (Typ) Gate Drivers With Bootstrap
Diode For Increased Efficiency
5-Bit Dynamic VID
Active Droop Compensation Enables Tight
Dynamic Regulation for Reduced Output
Capacitance
VGATE Terminal Provides Power-Good Signal
for All Three Outputs
Enable External Terminal (ENABLE_EXT)
32-Pin TSSOP PowerPAD Enhances Thermal
Performance
1% Reference Voltage Accuracy
technology. The TPS5300 provides a precise,
programmable supply voltage to a mobile processor or
other processor power applications. A ripple regulator
provides the core voltage, while two linear regulator
drivers regulate external NPN power transistors for the
I/O and CLK voltages. A 5-bit voltage identification
(VID) DAC allows programming for the ripple regulator
voltage to values between 0.925 V to 1.275 V in 25-mV
steps and 1.3 V to 2 V in 50-mV steps. Other voltage
ranges and steps can be easily set. The fast transient
response time and active voltage DROOP positioning
reduce the number of output capacitors required to
keep the output voltage within tight dynamic voltage
regulation limits. The power saving mode (PSM) allows
the user to select a single operating ramp or allows the
controller to automatically switch to lower frequencies
at low loads. The high-gain current sense differential
amplifier allows the use of small-value sense resistors
that minimize conduction losses.
VI = 12 V
APPLICATIONS
D Intel Mobile CPUs With SpeedStep
Technology
D AMD Mobile CPUs With PowerNow!
D
D
Technology
DSP Processors
Other One, Two, or Three Output
Point-of-Load Applications
DESCRIPTION
The TPS5300 is a hysteretic synchronous-buck
controller, with two on-chip linear regulator controllers,
incorporating dynamic output voltage positioning
Output Voltage Transient Load Response
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Speed Step is a trademark of Intel Corp.
PowerNow is a trademark of Advanced Micro Devices Inc.
PowerPAD is a trademark of Texas Instruments.
Copyright  2001, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
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1
TPS5300
SLVS334A – DECEMBER 2000 – REVISED SEPTEMBER 2001
description (continued)
The TPS5300 includes high-side and low-side gate drivers rated at 2 A typical, that enable efficient operation
at higher frequencies and drive larger or multiple power MOSFETs (such as 50-A output current applications).
An adaptive dead-time circuit minimizes dead-time losses while preventing cross-conduction of high-side and
low-side switches. All three outputs power up together as they track the same user programmable slowstart
voltage. The enable external (ENABLE_EXT) terminal allows the TPS5300 to activate external switching
controllers for additional system power requirements.
The TPS5300 features VCC undervoltage lockout, output overvoltage protection, output undervoltage
protection, and user-programmable overcurrent protection, and is packaged in a small 32-pin TSSOP
PowerPAD package.
pin assignments
TSSOP PACKAGE
(TOP VIEW)
DRV_CLK
VSENSE_CLK
DT_SET
ANAGND
VSENSE_CORE
SLOWST
VREFB
VHYST
OCP
DROOP
IOUT
PSM/LATCH
IS–
IS+
VGATE
DRVGND
2
1
32
2
31
3
30
4
29
5
28
6
27
7
26
8 THERMAL 25
9
24
PAD
10
23
11
22
12
21
13
20
14
19
15
18
16
17
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DRV_IO
VSENSE_IO
VBIAS
ENABLE_EXT
RAMP
VID0
VID1
VID2
VID3
VID4
VR_ON
BOOT
TG
PH
VCC
BG
TPS5300
SLVS334A – DECEMBER 2000 – REVISED SEPTEMBER 2001
absolute maximum ratings over operating free-air temperature (unless otherwise noted)†
Supply voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
Input voltage, VI: VBIAS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
VR_ON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 V
VID0, VID1, VID2, VID3, VID4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 V
PSM/LATCH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 V
IS–, IS+ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 V
RAMP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 V
VSENSE_CORE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 V
VSENSE_IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 V
VSENSE_CLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 V
All other input terminals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
BOOT to DRVGND voltage (high-side driver on) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 V
BOOT to PH voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
BOOT to TG voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
PH to DRVGND voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –1 V to 35 V
ANAGND to DRVGND voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±1 V
Output voltage, VO: VGATE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 V
ENABLE_EXT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 V
Continuous power dissipation, PD: Without PowerPad soldered, TA = 25°C, TJ = 125°C . . . . . . . . . . . . . . . . 1.2 W
With PowerPad soldered, TC = 25°C, TJ = 125°C . . . . . . . . . . . . . . . . . . 6.25 W
Operating junction temperature, TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 125°C
Storage temperature, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C
Lead temperature, T(lead) (soldering, 10 seconds) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
DISSIPATION RATING TABLE
PWP
PowerPAD mounted
PowerPAD unmounted
TA < 25°C
3.58 W
Derating Factor‡
0.0358 W/°C
TA = 70°C
1.96 W
TA = 85°C
1.43 W
1.78 W
0.0178 W/°C
0.98 W
0.71 W
JUNCTION-CASE THERMAL RESISTANCE TABLE
Junction-case thermal resistance
‡ Test Board Conditions:
0.72 °C/W
1. Thickness: 0.062”
2. 3” x 3” (for packages < 27 mm long)
3. 4” x 4” (for packages > 27 mm long)
4. 2 oz. Copper traces located on the top of the board (0,071 mm thick )
5. Copper areas located on the top and bottom of the PCB for soldering
6. Power and ground planes, 1 oz. Copper (0,036 mm thick)
7. Thermal vias, 0,33 mm diameter, 1,5 mm pitch
8. Thermal isolation of power plane
For more information, refer to TI technical brief SLMA002.
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3
VSENSE_CLK
2
DRV_IO
32
VSENSE_IO
31
ENABLE_EXT
V_GATE
29
OCP
15
DROOP
IOUT
9
11
10
Protection Circuitry
Vss is dominant
if Vss<Vref CLK
VR_ON
22
UVLO
Vss
UVLO
is HIGH if
VR_ON > 2.5V
and
Vcc > 4.46V
13
Vref CLK
x 25
Shutdown
Vss is dominant
if Vss<Vref IO
PWRGD
Vss
OCP_OVP
is HIGH if
OCP Core > 300mV
OCP_OVP or Vsense Core
or Vsense IO
or Vsense CLK
> 1.15 of their Vref
PWRGD
is LOW if
Vsense Core
or Vsense IO
or Vsense CLK
> 0.93 of their
Vref
14
30
BIAS
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Vcc
Shutdown
Clock and IO
ShutdownB
Q
S
Q
R
Drivers
VCC(+5V)
18
UVP
is HIGH if
Vss > Vref CLK,
and
Vsense IO
or Vsense CLK
< 0.75 of their
Vref
UVP
Regulator
Latch
disabled
Vbatt
20
Regulator
+
VID1 26
17
Vss
Vcc
Bandgap
19
Vss is dominant if
Vss<Vref
Vref
_
Controller
VID0 27
16
Vref
TG
PH
Vout
BG
DRVGND
Vss
and DAC
Power
Save
VID4 23
3
7
DT_SET
VREFB
8
VHYST
6
5
SLOWST
Vcc (5V)
BOOT
21
Core Voltage
VID3 24
IS+
Vbias
Vref IO
VID2 25
IS–
Hyst.
Mode
Set
Control
12
VSENSE_CORE PSM/LATCH
4
28
RAMP
ANAGND
TPS5300
DRV_CLK
1
SLVS334A – DECEMBER 2000 – REVISED SEPTEMBER 2001
functional schematic
4
Vout IO: 1.5V
Vin 3.3/5V
Vout CLK: 2.5V
Vin 3.3/5V
TPS5300
SLVS334A – DECEMBER 2000 – REVISED SEPTEMBER 2001
recommended operating conditions, 0 < TJ < 125°C (unless otherwise noted)
Supply voltage, Vbatt
Linear regulator supply voltage, VI(IO+CLK)
Supply voltage range, VCC, VBIAS
MIN
NOM
MAX
3
12.5
28
UNIT
V
3
3.3
6
V
4.5
5
6
V
dc and ac electrical characteristics over recommended operating free-air temperature range,
0 < TJ < 125°C, VIN = 3 V – 28 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Reference/Voltage Identification
VIH(VID)
VIL(VID)
High-level input voltage, D0–D4
Current source pullup to VCC
2.25
V
Low-level input voltage, D0–D4
1
V
Cumulative Reference (see Note 1)
0.925 V ≤ Vref(core) ≤ 2 V,
Hysteresis window = 30 mV (see Note 2)
V(CUM_ACCRR)
Initial accuracy ripple regulator
0.925 V ≤ Vref(core) ≤ 2 V, TJ = 25°C
Hysteresis window = 30 mV
–1.5%
1.5%
–1%
1%
–2.5%
2.5%
Buffered Reference
VO(VREFB)
Output voltage, VREFB
Hysteretic Comparator (core)
tPHL(HC)
Propagation delay time from (AC)
VSENSE_CORE to TG or BG
(excluding deadtime)
tPHL(HC_ramp)
I(VREFB) = 50 µA (see Note 2)
20-mV overdrive, pulse
0.925 V ≤ Vref ≤ 2 V (see Note 2)
220
Ramp circuit from 0 into 26 mV ramp
(see Note 2)
220
250
ns
ns
Overcurrent Protection (core)
Normal operation
V(OCP)
Trip point,
point OCP
235
During dynamic VID change
300
365
mV
400
Overvoltage Protection (core, IO, CLK)
V(OVP)
Trip point, OVP
Undervoltage Protection (IO, CLK)
Upper threshold
V(UVP)
Trip point, UVP
Bias UVLO (Resets fault latch)
Lower threshold
VIT(start_UVLO)
VIT(stop_UVLO)
Start threshold
Vhys
Hysteresis
115
119
75
3.3
VR_ON connected to GND and VI above
UVLO start threshold
%Vref
%Vref
4.46
Stop threshold
VBIAS quiescent current, I(ving1)
111
V
V
500
mV
20
µA
VR_ON UVLO (Resets fault latch)
VIT(start_VR_ON)
VIT(stop_VR_ON)
Start threshold
2.5
Stop threshold
1.3
V
V
Vhys
Hysteresis
475
mV
NOTES: 1. Cumulative reference accuracy is the combined accuracy of the reference voltage and the input offset voltage of the hysteretic
comparator. Cumulative accuracy equals to the average of the low-level and high-level thresholds of the hysteretic comparator.
2. Ensured by design, not production tested.
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5
TPS5300
SLVS334A – DECEMBER 2000 – REVISED SEPTEMBER 2001
electrical characteristics over recommended operating free-air temperature range, 0 < TJ < 125°C,
VIN = 3 V – 28 V (unless otherwise noted) (continued)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
10.4
13
15.6
µA
Slowstart
I(chg)
Charge current (I(chg) = (I(REFB)/5)
V(SS) = 0.5 V,
I(VREFB) = 65 µA VREFB = 1.35 V,
I(chg) = (I(VREFB)/5)
I(dischg)
Discharge current
V(SS) = 1.35 V,
Design for VIN(min) = 4.5 V
3
mA
VGATE (CORE, IO, CLK) (PWRGD of three outputs with open drain output)
V(VGATE)
Undervoltage trip point
(VSENSE_CORE, VSENSE_IO, and
VSENSE_CLK)
VIN and V(drv) above UVLO thresholds
85
90
95
VO(VGATE)
Output saturation voltage
IO = 2.5 mA
Enable EXT (SHUTDOWN of IC with open-drain output. Use pullup resistor to 5 V or 3.3 V)
0.5
0.75
V
VO(EN_EXT)
Output saturation voltage
DROOP Compensation
0.5
0.75
V
IO = 2.5 mA
Maximum output CMR
200
%Vref
mV
Propagation delay
15-mV to 150-mV swing,
0.925 V ≤ Vref ≤ 2 V, VCC = 5 V
(see Note 2)
Gain
See Note 2
25
V/V
VO(SO)
Output systematic offset
V(IS+) – V(IS–) = 1 mV,
1 mV input (see Note 2)
26
mV
VO(RO)
VOM
Output random offset
See Note 2
±15
mV
1.75
V
tPHL(HC)
200
500
ns
Current Sensing
G(CS)
t(VDSRESP)
Maximum output voltage swing
Response time (measured from 50% of
(V(IS+) – V(IS–)) to 50% of V(IOUT)
V(IS–) = 0.925 V – 2 V, V(IS+) is pulsed
from V(IS–) to (V(IS–) + 50 mV),
VCC = 5 V (see Note 2)
500
ns
2.3
V
PSM/LATCH Power Saving Mode (PSM Comparator)
V(startINH)
V(stopINH)
PSM comparator start threshold
Vhys(INH)
V(PSMth1)
Hysteresis
V(PSMth2)
V(PSMth3)
V(PSMth4)
Vhys(PSM)
OCP voltage trip points for PSM
R(tPSM3)
1.8
PSM ramp timing resistance
V
100
OCP↑
mV
90
120
150
30
60
90
Hysteresis
R(tPSM1)
R(tPSM2)
2.1
PSM comparator stop threshold
10
mV
mV
PH to CT, PSM = GND,
V(OCP) = 150 mV (see Note 3)
8
10
12
PH to CT, PSM = GND,
V(OCP) = 85 mV (see Note 3)
16
20
24
PH to CT, PSM = GND,
V(OCP) = 15 mV (see Note 3)
1
kΩ
MΩ
NOTES: 2. Ensured by design, not production tested.
3. The VBIAS voltage is required to be a quiet bias supply for the TPS5300 control logic. External noisy loads should use VCC instead
of the VBIAS voltage.
6
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TPS5300
SLVS334A – DECEMBER 2000 – REVISED SEPTEMBER 2001
electrical characteristics over recommended operating free-air temperature range, 0 < TJ < 125°C,
VIN = 3 V – 28 V (see test circuits) (unless otherwise noted) (continued)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
PSM/LATCH Fault Latch Disable
V(No_Latch/PSM)
Disable latch threshold
PSM enabled
V(No_Latch)
Disable latch threshold
PSM disabled
VBIAS + 0.7
V(Latch_enabled) Enable latch threshold
Thermal Shutdown
T(OTP)
Over temperature trip
point
T(hyst)
Hysteresis
Dynamic VID Change (No current limit)
Ι∆tSRC/SNK
Voltage change timing
current
V
ANAGND
ANAGND – 0.7
V
VBIAS
V
See Note 2
155
°C
See Note 2
25
°C
VCC = 5 V, V(ref1) = 1.35 V,
DT_SET = 0.925 VSRC/VSNK
14
µA
1.2
2
A
1.2
3.3
A
1.4
2
A
1.3
3.3
A
2.5
Ω
V(BOOT) – V(PH) = 4.5 V, V(TG) = 0.5 V
1.5
Ω
VCC = 4.5 V, V(BG) = 4 V
2.5
Ω
VCC = 4.5 V, V(BG) = 0.5 V
1.5
Ω
Cl = 3.3 nF, V(BOOT) = 4.5 V,
V(PH) = GND
10
ns
Cl = 3
3.3
3 nF
nF, VCC = 4.5
45V
10
ns
Output Drivers (see Note 4)
Duty cycle < 2%, tpw < 100 µs,
V(BOOT) – V(PH) = 4.5 V,
V(TG) – V(PH) = 0.5 V (src)
IO(src_TG)
IO(sink_TG)
Peak output current (see
Notes 2 and 4)
IO(src_BG)
Duty cycle < 2%, tpw < 100 µs,
VCC = 4.5 V, V(BG) = 4 V (src)
V(BOOT) – V(PH) = 4.5 V, V(TG) = 4 V
IO(sink_BG)
ro(src_TG)
ro(sink_TG)
ro(src_BG)
Duty cycle < 2%, tpw < 100 µs,
V(BOOT) – V(PH) = 4.5 V,
V(TG) – V(PH) = 4 V (sink)
Duty cycle < 2%, tpw < 100 µs,
VCC = 4.5 V, V(BG) = 0.5 V (src)
Out ut resistance (see
Output
Note 4)
ro(sink_BG)
tf(TG)
TG fall time (AC) (see
Note 5)
tr(TG)
TG rise time (AC) (see
Note 5)
tf(BG)
BG fall time (AC) (see
Note 5)
tr(BG)
BG rise time (AC) (see
Note 5)
High-Side Driver Quiescent Current
IQ(highdrq1)
Highdrive (TG)
quiescent current
VR_ON grounded, or VCC below UVLO
threshold; V(BOOT) = 5 V,
PH grounded (see Note 2)
2
µA
NOTES: 2. Ensured by design, not production tested.
4. The pulldown (sink) circuit of the high-side driver is a MOSFET transistor referenced to DRVGND. The driver circuits are bipolar
and MOSFET transistors in parallel. The peak output current rating is the combined current rating from the bipolar and MOSFET
transistors. The output resistance is the rds(on) of the MOSFET transistor when the voltage on the driver output is less than the
saturation voltage of the bipolar transistor.
5. Rise and fall times are measured from 10% to 90% of pulsed values.
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7
TPS5300
SLVS334A – DECEMBER 2000 – REVISED SEPTEMBER 2001
electrical characteristics over recommended operating free-air temperature range, 0 < TJ < 125°C,
VIN = 3 V – 28 V (see test circuits) (unless otherwise noted) (continued)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Adaptive Deadtime Circuit
VIH(TG)
VIL(TG)
TG – PH High-level input voltage
VIH(BG)
VIL(BG)
BG High-level input voltage
t(NUL)
TG – PH Low-level input voltage
BG Low-level input voltage
Driver nonoverlap time (AC)
V(IS–) = 0.925 V – 2 V (see Note 2)
V(IS–) = 0.925 V – 2 V (see Note 2)
2.4
V(IS–) = 0.925 V – 2 V (see Note 2)
V(IS–) = 0.925 V – 2 V (see Note 2)
3
V
1.33
V
V
CBG = 9 nF, 10% threshold on BG,
VCC = 5 V (see Note 2)
1.7
V
50
ns
Linear Regulator OUTPUT DRIVERs (IO, CLK) (see Note 4)
IO(src_LDODR_IO)
Peak out
output
ut current linear regula
regulator driver IO
IO(sink_LDODR_IO)
VCC = 5 V,
VSENSE_IO = 0.9 × V(REF_IO)
(see Note 2)
134
mA
VCC = 5 V,
VSENSE_IO = 1.1 × V(REF_IO)
(see Note 2)
14
µA
V(CUM_ACC_IO)
Initial accuracy IO condition:
closed loop; linear regulator
VCC = 5 V, Vref = 1.5 V, IO = 134 mA
V(CC_Line_Reg_IO)
VIN line regulation IO
5.5 V ≥ VCC ≥ 4.5 V,
3 V ≤ VIN (IO) ≤ 6 V, (see Note 2)
IO(src_LDODR_CLK)
Peak out
output
ut current regulator, drivdriv
er CLK
IO(sink_LDODR_CLK)
–1.7%
1.7%
5
mV
VCC = 5 V,
VSENSE_IO = 0.9 × VO(REF_IO)
(see Note 2)
10
mA
VCC = 5 V,
VSENSE_IO = 1.1 × VO(REF_IO)
(see Note 2)
14
µA
V(CUM_ACCCLK)
Initial accuracy CLK condition:
closed loop
VCC = 5 V, Vref = 2.5 V, IO = 10 mA
VCC(LineReg_CLK)
Line regulation CLK
5.5 V ≥ VCC ≥ 4.5 V,
3 V ≤ VIN (CLK) ≤ 6 V, (see Note 2)
–1.55%
1.55%
5
mV
NOTES: 2. Ensured by design, not production tested.
4. The pulldown (sink) circuit of the high-side driver is a MOSFET transistor referenced to DRVGND. The driver circuits are bipolar
and MOSFET transistors in parallel. The peak output current rating is the combined current rating from the bipolar and MOSFET
transistors. The output resistance is the rds(on) of the MOSFET transistor when the voltage on the driver output is less than the
saturation voltage of the bipolar transistor.
8
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TPS5300
SLVS334A – DECEMBER 2000 – REVISED SEPTEMBER 2001
Terminal Functions
TERMINAL
NAME
NO.
I/O
DESCRIPTION
ANAGND
4
Analog ground
BG
17
O
Bottom gate drive. BG is an output drive to the low-side synchronous rectifier FET.
BOOT
21
I
Bootstrap. Connect a 1-µF low-ESR ceramic capacitor to PH to generate a floating drive for the high-side
FET driver.
DROOP
10
I
DRV_CLK
1
O
Active voltage droop position voltage. DROOP is a voltage input used to set the amount of output-voltage,
set-point droop as a function of load current. The amount of droop compensation is set with a resistor divider
between IOUT and ANAGND. A voltage divider from VO to VSENSE_CORE sets the no-load offset.
CLK voltage regulator. DRV_CLK drives an external NPN bipolar power transistor for regulating CLK
voltage to VREF_CLK.
DRVGND
16
DRV_IO
32
O
Drives an external NPN bipolar power transistor for regulating IO voltage to VREF_IO.
DT_SET
3
I
DT_SET sets the transition time for speed step output voltage positioning. Attach a capacitor from DT_SET
to ground to program time.
ENABLE_EXT
29
O
Open drain output. ENABLE_EXT enables the external converters when the internal enable signal is high
(good), and disables when there is a fault with any regulator (OVP, UVP, OCPrr), VR_ON UVLO is low, or the
VBIAS UVLO is low. Can be connected to the enable terminal of an external linear regulator or switching
controller. A pullup resistor is required to set the desired voltage rail.
IS–
13
I
Current sense negative Kelvin connection. Connect to the node between the current sense resistor and the
output capacitors. Keep the PCB trace short and route trace next to the IS+ trace to help reduce loop
inductance noise pickup and cancel common mode noise through mutual coupling.
IS+
14
I
Current sense positive Kelvin connection. Connect to the node between the output inductor and the current
sense resistor. Keep the PCB trace short and route trace next to the IS-trace to help reduce loop inductance
noise and cancel common mode noise through mutual coupling.
IOUT
11
O
Current sense differential amplifier output. The voltage on IOUT equals
25 x (VI(+) – VI(–)) = 25 x (R(sense) x IL).
OCP
9
I
Overcurrent protection. Current limit trip point is set with a resistor divider between IOUT and ANAGND. The
typical OCP trip point should be set at 1.30 × I(max). The OCP voltage also sets the PSM automatic trip points.
PH
19
I/O
Phase voltage node. PH is used for bootstrap low reference. PH connects to the junction of the high-side and
low-side FET’s.
PSM/LATCH
12
I
PSM. Power saving mode boosts efficiency at low-load current by automatically decreasing the switching
frequency toward the natural converter operating frequency. A logic low (<1.8) disables PSM, maintaining
the higher switching frequency range set by ramp components. See Figure 1.
RAMP
28
I/O
Sets a ramp on the feedback signal to increase the switching frequency. Add a resistor from PH to RAMP and
connect RAMP to VSENSE_CORE for a dc-coupled ramp. Add a capacitor from RAMP to VSENSE_CORE
to set an ac-coupled ramp.
SLOWST
6
I
TG
20
O
Slowstart (softstart). A capacitor from SLOWST to GND sets the slowstart time for the ripple regulator and
the two linear regulators. The three converters will ramp up together while tracking the output voltage. A
current equal to I(VREFB)/5 charges the capacitor.
Top gate drive. TG is an output drive to the high-side power switching FET’s. It is also used in the
anticross-conduction circuit to eliminate shoot-through current.
VBIAS
30
I
VCC
18
VGATE
15
Drive ground. Ground for FET drivers. Connect to FET PWRGND
LATCH. Allows disabling fault latch. Recommend enabling fault latch protection
Analog VBIAS. It is recommended that at least a 1-µF capacitor be connected to ANAGND. Supply from VCC
through RC filter
Supply voltage. VCC is the supply voltage for the FET drivers. Add an external resistor/capacitor filter from
VCC to VBIAS. It is recommended that a 1-µF capacitor be connected to the DRVGND terminal.
O
Logical and output of the combined core, IO, and CLK powergood. VGATE outputs a logic high when all
(core, IO, CLK) output voltages are within 7% of the reference voltage. An open drain output allows setting to
desired voltage level through a pullup resistor.
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9
TPS5300
SLVS334A – DECEMBER 2000 – REVISED SEPTEMBER 2001
Terminal Functions (Continued)
TERMINAL
NAME
NO.
I/O
DESCRIPTION
Ripple regulator hysteresis set terminal. The hysteresis is set with a resistor divider from VREFB to ANGND.
The hysteresis voltage window will be ± the voltage between VREFB and VHYST.
VHYST
8
I
VID0
27
I
VID1
26
I
VID2
25
I
VID3
24
I
VID4
23
I
VREFB
7
O
Buffered ripple regulator reference voltage from VID network
VR_ON
22
I
Enables the drive signals to the MOSFET drivers. The comparator input can be used to monitor voltage,
such as the linear regulators’ input supply using a resistor divider.
VSENSE_CLK
2
I
CLK feedback voltage sense. Connect to CLK linear regulator output voltage to regulate.
VSENSE_CORE
5
I
Feedback voltage sense input for the core. Connect to ripple regulator output voltage to sense and regulate
output voltage. It is recommended that an RC low-pass filter be connected at this pin to filter high-frequency
noise.
VSENSE_IO
31
I
I/O feedback voltage sense. Connect to I/O linear regulator output voltage to regulate.
Voltage identification in
inputs
uts 0, 1, 2, 3, and 4. These terminals are digital inputs
in uts that set the output
out ut voltage of
the converter. The code pattern
attern for setting the out
output
ut voltage is located in the terminal functions table. These
terminals are internally pulled up to VBIAS.
detailed description
reference/voltage identification
The reference /voltage programming (VP) section consists of a temperature-compensated, bandgap reference
and a 5-bit voltage selection network. The five VID pins are inputs to the VID selection network and are TTL
compatible inputs that are internally pulled up to VCC with pullup resistors. The internal reference voltage can
be programmed from 0.925 V to 2 V with the VID pins. The VID codes are listed in Table 1. The output voltage
of the VP network, Vref, is within ±1.5% of the nominal setting. The ±1.5% tolerance is over the full VP range
of 0.925 V to 2 V, and includes a junction temperature range of 0°C to 125°C, and a VCC range of 4.5 V to 5.5 V.
The output of the reference/VP network is indirectly brought out through a buffer to the VREFB pin. The voltage
on this pin will be within ±5 mV of Vref. It is not recommended to drive loads with VREFB, other than setting the
hysteresis of the hysteretic comparator, because the current drawn from VREFB sets the charging current for
the slowstart capacitor. Refer to the slowstart section for additional information.
10
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TPS5300
SLVS334A – DECEMBER 2000 – REVISED SEPTEMBER 2001
detailed description (continued)
Table 1. Voltage Programming Code
VID PINS
0 = GROUND, 1 = FLOATING, OR PULLUP TO 5 V
Vref
VID4
VID3
VID2
VID1
VID0
(Vdc)
1
1
1
1
1
No CPU – Off
1
1
1
1
0
0.925
1
1
1
0
1
0.950
1
1
1
0
0
0.975
1
1
0
1
1
1.000
1
1
0
1
0
1.025
1
1
0
0
1
1.050
1
1
0
0
0
1.075
1
0
1
1
1
1.100
1
0
1
1
0
1.125
1
0
1
0
1
1.150
1
0
1
0
0
1.175
1
0
0
1
1
1.200
1
0
0
1
0
1.225
1
0
0
0
1
1.250
1
0
0
0
0
1.275
0
1
1
1
1
No CPU – Off
0
1
1
1
0
1.300
0
1
1
0
1
1.350
0
1
1
0
0
1.400
0
1
0
1
1
1.450
0
1
0
1
0
1.500
0
1
0
0
1
1.550
0
1
0
0
0
1.600
0
0
1
1
1
1.650
0
0
1
1
0
1.700
0
0
1
0
1
1.750
0
0
1
0
0
1.800
0
0
0
1
1
1.850
0
0
0
1
0
1.900
0
0
0
0
1
1.950
0
0
0
0
0
2.000
NOTE: If the VID bits are set to 11111 or 01111, then the high-side and low-side driver outputs
will be set low.
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11
TPS5300
SLVS334A – DECEMBER 2000 – REVISED SEPTEMBER 2001
detailed description (continued)
dynamic VID change
Dynamic VID change controls the rate of change of the programmed VID to allow transitioning within 100 µs,
while controlling the dv/dt to avoid large input surge currents. VID could change with any input voltage, output
voltage, or output current. A new change is ignored until the current transition is finished. Program the transition
by adding a capacitor from DT_SET to ANAGND.
C
I
+ Dt
DT_SET
DV
Dt
+
REF
V
14 µA Dt
*V
REF2
REF1
hysteretic comparator
The hysteretic comparator regulates the output voltage of the synchronous-buck converter. The hysteresis is
set by two external resistors and is centered around VREFB. The two external resistors form a resistor divider
from VREFB to ANAGND, and the divided down voltage connects to the VHYST terminal. The hysteresis of the
comparator will be equal to twice the voltage that is across the VREFB and VHYST pins. The maximum
hysteresis setting is 60 mV.
ramp generator
The ramp generator circuit is partially composed of the PSM circuit. An external resistor from PH to
VSENSE_CORE superimposes a ramp (proportional to VI and VO) onto the feedback voltage. This allows
increasing the operating frequency, and reduces frequency dependance on the output filter values. A capacitor
can be used to provide ac-coupling. Also, connecting a resistor from VI to VSENSE_CORE allows feed forward
to counteract any dc offsets due to the ramp generator or propagation delays limiting duty cycle.
power saving mode/latch
The power saving mode circuit reduces the operating frequency of the ripple regulator during light load. This
helps boost the efficiency during light loads by reducing the switching losses. Care should be taken to not allow
rms current losses to exceed the switching losses. A 2-bit binary weighted resistor ramp circuit allows setting
four operating frequencies.
The PSM/LATCH terminal allows disabling of the fault latch (see Table 2). This allows the user to troubleshoot
or implement an external protection circuit.
Table 2. PSM Program Modes
Pin Voltage
Function
1
< (ANAGND – 0.3 V)
Disable PSM and disable fault latch
2
ANAGND to 1.8 V
Disable PSM and enable fault latch
3
2.3 V to VBIAS
Enable PSM and enable fault latch
4
> (VBIAS + 0.3 V)
Enable PSM and disable fault latch
active voltage DROOP positioning
The droop compensation network reduces the load transient overshoot/undershoot on VO, relative to Vref.
VO(max) is programmed to a voltage greater than Vref in the Application Information drawing by an external
resistor divider from VO to the VSENSE_CORE pin to reduce the undershoot on VOUT during a low to high load
transient. The overshoot during a high-to-low load transient is reduced by subtracting the voltage that is on the
DROOP pin from Vref. The voltage on the IOUT pin is divided down with an external resistor divider, and
connected to the DROOP pin. Thus, under loaded conditions, VO is regulated to VO(max) – V(DROOP). The
continuous sensing of the inductor current allows a fast regulating voltage adjustment allowing higher transient
repetition rates.
12
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TPS5300
SLVS334A – DECEMBER 2000 – REVISED SEPTEMBER 2001
detailed description (continued)
low-side driver
The low-side driver is designed to drive low rds(on), N-channel MOSFETs. The current of the driver is typically
2-A source and 3.3-A sink. The supply to the low-side driver is internally connected to VCC.
high-side driver
The high-side driver is designed to drive low rds(on) N-channel MOSFETs. The current of the driver is typically
2-A source and 3.3-A sink. The high-side driver is configured as a floating bootstrap driver. The internal
bootstrap diode, connected between the DRV and BOOT pins, is a Schottky diode for improved drive efficiency.
The maximum voltage that can be applied between the BOOT pin and ground is 35 V.
deadtime control
The deadtime control prevents shoot-through current from flowing through the main power FET’s during the
switching transitions by actively controlling the turnon times of the MOSFET drivers. The high-side driver is not
allowed to turn on until the gate drive voltage to the low-side FET is below 1.7 V. The low-side driver is not
allowed to turn on until the gate drive voltage from the high-side FET to PH is below 1.3 V.
current sensing
Current sensing is achieved by sensing the voltage across a current-sense resistor placed in series between
the output inductor and the output capacitors. The sensing network consists of a high bandwidth differential
amplifier with a gain of 25x to allow using sense resistors with values as low as 1 mΩ. Sensing occurs at all times
to allow having real-time information for quick response during an active voltage droop positioning transition.
The voltage on the IOUT pin equals 25 times the sensed voltage.
VR_ON
The VR_ON terminal is a TTL compatible digital pin that is used to enable the controller. When VR_ON is low,
the output drivers are low, the linear regulator drivers are off, and the slowstart capacitor is discharged. When
VR_ON goes high, the short across the slowstart capacitor is released and normal converter operation begins.
When the system logic supply is connected to the VR_ON pin, the VR_ON pin can control power sequencing
by locking out controller operation until the system logic supply exceeds the input threshold voltage of the
VR_ON circuit. Thus, VCC and the system logic supply (either 5 V or 3.3 V) must be above UVLO thresholds
before the controller is allowed to start up. Likewise, a microprocessor or other external logic can also control
the sequencing through VR_ON.
VBIAS undervoltage lockout
The VBIAS undervoltage-lockout circuit disables the controller, while VBIAS is below the 4.46-V start threshold
during power up. The controller is disabled when VBIAS goes below 3.3 V. While the controller is disabled, the
output drivers will be low and the slowstart capacitor will be shorted. When VBIAS exceeds the start threshold,
the short across the slowstart capacitor is released and normal converter operation begins.
IO linear regulator driver
The IO linear regulator driver circuit drives a high power NPN external power transistor, allowing external power
dissipation. The IO voltage is ramped up with the slowstart with the other two converters. Under voltage
protection protects against hard shorts or extreme loading. The VSENSE_IO voltage is monitored by the VGATE
(powergood) circuit. A fault or shutdown on any converter will shut down the linear regulator.
CLK linear regulator driver
The CLK linear regulator driver circuit drives a lower power NPN external power transistor, allowing external
power dissipation. The CLK voltage is ramped up with the slowstart with the other two converters. Under voltage
protection protects against hard shorts or extreme loading. The VSENSE_CLK voltage is monitored by the
VGATE (powergood) circuit. A fault or shutdown on any converter will shut down the linear regulator.
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13
TPS5300
SLVS334A – DECEMBER 2000 – REVISED SEPTEMBER 2001
detailed description (continued)
slowstart
The slowstart circuit controls the rate at which VOUT powers up. A capacitor is connected between the SLOWST
and ANAGND pins and is charged by an internal current source. The value of the current source is proportional
to the reference voltage, so that the charging rate of C(SLOWST) is proportional to the reference voltage. By
making the charging current proportional to Vref, the power up time for VO will be independent of Vref. Thus,
C(SLOWST) can remain the same value for all VP settings. The slowstart charging current is determined by the
following equation:
I SLOWSTART +
I(VREFB)
(amps)
5
where, I(VREFB) is the current flowing out of the VREFB terminal. It is recommended that no additional loads be
connected to VREFB, other than the resistor divider for setting the hysteresis voltage. Thus, these resistor
values will determine the slowstart charging current. The maximum current that can be sourced by the VREFB
circuit is 500 µA. The equation for setting the slowstart time is:
tSLOWSTART = 5 × C(SLOWSTART) × R(VREFB)
(seconds)
where, R(VREFB) is the total external resistance from VREFB to ANAGND.
VGATE
The VGATE circuit monitors for an undervoltage condition on VO(VSENSE_CORE), VO(VSENSE_IO), and
VO(VSENSE_CLK). If any VO is 7% below its reference voltage, or if any UVLO (Vcc, VR_ON) threshold is not
reached, then the VGATE pin is pulled low. The VGATE terminal is an open drain output.
overvoltage protection
The overvoltage protection circuit monitors VO(VSENSE_CORE), VO(VSENSE_IO), and VO(VSENSE_CLK) for an
overvoltage condition. If any VO is 15% above its reference voltage, then a fault latch is set, then both the ripple
regulator output drivers and the linear regulator drivers are turned off. The latch will remain set until VBIAS goes
below the undervoltage lockout value or until VR_ON is pulled low.
overcurrent protection
The overcurrent protection circuit monitors the current through the current sense resistor. The overcurrent
threshold is adjustable with an external resistor divider between IOUT and ANAGND terminals, with the divider
voltage connected to the OCP terminal. If the voltage on the OCP terminal exceeds 200 mV, then a fault latch
is set and the output drivers (ripple regulator and linear regulators) are turned off. The latch remains set until
VBIAS goes below the undervoltage lockout value or until VR_ON is pulled low.
thermal shutdown
Thermal shutdown disables the controller if the junction temperature exceeds the 165°C thermal shutdown trip
point. The hysteresis is 10°C.
14
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TPS5300
SLVS334A – DECEMBER 2000 – REVISED SEPTEMBER 2001
APPLICATION INFORMATION
Figure 1 is a standard application schematic. The circuit can be divided into the power-stage section and the
control-circuit section. The power stage that includes the power FETs (Q1–Q3), input capacitor (C2), output filter
(L1 and C3), and the current sense resistor (R1) must be tailored to the input/output requirements of the
application. The design documentation and test results for different mobile CPU power supplies covering core
current from 13 A and up to 40 A is available from the factory upon request or can be found in applications notes.
The control circuit is basically the same for all applications with minor tweaking of specific values.
The main waveforms are shown in Figure 2 through Figure 5. These waveforms include the following:
D The output ripple and Vds voltage of the low-side FET in the whole input voltage range (see Figure 2).
D The dynamic output voltage change between the performance and battery modes of operation (see
Figure 3).
D The transient response characteristics on the load current step up and down transitions (see Figure 4).
D The typical start-up waveforms for core, clock and I/O voltages (see Figure 5).
The waveforms confirm the excellent dynamic characteristics of the hysteretic controller. The modification, that
includes an additional ramp signal superimposed to the input VSENSE_CORE internally and externally by
circuits R17, R22, C13, and C10 makes the switching frequency independent of the output filter characteristics.
It also decreases the comparator delay times by increasing efficiency overdrive. This approach is shown in
Figure 6.
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15
16
5V
ANAGND
GND
+V batt
3V to 24V
VID0
VID1
VID2
VID3
VID4
VR_ON
Figure 1. Standard Application Circuit
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GND
+ 3.3 V
J4
C5
1uF
C2
5 x 10 uF, cer ., 35V
V_GATE
J3
J2
+
R19
+
51.1
R8
5.11K
C16
1uF
C15
100uF
1uF
C11
R17 51.1K
1uF
C7
R5
1.50
R18 10.0K
Q4
FZT849TA
C14
47uF
R4
4.7
IRF7811A
Q1
Q2
IRF7811A
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
DRV_IO
R22
J5
10K
C9
1
2
3
4
5
6 0.1uF
7
8
9
10
11
12
13
14
15
16
GND
R9
15K
R14
100
R11
6.49K
4700pF
C12
0.01uF
C4
1.00K
0.003
R2
R1
+
R15
20.0K
R12
R10
+
47uF
C17
power pad
R13
150
1uF
C18
200K
R20
C8
0.1uF
2.00K
1K
C6
0.01uF
J6
J1
GND
Output
Vout 0.6V to 2V,
18A
GND
Vout
GND
Vout_CLK
2.5V, 70mA (150mA peak)
R21
(see Note 2)
1000pF
C10
R16 10.0K
6 x 100uF, 2V, Panasonic SP
C3
Note: Ground planes are tied at
Q5
FMMT489TA
Vout_IO
1.5V, 160mA (3.5A peak)
0.1uF
C13
DRV_CLK
VSENSE_CLK
DT_SET
ANAGND
VSENSE_CORE
TPS5300DAP
U1
VSENSE_IO
BIAS
ENABLE_EXT
RAMP
SLOWSTART
VID0
HYST
VREFB
VID2
VID1
OCP
DROOP
IOUT
PSM /LATCH
VID3
VID4
VR_ON
BOOT
IS–
TG
VGATE
DRVGND
IS+
PWRPAD
R3
D1 1.00K
30BQ040
PH
1.50
R6
VCC
BG
2.74
R7
Q3
IRF7811A
1000pF
C1
L1
1uH
TPS5300
SLVS334A – DECEMBER 2000 – REVISED SEPTEMBER 2001
APPLICATION INFORMATION
NOTES: A. Contact factory or see application notes for documentation and test results of different mobile core regulator applications at the
output current up to 40 A.
B. R21 allows VID code voltage adjustment.
TPS5300
SLVS334A – DECEMBER 2000 – REVISED SEPTEMBER 2001
APPLICATION INFORMATION
IO = 24 A
VI = 22 V
IO = 24 A
VI = 6 V
(a)
NOTE: Channel 1 = drain source voltage (10 V/div),
(b)
Channel 2 = output voltage ripple (50 nV/div)
Figure 2. Output Voltage Ripple and Low-Side FET Drain-Source Voltage
IO = 10 A
VI = 4.5 V
NOTE: Channel 1 = input voltage ripple, Channel 2 = output voltage, Channel 3 = VGATE signal, Channel 4 = input current.
Figure 3. Dynamic VID-Code Change Waveforms From 1.35 V to 1.6 V and Back
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17
TPS5300
SLVS334A – DECEMBER 2000 – REVISED SEPTEMBER 2001
APPLICATION INFORMATION
VI = 12 V
VI = 12 V
NOTE: The load current (M3) has 10-A step with a slew rate
of 30 A/µs. Channel 3 = drain source of low-side FET,
and channel 4 = input current.
NOTE: From bottom to top: VOUT IO, VOUT core, VOUT CLK,
and the voltage of the slow-start capacitor.
Figure 4. Output Voltage Transient Response
(Channel 2)
Figure 5. Start-Up Waveforms at 12 V Input
Voltage and 10-A Load Current on the
Switching Regulator
VHC
(VHI – VLO) – Hysteresis Window
(VMAX – VMIN) – Overshoot
Because of Delays
VMAX
VHI
VREF
VLO
VMIN
V(SENSE_CORE) Signal With
Superimposed Ramp
Output Ripple
t
Figure 6. Hysteretic Comparator Input Waveforms
18
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TPS5300
SLVS334A – DECEMBER 2000 – REVISED SEPTEMBER 2001
APPLICATION INFORMATION
switching cycle and frequency calculation
The switching cycle calculation is shown below.
V
Ts + I
Cadd
V
O
Hyst
Radd
(V * V
I
O)
) Tdel1
V
I ) Tdel2
V
O
V
I
V *V
I
O
where, VI = input voltage, VO = output voltage, Cadd = C10 and Radd = R22 + R17 in Figure 1, Hyst is the
hysteresis window, Tdel1 and Tdel2 are the comparator and drive circuit delays when the high-side and low-side
FETs turn on correspondingly. The switching frequency variation for the different input and output voltages is
shown in Figure 7. In this case the parameters of equation above are the following: Radd = 49.9 kΩ,
Cadd = 1060 pF, Tdel1 = 240 ns, Tdel2 = 250 ns, Hyst = 0.5% of VO. The lower-switching frequency at higher
input voltages helps to keep low switching losses during the input voltage range.
1000
Switching Frequency – KHz
900
800
VO = 2 V
700
VO = 1.65 V
600
500
400
VO = 1.3 V
300
200
100
0
4
5
6
7
8
9
10
VI – Input Voltage – V
11
12
13
Figure 7. Theoretical (Solid) and Measured (Points) Switching Frequency
output voltage
The output voltage with a dc decoupling capacitor (C13) is defined below:
V
O
+V
ref
ǒ1 ) R1
Ǔ
R2
where, R1 = R13 and R2 = R16 (see Figure 1)
additional literature
An Analytical Comparison of Alternative Control Techniques for Powering Next-Generation Microprocessors,
SEM–1400 TI/Unitrode Power Supply Design Seminar, Topic 1.
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19
TPS5300
SLVS334A – DECEMBER 2000 – REVISED SEPTEMBER 2001
MECHANICAL DATA
DA (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
38 PINS SHOWN
0,30
0,19
0,65
38
0,13 M
20
6,20
NOM
8,40
7,80
0,15 NOM
Gage Plane
1
19
0,25
A
0°–ā8°
0,75
0,50
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,10
30
32
38
A MAX
11,10
11,10
12,60
A MIN
10,90
10,90
12,40
DIM
4040066 / D 11/98
NOTES: A.
B.
C.
D.
20
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion.
Falls within JEDEC MO-153
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