DATA SHEET BIPOLAR ANALOG INTEGRATED CIRCUITS µPC8190K,µPC8191K RX/TX-IF SiMMIC FOR W-CDMA DESCRIPTION The µPC8190K and µPC8191K are silicon monolithic integrated circuit designed as receiver (RX) and transmitter (TX) IF section for W-CDMA. The µPC8190K is a RX-IF IC including IF-AGC amplifier and demodulator. The µPC8191K is a TX-IF IC including IF-AGC amplifier and quadrature modulator. These two ICs are suitable for kit-use for W-CDMA IF section. The ICs are developed using NEC’s new ultra high speed silicon bipolar process. FEATURES • RX-IF: 380 MHz, TX-IF: 570 MHz • Low power consumption • Built-in power saving function • Small size: 20-pin plastic QFN package (3.2 × 4.2 × 0.8 mm) APPLICAION • W-CDMA ORDERING INFORMATION Part Number Package Supplying Form µPC8190K-E1 20-pin plastic QFN • Embossed tape 12 mm wide. µPC8191K-E1 (3.2 × 4.2 × 0.8 mm) • Pin 1 indicates pull-out direction of tape • Qty 2.5 kpcs/reel Remark To order evaluation samples, please contact your local NEC sales office. Part number for sample order: µPC8190K, µPC8191K Caution electro-static sensitive devices. The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all devices/types available in every country. Please check with local NEC representative for availability and additional information. Document No. P15669EJ2V0DS00 (2nd edition) Date Published August 2001 NS CP(K) Printed in Japan © 2001 µPC8190K,µPC8191K APPLICATION EXAMPLE Variation of IF plan µPC8190K, µ PC8191K: RX-IF = 380 MHz, TX-IF = 570 MHz µPC8194K, µ PC8195K: RX-IF = 190 MHz, TX-IF = 380 MHz AGC + I/Q Demodulator µPC8190K, µPC8194K BPF LNA MIX BPF H RX = 2 110 to 2 170 MHz To Baseband 90˚ ANT 2nd LO = 760 MHz 1st LO DUPLX PLL1 PA H AGC + PA Driver TX = 1 920 to 1 980 MHz H MIX µ PC8172TB µ PC8187TB 2 PLL2 Data Sheet P15669EJ2V0DS 90˚ AGC + I/Q Modulator µPC8191K, µPC8195K From Baseband µPC8190K,µPC8191K INTERNAL BLOCK DIAGRAM AND PIN CONFIGURATION − µPC8190K (RX) − 11 VCC (Demod.) 12 TEST1 13 TEST2 14 GND (AGC, REG.) 15 VCC (AGC, REG.) (Top View) IF_IN 16 10 I IF_INb 17 9 Ib GND (AGC, REG.) 18 8 Q N.C. 19 REG. and Gain Control Phase Shifter (1/2) Data Sheet P15669EJ2V0DS 6 GND (Demod.) GND (Demod.) 5 LOb 4 LO 3 N.C. 2 Vcont 1 VPS 20 7 Qb 3 µPC8190K,µPC8191K PIN EXPLANATIONS − µPC8190K (RX) − Pin No. 1 Pin Name Applied Voltage (V) Pin Voltage (TYP.) Note (V) Vcont 0 to 3.0 − Functions and Applications Internal Equivalent Circuits Gain cnotrol pin of AGC amplifier. Variable gains are available in accordance with applied voltage. VCC 54 k 12 k 1 5k 2 N.C. − − 19 Non connection. This pin is not connected to internal circuit. This pin should be opened or grounded. 3 LO − − Local signal input pin of I/Q demodulator. VCC Input frequency is 760 MHz. 3 4 LOb − − 4 Bypass pin of local signal input for I/Q demodulator. 50 In the case of single local input, this pin must be decoupled with capacitor ex. 100 to 1 000 pF. 5 6 GND (Demod.) 0 − 50 GND Ground pin of I/Q demodulator. This pin should be grounded with minimum inductance. Form the ground pattern as widely as possible to minimize ground impeadance. 7 Qb − − 8 Q − − 9 Ib − − 10 I − − I/Q/Ib/Qb signal output pins. Each pin is an emitter follower. VCC 8.5 k Each of Ib and Qb is differential output of I and Q. Recommendable load impedance is 10 to 20 kΩ. 7 GND Note Pin voltage is measured at VCC = 3.0 V 4 Data Sheet P15669EJ2V0DS 8 9 10 µPC8190K,µPC8191K − µPC8190K (RX) − Pin No. Pin Name Applied Voltage (V) Pin Voltage (TYP.) Note (V) Functions and Applications 11 VCC (Demod.) 2.7 to 3.3 − Supply voltage pin of I/Q demodulator (phase shifter + I/Q Mixer). 12 TEST 1 0 − TEST pin. 13 TEST 2 0 − In actual use, this pin should be grounded. 14 GND (AGC, REG.) 0 − 18 Internal Equivalent Circuits Ground pin of AGC amplifier and internal regulator. This pin should be grounded with minimum inductance. Form the ground pattern as widely as possible to minimize ground impedance. 15 16 VCC (AGC, REG.) 2.7 to 3.3 IF_IN − − − Supply voltage pin of AGC amplifier and internal regulator. IF signal input pin. VCC This pin is input of AGC amplifier. Balance input between 16, 17 pin. 16 1.1 k Input frequency is 380 MHz. 17 IF_INb − − 17 IF signal input pin. 1.2 k In the case of signal local input, this pin must be decoupled with capacitor. 1.2 k GND 20 VPS H: 2.2 to VCC − Power saving pin. VCC This pin modulator can control Active/Sleep state with bias as follows. 100 k L: 0 to 0.5 VPS (V) State 0 to 0.5 Sleep Mode 2.2 to 3 Active Mode 20 100 k GND Note Pin voltage is measured at VCC = 3.0 V Data Sheet P15669EJ2V0DS 5 µPC8190K,µPC8191K ABSOLUTE MAXIMUM RATINGS − µPC8190K (RX) − Parameter Symbol Ratings Unit Supply Voltage VCC 4.0 V Applied Voltage VPS, Vcont −0.3 to VCC + 0.3 V Operating Ambient Temperature TA −40 to +85 °C Storage Temperature Tstg −55 to +150 °C RECOMMENDED OPERATING RANGE − µPC8190K (RX) − Parameter Symbol MIN. TYP. MAX. Unit Supply Voltage VCC 2.7 3.0 3.3 V Operating Ambient Temperature TA −25 25 85 °C IF Frequency fIF − 380 − MHz Local Frequency fLO − 760 − MHz Local Input Level PLO −18 −15 −12 dBm ELECTRICAL CHARACTERISTICS − µPC8190K (RX) − (Unless otherwise specified, VCC = 3.0 V, TA = +25°°C, fIF = 382.5 MHz, fLO = 760 MHz, PLO = −15 dBm, fI/Q = 2.5 MHz) Parameter Circuit Current Voltage Gain Input 3rd Order Intercept Point Symbol MIN. TYP. MAX. Unit No input signal − 9 12 mA At power-saving mode − − 1 µA V G1 Vcont = 2.5 V 68 77 − dB VG2 Vcont = 0.5 V − −20 −15 dB IIP3 Gain = +65 dB (RS= 600 Ω balanced), PIFin = −70 dBm −60 −55 − dBm Gain = −10 dB (RS= 600 Ω balanced), PIFin = −10 dBm 0 3 − dBm Leakage to I/Q port when local = 380 MHz and output = 30 mVP-P balanced − − −20 dBc 3 dB down 10 − − MHz Balanced output 1 − − VP-P ICC Local Leakage LOL I/Q Bandwidth fI/Q I/Q Maximum Output Swing VO (sat) Test Conditions I/Q Gain Balance AE fI/Q = 2.5 MHz − − ∆0.5 dB I/Q Phase Error PE fI/Q = 2.5 MHz − − ±4 deg. Gain Accuracy Gacc Vcont = 1 to 2 V − ∆4.6 ∆6 dB/V tPS − − 20 µs Rising Voltage from Power-saving Mode VPS on 2.2 − − V Falling Voltage from Power-saving Mode VPS off − − 0.5 V − − ∆0.5 dB Rise Time from Power-saving Mode Gain Flatness 6 Flat fIF ± 2.5 MHz Data Sheet P15669EJ2V0DS µPC8190K,µPC8191K STANDARD CHARACTERISTICS FOR REFERENCE − µPC8190K (RX) − (Unless otherwise specified, VCC = 3.0 V, TA = +25°°C, fIF = 382.5 MHz, fLO = 760 MHz, PLO = −15 dBm, fI/Q = 2.5 MHz) Parameter Noise Figure Symbol NF Error Vector Magnitude (Vector Error) EVM Gain 1 dB Compression Input Power Pin (1 dB) Test Conditions MIN. TYP. MAX. Unit Gain = +65 dB − 9.5 12 dB IF = 380 MHz, 3.84 Msps QPSK modulation, gain is adujsted − 3 − %rms Gain = +50 dB − −45 − dBm Data Sheet P15669EJ2V0DS 7 µPC8190K,µPC8191K MEASUREMENT CIRCUIT − µPC8190K (RX) − VCC 2.2 nF TOKO Balun transformer 616DB-1078 100 pF 2.2 nF µPC8190K 15 nH 1 pF 1.2 kΩ IF in AGC1 AGC2 AGC3 1µF 3.3 kΩ 1µF 3.3 kΩ 1µF 3.3 kΩ 1µF 3.3 kΩ I 12 pF IX 100 pF 68 nH Q REG. and Gain Control Phase Shifter (1/2) VPS LO Buffer 100 pF Remark 8 : AC connector : DC terminal : Feed through capacitor 100 pF Vcont LOin Data Sheet P15669EJ2V0DS QX µPC8190K,µPC8191K INTERNAL BLOCK DIAGRAM AND PIN CONFIGURATION − µPC8191K (TX) − 11 VCC (REG.) 12 GND (REG.) 13 GND (AGC, MIX) 14 GND (AGC, MIX) 15 VCC (AGC, MIX) (Top View) REG. and AGC_Control IFout 16 9 VPS IFoutb 17 GND (AGC, MIX) 18 10 Vcont LPF 8 VCC (Shifter) Data Sheet P15669EJ2V0DS Tank 5 6 LOb Tank 4 Ib 20 GND (Shifter) 3 7 LO Phase Shifter (1/2) Q 2 1/2 Qb 1 I 19 9 µPC8190K,µPC8191K PIN EXPLANATIONS − µPC8191K (TX) − Pin No. 1 Pin Name Applied Voltage (V) Pin Voltage (TYP.) Note (V) Qb VCC/2 − Functions and Applications Internal Equivalent Circuits Q signal input pin. Apply bias voltage externally. Maximum balance input voltage is 1 000 mVP-P (balance). 2 Q VCC/2 − 3 GND (Shifter) 0 − 1 2 Ground pin of I/Q modulator. This pin should be grounded with minimum inductance. Form the ground pattern as widely as possible to minimize ground impedance. 4 Tank 0 2.65 5 External inductor and capcitor can supress harmonics spurious of LO frequency. External 4 LC value should be determined according to LO input frequency and suppression level. 6 LOb 0 2.02 Bypass pin of local signal inpu for I/Q modulator. In the case of single local input, this pin must be decoupled with capacitor ex. 1 000 pF. 7 LO 0 2.02 Local signal input of I/Q modulator. The DC cut capacitor ex. 1 000 pF must be attaced to this pin. 8 VCC (Shifter) 2.7 to 3.3 − Supply voltage pin of I/Q modulator. 9 VPS 0 to 3.0 − Power saving pin of I/Q modulator + AGC amplifier. This pin modulator can control Active/Sleep state with bias as follows. VPS (V) State 0 to 0.5 Sleep Mode 2.2 to 3 Active Mode Note Pin voltage is measured at VCC = 2.85 V 10 5 Data Sheet P15669EJ2V0DS 50 kΩ 9 µPC8190K,µPC8191K − µPC8191K (TX) − Pin No. 10 Pin Name Applied Voltage (V) Pin Voltage (TYP.) Note (V) Vcont 0 to 3.0 − Functions and Applications Internal Equivalent Circuits Gain control pin of AGC amplifier. 10.5 kΩ Variable gains are available in accordance with applied voltage between 0 to 3.0 V. 2.5 kΩ 11 VCC (REG.) 2.7 to 3.3 − Supply voltage pin of internal regulator. 12 GND (REG.) 0 − Ground pin internal regulator. This pin should be grounded with minimum inductance. Form the ground pattern as widely as possible to minimize ground impedance. 13 14 GND (AGC, MIX) 0 − Ground pin of AGC amplifier + I/Q Mixer. This pin should be grounded with minimum inductance. 18 Form the ground pattern as widely as possible to minimize ground impedance. 15 VCC (AGC, MIX) 2.7 to 3.3 − Supply voltage pin of AGC amplifier + I/Q Mixer. 16 IFout 2.7 to 3.3 − IF output pin. The inductor must be attached between VCC and output pin due to open collector. External 16 Output frequency is 570 MHz which is 3/4 of local signal frequency 760 MHz. 17 IFoutb 2.7 to 3.3 − 1 kΩ 17 Balance output of IFout pin. The inductor must be attached between VCC and output pin due to open collector. 19 I VCC/2 − I signal input pin. Apply bias voltage externally. Maximum balance input voltage is 1 000 mVP-P (balance). 20 Ib VCC/2 − 19 20 Note Pin voltage is measured at VCC = 2.85 V Data Sheet P15669EJ2V0DS 11 µPC8190K,µPC8191K ABSOLUTE MAXIMUM RATINGS − µPC8191K (TX) − Parameter Symbol Ratings Unit Supply Voltage VCC 4.0 V Applied Voltage VPS, Vcont −0.3 to VCC + 0.3 V Operating Ambient Temperature TA −40 to +85 °C Storage Temperature Tstg −55 to +150 °C RECOMMENDED OPERATING RANGE − µPC8191K (TX) − Parameter Symbol Test Conditions MIN. TYP. MAX. Unit Supply Voltage VCC 2.7 3.0 3.3 V Operating Ambient Temperature TA −25 25 85 °C IF Frequency fIF − 570 − MHz Local Frequency fLO − 760 − MHz Local Input Level PLO −18 −15 −12 dBm IF Output Impedance ZIF Balance output internal resistance − 1 − kΩ I/Q Maximum Input Voltage VI/Q Balance input − 0.4 1 VP-P ELECTRICAL CHARACTERISTICS − µPC8191K (TX) − (Unless otherwise specified, VCC = 3.0 V, TA = +25°°C, fIF = 570 MHz, fLO = 760 MHz, PLO = −15 dBm, fI/Q = 10 kHz, 400 mVP-P balanced sine-wave) Parameter Circuit Current Output Power Symbol ICC Pout Test Conditions MIN. TYP. MAX. Unit No input signal − 30.5 38 mA At power-saving mode − 0 1 µA Vcont = 2.3 V, I/Q = 400mVP-P balanced −17 −13 − dBm Vcont = 0.3 V, I/Q = 400mVP-P balanced − −93 −88 dBm Local Leakage LOL − − −30 dBc Image Rejection ImR − − −30 dBc Output Harmonics 1 Hm1 Leakage when IF output = 190 MHz − − −20 dBc Output Harmonics 2 Hm2 Leakage when IF output = 380 MHz − − −30 dBc tPS − − 10 µs Rising Voltage from Power-saving Mode VPS on − − 2.2 V Falling Voltage from Power-saving Mode VPS off 0.5 − − V Rise Time from Power-saving Mode 12 Data Sheet P15669EJ2V0DS µPC8190K,µPC8191K STANDARD CHARACTERISTICS FOR REFERENCE − µPC8191K (TX) − (Unless otherwise specified, VCC = 3.0 V, TA = +25°°C, fIF = 570 MHz, fLO = 760 MHz, PLO = −15 dBm, fI/Q = 10 kHz, 400 mVP-P balanced sine-wave) Parameter Symbol Test Conditions MIN. TYP. MAX. Unit Output Noise Level 1 NFL1 Pout = −25 dBm, fIF ± 20 MHz − −148 − dBm/Hz Output Noise Level 2 NFL2 Pout = −65 dBm, fIF ± 20 MHz − −162 − dBm/Hz Error Vector Magnitude (Vector Error) EVM − 3 − %rms Adjacent Channel Power ACPR − −55 − dBc fIF ± 5 MHz Data Sheet P15669EJ2V0DS 13 µPC8190K,µPC8191K MEASUREMENT CIRCUIT − µPC8191K (TX) − VCC VCC 1 µF 1 µF VCC 1 µF 8 pF 1 µF 82 nH 12 nH REG. and AGC_Control IFout 1 µF TOKO Type B4F 617DB-1024 I 82 nH VCC VPS VCC 1/2 LOin 1nF 1 pF 14 1 µF 1nF Phase Shifter (1/2) : AC connector : DC terminal Vcont LPF Ib Remark 1 µF Qb Q Data Sheet P15669EJ2V0DS 15 nH µPC8190K,µPC8191K PACKAGE DIMENSIONS 20-PIN PLASTIC QFN (PIN-PITCH: 0.4 mm, UNIT: mm) 4.2±0.2 3.0±0.2 3.2±0.2 3.2±0.2 3.0±0.2 4.0±0.2 Pin 20 Pin 1 (Bottom View) 0.18±0.05 4.0±0.2 0.8±0.1 4.2±0.2 0.30±0.15 0.4 Data Sheet P15669EJ2V0DS 15 µPC8190K,µPC8191K NOTE ON CORRECT USE (1) Observe precautions for handling because this IC is an electrostatic sensitive device. (2) Form a ground pattern as widely as possible to minimize its impedance (to prevent undesires oscillation). (3) Keep the track length of the ground pins as short as possible. (4) Connect a bypass capacitor to the VCC pin. RECOMMENDED SOLDERING CONDITIONS This product should be soldered and mounted under the following recommended conditions. For soldering methods and conditions other than those recommended below, contact your NEC sales representative. Soldering Method Soldering Conditions Recommended Condition Symbol Infrared Reflow Package peak temperature: 235°C or below, Time: 30 seconds or less (at 210°C or higher), Note Count: 3 times or less, Exposure limit: None IR35-00-3 VPS Package peak temperature: 215°C or below, Time: 40 seconds or less (at 200°C or higher), Note Count: 3 times or less, Exposure limit: None VP15-00-3 Partial Heating Pin temperature: 300°C or below, Time: 3 seconds or less (per side of device), Note Exposure limit: None − Note After opening the dry pack, store it at 25°C or less and 65% RH or less for the allowable storage period. Caution Do not use different soldering methods together (except for partial heating). For the details the recommended soldering conditions, refer to the document SEMICONDUCTOR DEVICE MOUNTING TECHNOLOGY MANUAL (C10535E). 16 Data Sheet P15669EJ2V0DS µPC8190K,µPC8191K [MEMO] Data Sheet P15669EJ2V0DS 17 µPC8190K,µPC8191K [MEMO] 18 Data Sheet P15669EJ2V0DS µPC8190K,µPC8191K [MEMO] Data Sheet P15669EJ2V0DS 19 µPC8190K,µPC8191K • The information in this document is current as of August, 2001. The information is subject to change without notice. For actual design-in, refer to the latest publications of NEC's data sheets or data books, etc., for the most up-to-date specifications of NEC semiconductor products. Not all products and/or types are available in every country. Please check with an NEC sales representative for availability and additional information. • No part of this document may be copied or reproduced in any form or by any means without prior written consent of NEC. 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(Note) (1) "NEC" as used in this statement means NEC Corporation and also includes its majority-owned subsidiaries. (2) "NEC semiconductor products" means any semiconductor product developed or manufactured by or for NEC (as defined above). M8E 00. 4