CYPRESS W159

W159
Spread Spectrum System FTG for SMP Systems
Features
CPUdiv2, 3V33, APIC Output Jitter:............................250 ps
• Maximized EMI suppression using Cypress’s spread
spectrum technology (0.5% down spread)
• Seven skew-controlled copies of CPU and 16.667-MHz
synchronous APIC output
• Two copies of fixed-frequency 33-MHz outputs
• Four copies of 66-MHz fixed-frequency outputs
• Two copies of CPU/2 outputs for synchronous memory
reference
• One copy of 48-MHz USB output
• Two copies of 14.31818-MHz reference clock
• Programmable to 133- or 100-MHz operation
• Power management control pins for clock stop and shut
down
• Available in 56-pin SSOP
CPU, 3V33 Output Edge Rate:.................................. >1 V/ns
48-MHz, 3V66, REF Output Jitter:...............................500 ps
CPU0:6, CPUdiv2_0:1 Output Skew: ..........................175 ps
3V66, APIC0:6, 3V33 Output Skew:............................250 ps
CPU to 3V66 Output Offset: .......... 0.0 to 1.5 ns (CPU leads)
3V66 to 3V33 Output Offset: ........ 1.5 to 3.0 ns (3V66 leads)
CPU to APIC Output Offset: ............ 1 to 3.0 ns (CPU Leads)
CPU to 3V33 Output Offsets: ....... 1.5 to 4.0 ns (CPU Leads)
Logic inputs, except SEL133/100#, have 250-kΩ pull-up resistors.
Table 1. Pin Selectable Frequency
SEL133/100#
CPU0:6 (MHz)
PCI
Key Specifications
1
133 MHz
33.3 MHz
Supply Voltages: ...................................... VDDQ3 = 3.3V±5%
VDDQ2 = 2.5V±5%
0
100 MHz
33.3 MHz
CPU Output Jitter: ...................................................... 150 ps
[1]
Block Diagram
X1
X2
Pin Configuration
2
XTAL
OSC
REF_[0:1]
5
CPU_[0:4]
6W/4W#
2
CPU_[5:6]
2
CPUdiv2_[0:1]
PLL 1
4
SEL133/100#
3V66_[0:3]
÷2/÷1.5
2
÷2
PWRDWN#
Power
Down
Logic
3V33_[0:1]
5
÷4
APIC_[0:4]
2
APIC_[5:6]
FIXAPIC#
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
APIC3
APIC4
VDDQ2
APIC5
APIC6
GND
SPREAD#*
VDDQ2
CPU0
CPU1
GND
GND
CPU2
CPU3
VDDQ2
VDDQ2
CPU4
CPU5
GND
GND
CPU6
VDDQ2
PWRDWN#*
GND
CPUdiv2_0
CPUdiv2_1
VDDQ2
SEL133/100#
Note:
1. Pins denoted by * have a 250 kΩ pull-up resistor. Design
should not rely solely on internal pull-up resistor to set I/O
pins HIGH.
1
PLL2
Cypress Semiconductor Corporation
Document #: 38-07163 Rev. *A
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
W159
÷2
SPREAD#
APIC2
GND
APIC1
APIC0
VDDQ2
X1
X2
VDDQ3
REF0/FIXAPIC#*
REF1/TEST#*
GND
VDDQ3
GND
48MHz
VDDQ3
3V66_0
3V66_1
VDDQ3
GND
3V66_2
3V66_3
VDDQ3
3V33_0
3V33_1
GND
6W/4W#*
VDDQ3
GND
48MHz
•
3901 North First Street
•
San Jose
•
CA 95134 • 408-943-2600
Revised December 14, 2002
W159
Pin Definitions
Pin Name
CPU0:6
Pin
No.
48, 47, 44, 43,
40, 39, 36
Pin
Type
O
CPUdiv2_ 0:1
32, 31
O
3V33_0:1
23, 24
O
REF0/
FIXAPIC#*
9
I/O
REF1/TEST#*
10
I/O
APIC0:6
4, 3, 1, 56, 55
53, 52
O
48MHz
14
O
16, 17, 20, 21
29
O
I
X1
6
I
X2
7
O
6W/4W#*
26
I
SPREAD#
50
I
PWRDWN#
34
I
2, 11, 13, 19,
25, 28, 33, 37,
38, 45, 46, 51
8, 12, 15, 18,
22, 27
5, 30, 35, 41,
42, 49, 54
G
3V66_0:3
SEL133/100#
GND
VDDQ3
VDDQ2
P
P
Pin Description
CPU Clock Outputs 0 through 6: These seven CPU clocks run at a frequency set
by SEL133/100#. Output voltage swing is set by the voltage applied to VDDQ2. For
4-way SMP systems that do not require more than 5 CPU outputs, CPU5 and CPU6
can be disabled by asserting 6W/4W# during power-up.
Synchronous Memory Reference Clock Output 0 through 1: Reference clock
for Direct RDRAM clock generators running at 1/2 CPU clock frequency. Output
voltage swing is set by the voltage applied to VDDQ2. For systems using SDRAM,
CPUdiv2_0:1 output can be disabled by tying VDDQ2 on pin 35 to GND.
33-MHz Fixed-Frequency Output: These are fixed-frequency outputs that can be
used to drive PCI devices.
14.318-MHz Reference Clock Output/APIC Speed Select: During normal operations, this is a 3.3V 14.318-MHz reference output. During power-up, it is sampled
to determine the operating frequency of APIC. If the sample is a “1,” APIC will be
set at CPU/4. If it is a “0,” APIC will be fixed at 16.667 MHz.
14.318-MHz Reference Clock Output/Test Mode: During normal operations, this
is a 3.3V 14.318-MHz reference output. The input is sampled at power-up to determine if the device should initialize for normal operations or test mode.
Synchronous I/OAPIC Clock Outputs: APIC output frequency is determined by
FIXAPIC# strapping. For 4-way SMP systems that do not require more than 5 APIC
outputs, APIC5 and APIC6 can be disabled by asserting 4W/6W# during power up.
48-MHz Output: Fixed 48-MHz USB output. Output voltage swing is controlled by
voltage applied to VDDQ3.
66-MHz Output 0 through 3: Fixed 66-MHz outputs.
Frequency Selection Input: 3.3V LVTTL-compatible input that selects CPU output
frequency as shown in Table 1.
Crystal Connection or External Reference Frequency Input: Connect to either
a 14.318-MHz crystal or other reference signal.
Crystal Connection: An output connection for an external 14.318-MHz crystal. If
using an external reference, this pin must be left unconnected.
4-way/6-way Output Select: This input can be changed after initialization and has
an internal pull-up resistor. If left unconnected during power-up, the outputs are
configured so that all CPU and APIC outputs are active. If it is pulled down during
power-up, CPU5:6 and APIC5:6 will be disabled.
Active LOW Spread Spectrum Enable: 3.3V LVTTL-compatible input that enables
spread spectrum mode when held LOW.
Active LOW Power Down Input: 3.3V LVTTL-compatible asynchronous input that
requests the device to enter power down mode.
Ground Connection
Power Connection: Power supply for 3V33, 3V66, 48MHz, and REF output buffers,
core circuitry and PLL circuitry. Connect to 3.3V supply.
Power Connection: Power supply for APIC and CPU, CPUdiv2 output buffers.
Connect to 2.5V supply.
Overview
The W159 is designed to provide the essential frequency
sources to work with advanced multiprocessing Intel® architecture platforms. Split voltage supply signaling provides 2.5V
and 3.3V clock frequencies operating up to 133 MHz.
From a low-cost 14.31818-MHz reference crystal oscillator,
the W159 generates 2.5V clock outputs to support CPUs, core
logic chip set, and Direct RDRAM clock generators. It also provides skew-controlled PCI and IOAPIC clocks synchronous to
CPU clock, 48-MHz Universal Serial Bus (USB) clock, and replicates the 14.31818-MHz reference clock.
Document #: 38-07163 Rev. *A
All CPU, PCI, and IOAPIC clocks can be synchronously modulated for spread spectrum operations. Cypress employs proprietary techniques that provide the maximum EMI reduction
while minimizing the clock skews that could reduce system
timing margins. The use of spread spectrum modulation is
controlled by an external signal input.
The W159 also includes power management control inputs. By
using these inputs, system logic can stop CPU and/or PCI
clocks or power down the entire device to conserve system
power.
Page 2 of 11
W159
Spread Spectrum Generator
Where P is the percentage of deviation and F is the frequency
in MHz where the reduction is measured.
The device generates a clock that is frequency modulated in
order to increase the bandwidth that it occupies. By increasing
the bandwidth of the fundamental and its harmonics, the amplitudes of the radiated electromagnetic emissions are reduced. This effect is depicted in Figure 1.
The output clock is modulated with a waveform depicted in
Figure 2. This waveform, as discussed in “Spread Spectrum
Clock Generation for the Reduction of Radiated Emissions” by
Bush, Fessler, and Hardin produces the maximum reduction
in the amplitude of radiated electromagnetic emissions. The
deviation selected for this chip is –0.5% downspread. Figure
2 details the Cypress spreading pattern. Cypress does offer
options with more spread and greater EMI reduction. Contact
your local Sales representative for details on these devices.
As shown in Figure 1, a harmonic of a modulated clock has a
much lower amplitude than that of an unmodulated signal. The
reduction in amplitude is dependent on the harmonic number
and the frequency deviation or spread. The equation for the
reduction is
Spread Spectrum clocking is activated or deactivated by selecting the appropriate values for the SPREAD# input pin.
dB = 6.5 + 9*log10(P) + 9*log10(F)
Highest Peak
Spread
Spectrum
Enabled
NonSpread
Spectrum
100%
90%
80%
70%
60%
50%
40%
30%
20%
10%
100%
90%
80%
70%
60%
50%
40%
30%
20%
100%
80%
60%
40%
20%
0%
–20%
–40%
–60%
–80%
–100%
10%
Frequency Shift
Figure 1. Clock Harmonic with and without SSCG Modulation Frequency Domain Representation
Time
Figure 2. Modulation Waveform Profile
Document #: 38-07163 Rev. *A
Page 3 of 11
W159
Maximum Allowed Current
Table 2. Maximum Allowed Current
Max. 2.5V supply consumption
Max. discrete cap loads,
VDDQ2=2.625V
All static inputs=VDDQ3 or VSS
Max. 3.3V supply consumption
Max. discrete cap loads,
VDDQ3=3.465V
All static inputs=VDDQ3 or VSS
Power-down Mode
(PWRDWN#=0)
300 µA
500 µA
Full Active 100 MHz
SEL133/100#=0
120 mA
160 mA
Full Active 133 MHz
SEL133/100#=1
120 mA
160 mA
Condition
Table 3. Clock Enable Configuration[2, 3, 4]
PWRDWN#
CPUCLK
CPUdiv2
APIC
3V66
3V33
48MHz
REF
OSC.
VCOs
0
LOW
LOW
LOW
LOW
LOW
LOW
LOW
OFF
OFF
1
ON
ON
ON
ON
ON
ON
ON
ON
ON
Table 4. Power Management State Transition
Signal
Signal State
Latency[5]
PWRDWN#
1 (normal operation)
3 ms
0 (power down)
2 PCI clocks (max.)
Timing Diagram
PWRDWN# Timing Diagram[6, 7, 8, 9, 10]
CPUCLK
(internal)
PCI
(internal)
PWRDWN#
CPUCLK
(external)
PCI
(external)
VCO
Crystal
Notes:
2. LOW means outputs held static LOW as per latency requirement below.
3. ON means active.
4. PWRDWN# pulled LOW, impacts all outputs including REF and 48-MHz outputs.
5. Power-up latency is when PWRDWN# goes inactive (HIGH) to when the first valid clocks are driven from the device.
6. All internal timing is referenced to the CPUCLK.
7. The internal label means inside the chip and is a reference only. This, in fact, may not be the way that the control is designed.
8. PWRDWN is an asynchronous input and metastable conditions could exist. This signal is synchronized by the W159 internally.
9. The shaded sections on the VCO and the Crystal signals indicate an active clock.
10. Diagrams shown with respect to 133 MHz. Similar operation when CPUCLK is 100 MHz.
Document #: 38-07163 Rev. *A
Page 4 of 11
W159
Absolute Maximum Ratings[11]
Stresses greater than those listed in this table may cause permanent damage to the device. These represent a stress rating
only. Operation of the device at these or any other conditions
above those specified in the operating sections of this specification is not implied. Maximum conditions for extended periods may affect reliability.
.
Parameter
Description
Rating
Unit
V
VDD, VIN
Voltage on any pin with respect to GND
–0.5 to +7.0
–65 to +150
°C
0 to +70
°C
–55 to +125
°C
2 (min.)
kV
TSTG
Storage Temperature
TA
Operating Temperature
TB
Ambient Temperature under Bias
ESDPROT
Input ESD Protection
DC Electrical Characteristics: TA = 0°C to +70°C, VDDQ3 = 3.3V±5%, VDDQ2 = 2.5V±5%
Parameter
Description
Test Condition
Min.
Typ.
Max.
Unit
Supply Current
IDD-3.3V
Combined 3.3V Supply Current
CPU0:3 =133 MHz[12]
160
mA
IDD-2.5
Combined 2.5V Supply Current
CPU0:3 =133 MHz[12]
90
mA
Logic Inputs (All referenced to VDDQ3 = 3.3V)
VIL
Input Low Voltage
GND –
0.3
0.8
V
VIH
Input High Voltage
2.0
VDD +
0.3
V
IIL
Input Low Current[13]
–25
µA
IIH
[13]
IIL
IIH
Input High Current
Input Low Current, SEL133/100#
10
µA
[13]
–5
µA
[13]
5
µA
Max.
Unit
50
mV
Input High Current, SEL133/100#
Clock Outputs
CPU, CPUdiv2, IOAPIC (Referenced to VDDQ2)
Test Condition
Min.
Typ.
VOL
Output Low Voltage
IOL = 1 mA
VOH
Output High Voltage
IOH = –1 mA
2.2
IOL
Output Low Current
VOL = 1.25V
45
65
100
mA
IOH
Output High Current
VOH = 1.25V
45
65
100
mA
Min.
Typ.
Max.
Unit
50
mV
48MHz, REF (Referenced to VDDQ3)
Test Condition
V
VOL
Output Low Voltage
IOL = 1 mA
VOH
Output High Voltage
IOH = –1 mA
3.1
IOL
Output Low Current
VOL = 1.5V
45
65
100
mA
IOH
Output High Current
VOH = 1.5V
45
65
100
mA
Min.
Typ.
Max.
Unit
50
mV
3V33, 3V66 (Referenced to VDDQ3)
Test Condition
V
VOL
Output Low Voltage
IOL = 1 mA
VOH
Output High Voltage
IOH = –1 mA
3.1
IOL
Output Low Current
VOL = 1.5V
70
100
145
mA
IOH
Output High Current
VOH = 1.5V
65
95
135
mA
V
Notes:
11. Multiple Supplies: The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required.
12. All clock outputs loaded with 6" 60Ω transmission lines with 20-pF capacitors.
13. W159 logic inputs have internal pull-up devices, except SEL133/100# (pull-ups not CMOS level).
Document #: 38-07163 Rev. *A
Page 5 of 11
W159
DC Electrical Characteristics: TA = 0°C to +70°C, VDDQ3 = 3.3V±5%, VDDQ2 = 2.5V±5% (continued)
Parameter
Description
Test Condition
Min.
Typ.
Max.
Unit
Crystal Oscillator
VTH
X1 Input Threshold Voltage[14]
1.65
V
CLOAD
Load Capacitance, Imposed on
External Crystal[15]
18
pF
CIN,X1
X1 Input Capacitance[16]
28
pF
Pin X2 unconnected
Pin Capacitance/Inductance
CIN
Input Pin Capacitance
Except X1 and X2
5
pF
COUT
Output Pin Capacitance
6
pF
LIN
Input Pin Inductance
7
nH
3.3V AC Electrical Characteristics
TA = 0°C to +70°C, VDDQ3 = 3.3V±5%, VDDQ2 = 2.5V± 5%, fXTL = 14.31818 MHz
Spread Spectrum function turned off
AC clock parameters are tested and guaranteed over stated operating conditions using the stated lump capacitive load at the
clock output.[17]
3V66 Clock Outputs, 3V66_0:3 (Lump Capacitance Test Load = 30 pF)
Parameter
Description
Test Condition/Comments
Min.
Typ.
Max.
f
Frequency
Note 18
tH
High Time
Duration of clock cycle above 2.4V
4.95
tL
Low Time
Duration of clock cycle below 0.4V
4.55
tR
Output Rise Edge Rate
Measured from 0.4V to 2.4V
1
4
V/ns
tF
Output Fall Edge Rate
Measured from 2.4V to 0.4V
1
4
V/ns
tD
Duty Cycle
Measured on rising and falling edge at 1.5V
45
55
%
tJC
Jitter, Cycle-to-Cycle
Measured on rising edge at 1.5V. Maximum difference of cycle time between two adjacent
cycles.
500
ps
tSK
Output Skew
Measured on rising edge at 1.5V
250
ps
tO
CPU to 3V66 Clock Skew
Covers all 3V66 outputs. Measured on rising
edge at 1.5V. CPU leads 3V66 outputs.
1.5
ns
fST
Frequency Stabilization
Assumes full supply voltage reached within
from Power-up (cold start) 1 ms from power-up. Short cycles exist prior to
frequency stabilization.
3
ms
Zo
AC Output Impedance
Average value during switching transition.
Used for determining series termination value.
66.6
Unit
MHz
ns
ns
0
15
Ω
Notes:
14. X1 input threshold voltage (typical) is VDD/2.
15. The W159 contains an internal crystal load capacitor between pin X1 and ground and another between pin X2 and ground. Total load placed on crystal is 18 pF;
this includes typical stray capacitance of short PCB traces to crystal.
16. X1 input capacitance is applicable when driving X1 with an external clock source (X2 is left unconnected).
17. Period, jitter, offset, and skew measured on rising edge at 1.5V.
18. 3V66 is CPU/2 for CPU =133 MHz and (2 x CPU)/3 for CPU = 100 MHz.
Document #: 38-07163 Rev. *A
Page 6 of 11
W159
3V33 Clock Outputs, 3V33_0:1 (Lump Capacitance Test Load = 30 pF)
Parameter
Description
Test Condition/Comments
Min.
[19]
Typ. Max. Unit
tP
Period
Measured on rising edge at 1.5V
30
ns
tH
High Time
Duration of clock cycle above 2.4V
12
ns
tL
Low Time
Duration of clock cycle below 0.4V
12
ns
tR
Output Rise Edge Rate
Measured from 0.4V to 2.4V
1
tF
Output Fall Edge Rate
Measured from 2.4V to 0.4V
tD
Duty Cycle
Measured on rising and falling edge at 1.5V
tJC
Jitter, Cycle-to-Cycle
tSK
4
V/ns
1
4
V/ns
45
55
%
Measured on rising edge at 1.5V. Maximum difference of
cycle time between two adjacent cycles.
500
ps
Output Skew
Measured on rising edge at 1.5V
500
ps
tO
3V66 to 3V33 Clock
Skew
Covers all 3V66 outputs. Measured on rising edge at 1.5V.
3V66 leads 3V33 output.
1.5
3.0
ns
tq
CPU to 3V33 Clock
Skew
Covers all 3V33 outputs. Measured on rising edge at 1.5V.
CPU leads 3V33 output.
1.5
4.0
ns
fST
Frequency Stabilization
from Power-up (cold
start)
Assumes full supply voltage reached within 1 ms from
power-up. Short cycles exist prior to frequency stabilization.
3
ms
Zo
AC Output Impedance
Average value during switching transition. Used for determining series termination value.
Ω
15
REF Clock Outputs, REF0:1 (Lump Capacitance Test Load = 20 pF)
Parameter
Description
Test Condition/Comments
Min.
f
Frequency, Actual
Frequency generated by crystal oscillator
tR
Output Rise Edge Rate
Measured from 0.4V to 2.4V
0.5
tF
Output Fall Edge Rate
Measured from 2.4V to 0.4V
tD
Duty Cycle
Measured on rising and falling edge at 1.5V
fST
Frequency Stabilization from
Power-up (cold start)
Assumes full supply voltage reached within
1 ms from power-up. Short cycles exist prior to
frequency stabilization.
Zo
AC Output Impedance
Average value during switching transition. Used
for determining series termination value.
Typ.
Max.
14.318
Unit
MHz
2
V/ns
0.5
2
V/ns
45
55
%
3
ms
25
Ω
Note:
19. 3V33 clock is CPU/4 for CPU = 133 MHz and CPU/3 for CPU = 100 MHz.
Document #: 38-07163 Rev. *A
Page 7 of 11
W159
48-MHZ Clock Output (Lump Capacitance Test Load = 20 pF)
Parameter
Description
Test Condition/Comments
Min.
Typ.
Max.
Unit
f
Frequency, Actual
Determined by PLL divider ratio (see m/n below)
48.008
MHz
fD
Deviation from 48 MHz
(48.008 – 48)/48
+167
ppm
m/n
PLL Ratio
(14.31818 MHz x 57/17 = 48.008 MHz)
57/17
tR
Output Rise Edge Rate
Measured from 0.4V to 2.4V
0.5
tF
Output Fall Edge Rate
Measured from 2.4V to 0.4V
tD
Duty Cycle
Measured on rising and falling edge at 1.5V
fST
Frequency Stabilization
from Power-up (cold start)
Assumes full supply voltage reached within 1 ms
from power-up. Short cycles exist prior to frequency stabilization.
Zo
AC Output Impedance
Average value during switching transition. Used
for determining series termination value.
2
V/ns
0.5
2
V/ns
45
55
%
3
ms
Ω
25
2.5V AC Electrical Characteristics
TA = 0°C to +70°C, VDDQ3 = 3.3V±5%, VDDQ2= 2.5V±5%
fXTL = 14.31818 MHz
Spread Spectrum function turned off
AC clock parameters are tested and guaranteed over stated operating conditions using the stated lump capacitive load at the
clock output.[20]
CPU Clock Outputs, CPU0:6 (Lump Capacitance Test Load = 20 pF)
CPU = 133 MHz
Parameter
Description
Test Condition/Comments
CPU = 100 MHz
Min. Typ. Max. Min.
7.65
Typ. Max. Unit
tP
Period
Measured on rising edge at 1.25V
7.5
tH
High Time
Duration of clock cycle above 2.0V
1.87
3.0
ns
tL
Low Time
Duration of clock cycle below 0.4V
1.67
2.8
ns
tR
Output Rise Edge Rate Measured from 0.4V to 2.0V
tF
Output Fall Edge Rate
Measured from 2.0V to 0.4V
1
4
tD
Duty Cycle
Measured on rising and falling edge at
1.25V
45
55
tJC
Jitter, Cycle-to-Cycle
Measured on rising edge at 1.25V. Maximum difference of cycle time between
two adjacent cycles.
tSK
Output Skew
Measured on rising edge at 1.25V
fST
Frequency Stabilization from Power-up
(cold start)
Assumes full supply voltage reached
within 1 ms from power-up. Short cycles
exist prior to frequency stabilization.
Zo
AC Output Impedance
Average value during switching transition. Used for determining series termination value.
1
4
20
10
10.2
1
ns
4
V/ns
1
4
V/ns
45
55
%
250
250
ps
175
175
ps
3
3
ms
20
Ω
Note:
20. Period, Jitter, offset, and skew measured on rising edge at 1.25V.
Document #: 38-07163 Rev. *A
Page 8 of 11
W159
CPUdiv2 Clock Outputs, CPUdiv2_0:1 (Lump Capacitance Test Load = 20 pF)
CPU = 133 MHz
Parameter
Description
Test Condition/Comments
CPU = 100 MHz
Min. Typ. Max. Min.
Typ. Max.
Unit
tP
Period
tH
tL
tR
Output Rise Edge Rate Measured from 0.4V to 2.0V
1
4
1
4
V/ns
tF
Output Fall Edge Rate
Measured from 2.0V to 0.4V
1
4
1
4
V/ns
tD
Duty Cycle
Measured on rising and falling edge at
1.25V
45
55
45
55
%
tJC
Jitter, Cycle-to-Cycle
Measured on rising edge at 1.25V. Maximum difference of cycle time between
two adjacent cycles.
250
250
ps
175
175
ps
3
3
ms
Measured on rising edge at 1.25V
15
High Time
Duration of clock cycle above 2.0V
5.25
7.5
ns
Low Time
Duration of clock cycle below 0.4V
5.05
7.3
ns
tSK
Output Skew
Measured on rising edge at 1.25V
fST
Frequency Stabilization from Power-up
(cold start)
Assumes full supply voltage reached
within 1 ms from power-up. Short cycles
exist prior to frequency stabilization.
Zo
AC Output Impedance
Average value during switching transition. Used for determining series termination value.
15.3
20
20
20.4
ns
Ω
20
APIC Clock Outputs, APIC0:2 (Lump Capacitance Test Load = 20 pF)
Parameter
Description
Test Condition/Comments
Min
Typ
Max
16.67
Unit
f
Frequency
Note 21
tR
Output Rise Edge Rate
Measured from 0.4V to 2.0V
1
4
V/ns
tF
Output Fall Edge Rate
Measured from 2.0V to 0.4V
1
4
V/ns
tD
Duty Cycle
Measured on rising and falling edge at 1.25V
45
55
%
fST
Frequency Stabilization
from Power-up (cold start)
Assumes full supply voltage reached within
1 ms from power-up. Short cycles exist prior to
frequency stabilization.
3
ms
Zo
AC Output Impedance
Average value during switching transition. Used
for determining series termination value.
20
MHz
Ω
Note:
21. APIC clock is CPU/8 for CPU = 133 MHz and CPU/6 for CPU = 100 MHz.
Ordering Information
Ordering Code
Package
Name
W159
H
Package Type
56-pin SSOP (300 mils)
Intel is a registered trademark of Intel Corporation.
Document #: 38-07163 Rev. *A
Page 9 of 11
W159
Package Diagram
56-Pin Small Shrink Outline Package (SSOP, 300 mils)
Summary of nominal dimensions in inches:
Body Width: 0.296
Lead Pitch: 0.025
Body Length: 0.625
Body Height: 0.102
Document #: 38-07163 Rev. *A
Page 10 of 11
© Cypress Semiconductor Corporation, 2001. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
W159
Document Title: W159 Spread Spectrum System FTG for SMP Systems
Document Number: 38-07163
REV.
ECN NO.
Issue
Date
Orig. of
Change
Description of Change
**
110273
11/11/01
SZV
Change from Spec number: 38-00818 to 38-07163
*A
122804
12/14/02
RBI
Add Power up Requirements to Operating Conditions Information
Document #: 38-07163 Rev. *A
Page 11 of 11