W72M64V-XBX 2Mx64 3.3V Simultaneous Operation Flash Multi-Chip Package *Preliminary FEATURES ! Access Times of 100, 120, 150ns ! Unlock Bypass Program command ! Packaging • Reduces overall programming time when issuing multiple program command sequences • 159 PBGA, 13x22mm - 1.27mm pitch ! Ready/Busy output (RY/BY) ! 1,000,000 Erase/Program Cycles • Hardware method for detecting program or erase cycle completion ! Sector Architecture • Bank 1 (8Mb): eight 4K word, fifteen 32K word ! Hardware reset pin (RESET) • Bank 2 (24Mb): forty-eight 32K word • Hardware method of resetting the internal state machine to the read mode ! Bottom boot block ! Zero Power Operation ! WP/ACC input pin ! Organized as 2Mx64 or 2x2Mx32 • Write protect (WP) function allows protection of two outermost boot sectors, regardless of sector protect status ! Commercial, Industrial and Military Temperature Ranges ! 3.3 Volt for Read and Write Operations • Acceleration (ACC) function accelerates program timing ! Simultaneous Read/Write Operation: ! Sector Protection • Data can be continuously read from one bank while executing erase/program functions in another bank • Hardware method of locking a sector, either in-system or using programming equipment, to prevent any program or erase operation within that sector • Zero latency between read and write operations ! Erase Suspend/Resume • Temporary Sector Unprotect allows changing data in protected sectors in-system • Suspends erase operations to allow programming in same bank ! Data Polling and Toggle Bits Note: For programming information refer to Flash Programming W72M64V-XBX Application Note. • Provides a software method of detecting the status of program or erase cycles * Preliminary datasheet. This datasheet describes a product that is not characterized or qualified and is subject to change without notice. November 2003 Rev. 1 1 White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com W72M64V-XBX FIG 1: PIN CONFIGURATION FOR W72M64V-XBX TOP VIEW 1 A B 2 GND VCC GND 3 GND DQ41 4 GND WE3 5 VCC VCC 6 VCC DQ57 7 8 GND GND DNU WE4 PIN DESCRIPTION 9 10 GND VCC D VCC DQ40 DQ35 DQ37 DQ39 DQ56 DQ51 DQ53 DQ55 VCC E VCC DQ32 DQ42 DQ44 DQ46 DQ48 DQ58 DQ60 DQ62 VCC F GND CS3 DQ34 DQ36 DQ38 CS4 DQ50 DQ52 DQ54 GND DQ45 DQ47 DQ49 DQ59 DQ61 DQ63 Address Inputs WE1-4 Write Enables VCC VCC DQ43 Data Inputs/Outputs A0-20 VCC C DQ33 DQ 0-63 CS1-4 Chip Selects OE Output Enable RESET Hardware Reset WP/ACC Hardware Write Protect/Acceleration RY/BY Ready/Busy Output VCC Power Supply VCC G GND OE A0 DNU VCC A12 A16 DNU* A20 GND H GND A2 WP/ACC A11 GND VCC A7 A10 A15 GND J GND A3 A6 A9 VCC GND A1 RESET A13 GND K GND A4 A17 RY/BY GND A14 A5 A18 A8 GND L GND DQ17 WE2 DQ29 DNU DQ9 DQ4 WE1 A19 GND M VCC DQ24 DQ19 DQ21 DQ31 DQ1 DQ11 DQ6 DQ15 VCC N VCC DQ16 DQ26 DQ28 DQ23 DQ8 DQ3 DQ13 DQ7 VCC P VCC CS2 DQ18 DQ20 DQ30 DQ0 DQ10 DQ5 DQ14 VCC R VCC VCC DQ25 DQ27 DQ22 CS1 DQ2 DQ12 GND VCC T VCC GND GND GND VCC VCC GND GND GND VCC Ground DNU Do Not Use BLOCK DIAGRAM WE1 * Ball G8 is DNU on this device and will become A21 on the W74M64V-XBX GND WE2 CS1 WE4 WE3 CS4 CS3 CS2 RY/BY RESET OE A0-20 VCC 2M x 16 BYTE 2M x 16 BYTE 2M x 16 BYTE 2M x 16 WP/ACC DQ0-15 White Electronic Designs Corporation • Phoenix AZ • (602) 437-1520 2 DQ16-31 DQ32-47 DQ48-63 BYTE W72M64V-XBX ABSOLUTE MAXIMUM RATINGS Parameter CAPACITANCE (TA = +25°C) Unit Parameter Symbol Conditions Max Unit Operating Temperature -55 to +125 °C Supply Voltage Range (VCC) -0.5 to +4.0 V WE1-4 capacitance CWE VIN = 0 V, f = 1.0 MHz 25 pF -0.5 to Vcc +0.5 V CS1-4 capacitance C CS VIN = 0 V, f = 1.0 MHz 25 pF -55 to +150 °C Data I/O capacitance CI/O VI/O = 0 V, f = 1.0 MHz 12 pF Address input capacitance C AD VIN = 0 V, f = 1.0 MHz 25 pF RESET capacitance C RS VIN = 0 V, f = 1.0 MHz 20 pF RY/BY capacitance C RB VIN = 0 V, f = 1.0 MHz 20 pF WP/ACC capacitance CWA VIN = 0 V, f = 1.0 MHz 30 pF Signal Voltage Range Storage Temperature Range Endurance (write/erase cycles) 1,000,000 min. cycles NOTES: 1. Stresses above the absolute maximum rating may cause permanent damage to the device. Extended operation at the maximum levels may degrade performance and affect reliability. RECOMMENDED OPERATING CONDITIONS Parameter Symbol Min Supply Voltage Max This parameter is guaranteed by design but not tested. Unit V CC 3.0 3.6 V Operating Temp. (Mil.) TA -55 +125 °C Operating Temp. (Ind.) TA -40 +85 °C DATA RETENTION Parameter Test Conditions Min Unit Pattern Data 150°C 10 Years Retention Time 125°C 20 Years DC CHARACTERISTICS - CMOS COMPATIBLE (VCC = 3.3V ± 0.3V, TA = -55°C to +125°C) Parameter Symbol Conditions Min Max Unit Input Leakage Current I LI VCC = 3.6V, VIN = GND to VCC -10 10 µA Output Leakage Current ILO VCC = 3.6V, VOUT = GND to VCC -10 10 µA VCC Active Current for Read (1) I CC1 CS = V IL, OE = V IH, f = 5MHz 65 mA VCC Active Current for Program or Erase (2,3) I CC2 CS = VIL, OE = VIH, WE = VIL 120 mA VCC Standby Current (2) I CC3 VCC Reset Current (2) I CC4 RESET = VSS ± 0.3V Automatic Sleep Mode (2,4) I CC5 VIH = VCC ± 0.3V; VIL = VSS ± 0.3V 20 µA VCC Active Read-While-Program Current (1,2) I CC6 CS = VIL, OE = VIH 180 mA VCC Active Program-While-Erase Current (1,2) I CC7 CS = VIL, OE = VIH 180 mA VCC Active Program-While-Erase-Suspended Current (2,5) ICC8 140 mA ACC Accelerated Program Current I ACC 40 120 mA CS = RESET = V CC ± 0.3V CS = VIL, OE = VIH CS = VIL, OE = VIH ACC Pin VCC Pin 20 µA 20 µA Input Low Voltage VIL -0.5 0.8 V Input High Voltage VIH 0.7 x Vcc Vcc + 0.3 V Voltage for WP/ACC Sector Protect/Unprotect and Program Acceleration VHH Vcc = 3.0V + 0.3V 8.5 9.5 V 8.5 Voltage for Autoselect and Temporary Sector Unprotect VID Vcc = 3.0V + 0.3V Output Low Voltage VOL IOL = 4.0 mA, VCC = 3.0V Output High Voltage VOH1 IOH = -2.0 mA, VCC = 3.0V Low V CC Lock-Out Voltage (5) VLKO 0.85 X 2.3 12.5 V 0.45 V VCC V 2.5 V NOTES: 1. The ICC current listed includes both the DC operating current and the frequency dependent component (at 5 MHz). The frequency component typically is less than 8 mA/MHz, with OE at VIH. 2. Maximum ICC specifications are tested with VCC = VCC MAX 3. ICC active while Embedded Algorithm (program or erase) is in progress. 4. Automatic sleep mode enables the low power mode when addresses remain stable for tACC + 30ns. 5. Not 100% tested. 3 White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com W72M64V-XBX AC CHARACTERISTICS – WRITE/ERASE/PROGRAM OPERATIONS - CS CONTROLLED (VCC = 3.3V ± 0.3V, TA = -55°C to +125°C) Parameter Symbol -100 Min Max -120 Min Max -150 Unit Min Max Write Cycle Time t AVAV tWC 100 120 150 ns Write Enable Setup Time tWLEL tWS 0 0 0 ns Chip Select Pulse Width t ELEH tCP 45 50 50 ns Address Setup Time tAVWL t AS 0 0 0 ns Data Setup Time tDVEH tDS 45 50 50 ns Data Hold Time t EHDX tDH 0 0 0 ns Address Hold Time t ELAX tAH 45 50 50 ns Chip Select Pulse Width High t EHEL tCPH 30 30 30 Duration of Byte Programming Operation (1) tWHWH1 Sector Erase Time (2) tWHWH2 Read Recovery Time Before Write (3) 300 300 15 t GHEL 0 Chip Programming Time (4) 15 0 108 ns 300 µs 15 sec 108 sec 0 108 ns 1. Typical value for tWHWH1 is 7µs. 2. Typical value for tWHWH2 is 0.7 sec. 3. Guaranteed by design, but not tested. 4. Typical value is 36 sec. The typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes program faster than the maximum program times listed. AC TEST CONDITIONS FIG 2: AC TEST CIRCUIT Parameter IOL Current Source VZ ≈ 1.5V (Bipolar Supply D.U.T. IOH White Electronic Designs Corporation • Phoenix AZ • (602) 437-1520 4 Unit VIL = 0, VIH = 2.5 V Input Rise and Fall 5 ns Input and Output Reference Level 1.5 V Output Timing Reference Level 1.5 V NOTES: V Z is programmable from -2V to +7V. I OL & I OH programmable from 0 to 16mA. Tester Impedance Z 0 = 75Ω. V Z is typically the midpoint of V OH and V OL . I OL & I OH are adjusted to simulate a typical resistive load circuit. ATE tester includes jig capacitance. CEFF = 50 pf Current Source Typ Input Pulse Levels W72M64V-XBX AC CHARACTERISTICS – WRITE/ERASE/PROGRAM OPERATIONS - WE CONTROLLED (VCC = 3.3V ± 0.3V, TA = -55°C to +125°C) Parameter Symbol -100 Min Max -120 Min Max -150 Min Max Unit Write Cycle Time tAVAV tW C 100 120 150 ns Chip Select Setup Time tELWL tCS 0 0 0 ns Write Enable Pulse Width tWLWH tWP 50 50 65 ns Address Setup Time tAVWL tAS 0 0 0 ns Data Setup Time tDVWH tDS 50 50 65 ns Data Hold Time tWHDX t DH 0 0 0 ns ns Address Hold Time tWLAX tAH 50 50 65 Write Enable Pulse Width High tWHWL tWPH 30 30 35 Duration of Byte Programming Operation (1) tWHWH1 300 300 Sector Erase (2) tWHWH2 15 15 tGHWL 0 0 0 t VCS 50 50 50 Read Recovery Time before Write (3) VCC Setup Time Chip Programming Time (4) 108 Address Setup Time to OE low during toggle bit polling tASO Address Hold Time From CS or OE high during toggle 15 ns 300 µs 15 sec ns 108 µs 108 15 sec 15 ns ns tAHT 0 0 0 Output Enable High during toggle bit polling tOEPH 20 20 20 ns Latency Between Read and Write Operations tSR/W 0 0 0 ns tRB 0 0 0 ns tBUSY 90 90 90 ns Write Recovery Time from RY/BY Program/Erase Valid to RY/BY 1. 2. 3. 4. Typical value for t WHWH1 is 7µs. Typical value for tWHWH2 is 0.7 sec. Guaranteed by design, but not tested. Typical value is 36 sec. The typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes program faster than the maximum program times listed. AC CHARACTERISTICS – READ-ONLY OPERATIONS (VCC = 3.3V ± 0.3V, T A = -55°C to +125°C) Parameter Symbol -100 -120 -150 Min Max Min Max Min Max 100 120 150 Unit Read Cycle Time tAVAV t RC Address Access Time t AVQV t ACC 100 120 150 ns Chip Select Access Time t ELQV tCE 100 120 150 ns Output Enable to Output Valid tGLQV t OE 40 50 55 ns Chip Select High to Output High Z (1) t EHQZ t DF 20 20 20 ns Output Enable High to Output High Z (1) tGHQZ t DF 20 20 20 Output Hold from Addresses, CS or OE Change, Whichever occurs first t AXQX tOH 0 0 0 t OEH 0 0 0 10 10 10 Output Enable Hold Time (1) 1. Read Toggle and Data Polling ns ns ns Guaranteed by design, not tested. 5 White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com W72M64V-XBX FIG 3: AC WAVEFORMS FOR READ OPERATIONS tRC Addresses Addresses Stable tACC CS tDF tOE OE tOEH WE tCE tOH High Z Outputs Output Valid RESET RY/BY OV White Electronic Designs Corporation • Phoenix AZ • (602) 437-1520 6 High Z W72M64V-XBX AC CHARACTERISTICS – HARDWARE RESET (RESET) Parameter Symbol -100 Min RESET Pin Low (During Embedded Algorithms) to Read Mode (See Note) tready RESET Pin Low (NOT During Embedded Algorithms) to Read Mode (See Note) tready -120 Max Min -150 Max 20 Min 20 500 500 Unit Max 20 µs 500 ns RESET Pulse Width tRP 500 500 500 ns RESET High Time Before Read (See Note) tRH 50 50 50 ns tRPD 20 20 20 µs tRB 0 0 0 ns RESET Low to Standby Mode RY/BY Recovery Time Note: Not tested. FIG 4: RESET TIMINGS NOT DURING EMBEDDED ALGORITHMS RY/BY CS, OE tRH RESET tRP tReady FIG 5: RESET TIMINGS DURING EMBEDDED ALGORITHMS tReady RY/BY tRB CS, OE RESET tRP 7 White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com W72M64V-XBX FIG 6: PROGRAM OPERATION tAS tWC Addresses 555h PA PA PA tAS CS tCH OE tWHWH1 tWP WE tCS tDS tWPH tDH A0h Data Status PD tBUSY RY/BY VCC tVCS NOTES: 1. PA is the address of the memory location to be programmed. 2. PD is the data to be programmed at byte address. 3. DOUT is the output of the data written to the device. 4. Figure indicates last two bus cycles of four bus cycle sequence. White Electronic Designs Corporation • Phoenix AZ • (602) 437-1520 8 DOUT tRB W72M64V-XBX FIG 7: ACCELERATED PROGRAM TIMING DIAGRAM VHH WP/ACC VIL or VIH VIL or VIH tVHH tVHH FIG 8: CHIP/SECTOR ERASE OPERATION TIMINGS tAS tWC Addresses 2AAh SA VA VA tAH 555h for chip erase CS tCH OE tWP WE tCS tDS tWHWH2 tWPH tDH 55h Data In Progress 30h 10 for Chip Erase tBUSY Complete tRB RY/BY tVCS VCC Notes: 1. SA = Sector Address (for Sector Erase), VA = Valid Address for reading status data 9 White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com W72M64V-XBX FIG 9: BACK TO BACK READ/WRITE CYCLE TIMINGS Valid PA Valid PA Valid RA Valid PA Addresses tWC tWC tRC tWC tAH tCPH tACC tCE CS tCP tOE OE tOEH tWP WE tGHWL tDF tWPH tDS tOH tDH Valid In Data Valid Out Valid In Valid In tSR/W WE Controlled Write Cycle Read Cycle CS Controlled Write Cycle FIG. 10: DATA POLLING TIMINGS (DURING EMBEDDED ALGORITHMS) tRC VA Addresses VA VA tACC tCE CS tCH tOE OE tOEH tDF WE tOH DQ7 Complement Complement DQ0-DQ6 Status Data Status Data True True Valid Data Valid Data High Z High Z tBUSY RY/BY NOTE: VA = Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and array data read cycle. White Electronic Designs Corporation • Phoenix AZ • (602) 437-1520 10 W72M64V-XBX FIG 11: TOGGLE BIT TIMINGS (DURING EMBEDDED ALGORITHMS) tAHT tAS Addresses tAHT tASO CS tCEPH tOEH WE tOEPH OE tDH DQ6/DQ2 tOE Valid Status Valid Status (First Read) (Second Read) Valid Data Valid Status (Stops Toggling) Valid Data RY/BY NOTE: VA = Valid address, not required for DQ6. Illustration shows first two status cycle after command sequence, last status read cycle, and array data read cycle. FIG 12: DQ2 VS. DQ6 Enter Embedded Erasing WE Erase Suspend Erase Erase Resume Enter Erase Suspend Program Erase Suspend Program Erase Suspend Read Erase Suspend Read Erase Erase Complete DQ6 DQ2 NOTE: DQ2 toggles only when read at an address within an erase-suspended sector. The system may use OE or CS to toggle DQ2 and DQ 6. 11 White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com W72M64V-XBX FIG 13: SECTOR/SECTOR BLOCK PROTECT AND UNPROTECT TIMING DIAGRAM VID RESET VIH SA, A6, A1, A0 Verify Sector/Sector Block Protect or Unprotect 60h Data Valid* Valid* Valid* Status 40h 60h Sector/Sector Block Protect: 150 µs Sector/Sector Block Unprotect: 15 ms 1 µs CS WE OE NOTES: For sector protect, A6 = 0, A1 = 1, A0 = 0. For sector unprotect, A6 = 1, A 1 = 1, A0 = 0. AC CHARACTERISTICS – ALTERNATE CS CONTROLLED ERASE AND PROGRAM OPERATIONS Parameter Speed Options JEDEC Std Description 100 tAVAV tW C Write Cycle Time (1) 120 150 Unit Min 90 120 150 tAVWL tAS ns Address Setup Time Min 0 0 0 tELAX ns tAH Address Hold Time Min 45 50 50 ns tDVEH tDS Data Setup Time Min 45 50 50 ns tEHDX t DH Data Hold Time Min 0 0 0 ns t GHEL t GHEL Read Recovery Time Before Write (OE High to WE Low) Min 0 0 0 ns ns tWLEL tWS WE Setup Time Min 0 0 0 tEHWH tW H WE Hold Time Min 0 0 0 ns tELEH tCP CS Pulse Width Min 45 50 50 ns tEHEL tCPH tW H W H1 tW H W H1 CS Pulse Width High Programming Operation Min 30 30 30 ns Typ 9 9 9 tW H W H1 tW H W H1 µs Accelerated Programming Operation, Word or Byte Typ 7 7 7 tW H W H2 tW H W H2 µs Sector Erase Operation Typ 0.7 0.7 0.7 sec Byte NOTE: 1. Not tested. White Electronic Designs Corporation • Phoenix AZ • (602) 437-1520 12 W72M64V-XBX FIG 14: ALTERNATE CS CONTROLLED WRITE (ERASE/PROGRAM) OPERATION TIMINGS 555 for Program 2AA for Erase PA for Program SA for Sector Erase 555 for Chip Erase Data Polling PA Addresses tAS tWC tAH tWH WE tGHEL OE tCP CS tWS tWHWH1 OR 2 tCPH tDS tBUSY tDH Data DQ7 tHR A0 for Program 55 for Erase DOUT PD for Program 30 for Sector Erase 10 for Chip Erase RESET RY/BY NOTES: 1. Figure indicates last two bus cycles of a program or erase operation. 2. PA = program address, SA = sector address, PD = program data. 3. DQ 7 is the complement of the data written to the device. DOUT is the data written to the device. 13 White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com W72M64V-XBX PACKAGE: 159 PBGA BOTTOM VIEW 159 Y Ø 0.762 (0.030) NOM 10 9 8 7 6 5 4 3 2 1 A B D 19.05 (0.750) NOM 1.27 (0.050) NOM 22.1 (0.870) MAX C E F G H J K L M N P R T 1.27 (0.050) NOM 0.61 (0.024) NOM 11.43 (0.450) NOM 2.03 (0.080) MAX 13.1 (0.516) MAX ALL LINEAR DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES. ORDERING INFORMATION W 7 2M64 V XXX B X WHITE ELECTRONIC DESIGNS CORP. Flash ORGANIZATION, 2M x 64 User configurable as 2 x 2M x 32 3.3V Power supply ACCESS TIME (ns) 100 = 100ns 120 = 120ns 150 = 150ns PACKAGE TYPE: B = 159 Plastic BGA, 13mm x 22mm DEVICE GRADE: M = Military Screened I = Industrial C = Commercial White Electronic Designs Corporation • Phoenix AZ • (602) 437-1520 -55°C to +125°C -40°C to +85°C 0°C to +70°C 14 W72M64V-XBX Document Title 2M x 64 Simultaneous Operation Flash Multi-Chip Package Revision History Rev # History Release Date Status Rev 0 Initial Release November 2002 Advanced Rev 1 Update (pg 1, 14, 15) November 2003 Preliminary 1.1 Change status to preliminary 1.2 Change mechanical drawing to new style 15 White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com