WSF512K32-XXX White Electronic Designs 512KX32 SRAM / FLASH MODULE FEATURES PRELIMINARY* ■ Built in Decoupling Caps and Multiple Ground Pins for Low Noise Operation ■ Access Times of 25ns (SRAM) and 70, 90ns (FLASH) ■ Weight - 13 grams typical ■ Packaging 66 pin, PGA Type, 1.385" square HIP, Hermetic Ceramic HIP (Package 402) FLASH MEMORY FEATURES ■ 100,000 Erase/Program Cycles 68 lead, Hermetic CQFP (G2T), 22.4mm (0.880") square (Package 509) 4.57mm (0.180") height. Designed to fit JEDEC 68 lead 0.990" CQFJ footprint (Fig. 2). Package to be developed. ■ Sector Architecture 8 equal size sectors of 64KBytes each Any combination of sectors can be concurrently erased. Also supports full chip erase ■ 512Kx32 SRAM ■ 512Kx32 5V Flash ■ 5 Volt Programming; 5V ± 10% Supply ■ Organized as 512Kx32 of SRAM and 512Kx32 of Flash Memory with common Data Bus ■ Embedded Erase and Program Algorithms ■ Low Power CMOS ■ Page Program Operation and Internal Program Control Time. ■ Hardware Write Protection ■ Commercial, Industrial and Military Temperature Ranges ■ TTL Compatible Inputs and Outputs * This data sheet describes a product under development, not fully characterized, and is subject to change without notice. Note: Programming information available upon request. FIG. 1 PIN CONFIGURATION FOR WSF512K32-29H2X PIN DESCRIPTION TOP VIEW 1 11 12 23 34 45 I/O8 FWE2 I/O15 I/O24 VCC I/O31 I/O9 SWE2 I/O14 I/O25 SWE4 I/O30 I/O10 GND I/O13 I/O26 FWE4 I/O29 A14 I/O11 I/O12 A7 I/O27 I/O28 A16 A10 OE A12 A4 A1 A11 A9 A17 SWE1 A5 A2 A0 A15 FWE1 A13 A6 A3 A18 VCC I/O7 A8 FWE3 I/O23 I/O0 FCS I/O6 I/O16 SWE3 I/O22 I/O1 SCS I/O5 I/O17 GND I/O21 I/O2 I/O3 I/O4 I/O18 I/O19 I/O20 22 October 2002 Rev. 7 33 44 55 I/O0-31 56 Data Inputs/Outputs A0-18 Address Inputs SWE 1-4 SRAM Write Enables SCS SRAM Chip Select OE Output Enable VCC Power Supply GND Ground NC Not Connected FWE1-4 Flash Write Enables FCS Flash Chip Select BLOCK DIAGRAM FWE1 SWE1 FWE2 SWE2 FWE3 SWE3 FWE4 SWE4 OE A0-18 SCS FCS 512K x 8 Flash 512K x 8 Flash 512K x 8 Flash 512K x 8 Flash 512K x 8 SRAM 512K x 8 SRAM 512K x 8 SRAM 512K x 8 SRAM I/O0-7 I/O8-15 I/O16-23 I/O24-31 66 1 White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com WSF512K32-XXX White Electronic Designs FIG. 2 PIN CONFIGURATION FOR WSF512K32-29G2TX PIN DESCRIPTION TOP VIEW NC A0 A1 A2 A3 A4 A5 SWE3 GND SWE4 FWE1 A6 A7 A8 A9 A10 VCC I/O0-31 9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61 I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 GND I/O8 I/O9 I/O10 I/O11 I/O12 I/O13 I/O14 I/O15 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 I/O16 I/O17 I/O18 I/O19 I/O20 I/O21 I/O22 I/O23 GND I/O24 I/O25 I/O26 I/O27 I/O28 I/O29 I/O30 I/O31 0.940" The WEDC 68 lead G2T CQFP fills the same fit and function as the JEDEC 68 lead CQFJ or 68 PLCC. But the G2T has the TCE and lead inspection advantage of the CQFP form. Data Inputs/Outputs A0-18 Address Inputs SWE1-4 SRAM Write Enables SCS SRAM Chip Select OE Output Enable VCC Power Supply GND Ground NC Not Connected FWE1-4 Flash Write Enables FCS Flash Chip Select A18 SCS SWE1 FWE4 OE A17 FWE2 FWE3 SWE2 A16 FCS A15 A14 A13 A12 A11 VCC 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 BLOCK DIAGRAM FWE1 SWE1 FWE2 SWE2 FWE3 SWE3 FWE4 SWE4 OE A0-18 SCS FCS 512K x 8 Flash White Electronic Designs Corporation Phoenix AZ (602) 437-1520 2 512K x 8 Flash 512K x 8 Flash 512K x 8 Flash 512K x 8 SRAM 512K x 8 SRAM 512K x 8 SRAM 512K x 8 SRAM I/O0-7 I/O8-15 I/O16-23 I/O24-31 WSF512K32-XXX White Electronic Designs A BSOLUTE MAXIMUM RATINGS Parameter SRAM TRUTH TABLE Symbol Min Max Unit SCS OE SWE Mode Data I/O Power TA -55 +125 °C H X X Standby High Z Standby Active Operating Temperature Storage Temperature T STG -65 +150 °C L L H Read Data Out Signal Voltage Relative to GND VG -0.5 7.0 V L H H Read High Z Active Junction Temperature TJ 150 °C L X L Write Data In Active 7.0 V Supply Voltage -0.5 V CC NOTE: 1. FCS must remain high when SCS is low. Parameter Flash Data Retention 20 years Flash Endurance (write/erase cycles) 100,000 CAPACITANCE (TA = +25°C) Test NOTE: 1. Stresses above the absolute maximum rating may cause permanent damage to the device. Extended operation at the maximum levels may degrade performance and affect reliability. RECOMMENDED OPERATING CONDITIONS Parameter Symbol Min Max Unit Supply Voltage V CC 4.5 5.5 V Input High Voltage V IH 2.2 V CC + 0.3 V Input Low Voltage V IL -0.5 +0.8 V Symbol Condition OE Capacitance C OE V IN = 0V, f = 1.0MHz Max Unit 80 pF F/S WE1-4 Capacitance C WE V IN = 0V, f = 1.0MHz 30 pF F/S CS Capacitance C CS V IN = 0V, f = 1.0MHz 50 pF D0- 31 Capacitance CI /O V IN = 0V, f = 1.0MHz 30 pF A0-18 Capacitance C AD V IN = 0V, f = 1.0MHz 80 pF This parameter is guaranteed by design but not tested. DC CHARACTERISTICS (VCC = 5.0V, VSS = 0V, TA = -55°C TO +125°C) Parameter Max Unit Input Leakage Current I LI V CC = 5.5, V IN = GND to VCC 10 µA Output Leakage Current I LO SCS = VIH, OE = VIH, VOUT = GND to VCC 10 µA I CCx32 SCS = VIL, OE = FCS = VIH, f = 5MHz, V CC = 5.5 550 mA Standby Current I SB FCS = SCS = VIH, OE = VIH, f = 5MHz, V CC = 5.5 90 mA SRAM Output Low Voltage V OL I OL = 8mA, V CC = 4.5 0.4 SRAM Output High Voltage V OH I OH = -4.0mA, V CC = 4.5 Flash V CC Active Current for Read (1) I CC1 FCS = VIL, OE = SCS = VIH 250 mA Flash V CC Active Current for Program or Erase (2) I CC2 FCS = VIL, OE = SCS = VIH 300 mA Flash Output Low Voltage V OL I OL = 12.0mA, V CC = 4.5 0.45 V Flash Output High Voltage V OH1 I OH = -2.5 mA, V CC = 4.5 0.85 x V CC Flash Output High Voltage V OH2 I OH = -100 µA, V CC = 4.5 V CC -0.4 Flash Low V CC Lock Out Voltage V LKO SRAM Operating Supply Current x 32 Mode Symbol Conditions Min 2.4 3.2 V V V V 4.2 V NOTES: 1. The ICC current listed includes both the DC operating current and the frequency dependent component (@ 5 MHz). The frequency component typically is less than 2 mA/MHz, with OE at VIH. 2. ICC active while Embedded Algorithm (program or erase) is in progress. 3. DC test conditions: VIL = 0.3V, VIH = VCC - 0.3V 3 White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com WSF512K32-XXX White Electronic Designs SRAM AC CHARACTERISTICS (VCC = 5.0V, TA = -55°C TO +125°C) Parameter Symbol Read Cycle -25 Min SRAM AC CHARACTERISTICS (VCC = 5.0V, TA = -55°C TO +125°C) Unit Parameter Max Read Cycle Time t RC 25 Address Access Time tAA Output Hold from Address Change t OH Chip Select Access Time t ACS Output Enable to Output Valid t OE Chip Select to Output in Low Z t CLZ 1 3 Output Enable to Output in Low Z t OLZ 1 0 Chip Disable to Output in High Z t CHZ 1 12 Output Disable to Output in High Z t OHZ 1 12 Symbol Write Cycle -25 Min Unit Max ns Write Cycle Time t WC 25 ns ns Chip Select to End of Write tCW 20 ns ns Address Valid to End of Write t AW 20 ns 25 ns Data Valid to End of Write t DW 15 ns 15 ns Write Pulse Width t WP 20 ns ns Address Setup Time t AS 3 ns ns Address Hold Time t AH 0 ns ns Output Active from End of Write t OW 1 3 ns Write Enable to Output in High Z t WHZ 1 25 0 Data Hold from Write Time 1. This parameter is guaranteed by design but not tested. ns 15 ns 0 t DH ns 1. This parameter is guaranteed by design but not tested. FIG. 3 AC TEST CIRCUIT AC TEST CONDITIONS Parameter I OL Current Source VZ ≈ 1.5V D.U.T. (Bipolar Supply) C eff = 50 pf I OH Current Source White Electronic Designs Corporation Phoenix AZ (602) 437-1520 4 Typ Unit Input Pulse Levels VIL = 0, VIH = 3.0 V Input Rise and Fall 5 ns Input and Output Reference Level 1.5 V Output Timing Reference Level 1.5 V NOTES: V Z is programmable from -2V to +7V. I OL & I OH programmable from 0 to 16mA. Tester Impedance Z 0 = 75 W. V Z is typically the midpoint of V OH and V OL . I OL & I OH are adjusted to simulate a typical resistive load circuit. ATE tester includes jig capacitance. WSF512K32-XXX White Electronic Designs FIG. 4 SRAM TIMING WAVEFORM - READ CYCLE tRC ADDRESS tAA SCS tRC tCHZ tACS ADDRESS tCLZ tAA SOE tOH DATA I/O tOE tOLZ DATA VALID PREVIOUS DATA VALID DATA I/O tOHZ DATA VALID HIGH IMPEDANCE READ CYCLE 1, (SCS = OE = V IL, SWE = FCS = V IH) READ CYCLE 2, (SWE = FCS = V IH) FIG. 5 SRAM WRITE CYCLE - SWE CONTROLLED tWC ADDRESS tAW tAH tCW SCS tAS tWP SWE tOW tWHZ tDW DATA I/O tDH DATA VALID WRITE CYCLE 1, SWE CONTROLLED (FCS = VIH ) FIG. 6 SRAM WRITE CYCLE - SCS CONTROLLED tWC ADDRESS tAS WS32K32-XHX tAW tAH tCW SCS tWP SWE tDW DATA I/O tDH DATA VALID WRITE CYCLE 2, SCS CONTROLLED (FCS = V IH) 5 White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com WSF512K32-XXX White Electronic Designs FLASH AC CHARACTERISTICS WRITE/ERASE/PROGRAM OPERATIONS, FWE CONTROLLED (VCC = 5.0V, TA = -55°C TO +125°C) Parameter Symbol -70 Min -90 Max Min Unit Max Write Cycle Time t AVAV t WC 70 90 ns Chip Select Setup Time t ELWL t CS 0 0 ns Write Enable Pulse Width t WLWH t WP 45 45 ns Address Setup Time t AVWL t AS 0 0 ns Data Setup Time t DVWH t DS 45 45 ns Data Hold Time t WHDX t DH 0 0 ns ns Address Hold Time t WLAX t AH 45 45 Write Enable Pulse Width High t WHWL t WPH 20 20 Duration of Byte Programming Operation (1) t WHWH1 Chip and Sector Erase Time (2) t WHWH2 Read Recovery Time Before Write ns 300 15 t GHWL 300 µs 15 sec 0 0 µs t VCS 50 50 µs Output Enable Setup Time tOES 0 0 Output Enable Hold Time (4) tOEH 10 10 VCC Set-up Time Chip Programming Time 11 Chip Erase Time (3) 11 sec ns ns 64 64 sec NOTES: 1. Typical value for tWHWH1 is 7ns. 2. Typical value for tWHWH2 is 1sec. 3. Typical value for Chip Erase Time is 8sec. 4. For Toggle and Data Polling. FLASH AC CHARACTERISTICS READ ONLY OPERATIONS (VCC = 5.0V, TA = -55°C TO +125°C) Parameter Symbol -70 Min -90 Max Unit Max Read Cycle Time t AVAV t RC Address Access Time t AVQV t ACC 70 90 ns Chip Select Access Time t ELQV t CE 70 90 ns OE to Output Valid t GLQV t OE 35 35 ns Chip Select to Output High Z (1) t EHQZ t DF 20 20 ns OE High to Output High Z (1) t GHQZ t DF 20 20 Output Hold from Address, FCS or OE Change, whichever is first tAXQX tOH 1. Guaranteed by design, not tested. White Electronic Designs Corporation Phoenix AZ (602) 437-1520 6 70 Min 0 90 0 ns ns ns WSF512K32-XXX White Electronic Designs FLASH AC CHARACTERISTICS WRITE/ERASE/PROGRAM OPERATIONS, FCS CONTROLLED (VCC = 5.0V, TA = -55°C TO +125°C) Parameter Symbol Min -70 Max Min -90 Max Unit Write Cycle Time t AVAV t WC 70 90 ns FWE Setup Time t WLEL t WS 0 0 ns FCS Pulse Width t ELEH t CP 45 45 ns Address Setup Time t AVEL t AS 0 0 ns Data Setup Time t DVEH t DS 45 45 ns Data Hold Time t EHDX t DH 0 0 ns Address Hold Time t ELAX t AH 45 45 ns FCS Pulse Width High t EHEL tCPH 20 20 ns Duration of Programming Operation (1) t WHWH1 300 300 µs Sector Erase Time (2) t WHWH2 15 15 sec Read Recovery Time t GHEL 0 0 ns Chip Programming Time 11 sec Chip Erase Time (3) 64 sec NOTES: 1. Typical value for tWHWH1 is 7ns. 2. Typical value for tWHWH2 is 1sec. 3. Typical value for Chip Erase Time is 8sec. 7 White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com WSF512K32-XXX White Electronic Designs Note: Scs = VIH White Electronic Designs Corporation Phoenix AZ (602) 437-1520 8 Outputs FWE OE FCS Addresses High Z tACC tCE tOE Addresses Stable tRC Output Valid tOH tDF High Z FIG. 7 AC WAVEFORMS FOR FLASH MEMORY READ OPERATIONS WSF512K32-XXX White Electronic Designs 9 A0H tDH tWPH Data tDS tCS FWE OE 5.0 V tWP tGHWL tWC FCS NOTES: 1. PA is the address of the memory location to be programmed. 2. PD is the data to be programmed at byte address. 3. D7 is the output of the complement of the data written to the device. 4. DOUT is the output of the data written to the device. 5. Figure indicates last two bus cycles of four bus cycle sequence. 6. SCS = VIH Addresses 5555H tAS PA PD tAH tWHWH1 Data Polling D7 PA DOUT tOE tCE tRC tDF tOH FIG. 8 WRITE/ERASE/PROGRAM OPERATION, FLASH MEMORY FWE CONTROLLED White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com WSF512K32-XXX White Electronic Designs White Electronic Designs Corporation Phoenix AZ (602) 437-1520 AAH tDS tDH VCC tVCS 10 Data FWE OE FCS Notes: 1. SA is the sector address for Sector Erase. 2. SCS = VIH Addresses tGHWL tCS tWP tWPH 55H 2AAAH 5555H tAS tAH 5555H 80H 5555H AAH 2AAAH 55H SA 10H/30H FIG. 9 AC WAVEFORMS CHIP/SECTOR ERASE OPERATIONS FOR FLASH MEMORY WSF512K32-XXX White Electronic Designs High Z tWHWH 1 or 2 D7 D7 t OE D0-D6 = Invalid D0-D6 FWE OE FCS D7 t CH tOEH tCE t OE tWHWH 1 or 2 D7 D7 Valid Data D0-D7 Valid Data D7 = Valid Data t OH t DF High Z FIG. 10 AC WAVEFORMS FOR DATA POLLING DURING EMBEDDED ALGORITHM OPERATIONS FOR FLASH MEMORY Note: SCS = VIH 11 White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com WSF512K32-XXX White Electronic Designs A0H tDH tCPH NOTES: 1. PA represents the address of the memory location to be programmed. 2. PD represents the data to be programmed at byte address. 3. D7 is the output of the complement of the data written to the device. 4. DOUT is the output of the data written to the device. 5. Figure indicates the last two bus cycles of a four bus cycle sequence. 6. SCS = VIH White Electronic Designs Corporation Phoenix AZ (602) 437-1520 12 5.0 V tDS Data FCS OE tWS tWC FWE Addresses 5555H tGHEL tCP tAS PA PD tAH tWHWH1 Data Polling D7 PA DOUT FIG. 11 WRITE/ERASE/PROGRAM OPERATION FOR FLASH MEMORY, CS CONTROLLED WSF512K32-XXX White Electronic Designs PACKAGE 509: 68 LEAD, CERAMIC QUAD FLAT PACK, CQFP (G2T) 25.15 (0.990) ± 0.26 (0.010) SQ 4.57 (0.180) MAX 22.36 (0.880) ± 0.26 (0.010) SQ 0.27 (0.011) ± 0.04 (0.002) 0.25 (0.010) REF Pin 1 R 0.25 (0.010) 24.03 (0.946) ± 0.26 (0.010) 0.19 (0.007) ± 0.06 (0.002) 1° / 7° 1.0 (0.040) ± 0.127 (0.005) 23.87 (0.940) REF DETAIL A 1.27 (0.050) TYP SEE DETAIL "A" 0.38 (0.015) ± 0.05 (0.002) 20.3 (0.800) REF The WEDC 68 lead G2T CQFP fills the same fit and function as the JEDEC 68 lead CQFJ or 68 PLCC. But the G2T has the TCE and lead inspection advantage of the CQFP form. 0.940" ALL LINEAR DIMENSIONS ARE MILLIMETERS AND PARENTHETICALLY IN INCHES 13 White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com WSF512K32-XXX White Electronic Designs PACKAGE 402: 66 PIN, PGA TYPE, CERAMIC HEX-IN-LINE PACKAGE, HIP (H2) 35.2 (1.385) ± 0.38 (0.015) SQ PIN 1 IDENTIFIER SQUARE PAD ON BOTTOM 25.4 (1.0) TYP 5.7 (0.223) MAX 3.81 (0.150) ± 0.1 (0.005) 1.27 (0.050) ± 0.1 (0.005) 0.76 (0.030) ± 0.1 (0.005) 2.54 (0.100) TYP 1.27 (0.050) TYP DIA 15.24 (0.600) TYP 0.46 (0.018) ± 0.05 (0.002) DIA 25.4 (1.0) TYP ALL LINEAR DIMENSIONS ARE MILLIMETERS AND PARENTHETICALLY IN INCHES ORDERING INFORMATION W S F 512K32 - 29 X X X LEAD FINISH: Blank = Gold plated leads A = Solder dip leads DEVICE GRADE: M = Military Screened I = Industrial C = Commercial -55°C to +125°C -40°C to +85°C 0°C to +70°C PACKAGE TYPE: H2 = Ceramic Hex In-line Package, HIP (Package 402) G2T = 22.4mm Ceramic Quad Flat Pack, CQFP (Package 509) ACCESS TIME (ns) 29 = 25ns SRAM and 90ns FLASH ORGANIZATION, 512K x 32 SRAM and Flash Flash SRAM WHITE ELECTRONIC DESIGNS CORP. White Electronic Designs Corporation Phoenix AZ (602) 437-1520 14