DS26F31MQML Quad High Speed Differential Line Drivers General Description The DS26F31M is a quad differential line driver designed for digital data transmission over balanced lines. The DS26F31M meets all the requirements of EIA Standard RS422 and Federal Standard 1020. It is designed to provide unipolar differential drive to twisted-pair or parallel-wire transmission lines. The DS26F31M offers improved performance due to the use of state-of-the-art L-FAST bipolar technology. The L-FAST technology allows for higher speeds and lower currents by utilizing extremely short gate delay times. Thus, the DS26F31M features lower power, extended temperature range, and improved specifications. The circuit provides an enable and disable function common to all four drivers. The DS26F31M features TRI-STATE ® outputs and logical OR-ed complementary enable inputs. The inputs are all LS compatible and are all one unit load. The DS26F31M offers optimum performance when used with the DS26F32 Quad Differential Line Receiver. Features n n n n n Operation from single +5.0V supply Outputs won’t load line when VCC = 0V Output short circuit protection Meets the requirements of EIA standard RS-422 High output drive capability for 100Ω terminated transmission lines Ordering Information NS Part Number SMD Part Number NS Package Number DS26F31ME/883 5962–7802302M2A E20A Package Description 20LD Leadless Chip Carrier DS26F31MJ/883 5962–7802302MEA J16A 16LD Ceramic DIP DS26F31MW/883 5962–7802302MFA W16A DS26F31MWG/883 5962–7802302MZA WG16A 16LD Ceramic FlatPack DS26F31MJ-QMLV 5962–7802302VEA J16A 16LD Ceramic DIP DS26F31MJFQMLV 5962F7802302VEA 300k rd(Si) J16A 16LD Ceramic DIP DS26F31MW-QMLV 5962–7802302VFA W16A 16LD Ceramic FlatPack DS26F31MWFQMLV 5962F7802302VFA 300k rd(Si) W16A 16LD Ceramic FlatPack DS26F31MWGFQMLV 5962F7802302VZA 300k rd(Si) WG16A 16LD Ceramic SOIC 16LD Ceramic SOIC TRI-STATE ® is a registered trademark of National Semiconductor Corporation. © 2006 National Semiconductor Corporation DS201632 www.national.com DS26F31MQML Quad High Speed Differential Line Drivers March 2006 DS26F31MQML Connection and Logic Diagrams 20-Lead Ceramic Leadless Chip Carrier (E) 16-Lead Ceramic DIP Pictured 20163207 See NS Package Number E20A 20163201 Top View See NS Package Numbers J16A, W16A, or WG16A 20163202 FIGURE 1. Logic Symbol www.national.com 2 DS26F31MQML Absolute Maximum Ratings (Note 1) −65˚C ≤ TA ≤ +175˚C Storage Temperature Range Lead Temperature (Soldering, 60 sec.) 300˚C Supply Voltage 7.0V Input Voltage 7.0V Output Voltage 5.5V Maximum Power Dissipation at 25˚C (Note 3) 450mW Thermal Resistance θJA Ceramic DIP, derate above +25˚C @ 11.4mW/˚C 88˚C/mW Ceramic Flatpack, derate above +25˚C @ 6.6 mW/˚C 151˚C/mW Leadless Chip Carrier, derate above +25˚C @ 12.3 mW/˚C 81˚C/mW θJC Ceramic DIP 14˚C/mW Ceramic Flatpack 13˚C/mW Leadless Chip Carrier 15˚C/mW Recommended Operating Range −55˚C ≤ TA ≤ +125˚C Temperature Supply Voltage 4.5V to 5.5V Radiation Features DS26F31MJFQMLV 300 krads (Si) DS26F31MWFQMLV 300 krads (Si) DS26F31MWGFQMLV 300 krads (Si) Quality Conformance Inspection Mil-Std-883, Method 5005 - Group A Subgroup Description Temp ˚C 1 Static tests at 25 2 Static tests at 125 3 Static tests at -55 4 Dynamic tests at 25 5 Dynamic tests at 125 6 Dynamic tests at -55 7 Functional tests at 25 8A Functional tests at 125 8B Functional tests at -55 9 Switching tests at 25 10 Switching tests at 125 11 Switching tests at -55 12 Settling time at 25 13 Settling time at 125 14 Settling time at -55 3 www.national.com DS26F31MQML DS26F31M Electrical Characteristics DC Parameters (Note 8) Symbol Parameter Conditions Notes Min 2.0 VIH Logical "1" Input Voltage VCC = 4.5V (Note 4) VIL Logical "0" Input Voltage VCC = 5.5V (Note 4) VOH Logical "1" Output Voltage VCC = 4.5V, IOH = -20mA, VIL = 0.8V, VIH = 2V VOL Logical "0" Output Voltage VCC = 4.5V, IOL = 20mA, VIL = 0.8V, VIH = 2V Max Units Subgroups V 1, 2, 3 0.8 V 1, 2, 3 V 1, 2, 3 0.5 V 1, 2, 3 1, 2, 3 2.5 IIH Logical "1" Input Current VCC = 5.5V, VI = 2.7V (Note 7) -2.0 20 µA IIL Logical "0" Input Current VCC = 5.5V, VI = 0.4V (Note 7) 100 -200 µA 1, 2, 3 II Input Reverse Current VCC = 5.5V, VI = 7V (Note 7) -0.01 0.1 mA 1, 2, 3 IOZ TRI-STATE Output Current VCC = 5.5V, VO = 0.5V -20 µA 1, 2, 3 VCC = 5.5V, VO = 2.5V 20 µA 1, 2, 3 -1.5 V 1, 2, 3 mA 1, 2, 3 VI Input Clamp Voltage VCC = 4.5V, II = -18mA ISC Min Output Short Circuit Current VCC = 5.5V, VO = 0V ISC Max Output Short Circuit Current VCC = 5.5V, VO = 0V -150 mA 1, 2, 3 ICC Dis Power Supply Current VCC = 5.5V, VI = 0.8V or 2V, VEn = 0.8V, VEn = 2V 50 mA 1, 2, 3 ICC En Power Supply Current VCC = 5.5V, VEn = 2V, VEn = 0.8V 40 mA 1, 2, 3 Max Units Subgroups (Note 5) 16 nS 9 (Note 5) 24 nS 10, 11 -30 AC Parameters - Propagation Delay Time The following conditions apply, unless otherwise specified. AC: VCC = 5V, CL = 50pF or equivalent impedance provided by diode load Symbol tPLH Parameter Conditions Input to Output CL = 30pF tPHL Input to Output CL = 30pF tLZ Disable Time CL = 10 pF tHZ Disable Time CL = 10 pF tZL Enable Time CL = 30pF www.national.com 4 Notes Min (Note 6) 15 nS 9 (Note 6) 23 nS 10, 11 (Note 5) 17 nS 9 10, 11 (Note 5) 25 nS (Note 6) 15 nS 9 (Note 6) 23 nS 10, 11 (Note 5) 38 nS 9 (Note 5) 56 nS 10, 11 (Note 6) 35 nS 9 (Note 6) 53 nS 10, 11 (Note 5) 23 nS 9 (Note 5) 30 nS 10, 11 (Note 6) 20 nS 9 10, 11 (Note 6) 27 nS (Note 5) 28 nS 9 (Note 5) 40 nS 10, 11 (Note 6) 25 nS 9 (Note 6) 37 nS 10, 11 (Continued) AC Parameters - Propagation Delay Time (Continued) The following conditions apply, unless otherwise specified. AC: Symbol tZH VCC = 5V, CL = 50pF or equivalent impedance provided by diode load Parameter Conditions Enable Time Min (Note 5) CL = 30 pF Skew Notes Output to Output CL = 30pF Max Units Subgroups 32 nS 9 10, 11 (Note 5) 52 nS (Note 6) 30 nS 9 (Note 6) 50 nS 10, 11 (Note 5) 6.0 nS 9 (Note 5) 9.0 nS 10, 11 (Note 6) 4.5 nS 9 (Note 6) 7.0 nS 10, 11 DC Drift Parameters This section applies to -QMLV devices only and shall be read & recorded at TA = +25˚C before and after each burn-in & Subgroup B5, and shall not change by more than the limits indicated. The delta rejects shall be included in the PDA calculations. Symbol Parameter Conditions Notes Min Max Units Subgroups VOH Logical "1" Output Voltage VCC = 4.5V, IOH = -20mA, VIL = 0.8V, VIH = 2V. -250 250 mV 1 VOL Logical "0" Output Voltage VCC = 4.5V, IOL = 20mA, VIL = 0.8V, VIH = 2V. -50 50 mV 1 ICC En Power Supply Current VCC = 5.5V, VI = 0.8V or 2V, VEn = 2V, VEn = 0.8V. -8.0 8.0 mA 1 ICC Dis Power Supply Current VCC = 5.5V, VI = 0.8V or 2V, VEn = 0.8V, VEn = 2V. -8.0 8.0 mA 1 Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test conditions. Note 2: All currents into the device pins are positive; all currents out of the device pins are negative. All voltages are referenced to ground unless otherwise specified. Note 3: Power dissipation must be externally controlled at elevated temperatures. Note 4: Parameter tested go-no-go only. Note 5: Tested at 50pF, system capacitance exceed 10 and 30pF. Note 6: Testing at 50pF guarantees limits at 10 and 30pF. Note 7: The minimum limits apply to device Class Q & V. The limits specified for the INPUT LOW CURRENT represents the numerical range in which this parameter will pass. Note 8: Pre and post irradiation limits are identical to those listed under AC and DC electrical characteristics, except as listed in the Post Radiation Limits Table — if applicable. Radiation end point limits for the noted parameters are guaranteed only for the conditions, as specified. 5 www.national.com DS26F31MQML DS26F31M Electrical Characteristics DS26F31MQML Test Circuit and Timing Waveforms 20163203 FIGURE 2. AC Load Test Circuit for TRI-STATE Outputs 20163204 FIGURE 3. Propagation Delay (Notes 1, 2) 20163205 FIGURE 4. Enable and Disable Times (Note 2) Note 9: Diagram shown for Enable Low. Switches S1 and S2 open. Note 10: S1 and S2 of Load Circuit are closed except where shown. Note 11: Pulse Generator for all Pulses: Rate ≤ 1.0 MHz, ZO = 50Ω, tr ≤ 6.0 ns, tf ≤ 6.0 ns. Note 12: CL includes probe and jig capacitance. www.national.com 6 DS26F31MQML Typical Application 20163206 FIGURE 5. Typical Application 7 www.national.com DS26F31MQML Revision History Released 03/01/06 www.national.com Revision A Section Originator New Release, Corporate format L. Lytle 8 Changes 1 MDS data sheet converted into one Corp. data sheet format. MNDS26F31M-X-RH Rev 0B0 will be archived. DS26F31MQML Physical Dimensions inches (millimeters) unless otherwise noted 20-Lead Ceramic Leadless Chip Carrier (E) NS Package Number E20A 16-Lead Ceramic Dual-In-Line Package (J) NS Package Number J16A 9 www.national.com DS26F31MQML Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 16-Lead Ceramic Flatpak (W) NS Package Number W16A 16-Lead Ceramic SOIC (WG) NS Package Number WG16A www.national.com 10 DS26F31MQML Quad High Speed Differential Line Drivers Notes National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications. For the most current product information visit us at www.national.com. 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