DS16F95QML EIA-485/EIA-422A Differential Bus Transceiver General Description The DS16F95 Differential Bus Transceiver is a monolithic integrated circuit designed for bidirectional data communication on balanced multipoint bus transmission lines. The transceiver meets EIA standard RS-485 as well as RS-422A. The DS16F95 offers improved performance due to the use of state-of-the-art L-FAST bipolar technology. The L-FAST technology allows for higher speeds and lower currents by utilizing extremely short gate delay times. Thus, the DS16F95QML features lower power, extended temperature range and improved specifications. The DS16F95 combines a TRI-STATE ® differential input line receiver, both of which operate from a single 5.0V power supply. The driver and receiver have an active Enable that can be externally connected to function as a direction control. The driver differential outputs and the receiver differential inputs are internally connected to form differential input/ output (I/O) bus ports that are designed to offer minimum loading to the bus whenever the driver is disabled or when VCC = 0V. These ports feature wide positive and negative common mode voltage ranges, making the device suitable for multipoint applications in noisy environments. The driver is designed to accommodate loads of up to 60 mA of sink or source current and features positive and negative current limiting in addition to thermal shutdown for protection from line fault conditions. The DS16F95 can be used in transmission line applications employing the DS96F172 and the DS96F174 quad differential line drivers and the DS96F173 and DS96F175 quad differential line receivers. Features n n n n n n n n n n n n Radiation features DS16F95 guaranteed to 300k rd(Si) Meets EIA-485 and EIA-422A Meets SCSI-1 (5 MHZ) specifications Designed for multipoint transmission Wide positive and negative input/output bus voltage ranges Thermal shutdown protection Driver positive and negative current-limiting High impedance receiver input Receiver input hysteresis of 50 mV typical Operates from single 5.0V supply Reduced power consumption Pin compatible with DS3695 and SN75176A Ordering Information NS PART NUMBER SMD PART NUMBER NS PACKAGE NUMBER PACKAGE DISCRIPTION DS16F95E/883 5962–89615012A E20A 20LD LCC DS16F95J/883 5962–8961501PA J08A 8LD CERDIP DS16F95J-QMLV 5962–8961501VPA J08A 8LD CERDIP DS16F95JFQML 5962F8961501QPA 300k rd(Si) J08A 8LD CERDIP DS16F95JFQMLV 5962F8961501VPA 300k rd(Si) J08A 8LDS CERDIP 5962–8961501HA W10A 10LD CERPACK W10A 10LD CERPACK 5962–8961501VHA W10A 10LD CERPACK DS16F95W-SMD DS16F95W/883 DS16F95W-QMLV DS16F95WFQML 5962F8961501QHA 300k rd(Si) W10A 10LD CERPACK DS16F95WFQMLV 5962F8961501VHA 300k rd(Si) W10A 10LD CERPACK DS16F95WG/883 5962–8961501QXA WG10A 10LD Ceramic SOIC DS16F95WG-QMLV 5962–8961501VXA WG10A 10LD Ceramic SOIC DS16F95WGFQML 5962F8961501QXA 300k rd(Si) WG10A 10LD Ceramic SOIC DS16F95WGFQMLV 5962F8961501VXA 300k rd(Si) WG10A 10LD Ceramic SOIC TRI-STATE ® is a registered trademark of National Semiconductor Corporation. © 2005 National Semiconductor Corporation DS201425 www.national.com DS16F95QML EIA-485/EIA-422A Differential Bus Transceiver September 2005 DS16F95QML Connection Diagrams 20-Lead Ceramic Leadless Chip Carrier 20142521 See NS Package Number E20A 8-Lead Dual-In-Line Package 20142501 See NS Package Number J08A 10-Lead Flatpak/SOIC Package 20142522 See NS Package Number W10A, WG10A www.national.com 2 DS16F95QML Logic Diagram 20142520 Function Tables Driver Driver Input Enable Outputs DI DE A H H H L L H L H X L Z Z B Receiver Differential Inputs Enable Output A–B RE RO VID ≥ 0.2V L H VID ≤ −0.2V L L X H Z H = High Level L = Low Level X = Immaterial Z = High Impedance (Off) 3 www.national.com DS16F95QML Absolute Maximum Ratings (Note 1) −65˚C ≤ TA ≤ +175˚C Storage Temperature Range Lead Temperature (Soldering, 60 sec.) 300˚C Maximum Power Dissipation at 25˚C (Note 2) LCC ’E’ Package 1800 mW Cerdip ’J’ Package 1274 mW Cerpack ’W’ Package 725 mW Ceramic SOIC ’WG’ Package 725 mW Supply Voltage 7.0V Input Voltage (Bus Terminal) +15V/−10V Enable Input Voltage 5.5V Junction Temperature (TJ) +175˚C Thermal Resistance θJA 83˚C/W @ 0.5W 118˚C/W @ 1.0W 207˚C/W @ 0.5W 207˚C/W @ 0.5W LCC ’E’ Package Cerdip ’J’ Package Cerpack ’W’ Package Ceramic SOIC ’WG’ Package θJC LCC ’E’ Package Cerdip ’J’ Package Cerpack ’W’ Package Ceramic SOIC ’WG’ Package 17˚C/W 14˚C/W 18˚C/W 18˚C/W ESD Tolerance (Note 3) 500V Recommended Operating Conditions Supply Voltage (VCC) 4.50 to 5.50V Voltage at Any Bus Terminal (Separately or Common Mode) (VI or VCM) −7.0V to +12V Differential Input −7.0V to ± 12V Voltage (VID) Output Current HIGH (IOH) Driver Receiver −60mA −400µA Output Current LOW (IOL) Driver Receiver 60mA 16mA Operating Temperature (TA) −55˚C to +125˚C www.national.com 4 DS16F95QML Quality Conformance Inspection MIL-STD-883, Method 5005 - Group A Subgroup Description 1 Static tests at Temp ( C) +25 2 Static tests at +125 3 Static tests at -55 4 Dynamic tests at +25 5 Dynamic tests at +125 6 Dynamic tests at -55 7 Functional tests at +25 8A Functional tests at +125 8B Functional tests at -55 9 Switching tests at +25 10 Switching tests at +125 11 Switching tests at -55 DC - Driver Electrical Characteristics (Note 10) The following conditions apply to all parameters, unless otherwise specified. VCC = 5.5V Symbol Parameter VOD1 Differential Vout VOD2 Differential Vout Figure 1 VCC = 4.5V, RL = 100Ω Delta VOD Change In Differential Vout VCC = 4.5V, RL = 100Ω (Note 4) -200 200 VCC = 4.5V, RL = 54Ω (Note 4) -200 (Note 4) (Note 4) Delta VOC Conditions Notes Unit Sub-group 6 V 1, 2, 3 VCC = 5.5V, IO = 0A, VIN = 2V 6 V 1, 2, 3 V 1, 2, 3 V 1, 2, 3 mV 1, 2, 3 200 mV 1, 2, 3 -200 200 mV 1, 2, 3 -200 200 mV 1, 2, 3 RL = 100Ω 3 V 1, 2, 3 RL = 54Ω 3 V 1, 2, 3 2 VCC = 4.5V, RL = 54Ω Change In Common Mode Vout VCC = 4.5V, RL = 100Ω Common Mode Vout Max VCC = 5.5V, IO = 0A, VIN = .8V VCC = 4.5V, RL = 54Ω VOC Min 1.5 IIH Logical "1" Input Current VI = 2.4V 20 uA 1, 2, 3 IO Output Current Output Disable, VO = 12V 1 mA 1, 2, 3 mA 1, 2, 3 mA 1, 2, 3 mA 1, 2, 3 Output Disable, VO = -7V (Note 5) -0.8 1 VCC = 0, Output Disable, VO = 12V (Note 5) -0.8 VIN = 3V, VOUT = -7V (Note 5) -250 VIN = 3V, VOUT = 0V (Note 5) -150 VCC = 0, Output Disable, VO = -7V IOS Output Short Circuit VIN = 3V, VOUT = VCC 150 1, 2, 3 1, 2, 3 mA 1, 2, 3 VIN = 3V, VOUT = 12V 250 mA 1, 2, 3 VIN = 0V, VOUT = 12V 250 mA 1, 2, 3 VIN = 0V, VOUT = VCC VOH mA mA mA 1, 2, 3 VIN = 0V, VOUT = -7V (Note 5) -250 mA 1, 2, 3 VIN = 0V, VOUT = 0V (Note 5) -150 mA 1, 2, 3 3 V 1, 2, 3 Logical "1" Output Voltage VCC = 4.5V, IO = -20mA VOL Logical "0" Output Voltage VCC = 4.5V, IO = 20mA VOD3 Differential Vout VCM = -7V to 12V 150 2 1 5 V 1, 2, 3 V 1, 2, 3 www.national.com DS16F95QML DC - Receiver Electrical Characteristics (Note 10) The following conditions apply to all parameters, unless otherwise specified. VCC = 5.5V Symbol Parameter Conditions VOH Logical "1" Output Voltage Figure 2 VCC = 4.5V, VLD = 200mV, IOH = -400uA Logical "0" Output Voltage Figure 2 VCC = 4.5V, VLD = -200mV, IOL = 8mA VCC = 4.5V, VLD = -200mV, IOL = 16mA VOL II Line Input Current Notes Min Max Unit Sub-group V 1, 2, 3 .45 V 1, 2, 3 .5 V 1, 2, 3 1 mA 1, 2, 3 mA 1, 2, 3 mA 1, 2, 3 mA 1, 2, 3 2.5 Untested Input = 0V, VI = 12V Untested Input = 0V, VI = -7V (Note 5) VCC = 0V, Untested Input = 0V, VI = 12V (Note 5) -.8 1 -.8 VCC = 0V, Untested Input = 0V, VI = -7V IIH Logical "1" Input Current VI = 2.7V (Receiver) uA 1, 2, 3 RIN Input Resistance Untested Input = 0V, VI = 12V (Note 6) 10 KΩ 1, 2, 3 Untested Input = 0V, VI = -7V (Note 6) 10 KΩ 1, 2, 3 VCC = 0V, Untested Input = 0V, VI = 12V (Note 6) 10 KΩ 1, 2, 3 VCC = 0V, Untested Input = 0V, VI = -7V (Note 6) 10 KΩ 1, 2, 3 uA 1, 2, 3 20 IOZ High Impedance State VI = .4V VI = 2.4V -20 20 uA 1, 2, 3 IOS Output Short Circuit VIN = 1V, VOUT = 0V -85 -15 mA 1, 2, 3 VTH Differential Input High Threshold VCC = 4.5V, VO = 2.5V, VCM = 12V & 0V & -7V, IO = -.4mA .2 V 1, 2, 3 VCC = 5.5V, Vo = 2.5V, VCM = 12V & 0V & -7V, IO = -.4mA .2 V 1, 2, 3 VT1 VTH+ (VTH-) -20 20 Differential Input Low Threshold VCC = 4.5V, VO = .5V, VCM = 12V & 0V & -7V, IO = 8mA -.2 V 1, 2, 3 VCC = 5.5V, VO = .5V, VCM = 12V & 0V & -7V, IO = 8mA -.2 V 1, 2, 3 VCC = 4.5V, VCM = 0V 35 mV 1, 2, 3 VCC = 5.5V, VCM = 0V 35 mV 1, 2, 3 Hyteresis www.national.com 6 (Note 10) The following conditions apply to all parameters, unless otherwise specified. VCC = 5.5V Symbol Parameter Conditions ICC Supply Current ICC Both Disable Max Unit Sub-group RE = 2V, DE = .8V 25 mA 1, 2, 3 28 mA 1, 2, 3 ICC Supply Current ICC Both Enable RE =.8V, DE = 2V VIC Input Clamp Volt II = -18mA VIH Logical "1" Input Voltage VIL Logical "0" Input Voltage VIH Logical "1" Enable Input Voltage VIL Logical "0" Enable Input Voltage I IL Logical "0" Input Current Notes Min -1.3 V 1, 2, 3 2 V 1, 2, 3 V 1, 2, 3 V 1, 2, 3 V 1, 2, 3 uA 1, 2, 3 .8 2 .8 VI = .4V AC - Driver Electrical Characteristics (Note 5) -50 (Note 10) The following conditions apply to all parameters, unless otherwise specified. VCC = 5V, PRR = 1MHZ, TR ≤ TF ≤ 6nS, 50% duty cycle, AMP = 3V, VLO, ZOUT = 50Ω Symbol Parameter tDD Differential Output Delay Time Figure 3 tTD tPLH tPHL Notes Min Max Unit Sub-group (Note 9) 8 25 nS 9 (Note 9) 8 30 nS 10, 11 (Notes 8, 9) 8 25 nS 9 (Notes 8, 9) 8 30 nS 10, 11 Propagation Delay Time Low to RL = 27Ω High Figure 4 6 18 nS 9 6 25 nS 10, 11 Propagation Delay Time high to RL = 27Ω Low Figure 4 6 18 nS 9 6 25 nS 10, 11 35 nS 9 45 nS 10, 11 40 nS 9 50 nS 10, 11 30 nS 9 40 nS 10, 11 30 nS 9 40 nS 10, 11 6 nS 9 12 nS 10, 11 Differential Output Transition Time Figure 3 Conditions RL = 60Ω RL = 60Ω Output Enable Time to H Figure 5 RL = 110Ω tPZL Output Enable Time to L Figure 6 RL = 110Ω tPHZ Output Disable Time to H Figure 5 RL = 110Ω Output Disable Time to L Figure 6 RL = 110Ω tPZH tPLZ TSKEW Differential Output Skew Time Figure 3 7 www.national.com DS16F95QML DC - Both Driver and Receiver Electrical Characteristics DS16F95QML AC - Receiver Electrical Characteristics (Note 10) The following conditions apply to all parameters, unless otherwise specified. VCC = 5V, PRR = 1MHZ, TR ≤ TF ≤ 6nS, 50% duty cycle, AMP = 3V, VLO, ZOUT = 50Ω Symbol tPLH tPHL tPZH tPZL Parameter Conditions Notes Min Max Unit Sub-group Propagation Delay Time Low to CL = 15pF High Figure 7 10 27 nS 9 10 38 nS 10, 11 Propagation Delay Time High to Low Figure 7 CL = 15pF 10 27 nS 9 10 38 nS 10, 11 Output Enable Time to H Figure 8 CL = 15pF 20 nS 9 30 nS 10, 11 Output Enable Time to L Figure 8 CL = 15pF 20 nS 9 |tPLH - tPHL| Output to Output Delay Time Figure 7 tPHZ Output Disable Time From H Figure 8 CL = 20pF CL = 5pF tPLZ Output Disable Time From L Figure 8 30 nS 10, 11 8 nS 9 16 nS 10, 11 (Notes 7, 15) 30 nS 9 (Note 7) 40 nS 10, 11 (Note 7) 20 nS 9 (Note 7) 30 nS 10, 11 20 nS 9 30 nS 10, 11 CL = 5pF Note 1: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the devices should be operated at these limits. The tables of “Electrical Characteristics” provide conditions for actual device operation. Note 2: Above TA = 25˚C, derate E package 12.1mW˚C, J package 8.5 mW/˚C, W & WG package 4.8mW/˚C. Note 3: Human body model, 1.5kΩ in series with 100pF Note 4: ∆|VOD| and ∆|VOC| are the changes in magnitude of VOD and VOC, respectively, that occur when the input is changed from a high level to a low level. Note 5: Negative sign of the limits indicates the direction of the current flow only. Note 6: RIN is guaranteed by testing “Line Input Current” (II). Note 7: Testing at 20pF assures conformance to spec at 5pF. Note 8: tTD = Non-inverting output rise time + inverting output fall time / 2, Non-inverting output fall time + inverting output rise time / 2. Note 9: Rise time 20% to 80%, Fall time 80% to 20%. Note 10: Pre and post irradiation limits are identical to those listed under A C and DC electrical characteristics. These parts may be dose rate sensitive in a space environment and demonstrate enhanced low dose rate effect. Radiation end point limits for the noted parameters are guaranteed only for the conditions as specified in MIL-STD 883, Method 1019, condition A. Parameter Measurement Information 20142502 FIGURE 1. Driver VOD and VOC (Note 14) 20142503 FIGURE 2. Receiver VOH and VOL www.national.com 8 DS16F95QML Parameter Measurement Information (Continued) 20142504 20142505 tSKEW = |tPLHD–tPHLD| FIGURE 3. Driver Differential Output Delay and Transition Times (Notes 11, 13) 20142506 20142507 FIGURE 4. Driver Propagation Times (Notes 11, 12) 9 www.national.com DS16F95QML Parameter Measurement Information (Continued) 20142509 20142508 FIGURE 5. Driver Enable and Disable Times (tZH, tHZ) (Notes 11, 12, 13) 20142511 20142510 FIGURE 6. Driver Enable and Disable Times (tZL, tLZ) (Notes 11, 12, 13) 20142513 20142512 FIGURE 7. Receiver Propagation Delay Times (Notes 11, 12) www.national.com 10 DS16F95QML Parameter Measurement Information (Continued) 20142517 20142514 20142518 20142515 20142516 FIGURE 8. Receiver Enable and Disable Times (Notes 11, 12, 14) Note 11: The input pulse is supplied by a generator having the following characteristics: PRR = 1.0 MHz, 50% duty cycle, tr ≤ 6.0 ns, tf ≤ 6.0 ns, ZO = 50Ω. Note 12: CL includes probe and stray capacitance. Note 13: DS16F95 Driver enable is Active-High. Note 14: All diodes are 1N916 or equivalent. Note 15: Testing at 20 pF assures conformance to 5 pF specification. 11 www.national.com DS16F95QML Typical Application 20142519 The line should be terminated at both ends in its characteristic impedance, typically 120Ω. Stub lengths off the main line should be kept as short as possible. www.national.com 12 Date Released Revision A Section Originator New Release, Corporate format 13 R. Malone Changes 1 MDS data sheet converted into Corporate data sheet format. MDS data sheet MNDS16F95-X-RH, Rev. 0A1 will be Archived. www.national.com DS16F95QML Revision History DS16F95QML Physical Dimensions inches (millimeters) unless otherwise noted 20-Lead Ceramic Leadless Chip Carrier (E) NS Package Number E20A 8 Narrow Lead Ceramic Dual-In-Line Package (J) NS Package Number J08A www.national.com 14 DS16F95QML Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 10-Lead Ceramic SOIC (WG) NS Package Number WG10A 10-Lead Ceramic Flatpak (W) NS Package Number W10A 15 www.national.com DS16F95QML EIA-485/EIA-422A Differential Bus Transceiver Notes National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications. For the most current product information visit us at www.national.com. LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. 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