74GTL1655 16 BIT LVTTL TO GTL/GTL + UNIVERSAL BUS TRANSCEIVERS WITH LIVE INSERTION ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ HIGH SPEED GTL/GTL+ UNIVERSAL TRANSCEIVER : tPD = 4.6 ns (MAX.) A to B at VCC = 3V COMBINES D-TYPE LATCHES AND D-TYPE FLIP-FLOPS FOR OPERATION IN TRANSPARENT, LATCHED, OR CLOCKED MODE OPERATING VOLTAGE RANGE: VCC(OPR) = 3.0V to 3.6V SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL=24mA (MIN) at VCC = 3V (A PORT) OUTPUT IMPEDANCE: IOL = 100mA (MIN) at VCC = 3V (B PORT) HIGH-IMPEDANCE STATE DURING POWER UP AND POWER DOWN up to Vcc=1.5V PERMITT LIVE INSERTION B-PORT PRECHARGED BY BIASVcc REDUCE NOISE ON THE LINE DURING LIVE INSERTION EDGE RATE-CONTROL INPUT CONFIGURES THE B-PORT OUTPUT RISE AND FALL TIMES BUS HOLD ON DATA INPUTS ELIMINATES THE NEED FOR EXTERNAL PULL-UP/ PULL-DOWN RESISTORS (A PORT) DISTRIBUTED VCC AND GND PIN CONFIGURATION MINIMIZES HIGH-SPEED SWITCHING NOISE IN PARALLEL COMUNICATIONS . PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 1655 TSSOP ORDER CODES PACKAGE TSSOP TUBE T &R 74GTL1655TTR PIN CONNECTION DESCRIPTION The 74GTL1655 devices are 16-bit high-drive (100mA), low-output-impedance universal bus transceivers designed for backplane applications. The 74GTL1655 devices provide live-insertion capability for backplane applications by tolerating active signals on the data ports when the devices are powered off. In addition, a biasing pin preconditions the GTL/GTL+ port to minimize disruption to an active backplane. The edge rate-control (VERC) input is provided so the rise and fall time of the B outputs can be configured to optimize for various backplane loading conditions. Data flow in each direction is controlled by output-enable (OEAB and OEBA), December 2001 1/14 74GTL1655 latch-enable (LEAB and LEBA), and clock (CLK) inputs. For A-to-B data flow, the devices operate in the transparent mode when LEAB is high. When LEAB is low, the A data is latched if CLK is held at a high or low logic level. If LEAB is low, the A data is stored in the latch/flip-flop on the low-to-high transition of CLK. When OEAB is low, the outputs are active. When OEAB is high, the outputs are in the high-impedance state. Data flow for B to A is similar to that of A to B, but uses OEBA, LEBA, and CLK. The output enable (OE) is used to disable both ports simultaneously. Active bus-hold circuitry is provided on the A port to hold unused or floating data inputs at a valid logic level. When VCC is between 0 and 1.5 V, the device is in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 1.5V , OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. All input and output are equipped with protection circuits against static discharge, giving them 2KV ESD immunity and transient excess voltage. INPUT AND OUTPUT EQUIVALENT CIRCUIT PIN DESCRIPTION PIN N° SYMBOL 1, 2 4, 6, 7, 9, 11, 13, 14, 16 17, 19, 20, 22, 23, 25, 27, 29 31, 32 33 34, 35 36 1OEAB, 1OEBA 1A1 to 1A8 2A1 to 2A8 2OEAB, 2OEBA OE 2LEBA, 2LEAB BIAS VCC 37, 38, 40, 42, 43, 45, 46, 48 41 2B8 to 2B1 V REF Data Inputs/Outputs GTL/GTL+ GTL Voltage Reference Input 49, 51, 52, 54, 55, 56, 58, 59 61 2A1 to 2A8 VERC Data Inputs/Outputs GTL/GTL+ Edge Rate Control 62, 63 64 1LEBA, 1LEAB CLK 5, 8, 10, 12, 18, 21, 24, 26, 30, 39, 44, 47, 53, 57, 60 3, 15, 28, 50 GND Ground (0V) VCC Positive Supply Voltage 2/14 NAME AND FUNCTION Output Enable Input Data Inputs/Outputs LVTTL Data Inputs/Outputs LVTTL Output Enable Input Output Enable Input Latch Enable Pre-Charge Supply Voltage Latch Enable Clock Input (LOW to HIGH edge triggered) 74GTL1655 FUNCTION TABLE (1) INPUTS OUTPUT MODE OEAB LEAB CLK A B H L L X H H X X X X L H Z L H L L L L Registered L L H H Registered L L X B0(2) Previous State X (3) Previous State L H L L Isolation Transparent Transparent B0 1) A to B data flow is shown. B to A flow is similar, but uses OEBA, LEBA and CLK 2) Output level before the indicated steady-state input conditions were established, provided that CLK was high before LEAB went low 3) Output level before the indicated steady-state input conditions were established OUTPUT ENABLE TRUTH TABLE INPUTS OUTPUTS OE OEAB OEBA A PORT B PORT L L L L H L L H H X L H L H X Active Z Active Z Z Active Active Z Z Z B-PORT EDGE RATE CONTROL (VERC) TRUTH TABLE INPUT VERC LOGIC LEVEL OUTPUT B PORT EDGE RATE NOMINAL VOLTAGE H VCC Slow L GND Fast 3/14 74GTL1655 LOGIC DIAGRAM 4/14 74GTL1655 ABSOLUTE MAXIMUM RATINGS Symbol Value Unit VCC Supply Voltage, Bias VCC Parameter -0.5 to +4.6 V VIA DC Input Voltage A Side, Control Input -0.5 to +4.6 V VIB DC Input Voltage B Side, VERC , VREF -0.5 to +4.6 V VOA DC Output Voltage A Side -0.5 to +4.6 V VOB DC Output Voltage B Side -0.5 to +4.6 V - 50 mA IIK DC Input Diode Current IOK DC Output Diode Current - 50 mA IOA DC Output Current A Side ± 48 mA IOB DC Output Current B Side in the Low State Tstg Storage Temperature TL Lead Temperature (10 sec) 200 mA -65 to +150 °C 300 °C Absolute Maximum Rating are those value beyond which damage to the device may occur. Functional operation under these condition is not implied RECOMMENDED OPERATING CONDITIONS Value Symbol Parameter VCC Supply Voltage VTT Termination Voltage VREF VI VIH V IL Unit Min. Typ. Max. 3.0 3.3 3.6 GTL GTL+ GTL GTL+ B port 1.14 1.35 0.74 0.87 1.2 1.5 0.8 1 0 1.26 1.65 0.87 1.1 VTT other 0 VCC High Level Input Voltage B port VREF+0.05 2 Low Level Input Voltage other B port Supply Voltage Input Voltage V V V V VREF-0.05 other V 0.8 V IIK Input Clamp Current -18 mA IOH High Level Output Current A port -24 mA Low Level Output Current A port B port 24 100 mA IOL dt/dVCC Top Power -up ramp rate 200 Operating Temperature -40 µs/V 85 °C 1) VTT and RTT can be adjusted to adapt backplane impedance if DC raccomanded IOL ratings are not exceeded 2) VREF can be adjusted to optimaze noise margin (typ two-thirds VTT) 5/14 74GTL1655 DC SPECIFICATIONS Test Condit ion Symbol VIK VOHA VOLA VOLB II Parameter High Level Input Voltage High Level Ouput Voltage A Port II(HOLD) IOZHB IOZLB IOZ (*) IOZPU IOZPD ICC Min. 3 3 to 3.6 Max. -1.2 IO=-100µA V CC-0.2 IO=-12mA 2.4 IO=-24mA 2.2 Low Level Ouput Voltage A Port 3 to 3.6 IO=100µA 0.2 3 IO=12mA 0.4 3 IO=24mA 0.55 Low Level Ouput Voltage B Port 3 IO=40mA 0.2 Input Current Control Power Off Leakage Current Bus Hold A Port Input Current V V V 3 IO=80mA 0.4 3 IO=100mA 0.5 3.6 VI = VCC or GND ±10 µA 3.6 VI = VTT or GND ±10 µA 0 VI or VO = 0 to 3.6V ±100 µA 3 VI = 0.8V 75 3 V I = 2V -75 ± 500 V 20 µA 3.6 VI = 0 to VCC Output Current B 3.6 VO = 1.5V 10 µA Output Current B 3.6 VO = 0.4V -10 µA Output Current A 3.6 V O = VCC or GND ±10 µA Output Current A 0 to 1.5 ±50 µA 3-State Output Current A Port 1.5 to 0 V O = 0.5 to 3V OE = LOW V O = 0.5 to 3V OE = LOW VI = VCC or GND IO =0 ±50 µA 40 mA 1 mA 3-State Port 3-State Port 3-State Port 3-State Port Quiescent Supply Current ∆ Supply Current except B port CI Control Input Capacitance Input Capacitance A Port Input Capacitance B Port 3.6 3.6 10 VIN = VCC or GND One input VCC =0.6V VIN = VCC or GND 3 5 pF V O = VCC or GND 5 6 6 8 pF (*) For I/O ports, the parameter IOZ includes the input leakage current 6/14 Typ. Unit 3 ∆ICC CO -40 to 85 °C VCC (V) 3 B Port Ioff Value 74GTL1655 LIVE INSERTION SPECIFICATIONS Test Condit ion Symbol Parameter ICC (Bias Quiescent Bias Current Vcc) Value -40 to 85 °C VCC (V) Min. 0 to 3.0 VO(Bport) = 0 to 1.2V 3 to 3.6 V I(Bias Vcc) = 3 to 3.6V VO Output Voltage B Port 0 VI(Bias Vcc) = 3.3V 1 IO Output Current B Port 0 V O(Bport) = 0.4V V I(Bias Vcc) = 3 to 3.6V -1 0 to 3.6 0 to 1.5 OE = 3.3V OE = 0 to 3.3V Typ. Unit Max. 5 mA 10 µA 1.2 V µA 100 100 µA µA AC ELECTRICAL CHARACTERISTICS for GTL (VCC=3.3 ± 0.3V, VTT=1.2V, VREF=0.8V, VERC=VCC or GND) Value Symbol Parameter -40 to 85 °C Test Condit ion Min. fMAX Maximum Frequency tPLH A to B or B to A Propagation Delay Time A to B VERC=VCC R1=12.5Ω CL=30pF Propagation Delay Time CK to B VERC=VCC RL=12.5Ω CL=30pF Propagation Delay Time LEAB to B VERC=VCC RL=12.5Ω CL=30pF Enable Delay Time OEAB or OE to B Disable Delay Time OEAB or OE to B Propagation Delay Time A to B VERC=VCC RL=12.5Ω CL=30pF Propagation Delay Time CK to B VERC=GND RL=12.5Ω C L=30pF Propagation Delay Time LEAB to B VERC=GND RL=12.5Ω C L=30pF Enable Delay Time OEAB or OE to B Disable Delay Time OEAB or OE to B Propagation Delay Time B to A VERC=GND RL=12.5Ω C L=30pF Propagation Delay Time CK to A RL=500Ω Propagation Delay Time LEBA to A RL=500Ω tPHL tPLH tPHL tPLH tPHL t EN tDIS tPLH tPHL tPLH tPHL tPLH tPHL t EN tDIS tPLH tPHL tPLH tPHL tPLH tPHL Typ. Unit Max. 160 VERC=GND RL=12.5Ω C L=30pF RL=500Ω CL=50pF CL=50pF CL=50pF MHz 1.5 5.2 1.5 6.2 1.5 5.5 1.5 5.8 1.5 5.8 1.5 6.4 1.5 5.4 1.5 6.2 1.5 4.3 1.5 4.6 1.5 4.3 1.5 4.9 1.5 4.9 1.5 4.8 1.5 4.8 1.5 4.2 1.5 4.7 1.5 4.8 1.5 4 1.5 4 1.5 4 1.5 3.7 ns ns ns ns ns ns ns ns ns ns ns 7/14 74GTL1655 Value Symbol Parameter -40 to 85 °C Test Condit ion Min. t EN Enable Delay Time OEBA or OE to A tDIS Disable Delay Time OEBA or OE to A Set-up Time t SU tH Hold Time tW Pulse duration Slew rate Slew rate B output both transition (0.6 to 1.3V) tsk RL=500Ω R 1=500ΩCL=50pF Data before clock Data before LE Ck High Ck Low Data after clock Data after LE Ck High or LOW LE High CK High or Low VERC=VCC Typ. Unit Max. 1 4.6 1 6.1 2.7 2.8 2.6 0.4 0.9 3 3 ns ns ns ns 1 VERC=GND 1 Skew between drivers (in Switching in the same direction the same package) Switching in any direction 1 1 ns/V ns AC ELECTRICAL CHARACTERISTICS for GTL+ (VCC=3.3 ± 0.3V, VTT=1.5V, VREF=1.0V, VERC=VCC or GND) Value Symbol Parameter -40 to 85 °C Test Condit ion Min. fMAX Maximum Frequency tPLH B to A or A to B Propagation Delay Time A to B VERC=VCC RL=12.5Ω CL=30pF Propagation Delay Time CK to B VERC=VCC RL=12.5Ω CL=30pF Propagation Delay Time LEAB to B VERC=VCC RL=12.5Ω CL=30pF Enable Delay Time OEAB or OE to B Disable Delay Time OEAB or OE to B Propagation Delay Time A to B VERC=VCC RL=12.5Ω CL=30pF Propagation Delay Time CK to B VERC=GND RL=12.5Ω C L=30pF Propagation Delay Time LEAB to B VERC=GND RL=12.5Ω C L=30pF Enable Delay Time OEAB or OE to B Disable Delay Time OEAB or OE to B VERC=GND RL=12.5Ω C L=30pF tPHL tPLH tPHL tPLH tPHL t EN tDIS tPLH tPHL tPLH tPHL tPLH tPHL t EN tDIS Typ. Unit Max. 160 VERC=GND RL=12.5Ω C L=30pF MHz 1.5 5.1 1.5 6.5 1.5 5.4 1.5 6.2 1.5 5.7 1.5 6.7 1.5 5.5 1.5 5.8 1.0 4.3 1.0 4.9 1.0 4.0 1.0 5.5 1.0 4.0 1.0 5.4 1.0 5.1 1.0 4.9 ns ns ns ns ns ns ns ns 8/14 74GTL1655 Value Symbol Parameter tPLH Propagation Delay Time B to A RL=500Ω Propagation Delay Time CK to A RL=500Ω Propagation Delay Time LEBA to A RL=500Ω -40 to 85 °C Test Condit ion Min. tPHL tPLH tPHL tPLH tPHL Enable Delay Time OEBA or OE to A Disable Delay Time tDIS OEBA or OE to A Slew rate Slew rate B output both transition (0.6 to 1.3V) t EN tW t SU tH tsk 9/14 CL=50pF CL=50pF CL=50pF RL=500Ω R 1=500ΩCL=50pF Typ. Unit Max. 1.5 4.8 1.5 4.7 1.5 4.4 1.5 4.1 1.5 4 1.5 3.7 1 4.2 1 6.1 VERC=VCC RL=12.5Ω CL=30pF 1 VERC=GND RL=12.5Ω C L=30pF Pulse duration LE High CK High or Low Set-up Time Data before clock Data before LE Ck High Ck Low Hold Time Data after clock Data after LE Ck High or LOW Skew between drivers (in Switching in the same direction the same package) Switching in any direction 1 3 3 2.7 2.8 2.6 0.4 0.9 ns ns ns ns ns/V ns ns ns 1 1 ns 74GTL1655 TEST CIRCUIT FOR ”A” OUTPUTS Test Switch tPLH, tPHL Open tPZL, tPLZ 6V tPZH, tPHZ GND C L = 50pF or equivalent (includes jig and probe capacitance) R L = R1 = 500Ω or equivalent R T = ZOUT of pulse generator (typically 50Ω) tr=tf <=2.5ns TEST CIRCUIT FOR ”B” OUTPUTS C L = 30pF or equivalent (includes jig and probe capacitance) R L = R1 = 12.5Ω or equivalent R T = ZOUT of pulse generator (typically 50Ω) tr=tf <=2.5ns 10/14 74GTL1655 WAVEFORM 1: PULSE DURATION (A PORT, CONTROL PIN) WAVEFORM 2: CLOCK TO B PORT PROPAGATION DELAY TIME WAVEFORM 3: CLOCK TO A PORT PROPAGATION DELAY TIME 11/14 74GTL1655 WAVEFORM 4: SETUP AND HOLD TIME WAVEFORM 4: ENABLE AND DISABLE TIME (A PORT) 12/14 74GTL1655 TSSOP64 MECHANICAL DATA mm. inch DIM. MIN. TYP MAX. A MIN. TYP. 1.1 A1 0.05 0.043 0.15 A2 MAX. 0.002 0.006 0.9 0.035 b 0.17 0.27 0.0067 0.011 c 0.09 0.20 0.0035 0.0079 D 16.9 17.1 0.665 0.673 E 8.1 E1 0.318 6.0 6.2 e 0.236 0.5 BSC 0.244 0.0197 BSC K 0° 8° 0° 8° L 0.50 0.75 0.020 0.030 A A2 A1 b K e L E c D E1 PIN 1 IDENTIFICATION 1 7187824A 13/14 74GTL1655 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics 2001 STMicroelectronics - Printed in Italy - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco Singapore - Spain - Sweden - Switzerland - United Kingdom - United States. http://www.st.com 14/14