Revised July 2002 GTLP36T612 36-Bit LVTTL/GTLP Universal Bus Transceiver General Description Features The GTLP36T612 is an 36-bit universal bus transceiver which provides LVTTL to GTLP signal level translation. It allows for transparent, latched and clocked modes of data transfer. The device provides a high speed interface for cards operating at LVTTL logic levels and a backplane operating at GTLP logic levels. High speed backplane operation is a direct result of GTLP’s reduced output swing (< 1V), reduced input threshold levels and output edge rate control. The edge rate control minimizes bus settling time. GTLP is a Fairchild Semiconductor derivative of the Gunning Transistor logic (GTL) JEDEC standard JESD8-3. ■ Bidirectional interface between GTLP and LVTTL logic levels Fairchild’s GTLP has internal edge-rate control and is Process, Voltage, and Temperature (PVT) compensated. Its function is similar to BTL or GTL but with different output levels and receiver thresholds. GTLP output LOW level is less than 0.5V, the output HIGH is 1.5V and the receiver threshold is 1.0V. ■ Designed with edge rate control circuitry to reduce output noise on the GTLP port ■ Partitioned as two 18-Bit transceivers with individual latch timing and output control ■ VREF pin provides external supply reference voltage for receiver threshold adjustibility ■ Special PVT compensation circuitry to provide consistent performance over variations of process, supply voltage and temperature ■ TTL compatible driver and control inputs ■ Designed using Fairchild advanced BiCMOS technology ■ Bushold data inputs on A port to eliminate the need for external pull-up resistors for unused inputs ■ Power up/down and power off high impedance for live insertion ■ Open drain on GTLP to support wired-or connection ■ Flow through pinout optimizes PCB layout ■ D-type flip-flop, latch and transparent data paths ■ A Port source/sink −24mA/+24mA ■ B Port sink +50mA ■ For more information see AN-5026, Using BGA Packages Ordering Code: Order Number GTLP36T612G (Note 1)(Note 2) Package Number BGA114A Package Description 114-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide Note 1: Ordering code “G” indicates Trays. Note 2: Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. © 2002 Fairchild Semiconductor Corporation DS500590 www.fairchildsemi.com GTLP36T612 36-Bit LVTTL/GTLP Universal Bus Transceiver September 2001 GTLP36T612 Truth Table Pin Descriptions (Note 3) Pin Names Inputs Output CEAB OEAB LEAB CLKAB A B Mode Description OEAB A-to-B Output Enable (Active LOW) (LVTTL Level) OEBA B-to-A Output Enable (Active LOW) (LVTTL Level) CEAB A-to-B Clock/LE Enable (Active LOW) (LVTTL Level) CEBA B-to-A Clock/LE Enable (Active LOW) (LVTTL Level) LEAB A-to-B Latch Enable (Transparent HIGH) (LVTTL Level) LEBA B-to-A Latch Enable (Transparent HIGH) (LVTTL Level) VREF GTLP Input Threshold Reference Voltage Note 3: A-to-B data flow is shown. B-to-A data flow is similar but uses OEBA, LEBA, CLKBA, and CEBA. CLKAB A-to-B Clock (LVTTL Level) Note 4: Output level before the indicated steady state input conditions were established, provided that CLKAB was HIGH before LEAB went LOW. CLKBA B-to-A Clock (LVTTL Level) Note 5: Output level before the indicated steady-state input conditions were established. A1–A18 A-to-B Data Inputs or B-to-A 3-STATE Outputs B1–B18 B-to-A Data Inputs or A-to-B Open Drain Outputs X H X X X Z Latched L L L H X B0 (Note 4) storage L L L L X B0 (Note 5) of A data X L H X L L X L H X H H L L L ↑ L L Clocked L L L ↑ H H storage Transparent of A data H L L X X B0 (Note 5) Clock inhibit FBGA Pin Assignments Connection Diagram Number in front of each pin indicates word. Pin Assignment for FBGA 1 2 A 1A2 1A1 1OEAB 1CLKAB 3 4 5 6 1B2 1B1 B 1A4 1A3 1LEAB C 1A6 1A5 VCC 1CEAB 1B4 1B3 VCC 1B6 D 1A8 1A7 1B5 GND GND 1B8 E 1A10 1B7 1A9 GND GND 1B10 F 1B9 1A12 1A11 GND GND 1B12 1B11 G 1A14 1A13 VCC VREF 1B14 1B13 H 1A16 1A15 1OEBA 1CEBA 1B16 1B15 J 1A18 1A17 1LEBA 1CLKBA 1B18 1B17 K (Top Thru View) www.fairchildsemi.com 2 L 2A2 2A1 2OEAB 2CLKAB 2B2 2B1 M 2A4 2A3 2LEAB 2CEAB 2B4 2B3 N 2A6 2A5 VCC VCC 2B6 2B5 P 2A8 2A7 GND GND 2B8 2B7 R 2A10 2A9 GND GND 2B10 2B9 T 2A12 2A11 GND GND 2B12 2B11 U 2A14 2A13 VCC VREF 2B14 2B13 V 2A16 2A15 2OEBA 2CEBA 2B16 2B15 W 2A18 2A17 2LEBA 2CLKBA 2B18 2B17 The GTLP36T612 is an 36-bit registered transceiver containing D-type flip-flop, latch and transparent modes of operation for the data path. Data flow in each direction is controlled by the clock enables (CEAB and CEBA), latch enables (LEAB and LEBA), clock (CLKAB and CLKBA) and output enables (OEAB and OEBA). The clock enables (CEAB and CEBA) and the output enables (OEAB and OEBA) control the 18 bits of data for the A-to-B and B-to-A directions respectively. For A-to-B data flow, when CEAB is LOW, the device operates on the LOW-to-HIGH transition of CLKAB for the flip-flop and on the HIGH-to-LOW transition of LEAB for the latch path. That is, if CEAB is LOW and LEAB is LOW the A data is latched regardless as to the state of CLKAB (HIGH or LOW) and if LEAB is HIGH the device is in transparent mode. When OEAB is LOW the outputs are active. When OEAB is HIGH the outputs are HIGH impedance. The data flow of B-to-A is similar except that CEBA, OEBA, LEBA, and CLKBA are used. Logic Diagram 3 www.fairchildsemi.com GTLP36T612 Functional Description GTLP36T612 Absolute Maximum Ratings(Note 6) Supply Voltage (VCC ) −0.5V to +4.6V DC Input Voltage (VI) −0.5V to +4.6V Recommended Operating Conditions (Note 8) Supply Voltage VCC /VCCQ DC Output Voltage (VO) 3.15V to 3.45V Bus Termination Voltage (VTT) −0.5V to +4.6V Outputs 3-STATE −0.5V to VCC + 0.5V Outputs Active (Note 7) DC Output Sink Current into GTLP 1.47V to 1.53V VREF 0.98V to 1.02V Input Voltage (VI) A Port IOL 48 mA DC Output Source Current from A Port IOH on A Port and Control Pins 0.0V to 3.45V on B Port 0.0V to 3.45V −48 mA HIGH Level Output Current (IOH) 100 mA LOW Level Output Current (IOL) DC Output Sink Current into −24 mA A Port B Port in the LOW State, IOL DC Input Diode Current (IIK) +24 mA A Port VI < 0V −50 mA +50 mA B Port DC Output Diode Current (IOK) −40°C to +85°C Operating Temperature (TA) VO < 0V −50 mA VO > VCC +50 mA Note 6: Absolute Maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation under absolute maximum rated conditions in not implied. >2000V ESD Performance −65°C to +150 °C Storage Temperature (TSTG) Note 7: IO Absolute Maximum Rating must be observed. Note 8: Unused inputs must be held HIGH or LOW. DC Electrical Characteristics Over Recommended Operating Free-Air Temperature Range, VREF = 1.0V (unless otherwise noted). Symbol VIH VIL Test Conditions Min Typ B Port VREF +0.05 Others 2.0 B Port 0.0 VTT VREF − 0.05 Others VREF VOH 0.8 GTLP (Note 10) 1.0 VCC = 3.15V VIK A Port II = −18 mA VCC, VCCQ = Min to Max (Note 11) IOH = −100 µA VCC = 3.15V VOL A Port B Port II 0.2 VCC = 3.15V IOL = 40 mA 0.40 IOL = 50 mA 0.55 Control Pins VCC = Min to Max (Note 11) VI = 3.45V or 0V ±5 VCC = 3.45V VI = 0V −10 VI = 3.45 10 A Port A Port VCC = 3.45V VCC = 3.45V B Port A or B Ports (VCC/VCCQ) www.fairchildsemi.com 5 VI = 0 −5 VI = 0.8V B Port A Port VI = VCC VI or VO = 0 to 3.45V VCC = 3.15V 30 75 VI = 2.0V −75 VO = 3.45 10 VO = 3.45V 5 VO = 0V −10 VO = 0V −5 VCC = 3.45V Outputs HIGH 60 80 IO = 0 Outputs LOW 60 80 VI = VCC or GND Outputs Disabled 60 90 4 V V V 0.5 A Port and Control Pins VCC = 0 ICC 2.0 IOL = 24mA IOFF IOZL 2.4 IOH = -24mA VCC, VCCQ = Min to Max (Note 11) IOL = 100 µA II(hold) V VCC –0.2 IOH = −8 mA VCC = 3.15V VCC = 3.45V Units V −1.2 A Port B Port IOZH Max (Note 9) V V µA µA µA µA µA µA µA mA Symbol (Continued) Test Conditions Min Typ Max (Note 9) ∆ICC A Port and VCC = 3.45V, (Note 12) Control Pins A or Control Inputs at VCC or GND Ci Control Pins VI = VCC or 0 6 A Port VI = VCC or 0 7.5 B Port VI = VCC or 0 9.0 One Input at 2.7V 2 Units mA pF Note 9: All typical values are at VCC = 3.3V, VCCQ = 3.3V, and TA = 25°C. Note 10: GTLP VREF and VTT are specified to 2% tolerance since signal integrity and noise margin can be significantly degraded if these supplies are noisy. In addition, VTT and Rterm can be adjusted beyond the recommended operating conditions to accommodate backplane impedances other than 50Ω, but must remain within the boundaries of the DC Absolute Maximum ratings. Similarly VREF can be adjusted to optimize noise margin. Note 11: For conditions shown as Min or Max, use the appropriate value specified under recommended operating conditions. Note 12: This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND. AC Operating Requirements Over recommended ranges of supply voltage and operating free-air temperature, VREF = 1.0V (unless otherwise noted). Symbol fMAX Maximum Clock Frequency tWIDTH Pulse Duration tSU tHOLD Setup Time Hold Time Test Conditions Min 175 LEAB or LEBA HIGH 3.0 CLKAB or CLKBA HIGH or LOW 3.0 A before CLKAB↑ 1.1 B before CLKBA↑ 3.0 A before LEAB 1.1 B before LEBA 2.7 CEAB before CLKAB↑ 1.2 CEBA before CLKBA↑ 1.4 A after CLKAB↑ 0.0 B after CLKBA↑ 0.0 A after LEAB 0.8 B after LEBA 0.0 CEAB after CLKAB↑ 1.0 CEBA after CLKBA↑ 1.9 5 Max Unit MHz ns ns ns www.fairchildsemi.com GTLP36T612 DC Electrical Characteristics GTLP36T612 AC Electrical Characteristics Over recommended range of supply voltage and operating free-air temperature, VREF = 1.0V (unless otherwise noted). CL = 30 pF for B Port and CL = 50 pF for A Port. Symbol tPLH From To (Input) (Output) A B tPHL tPLH LEAB B tPHL tPLH CLKAB B tPHL tPLH OEAB B tPHL tRISE Transition Time, B Outputs (20% to 80%) tFALL Transition Time, B Outputs (20% to 80%) tPLH 4.1 6.3 1.0 2.7 4.4 2.2 4.2 6.3 1.0 2.4 4.2 2.2 4.4 6.5 1.0 2.5 4.4 2.0 3.8 5.6 1.0 2.6 4.3 3.1 1.8 3.8 5.8 A 0.3 2.2 4.6 0.4 2.4 4.6 CLKBA A 0.5 2.4 4.6 0.6 2.6 4.6 0.3 2.7 5.2 0.3 2.5 5.2 OEBA A Note 13: All typical values are at VCC = 3.3V, and TA = 25°C. 6 3.8 Unit ns ns ns ns ns 2.1 LEBA tPHZ, tPLZ www.fairchildsemi.com 2.1 1.8 tPHL tPZH, tPZL Max A tPHL tPLH Typ (Note 13) B tPHL tPLH Min 5.8 ns ns ns ns Test Circuit for A Outputs Test Test Circuit for B Outputs S tPLH/tPHL Open tPLZ/tPZL 6V Note B: For B Port, CL = 30 pF is used for worst case. tPHZ/tPZH GND Note A: CL includes probes and Jig capacitance. Voltage Waveform - Propagation Delay Times Voltage Waveform - Setup and Hold Times Voltage Waveform - Pulse Width Voltage Waveform - Enable and Disable times Output Waveform 1 is for an output with internal conditions such that the output is LOW except when disabled by the control output. Output Waveform 2 is for an output with internal conditions such that the output is HIGH except when disabled by the control output. Input and Measure Conditions A or LVTTL Pins B or GTLP Pins VinHIGH 3.0 1.5 VinLOW 0.0 0.0 VM 1.5 1.0 VX VOL + 0.3V N/A VY VOH − 0.3V N/A All input pulses have the following characteristics: Frequency = 10MHz, tRISE = tFALL = 2 ns (10% to 90%), Z O = 50Ω. The outputs are measured one at a time with one transition per measurement. 7 www.fairchildsemi.com GTLP36T612 Test Circuits and Timing Waveforms GTLP36T612 36-Bit LVTTL/GTLP Universal Bus Transceiver Physical Dimensions inches (millimeters) unless otherwise noted 114-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide Package Number BGA114A Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com www.fairchildsemi.com 8