SN54GTL1655, SN74GTL1655 16-BIT LVTTL-TO-GTL/GTL+ UNIVERSAL BUS TRANSCEIVERS WITH LIVE INSERTION SCBS696E – JULY 1997 – REVISED NOVEMBER 1999 D D D D D D D D D SN74GTL1655 . . . DGG PACKAGE (TOP VIEW) Members of the Texas Instruments Widebus Family UBT (Universal Bus Transceiver) Combines D-Type Latches and D-Type Flip-Flops for Operation in Transparent, Latched, or Clocked Mode Translate Between GTL/GTL+ Signal Level and LVTTL Logic Levels High-Drive (100 mA), Low-Output-Impedance (12 Ω) Bus Transceiver (B Port) Edge-Rate-Control Input Configures the B-Port Output Rise and Fall Times Ioff, Power-Up 3-State, and BIAS VCC Support Live Insertion Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors on A Port Distributed VCC and GND-Pin Configuration Minimizes High-Speed Switching Noise Package Options Include Thin Shrink Small-Outline (DGG) and Ceramic Quad Flat (HV) Packages 1OEAB 1OEBA VCC 1A1 GND 1A2 1A3 GND 1A4 GND 1A5 GND 1A6 1A7 VCC 1A8 2A1 GND 2A2 2A3 GND 2A4 2A5 GND 2A6 GND 2A7 VCC 2A8 GND 2OEAB 2OEBA description The ’GTL1655 devices are high-drive (100 mA), low-output-impedance (12 Ω) 16-bit universal bus transceivers (UBT) that provide LVTTL-toGTL/GTL+ and GTL/GTL+-to-LVTTL signal-level translation. They are partitioned as two 8-bit transceivers and combine D-type flip-flops and D-type latches to allow for transparent, latched, and clocked modes of data transfer similar to the ’16501 function. These devices provide an interface between cards operating at LVTTL logic levels and a backplane operating at GTL/GTL+ signal levels. Higher-speed operation is a direct result of the reduced output swing (<1 V), reduced input threshold levels and output edge control (OEC). The high drive is suitable for driving double-terminated low-impedance backplanes using incident-wave switching. 1 64 2 63 3 62 4 61 5 60 6 59 7 58 8 57 9 56 10 55 11 54 12 53 13 52 14 51 15 50 16 49 17 48 18 47 19 46 20 45 21 44 22 43 23 42 24 41 25 40 26 39 27 38 28 37 29 36 30 35 31 34 32 33 CLK 1LEAB 1LEBA VERC GND 1B1 1B2 GND 1B3 1B4 1B5 GND 1B6 1B7 VCC 1B8 2B1 GND 2B2 2B3 GND 2B4 2B5 VREF 2B6 GND 2B7 2B8 BIAS VCC 2LEAB 2LEBA OE Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Widebus, UBT, and OEC are trademarks of Texas Instruments Incorporated. Copyright 1999, Texas Instruments Incorporated UNLESS OTHERWISE NOTED this document contains PRODUCTION DATA information current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SN54GTL1655, SN74GTL1655 16-BIT LVTTL-TO-GTL/GTL+ UNIVERSAL BUS TRANSCEIVERS WITH LIVE INSERTION SCBS696E – JULY 1997 – REVISED NOVEMBER 1999 description (continued) The user has the flexibility of using this device at either GTL (VTT = 1.2 V and VREF = 0.8 V) or the preferred higher noise margin GTL+ (VTT = 1.5 V and VREF = 1 V) signal levels. GTL+ is the Texas Instruments derivative of the Gunning transceiver logic (GTL) JEDEC standard JESD 8-3. The B port normally operates at GTL or GTL+ signal levels, while the A-port and control inputs are compatible with LVTTL logic levels but are not 5-V tolerant. VREF is the reference input voltage for the B port. These devices are uniquely partitioned as two 8-bit transceivers with individual latch timing and output signals, but with a common clock and output enable inputs for both transceiver words. Data flow for each word is determined by the respective latch enables (xLEAB and xLEBA), output enables (xOEAB and xOEBA), and clock (CLK). The output enables (1OEAB, 1OEBA, 2OEAB, and 2OEBA) control byte 1 and byte 2 data for the A-to-B and B-to-A directions, respectively. For A-to-B data flow, the devices operate in the transparent mode when LEAB is high. When LEAB transitions low, the A data is latched independent of CLK high or low. If LEAB is low, the A data is registered on the CLK low-to-high transition. When OEAB is low, the outputs are active. With OEAB high, the outputs are in the high-impedance state. Data flow for the B-to-A direction is identical, but uses OEBA, LEBA, and CLK. Note that CLK is common to both directions and both 8-bit words. OE is also common and is used to disable all I/O ports simultaneously. The ’GTL1655 is featured with adjustable edge-rate control (VERC). Changing VERC input voltage between GND and VCC adjusts the B-port output rise and fall times. This allows the designer to optimize for various loading conditions. These devices are fully specified for live-insertion applications using Ioff, power-up 3-state, and BIAS VCC. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down, which prevents driver conflict. The BIAS VCC circuitry precharges and preconditions the B-port input/output connections, preventing disturbance of active data on the backplane during card insertion or removal, and permits true live-insertion capability. When VCC is between 0 and 1.5 V, the device is in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 1.5 V, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. Active bus-hold circuitry holds unused or undriven LVTTL inputs at a valid logic state. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended. The SN54GTL1655 is characterized for operation over the full military temperature range of –55°C to 125°C. The SN74GTL1655 is characterized for operation from –40°C to 85°C. 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN54GTL1655, SN74GTL1655 16-BIT LVTTL-TO-GTL/GTL+ UNIVERSAL BUS TRANSCEIVERS WITH LIVE INSERTION SCBS696E – JULY 1997 – REVISED NOVEMBER 1999 1OEBA 1OEAB NC CLK 1LEAB 1LEBA VERC GND 1B1 1B2 GND 11 59 12 58 13 57 14 56 15 55 16 54 17 53 18 52 19 51 20 50 21 49 22 48 23 47 24 46 25 45 26 44 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 1B3 1B4 1B5 GND 1B6 1B7 VCC 1B8 NC 2B1 GND 2B2 2B3 GND 2B4 2B5 VREF 2B8 2B7 GND 2B6 9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61 60 2A8 GND 2OEAB 2OEBA NC OE 2LEBA 2LEAB BIAS V CC 10 2A6 GND 2A7 V CC 1A4 GND 1A5 GND 1A6 1A7 VCC 1A8 NC 2A1 GND 2A2 2A3 GND 2A4 2A5 GND GND 1A1 VCC GND 1A3 1A2 SN54GTL1655 . . . HV PACKAGE (TOP VIEW) NC – No internal connection POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 SN54GTL1655, SN74GTL1655 16-BIT LVTTL-TO-GTL/GTL+ UNIVERSAL BUS TRANSCEIVERS WITH LIVE INSERTION SCBS696E – JULY 1997 – REVISED NOVEMBER 1999 Function Tables FUNCTION† INPUTS LEAB CLK A OUTPUT B H X X X Z Isolation L H X L L Transparent L H X H H Transparent L L ↑ L L Registered L L ↑ H L L H X H B0‡ Previous State OEAB MODE Registered B0§ Previous State † A-to-B data flow is shown. B-to-A flow is similar, but uses OEBA, LEBA, and CLK. ‡ Output level before the indicated steady-state input conditions were established, provided that CLK was high before LEAB went low § Output level before the indicated steady-state input conditions were established L L L X OUTPUT ENABLE INPUTS OUTPUTS OE OEAB OEBA A PORT B PORT L L L Active Active L L H Z Active L H L Active Z L H H Z Z H X X Z Z B-PORT EDGE-RATE CONTROL (VERC) INPUT VERC LOGIC LEVEL NOMINAL VOLTAGE H VCC GND L 4 POST OFFICE BOX 655303 OUTPUT B PORT EDGE RATE Slow Fast • DALLAS, TEXAS 75265 SN54GTL1655, SN74GTL1655 16-BIT LVTTL-TO-GTL/GTL+ UNIVERSAL BUS TRANSCEIVERS WITH LIVE INSERTION SCBS696E – JULY 1997 – REVISED NOVEMBER 1999 logic diagram (positive logic) 41 VREF 61 VERC 64 CLK 63 1LEAB 62 1LEBA 1OEBA 2 1 1OEAB 33 OE 1A1 4 1D C1 59 1B1 CLK 1D C1 CLK To Seven Other Channels Pin numbers shown are for the DGG package. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 SN54GTL1655, SN74GTL1655 16-BIT LVTTL-TO-GTL/GTL+ UNIVERSAL BUS TRANSCEIVERS WITH LIVE INSERTION SCBS696E – JULY 1997 – REVISED NOVEMBER 1999 logic diagram (positive logic) (continued) 41 VREF 61 VERC 64 CLK 35 2LEAB 34 2LEBA 2OEBA 32 31 2OEAB 33 OE 2A1 17 1D C1 CLK 1D C1 CLK To Seven Other Channels Pin numbers shown are for the DGG package. 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 48 2B1 SN54GTL1655, SN74GTL1655 16-BIT LVTTL-TO-GTL/GTL+ UNIVERSAL BUS TRANSCEIVERS WITH LIVE INSERTION SCBS696E – JULY 1997 – REVISED NOVEMBER 1999 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC, BIAS VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V Input voltage range, VI (see Note 1): A-port and control pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V B port, VERC, and VREF . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V Voltage range applied to any output in the high or power-off state, VO (see Note 1): A port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V B port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V Current into any output in the low state, IO: A port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 mA B port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 mA Current into any A-port output in the high state, IO (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 mA Continuous current through each VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA Package thermal impedance, θJA (see Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 2. This current flows only when the output is in the high state and VO > VCC. 3. The package thermal impedance is calculated in accordance with JESD 51. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 SN54GTL1655, SN74GTL1655 16-BIT LVTTL-TO-GTL/GTL+ UNIVERSAL BUS TRANSCEIVERS WITH LIVE INSERTION SCBS696E – JULY 1997 – REVISED NOVEMBER 1999 recommended operating conditions (see Notes 4 through 6) SN54GTL1655 BIAS VCC Supply voltage VTT Termination voltage VREF Supply voltage VI Input voltage High-level input voltage NOM VIL MIN NOM MAX 3 3.3 3.6 3 3.3 3.6 1.14 1.2 1.26 1.14 1.2 1.26 GTL+ 1.35 1.5 1.65 1.35 1.5 1.65 GTL 0.74 0.8 0.87 0.74 0.8 0.87 GTL+ 0.87 1 1.1 0.87 1 1.1 B port 0 0 VTT VCC 0 Except B port VERC Except B port and ERC VREF+50 mV VCC–0.6 2 VERC Except B port and ERC VTT VCC 0 VREF+50 mV VCC–0.6 VCC VCC UNIT V V V V V 2 B port Low-level input voltage SN74GTL1655 MAX GTL B port VIH MIN GND VREF–50 mV 0.6 GND VREF–50 mV 0.6 V 0.8 0.8 –18 –18 mA A port –24 mA A port 24 B port 100 IIK Input clamp current IOH High-level output current IOL Low-level output current ∆t/∆VCC Power-up ramp rate 200 200 mA µs/V TA Operating free-air temperature –55 125 –40 85 °C NOTES: 4. All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. 5. Normal connection sequence is GND first, BIAS VCC = 3.3 V second, and VCC = 3.3 V, I/O, control inputs, VTT and VREF (any order) last. However, if the B-port I/O precharge is not required, the acceptable connection sequence is GND first and VCC = 3.3 V, BIAS VCC = 3.3 V, I/O, control inputs, VTT and VREF (any order) last. When VCC is connected, the BIAS VCC circuitry is disabled. 6. VTT and RTT can be adjusted to accommodate backplane impedances as long as they do not exceed the DC absolute IOL ratings. Similarly, VREF can be adjusted to optimize noise margins, but normally is 2/3 VTT. PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN54GTL1655, SN74GTL1655 16-BIT LVTTL-TO-GTL/GTL+ UNIVERSAL BUS TRANSCEIVERS WITH LIVE INSERTION SCBS696E – JULY 1997 – REVISED NOVEMBER 1999 electrical characteristics over recommended operating free-air temperature range, VREF = 1 V and VTT = 1.5 V (unless otherwise noted) PARAMETER VIK VOH A port A port VOL B port II Control inputs B port Ioff II(hold) ( ) MIN VCC = 3 V, II = –18 mA VCC = 3 V to 3.6 V, IOH = –100 µA IOH = –12 mA VCC = 3 V IOH = –24 mA VCC = 3 V VCC = 3 3.6 6V 2.2 VI = VTT or GND VI or VO = 0 to 3.6 V VCC = 3.6 V‡, VCC = 3.6 V, VI = 0 to VCC VO = 1.5 V VCC = 3.6 V, VCC = 3.6 V, VO = 0.4 V VO = VCC or GND UNIT V V 2.2 IOL = 100 mA VI = VCC or GND VCC = 3 V –1.2 VCC–0.2 2.4 IOL = 40 mA IOL = 80 mA VI = 0.8 V VI = 2 V SN74GTL1655 TYP† MAX MIN –1.2 VCC–0.2 2.4 VCC = 3 V to 3.6 V, IOL = 100 µA IOL = 12 mA VCC = 3 V IOL = 24 mA VCC = 0, A port SN54GTL1655 TYP† MAX TEST CONDITIONS 0.2 0.2 0.4 0.4 0.55 0.55 0.2 0.2 0.4 0.4 0.5 0.5 ±10 ±10 ±10 ±10 ±100 75 V µA µA 75 –75 µA –75 ±500 ±500 10 10 µA –10 –10 µA ±10 ±10 µA IOZH IOZL IOZ§ B port IOZPU A port VCC = 0 to 3.6 V, VO = 0.5 V to 3 V, OE = low ±50* ±50 µA IOZPD A port VCC = 3.6 V to 0, VO = 0.5 V to 3 V, OE = low ±50* ±50 µA 80 80 A or B port VCC = 3.6 V, IO = 0, VI = VCC or GND Outputs high ICC Outputs low 80 80 Outputs disabled 80 80 1 1 mA pF B port A port ∆ICC¶ Except B port VCC = 3.6 V, A-port or control inputs at VCC or GND, One input at VCC – 0.6 V Ci Control inputs VI = VCC or 0 Ciio A port B port VO = VCC or 0 3 5 3 5 5 6 5 6 6 8 6 8 mA pF * On products compliant to MIL-PRF-38535, this parameter is not production tested. † All typical values are at VCC = 3.3 V, TA = 25°C. ‡ This is the bus-hold maximum dynamic current. It is the minimum overdrive current required to switch the input from one state to another. § For I/O ports, the parameter IOZ includes the input leakage current. ¶ This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND. PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 9 SN54GTL1655, SN74GTL1655 16-BIT LVTTL-TO-GTL/GTL+ UNIVERSAL BUS TRANSCEIVERS WITH LIVE INSERTION SCBS696E – JULY 1997 – REVISED NOVEMBER 1999 live-insertion specifications over recommended operating free-air temperature range PARAMETER ICC (BIAS VCC) VO IO B port B port SN54GTL1655 TEST CONDITIONS MIN VCC = 0 to 3 V VCC = 3 V to 3.6 V V ((B port)) = 0 to 1.2 V,, VI (BIAS VCC) = 3 V to 3.6 V VCC = 0, VCC = 0, VI (BIAS VCC) = 3.3 V V (B port) = 0.4 V, VI (BIAS VCC) = 3 V to 3.6 V VCC = 0 to 3.6 V, VCC = 0 to 1.5 V, OE = 3.3 V OE = 0 to 3.3 V 1 MAX SN74GTL1655 MIN MAX UNIT 5 5 mA 10 10 µA 1.2 V 100 100 µA 100 100 1.2 –1 1 –1 timing requirements over recommended ranges of supply voltage and operating free-air temperature, VTT = 1.2 V, VREF = 0.8 V and VERC = VCC or GND for GTL (unless otherwise noted) SN54GTL1655 MIN fclock Clock frequency tw Pulse duration th Setup time Hold time 3 3 CLK high or low 3 3 2.7 2.7 CLK high 2.8 2.8 CLK low 2.6 2.6 0.4 0.4 0.9 0.9 Data before LE↓ Data after CLK↑ Data after LE↓ CLK high or low POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MAX 160 LE high PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. 10 MIN 160 Data before CLK↑ tsu MAX SN74GTL1655 UNIT MHz ns ns ns SN54GTL1655, SN74GTL1655 16-BIT LVTTL-TO-GTL/GTL+ UNIVERSAL BUS TRANSCEIVERS WITH LIVE INSERTION SCBS696E – JULY 1997 – REVISED NOVEMBER 1999 A-to-B switching characteristics over recommended ranges of supply voltage and operating free-air temperature, VTT = 1.2 V, VREF = 0.8 V and VERC = VCC or GND for GTL (see Figure 1) PARAMETER fmax tPLH tPHL tPLH tPHL tPLH tPHL ten tdis tPLH tPHL tPLH tPHL tPLH tPHL ten tdis Slew rate (VERC = VCC) FROM (INPUT) TO (OUTPUT) SN54GTL1655 MIN MAX 160 A VERC = VCC B CLK VERC = VCC B LEAB VERC = VCC B OEAB or OE VERC = VCC B A VERC = GND B CLK VERC = GND B LEAB VERC = GND B OEAB or OE VERC = GND B SN74GTL1655 MIN MAX 160 UNIT MHz 3.1 5.2 3.1 5.2 2.6 6.2 2.6 6.2 3.4 5.5 3.4 5.5 2.4 5.8 2.4 5.8 3.5 5.8 3.5 5.8 2.6 6.4 2.6 6.4 3.3 5.4 3.3 5.4 2.7 5.9 2.7 5.9 2.3 4.3 2.3 4.3 1.9 4.3 1.9 4.3 2.7 4.8 2.7 4.8 1.8 4.3 1.8 4.3 2.8 4.9 2.8 4.9 2 4.8 2 4.8 2.5 4.5 2.5 4.5 2 4.2 2 4.2 ns ns ns ns ns ns ns ns Both transitions, B outputs (0.6 V to 1.3 V) 1 1 ns/V Both transitions, B outputs (0.6 V to 1.3 V) 1 1 ns/V tsk(o)† Skew between drivers in the same package (switching in the same direction) 1 1 ns tsk(o)‡ Skew between drivers switching in any direction in the same package 1 1 ns Slew rate (VERC = GND) † Skew values are applicable for through mode only. ‡ Skew values are applicable for CLK mode only, with all outputs switching simultaneously. PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 11 SN54GTL1655, SN74GTL1655 16-BIT LVTTL-TO-GTL/GTL+ UNIVERSAL BUS TRANSCEIVERS WITH LIVE INSERTION SCBS696E – JULY 1997 – REVISED NOVEMBER 1999 B-to-A switching characteristics over recommended ranges of supply voltage and operating free-air temperature, VTT = 1.2 V and VREF = 0.8 V for GTL (see Figure 1) PARAMETER fmax tPLH tPHL tPLH tPHL tPLH tPHL ten tdis FROM (INPUT) TO (OUTPUT) MIN MAX SN74GTL1655 MIN 160 B A CLK A LEBA A OEBA or OE A MAX 160 1.8 4.7 1.8 4.7 2.3 4.6 2.3 4.6 1.6 4 1.6 4 1.5 3.4 1.5 3.4 1.7 4 1.7 4 1.4 3.5 1.4 3.5 1.3 4.2 1.3 4.2 2 6.1 2 6.1 UNIT MHz ns ns ns ns tsk(o)† Skew between drivers in the same package (switching in the same direction) 1 1 ns tsk(o)‡ Skew between drivers switching in any direction in the same package 1 1 ns † Skew values are applicable for through mode only. ‡ Skew values are applicable for CLK mode only, with all outputs switching simultaneously. PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. 12 SN54GTL1655 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN54GTL1655, SN74GTL1655 16-BIT LVTTL-TO-GTL/GTL+ UNIVERSAL BUS TRANSCEIVERS WITH LIVE INSERTION SCBS696E – JULY 1997 – REVISED NOVEMBER 1999 timing requirements over recommended ranges of supply voltage and operating free-air temperature, VTT = 1.5 V, VREF = 1 V and VERC = VCC or GND for GTL+ (unless otherwise noted) SN54GTL1655 MIN fclock Clock frequency tw Pulse duration tsu Setup time MIN 160 3 3 CLK high or low 3 3 Data before LE↓ 2.7 2.7 CLK high 2.8 2.8 CLK low 2.6 2.6 0.4 0.4 0.9 0.9 Data after CLK↑ Hold time Data after LE↓ CLK high or low MAX 160 LE high Data before CLK↑ th MAX SN74GTL1655 UNIT MHz ns ns ns A-to-B switching characteristics over recommended ranges of supply voltage and operating free-air temperature, VTT = 1.5 V, VREF = 1 V and VERC = VCC or GND for GTL+ (see Figure 1) PARAMETER fmax tPLH tPHL tPLH tPHL tPLH tPHL ten tdis ten tdis tPLH tPHL tPLH tPHL tPLH tPHL ten tdis ten tdis Slew rate (VERC = VCC) FROM (INPUT) TO (OUTPUT) SN54GTL1655 MIN MAX 160 A VERC = VCC B CLK VERC = VCC B LEAB VERC = VCC B OEAB VERC = VCC B OE VERC = VCC B A VERC = GND B CLK VERC = GND B LEAB VERC = GND B OEAB VERC = GND B OE VERC = GND B SN74GTL1655 MIN MAX 160 UNIT MHz 3 5.1 3 5.1 2.9 6.5 2.9 6.5 3.4 5.4 3.4 5.4 2.7 6.2 2.7 6.2 3.5 5.7 3.5 5.7 2.8 6.7 2.8 6.7 3.3 5.4 3.3 5.4 3 6.3 3 6.3 3 5.5 3 5.5 3.6 5.8 3.6 5.8 2.3 4.3 2.3 4.3 2 4.4 2 4.4 2.7 4.8 2.7 4.8 1.9 4.5 1.9 4.5 2.8 4.9 2.8 4.9 2.1 4.9 2.1 4.9 2.5 4.5 2.5 4.5 2.1 4.4 2.1 4.4 2.5 4.6 2.5 4.6 2.9 4.9 2.9 4.9 ns ns ns ns ns ns ns ns ns ns Both transitions, B outputs (0.6 V to 1.3 V) 1 1 ns/V Both transitions, B outputs (0.6 V to 1.3 V) 1 1 ns/V tsk(o)† Skew between drivers in the same package (switching in the same direction) 1 1 ns tsk(o)‡ Skew between drivers switching in any direction in the same package 1 1 ns Slew rate (VERC = GND) † Skew values are applicable for through mode only. ‡ Skew values are applicable for CLK mode only, with all outputs switching simultaneously. PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 13 SN54GTL1655, SN74GTL1655 16-BIT LVTTL-TO-GTL/GTL+ UNIVERSAL BUS TRANSCEIVERS WITH LIVE INSERTION SCBS696E – JULY 1997 – REVISED NOVEMBER 1999 B-to-A switching characteristics over recommended ranges of supply voltage and operating free-air temperature, VTT = 1.5 V and VREF = 1 V for GTL+ (see Figure 1) PARAMETER fmax tPLH tPHL tPLH tPHL tPLH tPHL ten tdis ten tdis FROM (INPUT) TO (OUTPUT) MIN MAX 160 B A CLK A LEBA A OEBA A OE A SN74GTL1655 MIN MAX 160 UNIT MHz 2 4.8 2 4.8 2.4 4.7 2.4 4.7 1.6 4.4 1.6 4.4 1.5 3.4 1.5 3.4 1.7 4 1.7 4 1.4 3.5 1.4 3.5 1.3 4.2 1.3 4.2 2 6.1 2 6.1 2.2 4.7 2.2 4.7 4.1 6.3 4.1 6.3 ns ns ns ns ns tsk(o)† Skew between drivers in the same package (switching in the same direction) 1 1 ns tsk(o)‡ Skew between drivers switching in any direction in the same package 1 1 ns † Skew values are applicable for through mode only. ‡ Skew values are applicable for CLK mode only, with all outputs switching simultaneously. PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. 14 SN54GTL1655 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN54GTL1655, SN74GTL1655 16-BIT LVTTL-TO-GTL/GTL+ UNIVERSAL BUS TRANSCEIVERS WITH LIVE INSERTION SCBS696E – JULY 1997 – REVISED NOVEMBER 1999 PARAMETER MEASUREMENT INFORMATION VTT 6V 500 Ω From Output Under Test S1 Open CL = 50 pF (see Note A) 500 Ω 12.5 Ω From Output Under Test CL = 30 pF (see Note A) S1 Open 6V GND TEST tPLH/tPHL tPLZ/tPZL tPHZ/tPZH GND LOAD CIRCUIT FOR B OUTPUTS LOAD CIRCUIT FOR A OUTPUTS tw 3V Input 3V Timing Input 1.5 V 0V 1.5 V 1.5 V tsu 0V VOLTAGE WAVEFORMS PULSE DURATION 3V Input Test Point 1.5 V 1.5 V th 3V Data Input A Port 1.5 V Data Input B Port VREF 1.5 V 0V VTT VREF 0V 0V tPLH VOLTAGE WAVEFORMS SETUP AND HOLD TIMES tPHL VTT Output VREF VREF 3V VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES (CLK to B port) 1.5 V 0V Output Waveform 1 S1 at 6 V (see Note B) 1.5 V 3V 1.5 V 1.5 V VOL Output Waveform 2 S1 at GND (see Note B) VOL + 0.3 V VOL tPHZ tPZH tPHL VOH Output 1.5 V tPLZ tPZL 1.5 V tPLH 1.5 V 0V 3V Input Output Control 1.5 V VOH VOH – 0.3 V ≈0 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES (A port) VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES (CLK to A port) NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns. D. The outputs are measured one at a time with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. Figure 1. Load Circuits and Voltage Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 15 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. 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