CIRRUS CS5364-CQZ

CS5364
114 dB, 192 kHz, 4-Channel A/D Converter
Features
 Advanced Multi-bit Delta-Sigma Architecture
 24-Bit Conversion
 Separate 1.8 V to 5 V Logic Supplies for
Control and Serial Ports
 114 dB Dynamic Range
 High-Pass Filter for DC Offset Calibration
 -105 dB THD+N
 Overflow Detection
 Supports Audio Sample Rates up to 216 kHz
 Footprint Compatible with the 8-Channel
CS5368
 Selectable Audio Interface Formats
–
Left-Justified, I²S, TDM
–
4-Channel TDM Interface Formats
 Supports Standard I²C® or SPI™ Control
 Low Latency Digital Filter
Interface
 Less than 365 mW Power Consumption
 On-Chip Oscillator Driver
 Operation as System Clock Master or Slave
 Auto-Detect Speed in Slave Mode
 Individual Channel HPF Disable
 Overflow Detection for Individual Channels
 Mute Control for Individual Channels
 Independent Power-Down Control per Channel
 Differential Analog Architecture
Pair
Control Interface
I2C, SPI
or Pins
Configuration
Registers
Internal
Oscillator
4 Differential
Analog Inputs
Multi-bit
ΔΣ ADC
Decimation
Filter
High Pass
Filter
Serial
Audio Out
PCM or
TDM
Level
Translator
VLC
1.8 - 5V
VD
3.3 - 5V
Level
Translator
VA
5V
Voltage
Reference
Additional Control Port Features
Device
Control
Digital
Audio
VLS
1.8 - 5V
http://www.cirrus.com
Copyright © Cirrus Logic, Inc. 2007
(All Rights Reserved)
JULY '07
DS625F2
CS5364
Description
The CS5364 is a complete 4-channel analog-to-digital converter for digital audio systems. It performs sampling, analog-to-digital conversion, and anti-alias filtering, generating 24-bit values for all 4-channel inputs in serial form at
sample rates up to 216 kHz per channel.
The CS5364 uses a 5th-order, multi-bit delta sigma modulator followed by low latency digital filtering and decimation, which removes the need for an external anti-aliasing filter. The ADC uses a differential input architecture which
provides excellent noise rejection.
Dedicated level translators for the Serial Port and Control Port allow seamless interfacing between the CS5364 and
other devices operating over a wide range of logic levels. In addition, an on-chip oscillator driver provides clocking
flexibility and simplifies design.
The CS5364 is the industry’s first audio A/D to support a high-speed TDM interface which provides a serial output
of 4 channels of audio data with sample rates up to 216 kHz within a single data stream. It further reduces layout
complexity and relieves input/output constraints in digital signal processors.
The CS5364 is available in 48-pin LQFP package in both Commercial (-40° to 85°C) and Automotive grades
(-40° to +105°C). The CDB5364 Customer Demonstration board is also available for device evaluation and
implementation suggestions. Please see “Ordering Information” on page 41 for complete ordering information.
The CS5364 is ideal for high-end and pro-audio systems requiring unrivaled sound quality, transparent conversion,
wide dynamic range and negligible distortion, such as A/V receivers, digital mixing consoles, multi-channel recorders, outboard converters, digital effect processors, and automotive audio systems.
2
DS625F2
CS5364
TABLE OF CONTENTS
1. PIN DESCRIPTION ................................................................................................................................. 6
2. TYPICAL CONNECTION DIAGRAM ..................................................................................................... 9
3. CHARACTERISTICS AND SPECIFICATIONS .................................................................................... 10
RECOMMENDED OPERATING CONDITIONS ................................................................................. 10
ABSOLUTE RATINGS ....................................................................................................................... 10
SYSTEM CLOCKING ......................................................................................................................... 10
DC POWER ........................................................................................................................................ 11
LOGIC LEVELS ................................................................................................................................. 11
PSRR, VQ AND FILT+ CHARACTERISTICS .................................................................................... 11
ANALOG CHARACTERISTICS (COMMERCIAL) .............................................................................. 12
ANALOG PERFORMANCE (AUTOMOTIVE) ..................................................................................... 13
DIGITAL FILTER CHARACTERISTICS ............................................................................................. 14
OVERFLOW TIMEOUT ...................................................................................................................... 14
SERIAL AUDIO INTERFACE - I²S/LJ TIMING ................................................................................... 15
SERIAL AUDIO INTERFACE - TDM TIMING ..................................................................................... 16
SWITCHING SPECIFICATIONS - CONTROL PORT - I²C TIMING ................................................... 17
SWITCHING SPECIFICATIONS - CONTROL PORT - SPI TIMING .................................................. 18
4. APPLICATIONS ................................................................................................................................... 19
4.1 Power ............................................................................................................................................. 19
4.2 Control Port Mode and Stand-Alone Operation .............................................................................. 19
4.2.1 Stand-Alone Mode ................................................................................................................. 19
4.2.2 Control Port Mode ................................................................................................................. 19
4.3 Master Clock Source ...................................................................................................................... 20
4.3.1 On-Chip Crystal Oscillator Driver .......................................................................................... 20
4.3.2 Externally Generated Master Clock ....................................................................................... 20
4.4 Master and Slave Operation ........................................................................................................... 21
4.4.1 Synchronization of Multiple Devices ...................................................................................... 21
4.5 Serial Audio Interface (SAI) Format ................................................................................................ 22
4.5.1 I²S and LJ Format .................................................................................................................. 22
4.5.2 TDM Format .......................................................................................................................... 23
4.5.3 Configuring Serial Audio Interface Format ............................................................................ 23
4.6 Speed Modes ................................................................................................................................. 23
4.6.1 Sample Rate Ranges ............................................................................................................ 23
4.6.2 Using M1 and M0 to Set Sampling Parameters .................................................................... 23
4.6.3 Master Mode Clock Dividers ................................................................................................. 24
4.6.4 Slave Mode Audio Clocking With Auto-Detect ...................................................................... 24
4.7 Master and Slave Clock Frequencies ............................................................................................. 25
4.8 Reset .............................................................................................................................................. 27
4.8.1 Power-Down Mode ................................................................................................................ 27
4.9 Overflow Detection ......................................................................................................................... 27
4.9.1 Overflow in Stand-Alone Mode .............................................................................................. 27
4.9.2 Overflow in Control Port Mode .............................................................................................. 27
4.10 Analog Connections ..................................................................................................................... 28
4.11 Optimizing Performance in TDM Mode ........................................................................................ 29
4.12 DC Offset Control ......................................................................................................................... 29
4.13 Control Port Operation .................................................................................................................. 30
4.13.1 SPI Mode ............................................................................................................................. 30
4.13.2 I²C Mode .............................................................................................................................. 31
5. REGISTER MAP ................................................................................................................................... 32
5.1 Register Quick Reference ............................................................................................................. 32
5.2 00h (REVI) Chip ID Code & Revision Register ............................................................................... 32
DS625F2
3
CS5364
5.3 01h (GCTL) Global Mode Control Register ................................................................................... 32
5.4 02h (OVFL) Overflow Status Register ........................................................................................... 33
5.5 03h (OVFM) Overflow Mask Register ............................................................................................ 33
5.6 04h (HPF) High-Pass Filter Register ............................................................................................. 34
5.7 05h Reserved ................................................................................................................................ 34
5.8 06h (PDN) Power Down Register .................................................................................................. 34
5.9 07h Reserved ................................................................................................................................ 34
5.10 08h (MUTE) Mute Control Register .............................................................................................. 34
5.11 09h Reserved .............................................................................................................................. 35
5.12 0Ah (SDEN) SDOUT Enable Control Register ............................................................................ 35
6. FILTER PLOTS ..................................................................................................................................... 36
7. PARAMETER DEFINITIONS ................................................................................................................ 39
8. PACKAGE DIMENSIONS ................................................................................................................... 40
THERMAL CHARACTERISTICS ....................................................................................................... 40
9. ORDERING INFORMATION ................................................................................................................ 41
10. REVISION HISTORY ......................................................................................................................... 41
LIST OF FIGURES
Figure 1. CS5364 Pinout ............................................................................................................................. 6
Figure 2. Typical Connection Diagram ........................................................................................................ 9
Figure 3. I²S/LJ Timing .............................................................................................................................. 15
Figure 4. TDM Timing ............................................................................................................................... 16
Figure 5. I²C Timing .................................................................................................................................. 17
Figure 6. SPI Timing ................................................................................................................................. 18
Figure 7. Crystal Oscillator Topology ........................................................................................................ 20
Figure 8. Master/Slave Clock Flow ........................................................................................................... 21
Figure 9. Master and Slave Clocking for a Multi-Channel Application ...................................................... 21
Figure 10. I²S Format ................................................................................................................................ 22
Figure 11. LJ Format ................................................................................................................................. 22
Figure 12. TDM Format ............................................................................................................................. 23
Figure 13. Master Mode Clock Dividers .................................................................................................... 24
Figure 14. Slave Mode Auto-Detect Speed ............................................................................................... 24
Figure 15. Recommended Analog Input Buffer ......................................................................................... 28
Figure 16. SPI Format ............................................................................................................................... 30
Figure 17. I²C Write Format ...................................................................................................................... 31
Figure 18. I²C Read Format ...................................................................................................................... 31
Figure 19. SSM Passband ........................................................................................................................ 36
Figure 20. DSM Passband ........................................................................................................................ 36
Figure 21. QSM Passband ........................................................................................................................ 36
Figure 22. SSM Stopband ......................................................................................................................... 37
Figure 23. DSM Stopband ......................................................................................................................... 37
Figure 24. QSM Stopband ........................................................................................................................ 37
Figure 25. SSM -1 dB Cutoff ..................................................................................................................... 38
Figure 26. DSM -1 dB Cutoff .................................................................................................................... 38
Figure 27. QSM -1 dB Cutoff ..................................................................................................................... 38
4
DS625F2
CS5364
LIST OF TABLES
Table 1. Power Supply Pin Definitions ...................................................................................................... 19
Table 2. DIF1 and DIF0 Pin Settings ........................................................................................................ 23
Table 3. M1 and M0 Settings .................................................................................................................... 23
Table 4. Frequencies for 48 kHz Sample Rate using LJ/I²S ..................................................................... 25
Table 5. Frequencies for 96 kHz Sample Rate using LJ/I²S ..................................................................... 25
Table 6. Frequencies for 192 kHz Sample Rate using LJ/I²S ................................................................... 25
Table 7. Frequencies for 48 kHz Sample Rate using TDM ....................................................................... 25
Table 8. Frequencies for 48 kHz Sample Rate using TDM ....................................................................... 25
Table 9. Frequencies for 96 kHz Sample Rate using TDM ....................................................................... 26
Table 10. Frequencies for 96 kHz Sample Rate using TDM ..................................................................... 26
Table 11. Frequencies for 192 kHz Sample Rate using TDM ................................................................... 26
Table 12. Frequencies for 192 kHz Sample Rate using TDM ................................................................... 26
DS625F2
5
CS5364
DIF1/AD1/CDIN
DIF0/AD0/CS
M1/SCL/CCLK
M0/SDA/CDOUT
RST
MDIV
GND
GND
GND
GND
AIN1+
AIN1-
1. PIN DESCRIPTION
48 47 46 45 44 43 42 41 40 39 38 37
AIN2+
1
36
OVFL
AIN2-
2
VLC
GND
3
VA
4
35
34
33
REF_GND
5
FILT+
6
VQ
GND
7
8
VA
CLKMODE
VD
32
31
GND
30
SDOUT1/TDM
29
GND
9
28
VLS
GND
10
27
SDOUT2
AIN4+
11
12
26
25
TSTO
AIN4-
CS5364
TDM
SCLK
LRCK/FS
MCLK
XTO
XTI
VX
GND
GND
GND
GND
GND
AIN3-
AIN3+
13 14 15 16 17 18 19 20 21 22 23 24
Figure 1. CS5364 Pinout
6
DS625F2
CS5364
Pin Name
Pin #
Pin Description
AIN2+, AIN2AIN4+, AIN4AIN3+, AIN3AIN1+, AIN1-
1,2
11,12
13,14
47,48
Differential Analog (Inputs) - Audio signals are presented differently to the delta sigma modulators via the AIN+/- pins.
GND
3,8
10,15
16,17
18,19
29,32
43,44
45,46
Ground (Input) - Ground reference. Must be connected to analog ground.
VA
4,9
Analog Power (Input) - Positive power supply for the analog section
REF_GND
5
Reference Ground (Input) - For the internal sampling circuits. Must be connected to analog
ground..
FILT+
6
Positive Voltage Reference (Output) - Reference voltage for internal sampling circuits.
VQ
7
Quiescent Voltage (Output) - Filter connection for the internal quiescent reference voltage.
VX
20
Crystal Oscillator Power (Input) - Also powers control logic to enable or disable oscillator circuits.
XTI
XTO
21
22
Crystal Oscillator Connections (Input/Output) - I/O pins for an external crystal which may be
used to generate MCLK.
MCLK
23
System Master Clock (Input/Output) - When a crystal is used, this pin acts as a buffered MCLK
Source (Output). When the oscillator function is not used, this pin acts as an input for the system
master clock. In this case, the XTI and XTO pins must be tied low.
LRCK/FS
24
Serial Audio Channel Clock (Input/Output)
In I²S mode, Serial Audio Channel Select. When low, the odd channels are selected.
In LJ mode, Serial Audio Channel Select. When high, the odd channels are selected.
In TDM Mode a frame sync signal. When high, it marks the beginning of a new frame of serial
audio samples. In Slave Mode, this pin acts as an input pin.
SCLK
25
Main timing clock for the Serial Audio Interface (Input/Output) - During Master Mode, this pin
acts as an output, and during Slave Mode it acts as an input pin.
TSTO
26
Test Out (Output) - Must be left unconnected.
SDOUT2
27
Serial Audio Data (Output) - Channels 3,4.
VLS
28
Serial Audio Interface Power - Positive power for the serial audio interface.
SDOUT1/TDM
30
Serial Audio Data (Output) - Channels 1,2
TDM
31
TDM - TDM is complementary TDM data.
VD
33
Digital Power (Input) - Positive power supply for the digital section/
VLC
35
Control Port Interface Power - Positive power for the control port interface.
OVFL
36
Overflow (Output, open drain) - Detects an overflow condition on both left and right channels.
RST
41
Reset (Input) - The device enters a low power mode when low.
DS625F2
7
CS5364
Stand-Alone Mode
CLKMODE
34
CLKMODE (Input) - Setting this pin HIGH places a divide-by-1.5 circuit in the MCLK path to the
core device circuitry.
DIF1
DIF0
37
38
DIF1, DIF0 (Input) - Sets the serial audio interface format.
M1
M0
39
40
Mode Selection (Input) - Determines the operational mode of the device.
MDIV
42
MCLK Divider (Input) - Setting this pin HIGH places a divide-by-2 circuit in the MCLK path to the
core device circuitry.
CLKMODE
34
CLKMODE (Input) - This pin is ignored in Control Port Mode and the same functionality is
obtained from the corresponding bit in the Global Control Register. Note: Should be connected
to GND when using the part in Control Port Mode.
AD1/CDIN
37
I²C Format, AD1 (Input) - Forms the device address input AD[1].
SPI Format, CDIN (Input) - Becomes the input data pin.
AD0/CS
38
I²C Format, AD0 (Input) - Forms the device address input AD[0].
SPI Format, CS (Input) - Acts as the active low chip select input.
SCL/CCLK
39
I²C Format, SCL (Output) - Acts as the serial clock output from the CS5364.
SPI Format, CCLK (Output) - Acts as the serial clock output from the CS5364.
SDA/CDOUT
40
I²C Format SDA (Input/Output) - Acts as an input/output data pin.
SPI Format CDOUT (Output) - Acts as an output only data pin.
MDIV
42
MCLK Divider (Input) - This pin is ignored in Control Port Mode, and the same functionality is
obtained from the corresponding bit in the Global Control Register.
Note: Should be connected to GND when using the part in Control Port Mode.
Control Port Mode
8
DS625F2
CS5364
2. TYPICAL CONNECTION DIAGRAM
Resistor may only be used if
VD is derived from VA. If used,
do not drive any other logic
from VD.
+5V
+
0.01 μF
1 μF
5.1 Ω
4, 9
VA
6
220 μ F
1μF
+
+
0.1 μF
5
7
0.1 μF
Channel 1 Analog
Input Buffer
Channel 2 Analog
Input Buffer
Channel 3 Analog
Input Buffer
Channel 4 Analog
Input Buffer
8
47
48
1
2
13
14
11
12
+
+5V to 3.3V
1 μF
0.01 μF
33
VD
FILT+
VLC
REF_GND
VQ
35
MODE1/SCL/CCLK
MODE0/SDA/CDOUT
OVFL
DIF1/AD1/CDIN
DIF0/AD0/CS
RST
MDIV
GND
AIN 1+
AIN 1-
40
36
37
38
41
42
34
CLKMODE
AIN 2+
+5V to 1.8V
0.01 μF
Power Down
and Mode
Settings
AIN 2AIN 3+
CS5364
AIN 3-
A/D CONVERTER
VLS
28
+5V to 1.8V
0.01 μF
AIN 4+
SDOUT1/TDM
AIN 4-
SDOUT2
TDM
RESERVED
LRCK/FS
SCLK
MCLK
VX
XTI
XTO
30
27
31
26
Audio Data
Processor
24
25
23
20
Timing Logic
and Clock
+5V
21
22
GND
3, 8,10, 15, 16, 17, 18,
19, 29, 32, 43, 44, 45, 46
Figure 2. Typical Connection Diagram
For analog buffer configurations, refer to Cirrus Application Note AN241. Also, a low-cost single-ended-to-differential solution is provided on the Customer Evaluation Board.
DS625F2
9
CS5364
3. CHARACTERISTICS AND SPECIFICATIONS
RECOMMENDED OPERATING CONDITIONS
GND = 0 V, all voltages with respect to 0 V.
Parameter
DC Power Supplies:
Symbol
Min
Typ
Max
Unit
Positive Analog
Positive Crystal
Positive Digital
Positive Serial Logic
Positive Control Logic
VA
VX
VD
VLS
VLC
4.75
4.75
3.14
1.711
1.71
5.0
5.0
3.3
3.3
3.3
5.25
V
(-CQZ)
(-DQZ)
TAC
TAA
-40
-40
-
85
105
°C
Ambient Operating Temperature
1. TDM Quad-Speed Mode specified to operate correctly at VLS ≥ 3.14 V.
ABSOLUTE RATINGS
Operation beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed
at these extremes. Transient currents up to ±100 mA on the analog input pins will not cause SCR latch-up.
Parameter
DC Power Supplies:
Positive Analog
Positive Crystal
Positive Digital
Positive Serial Logic
Positive Control Logic
Input Current
Symbol
Min
Typ
Max
Units
VA
VX
VD
VLS
VLC
-0.3
-
+6.0
V
Iin
-10
+10
mA
Analog Input Voltage
VIN
Digital Input Voltage
VIND
-0.3
VA+0.3
-
VL+0.3
Ambient Operating Temperature (Power Applied)
TA
-50
+95
Storage Temperature
Tstg
-65
+150
Symbol
Min
Input Master Clock Frequency
MCLK
Input Master Clock Duty Cycle
tclkhl
V
°C
SYSTEM CLOCKING
Parameter
10
Typ
Max
Unit
0.512
55.05
MHz
40
60
%
DS625F2
CS5364
DC POWER
MCLK = 12.288 MHz; Master Mode. GND = 0 V.
Parameter
Symbol
Min
Typ
Max
Unit
VA = 5 V
VX = 5 V
VD = 5 V
VD = 3.3 V
VLS, VLC = 5 V
VLS, VLC = 3.3 V
IA
IX
ID
ID
IL
IL
-
51
4
44
25
3
1
56
8
48
28
4
2
mA
mA
mA
mA
mA
mA
VA = 5 V
VLS, VLC,VD = 5 V
IA
ID
-
50
500
-
μA
μA
All Supplies = 5 V
VA = 5 V, VD = VLS = VLC = 3.3 V
-
-
510
360
2.75
580
419
-
mW
mW
mW
mW
Power Supply Current
(Normal Operation)
Power Supply Current
(Power-Down) (Note 1)
Power Consumption
(Normal Operation)
(Power-Down) (Note 1)
1. Power-Down is defined as RST = LOW with all clocks and data lines held static at a valid logic level.
LOGIC LEVELS
Parameter
High-Level Input Voltage
%VLS/VLC
Symbol
Min
VIH
70
Low-Level Input Voltage
%VLS/VLC
VIL
High-Level Output Voltage at 100 μA load
%VLS/VLC
VOH
85
Low-Level Output Voltage at -100 μA load
%VLS/VLC
VOL
-
Iin
-10
OVFL Current Sink
Typ
Max
-
30
-
logic pins only
%
15
-4
Input Leakage Current
Units
-
-
mA
10
μA
PSRR, VQ AND FILT+ CHARACTERISTICS
MCLK = 12.288 MHz; Master Mode. Valid with the recommended capacitor values on FILT+ and VQ as shown in
the “Typical Connection Diagram”.
Parameter
Power Supply Rejection Ratio at (1 kHz)
Symbol
Min
PSRR
Typ
Max
Unit
-
65
-
dB
VQ Nominal Voltage
Output Impedance
Maximum allowable DC current source/sink
-
VA/2
25
10
-
V
kΩ
μA
Filt+ Nominal Voltage
Output Impedance
Maximum allowable DC current source/sink
-
VA
4.4
10
-
V
kΩ
μA
DS625F2
11
CS5364
ANALOG CHARACTERISTICS (COMMERCIAL)
Test Conditions (unless otherwise specified). VA = 5 V, VD = VLS = VLC 3.3 V, and TA = 25° C. Full-scale input
sine wave. Measurement Bandwidth is 10 Hz to 20 kHz.
Parameter
Min
Typ
Max
Unit
108
105
114
111
-
dB
-
-105
-91
-51
-99
-45
dB
108
105
-
114
111
108
-
dB
-
-105
-91
-51
-102
-99
-45
-
dB
108
105
-
114
111
108
-
dB
-
-105
-91
-51
-102
-99
-45
-
dB
-
110
-
dB
Interchannel Gain Mismatch
-
0.1
-
dB
Gain Error
-5
-
5
%
Single-Speed Mode
Symbol
Fs = 48 kHz
Dynamic Range
A-weighted
unweighted
-1 dB
-20 dB
-60 dB
Total Harmonic Distortion + Noise
referred to typical full scale
Double-Speed Mode
Dynamic Range
Fs = 96 kHz
A-weighted
unweighted
40 kHz bandwidth unweighted
Total Harmonic Distortion + Noise
referred to typical full scale
40 kHz bandwidth
Quad-Speed Mode
Dynamic Range
THD+N
-1 dB
-20 dB
-60 dB
-1dB
THD+N
Fs = 192 kHz
A-weighted
unweighted
40 kHz bandwidth unweighted
Total Harmonic Distortion + Noise
referred to typical full scale
40 kHz bandwidth
-1 dB
-20 dB
-60 dB
-1dB
THD+N
Dynamic Performance for All Modes
Interchannel Isolation
DC Accuracy
Gain Drift
Offset Error
HPF enabled
HPF disabled
-
± 100
-
ppm/°C
0
-
-
100
LSB
1.07*VA
1.13*VA
1.19*VA
Vpp
-
250
-
kΩ
-
82
-
dB
Analog Input Characteristics
Full-scale Differential Input Voltage
Input Impedance (Differential)
Common Mode Rejection Ratio
12
CMRR
DS625F2
CS5364
ANALOG PERFORMANCE (AUTOMOTIVE)
Test Conditions (unless otherwise specified). VA = 5.25 to 4.75 V, VD = 5.25 to 3.14 V, VLS = VLC = 5.25 to 1.71 V
and TA = -40° to +85° C. Full-scale input sine wave. Measurement Bandwidth is 10 Hz to 20 kHz.
Parameter
Min
Typ
Max
Unit
106
103
114
111
-
dB
-
-105
-91
-51
-97
-45
dB
106
103
-
114
111
108
-
dB
-
-105
-91
-51
-102
-97
-45
-
dB
106
103
-
114
111
108
-
dB
-
-105
-91
-51
-102
-97
-45
-
dB
-
110
-
dB
Interchannel Gain Mismatch
-
0.1
-
dB
Gain Error
-7
-
7
%
Single-Speed Mode
Symbol
Fs = 48 kHz
Dynamic Range
A-weighted
unweighted
-1 dB
-20 dB
-60 dB
Total Harmonic Distortion + Noise
referred to typical full scale
Double-Speed Mode
Dynamic Range
Fs = 96 kHz
A-weighted
unweighted
40 kHz bandwidth unweighted
Total Harmonic Distortion + Noise
referred to typical full scale
40 kHz bandwidth
Quad-Speed Mode
Dynamic Range
THD+N
-1 dB
-20 dB
-60 dB
-1 dB
THD+N
Fs = 192 kHz
A-weighted
unweighted
40 kHz bandwidth unweighted
Total Harmonic Distortion + Noise
referred to typical full scale
40 kHz bandwidth
-1 dB
-20 dB
-60 dB
-1 dB
THD+N
Dynamic Performance for All Modes
Interchannel Isolation
DC Accuracy
Gain Drift
Offset Error
HPF enabled
HPF disabled
-
± 100
-
ppm/°C
0
-
-
100
LSB
1.02*VA
1.13*VA
1.24*VA
Vpp
250
-
kΩ
82
-
dB
Analog Input Characteristics
Full-scale Input Voltage
Input Impedance (Differential)
Common Mode Rejection Ratio
DS625F2
CMRR
-
13
CS5364
DIGITAL FILTER CHARACTERISTICS
Parameter
Symbol
Min
Typ
Max
Unit
Single-Speed Mode (2 kHz to 54 kHz sample rates)
0
0.47
Fs
Passband Ripple
Passband (Note 1)
(-0.1 dB)
-0.035
0.035
dB
Stopband (Note 1)
0.58
Stopband Attenuation
-
-95
Total Group Delay (Fs = Output Sample Rate)
tgd
-
Fs
-
12/Fs
dB
s
Double-Speed Mode (54 kHz to 108 kHz sample rates)
Passband (Note 1)
(-0.1 dB)
0
Passband Ripple
-0.035
Stopband (Note 1)
0.68
Stopband Attenuation
-
-92
Total Group Delay (Fs = Output Sample Rate)
tgd
-
0.45
Fs
0.035
dB
Fs
9/Fs
dB
s
Quad-Speed Mode (108 kHz to 216 kHz sample rates)
0
0.24
Fs
Passband Ripple
Passband (Note 1)
(-0.1 dB)
-0.035
0.035
dB
Stopband (Note 1)
0.78
Stopband Attenuation
-92
-
dB
Total Group Delay (Fs = Output Sample Rate)
tgd
-
Fs
-
5/Fs
s
-
1
20
-
Hz
10
-
Deg
-
0
dB
105/Fs
-
s
High-Pass Filter Characteristics
Frequency Response (Note 2)
-3.0 dB
-0.13 dB
Phase Deviation (Note 2)
@ 20 Hz
-
Passband Ripple
Filter Settling Time
Notes:
1. The filter frequency response scales precisely with Fs.
2. Response shown is for Fs equal to 48 kHz. Filter characteristics scale with Fs.
OVERFLOW TIMEOUT
Logic "0" = GND = 0 V; Logic "1" = VLS; CL = 30 pF, timing threshold is 50% of VLS.
Parameter
Symbol
Min
Typ
Max
Unit
-
(217-1)/Fs
2972
683
-
ms
OVFL time-out on overrange condition
Fs = 44.1 kHz
Fs = 192 kHz
14
DS625F2
CS5364
SERIAL AUDIO INTERFACE - I²S/LJ TIMING
The serial audio port is a three-pin interface consisting of SCLK, LRCK and SDOUT.
Logic "0" = GND = 0 V; Logic "1" = VLS; CL = 20 pF, timing threshold is 50% of VLS.
Parameter
Symbol
Min
Typ
Max
Unit
-
2
54
108
-
54
108
216
kHz
1/(64*216 kHz)
(CLKMODE = 0)(Note 2)
(CLKMODE = 1)(Note 2)
tPERIOD
tHIGH
tHIGH
64*Fs
72.3
40
28
50
33
64*Fs
60
38
Hz
ns
%
%
before SCLK rising
after SCLK rising
tSETUP1
tHOLD1
20
20
-
-
ns
before SCLK rising
after SCLK rising (VLS = 1.8 V)
after SCLK rising (VLS = 3.3 V)
after SCLK rising (VLS = 5 V)
tSETUP2
tHOLD2
tHOLD2
tHOLD2
10
20
10
5
-
-
ns
1/(64*216 kHz)
tPERIOD
tHIGH
72.3
28
64*Fs
-
65
Hz
ns
%
before SCLK rising
after SCLK rising
tSETUP1
tHOLD1
20
20
-
-
ns
before SCLK rising (VLS = 1.8 V)
before SCLK rising (VLS = 3.3 V)
before SCLK rising (VLS = 5 V)
after SCLK rising (VLS = 1.8 V)
after SCLK rising (VLS = 3.3 V)
after SCLK rising (VLS = 5 V)
tSETUP2
tSETUP2
tSETUP2
tHOLD2
tHOLD2
tHOLD2
4
10
10
20
10
5
-
-
ns
Sample Rates
Single-Speed Mode
Double-Speed Mode
Quad-Speed Mode
Master Mode
SCLK Frequency
SCLK Period
SCLK Duty Cycle (Note 1)
LRCK setup
LRCK hold
SDOUT setup
SDOUT hold
Slave Mode
SCLK Frequency (Note 3)
SCLK Period
SCLK Duty Cycle
LRCK setup
LRCK hold
SDOUT setup
SDOUT hold
Notes:
1. Duty cycle of generated SCLK depends on duty cycle of received MCLK as specified under “System
Clocking” on page 10.
2. CLKMODE functionality described in Section 4.6.3 "Master Mode Clock Dividers" on page 24.
3. In Slave Mode, the SCLK/LRCK ratio can be set according to preference. However, chip performance
is guaranteed only when using the ratios in Section 4.7 Master and Slave Clock Frequencies on page
25.
t PERIOD
t HIGH
SCLK
t HOLD1
LRCK
channel
tSET UP1
channel
t SET UP2
SDOUT
data
t HOLD2
data
Figure 3. I²S/LJ Timing
DS625F2
15
CS5364
SERIAL AUDIO INTERFACE - TDM TIMING
The serial audio port is a three-pin interface consisting of SCLK, LRCK and SDOUT.
Logic "0" = GND = 0 V; Logic "1" = VLS; CL = 20 pF, timing threshold is 50% of VLS.
Parameter
Symbol
Min
Typ
Max
Unit
-
2
54
108
-
54
108
216
kHz
kHz
kHz
1/(256*216 kHz)
(CLKMODE = 0)(Note 3)
(CLKMODE = 1)(Note 3)
tPERIOD
tHIGH1
tHIGH1
256*Fs
18
40
28
50
33
256*Fs
60
38
Hz
ns
%
%
before SCLK rising (Single-Speed Mode)
before SCLK rising (Double-Speed Mode)
before SCLK rising (Quad-Speed Mode)
in SCLK cycles
tSETUP1
tSETUP1
tSETUP1
tHIGH2
20
18
5
128
-
128
ns
ns
ns
-
before SCLK rising
after SCLK rising
tSETUP2
tHOLD2
5
5
-
-
ns
ns
1/(256*216 kHz)
tPERIOD
tHIGH1
18
28
256*Fs
-
65
Hz
ns
%
before SCLK rising (Single-Speed Mode)
before SCLK rising (Double-Speed Mode)
before SCLK rising (Quad-Speed Mode)
in SCLK cycles
tSETUP1
tSETUP1
tSETUP1
tHIGH2
20
20
10
1
-
244
ns
ns
ns
-
before SCLK rising
after SCLK rising
tSETUP2
tHOLD2
5
5
-
-
ns
ns
Sample Rates
Single-Speed Mode
Double-Speed Mode
Quad-Speed Mode1
Master Mode
SCLK Frequency
SCLK Period
SCLK Duty Cycle (Note 2)
FS setup
FS setup
FS setup
FS width
SDOUT setup
SDOUT hold
Slave Mode
SCLK Frequency (Note 4)
SCLK Period
SCLK Duty Cycle
FS setup
FS setup
FS setup
FS width
SDOUT setup
SDOUT hold
Notes:
1. TDM Quad-Speed Mode only specified to operate correctly at VLS ≥ 3.14 V.
2. Duty cycle of generated SCLK depends on duty cycle of received MCLK as specified under “System
Clocking” on page 10.
3. CLKMODE functionality described in Section 4.6.3 "Master Mode Clock Dividers" on page 24.
4. In Slave Mode, the SCLK/LRCK ratio can be set according to preference; chip performance is guaranteed only when using the ratios in Section 4.7 Master and Slave Clock Frequencies on page 25.
t PERIOD
t HIGH1
SCLK
t HIGH2
t SETUP1
FS
new frame
t SETUP2
SDOUT
data
t HOLD2
data
data
Figure 4. TDM Timing
16
DS625F2
CS5364
SWITCHING SPECIFICATIONS - CONTROL PORT - I²C TIMING
Inputs: Logic 0 = DGND, Logic 1 = VLC, SDA CL = 30 pF
Symbol
Min
Max
Unit
SCL Clock Frequency
Parameter
fscl
-
100
kHz
RST Rising Edge to Start
tirs
600
ns
Bus Free Time Between Transmissions
tbuf
4.7
µs
Start Condition Hold Time (prior to first clock pulse)
thdst
4.0
Clock Low time
tlow
4.7
Clock High Time
thigh
4.0
Setup Time for Repeated Start Condition
tsust
4.7
thdd
0
tsud
600
trc
-
1
SDA Hold Time from SCL Falling
(Note 1)
SDA Setup time to SCL Rising
Rise Time of SCL and SDA
-
µs
ns
µs
tfc
-
300
ns
Setup Time for Stop Condition
tsusp
4.7
-
µs
Acknowledge Delay from SCL Falling
tack
300
1000
ns
Fall Time SCL and SDA
Notes:
1. Data must be held for sufficient time to bridge the transition time, tfc, of SCL.
RST
t
irs
Stop
Re p e at e d
Sta rt
Sta rt
t rd
t fd
Stop
SDA
t
buf
t
t
hdst
t
high
t fc
hdst
t susp
S CL
t
lo w
t
hdd
t sud
t ack
t sust
t rc
Figure 5. I²C Timing
DS625F2
17
CS5364
SWITCHING SPECIFICATIONS - CONTROL PORT - SPI TIMING
Inputs: Logic 0 = DGND, Logic 1 = VLC, CDOUT CL = 30 pF
Parameter
Symbol
Min
Max
Units
CCLK Clock Frequency
fsck
0
6.0
MHz
RST Rising Edge to CS Falling
tsrs
20
CS Falling to CCLK Edge
tcss
20
CS High Time Between Transmissions
tcsh
1.0
CCLK Low Time
tscl
66
CCLK High Time
tsch
66
CDIN to CCLK Rising Setup Time
tdsu
40
tdh
15
(Note 1)
CCLK Rising to DATA Hold Time
CCLK Falling to CDOUT Stable
tpd
Rise Time of CDOUT
tr1
Fall Time of CDOUT
tf1
Rise Time of CCLK and CDIN
(Note 2)
tr2
Fall Time of CCLK and CDIN
(Note 2)
tf2
ns
μs
-
50
ns
25
-
100
Notes:
1. Data must be held for sufficient time to bridge the transition time of CCLK.
2. For fsck <1 MHz
RST
tsrs
CS
tcss
tsch
tcsh
tscl
tr2
CCLK
tf2
tdsu
tdh
CDIN
tpd
CDOUT
Figure 6. SPI Timing
18
DS625F2
CS5364
4. APPLICATIONS
4.1
Power
CS5364 features five independent power pins that power various functional blocks within the device and
allow for convenient interfacing to other devices. Table 1 shows what portion of the device is powered from
each supply pin. Please refer to “Recommended Operating Conditions” on page 10 for the valid range of
each power supply pin. The power supplied to each power pin can be independent of the power supplied to
any other pin.
Power Supply Pin
Pin Name
Pin Number
Functional Block
VA
4, 9
Analog Core
VX
20
Crystal Oscillator
VD
33
Digital Core
VLS
28
Serial Audio Interface
VLC
35
Control Logic
Table 1. Power Supply Pin Definitions
To meet full performance specifications, the CS5364 requires normal low-noise board layout. The “Typical
Connection Diagram” on page 9 shows the recommended power arrangements, with the VA pins connected
to a clean supply. VD, which powers the digital filter, may be run from the system logic supply, or it may be
powered from the analog supply via a single-pole decoupling filter.
Decoupling capacitors should be placed as near to the ADC as possible, with the lower value high-frequency capacitors placed nearest to the device leads. Clocks should be kept away from the FILT+ and VQ pins
in order to avoid unwanted coupling of these signals into the device. The FILT+ and VQ decoupling capacitors must be positioned to minimize the electrical path to ground.
The CDB5364 evaluation board demonstrates optimum layout for the device.
4.2
Control Port Mode and Stand-Alone Operation
4.2.1 Stand-Alone Mode
In Stand-Alone Mode, the CS5364 is programmed exclusively with multi-use configuration pins. This mode
provides a set of commonly used features, which comprise a subset of the complete set of device features
offered in Control Port Mode.
To use the CS5364 in Stand-Alone Mode, the configuration pins must be held in a stable state, at valid logic
levels, and RST must be asserted until the power supplies and clocks are stable and valid. More information on the reset function is available in Section 4.5 on page 22.
4.2.2 Control Port Mode
In Control Port Mode, all features of the CS5364 are available. Four multi-use configuration pins become
software pins that support the I²C or SPI bus protocol. To initiate Control Port Mode, a controller that supports I²C or SPI must be used to enable the internal register functionality. This is done by setting the CPEN bit (Bit 7 of the Global Control Port Register). Once CP-EN is set, all of the device configuration pins
are ignored, and the internal register settings determine the operating modes of the part. Figure 4.13 on
page 30 provides detailed information about the I²C and SPI bus protocols.
DS625F2
19
CS5364
4.3
Master Clock Source
The CS5364 requires a Master Clock that can come from one of two sources: an on-chip crystal oscillator
driver or an externally generated clock.
4.3.1 On-Chip Crystal Oscillator Driver
When using the on-board crystal oscillator driver, the XTI pin (pin 21) is the input for the Master Clock
(MCLK) to the device. The XTO pin (pin 22) must not be used to drive anything other than the oscillator
tank circuitry. When using the on-board crystal driver, the topology shown in Figure 7 must be used. The
crystal oscillator manufacturer supplies recommended capacitor values. A buffered copy of the XTI input is
available as an output on the MCLK pin (pin 23), which is level-controlled by VLS and may be used to synchronize other parts to the device.
XTI
XTO
21
22
Figure 7. Crystal Oscillator Topology
4.3.2 Externally Generated Master Clock
If an external clock is used, the XTI and XTO pins must be grounded, and the MCLK pin becomes an input
for the system master clock. The incoming MCLK should be at the logic level set by the user on the VLS
supply pin.
20
DS625F2
CS5364
4.4
Master and Slave Operation
CS5364 operation depends on two clocks that are synchronously derived from MCLK: SCLK and LRCK/FS.
See Section 4.5 on page 22 for a detailed description of SCLK and LRCK/FS.
The CS5364 can operate as either clock master or clock slave with respect to SCLK and LRCK/FS. In Master Mode, the CS5364 derives SCLK and LRCK/FS synchronously from MCLK and outputs the derived
clocks on the SCLK pin (pin 25) and the LRCK/FS pin (pin 24), respectively. In Slave Mode, the SCLK and
LRCK/FS are inputs, and the input signals must be synchronously derived from MCLK by a separate device
such as another CS5364 or a microcontroller. Figure 8 illustrates the clock flow of SCLK and LRCK/FS in
both Master and Slave Modes.
The Master/Slave operation is controlled through the settings of M1 and M0 pins in Stand-Alone Mode or
by the M[1] and M[0] bits in the Global Mode Control Register in Control Port Mode. See Section 4.6 on page
23 for more information regarding the configuration of M1 and M0 pins or M[1] and M[0] bits.
ADC as
clock
master
SCLK
LRCK/FS
Controller
ADC as
clock
slave
SCLK
LRCK/FS
Controller
Figure 8. Master/Slave Clock Flow
4.4.1 Synchronization of Multiple Devices
To ensure synchronous sampling in applications where multiple ADCs are used, the MCLK and LRCK must
be the same for all CS5364 devices in the system. If only one master clock source is needed, one solution
is to place one CS5364 in Master Mode, and slave all of the other devices to the one master, as illustrated
in Figure 9. If multiple master clock sources are needed, one solution is to supply all clocks from the same
external source and time the CS5364 reset de-assertion with the falling edge of MCLK. This will ensure that
all converters begin sampling on the same clock edge.
Master
ADC
SCLK & LRCK/FS
Slave1
ADC
Slave2
ADC
Slave3
ADC
Figure 9. Master and Slave Clocking for a Multi-Channel Application
DS625F2
21
CS5364
4.5
Serial Audio Interface (SAI) Format
The SAI port consists of two timing pins (SCLK, LRCK/FS) and four audio data output pins (SDOUT1/TDM,
SDOUT2, SDOUT3/TDM and SDOUT4). The CS5364 output is serial data in I²S, Left-Justified (LJ), or Time
Division Multiplexed (TDM) digital audio interface formats. These formats are available to the user in both
Stand-Alone Mode and Control Port Mode.
4.5.1 I²S and LJ Format
The I²S and LJ formats are both two-channel protocols. During one LRCK period, two channels of data are
transmitted, odd channels first, then even. The MSB is always clocked out first.
In Slave Mode, the number of SCLK cycles per channel is fixed as described under “Serial Audio Interface
- I²S/LJ Timing” on page 15. In Slave Mode, if more than 32 SCLK cycles per channel are received from a
master controller, the CS5364 will fill the longer frame with trailing zeros. If fewer than 24 SCLK cycles per
channel are received from a master, the CS5364 will truncate the serial data output to the number of SCLK
cycles received. For a complete overview of serial audio interface formats, please refer to Cirrus Logic Application Note AN282.
receiver latches data on rising edges of SCLK
SCLK
LRCK
SDOUT
Even Channels 2,4, ...
Odd Channels 1,3, ...
MSB
...
LSB
MSB
...
LSB
MSB
Figure 10. I²S Format
receiver latches data on rising edges of SCLK
SCLK
LRCK
SDOUT
Even Channels 2,4, ...
Odd Channels 1,3, ...
MSB
...
LSB
MSB
...
LSB
MSB
Figure 11. LJ Format
22
DS625F2
CS5364
4.5.2 TDM Format
In TDM Mode, all four channels of audio data are serially clocked out during a single Frame Sync (FS) cycle, as shown in Figure 12. The rising edge of FS signifies the start of a new TDM frame cycle. Each channel slot occupies 32 SCLK cycles, with the data left justified and with MSB first. TDM output data should be
latched on the rising edge of SCLK within time specified under ‘Serial Audio Interface - TDM Timing” section
on page 16. The TDM data output port resides on the SDOUT1 pin. The TDM output pin is complimentary
TDM data. All SDOUT pins will remain active during TDM Mode. Refer to Section 4.11 “Optimizing Performance in TDM Mode” on page 29 for critical system design information.
FS
SCLK
TDM OUT
LSB MSB
LSB MSB
LSB MSB
LSB MSB
LSB
Channel 1
Channel 2
Channel 3
Channel 4
32 clks
32 clks
32 clks
32 clks
32 clks
32 clks
32 clks
32 clks
Data
MSB
LSB
Zeroes
Figure 12. TDM Format
4.5.3 Configuring Serial Audio Interface Format
The serial audio interface format of the data is controlled by the configuration of the DIF1 and DIF0 pins in
Stand-Alone Mode or by the DIF[1] and DIF[0] bits in the Global Mode Control Register in Control Port
Mode, as shown in Table 2.
DIF1
DIF0
Mode
0
0
Left-Justified
0
1
I²S
1
0
TDM
1
1
Reserved
Table 2. DIF1 and DIF0 Pin Settings
4.6
Speed Modes
4.6.1 Sample Rate Ranges
CS5364 supports sampling rates from 2 kHz to 21 kHz, divided into three ranges: 2 kHz - 54 kHz, 54 kHz 108 kHz, and 108 kHz - 216 kHz. These sampling speed modes are called Single-Speed Mode (SSM),
Double-Speed Mode (DSM), and Quad-Speed Mode (QSM), respectively.
4.6.2 Using M1 and M0 to Set Sampling Parameters
The Master/Slave operation and the sample rate range are controlled through the settings of the M1 and
M0 pins in Stand-Alone Mode, or by the M[1] and M[0] bits in the Global Mode Control Register in Control
Port Mode, as shown in Table 3.
M1
M0
Mode
Frequency Range
0
0
Single-Speed Master Mode (SSM)
2 kHz - 54 kHz
0
1
Double-Speed Master Mode (DSM)
54 kHz - 108 kHz
1
0
Quadruple-Speed Master Mode (QSM)
108 kHz - 216 kHz
1
1
Auto-Detected Speed Slave Mode
2 kHz - 216 kHz
Table 3. M1 and M0 Settings
DS625F2
23
CS5364
4.6.3
Master Mode Clock Dividers
Figure 13 shows the configuration of the MCLK dividers and the sample rate dividers for Master Mode, including the significance of each MCLK divider pin (in Stand-Alone Mode) or bit (in Control Port Mode).
SAMPLE RATE DIVIDERS
MCLK DIVIDERS
MCLK
pin
0/1
0/1
÷1
÷1
÷1
÷ 1.5
÷2
÷2
CLKMODE
bit
CLKMODE
MDIV
MDIV1
÷ 256
Single
Speed
00
÷ 128
Double
Speed
01
÷ 64
Quad
Speed
10
0/1
LRCK/ FS
M1 M0
÷4
Single
Speed
00
÷2
Double
Speed
01
÷1
Quad
Speed
10
n/a
MDIV0
SCLK
Figure 13. Master Mode Clock Dividers
4.6.4
Slave Mode Audio Clocking With Auto-Detect
In Slave Mode, CS5364 auto-detects speed mode, which eliminates the need to configure M1 and M0 when
changing among speed modes. The external MCLK is subject to clock dividers as set by the clock divider
pins in Stand-Alone Mode or the clock divider bits in Control Port Mode. The CS5364 compares the divideddown, internal MCLK to the incoming LRCK/FS and sets the speed mode based on the MCLK/LRCK ratio
as shown in Figure 14.
MCLK DIVIDERS
External
MCLK
0/1
0/1
÷1
÷1
÷1
÷ 1.5
÷2
÷2
SPEED MODE
0/1
pin
CLKMODE
MDIV
n/a
bit
CLKMODE
MDIV1
MDIV0
Internal
MCLK
÷LRCK
256
Single-Speed
128
Double-Speed
64
Quad-Speed
LRCK
Figure 14. Slave Mode Auto-Detect Speed
24
DS625F2
CS5364
4.7
Master and Slave Clock Frequencies
Tables 4 through 12 show the clock speeds for sample rates of 48 kHz, 96 kHz and 192 kHz. The
MCLK/LRCK ratio should be kept at a constant value during each mode. In Master Mode, the device outputs
the frequencies shown. In Slave Mode, the SCLK/LRCK ratio can be set according to design preference.
However, device performance is guaranteed only when using the ratios shown in the tables.
Control Port Mode only
LJ/I²S MASTER OR SLAVE
SSM Fs = 48 kHz
MCLK Divider
÷4
÷3
÷2
÷1.5
÷1
MCLK (MHz)
49.152
36.864
24.576
18.384
12.288
SCLK (MHz)
3.072
3.072
3.072
3.072
3.072
MCLK/LRCK Ratio
1024
768
512
384
256
SCLK/LRCK Ratio
64
64
64
64
64
Table 4. Frequencies for 48 kHz Sample Rate using LJ/I²S
LJ/I²S MASTER OR SLAVE
DSM Fs = 96 kHz
MCLK Divider
÷4
÷3
÷2
÷1.5
÷1
MCLK (MHz)
49.152
36.864
24.567
18.384
12.288
SCLK (MHz)
6.144
6.144
6.144
6.144
6.144
MCLK/LRCK Ratio
512
384
256
192
128
SCLK/LRCK Ratio
64
64
64
64
64
÷1.5
÷1
Table 5. Frequencies for 96 kHz Sample Rate using LJ/I²S
LJ/I²S MASTER OR SLAVE
QSM Fs = 192 kHz
MCLK Divider
÷4
÷3
÷2
MCLK (MHz)
49.152
36.864
24
18.384
12.288
SCLK (MHz)
12.288
12.288
12.288
12.288
12.288
MCLK/LRCK Ratio
256
192
128
96
64
SCLK/LRCK Ratio
64
64
64
64
64
Table 6. Frequencies for 192 kHz Sample Rate using LJ/I²S
TDM MASTER
SSM Fs = 48 kHz
MCLK Divider
÷4
÷3
÷2
÷1.5
÷1
MCLK (MHz)
49.152
36.864
24.567
18.384
12.288
SCLK (MHz)
12.288
12.288
12.288
12.288
12.288
MCLK/FS Ratio
1024
768
512
384
256
SCLK/FS Ratio
256
256
256
256
256
Table 7. Frequencies for 48 kHz Sample Rate using TDM
TDM SLAVE
SSM Fs = 48 kHz
MCLK Divider
÷4
÷3
÷2
÷1.5
÷1
MCLK (MHz)
49.152
36.864
24.567
18.384
12.288
SCLK (MHz)
12.288
12.288
12.288
12.288
12.288
MCLK/FS Ratio
1024
768
512
384
256
SCLK/FS Ratio
256
256
256
256
256
Table 8. Frequencies for 48 kHz Sample Rate using TDM
DS625F2
25
CS5364
TDM MASTER
DSM Fs = 96 kHz
MCLK Divider
÷4
÷3
÷2
-
-
MCLK (MHz)
49.152
36.864
24.567
-
-
SCLK (MHz)
24.576
24.576
24.576
-
-
MCLK/FS Ratio
512
384
256
-
-
SCLK/FS Ratio
256
256
256
-
-
Table 9. Frequencies for 96 kHz Sample Rate using TDM
TDM SLAVE
DSM Fs = 96 kHz
MCLK Divider
÷4
÷3
÷2
÷1.5
÷1
MCLK (MHz)
49.152
36.864
24.567
18.384
12.288
SCLK (MHz)
24.576
24.576
24.576
24.576
24.576
MCLK/FS Ratio
512
384
256
192
128
SCLK/FS Ratio
256
256
256
256
256
Table 10. Frequencies for 96 kHz Sample Rate using TDM
TDM MASTER
QSM Fs = 192 kHz
MCLK Divider
÷4
-
-
-
-
MCLK (MHz)
49.152
-
-
-
-
SCLK (MHz)
49.152
-
-
-
-
MCLK/FS Ratio
256
-
-
-
-
SCLK/FS Ratio
256
-
-
-
-
Table 11. Frequencies for 192 kHz Sample Rate using TDM
TDM SLAVE
QSM Fs = 192 kHz
MCLK Divider
÷4
÷3
÷2
÷1.5
÷1
MCLK (MHz)
49.152
36.864
24.567
18.384
12.288
SCLK (MHz)
49.152
49.152
49.152
49.152
49.152
MCLK/FS Ratio
256
192
128
96
64
SCLK/FS Ratio
256
256
256
256
256
Table 12. Frequencies for 192 kHz Sample Rate using TDM
26
DS625F2
CS5364
4.8
Reset
The device should be held in reset until power is applied and all incoming clocks are stable and valid. Upon
de-assertion of RST, the state of the configuration pins is latched, the state machine begins, and the device
starts sending audio output data a maximum of 524288 MCLK cycles after the release of RST. When changing between mode configurations in Stand-Alone Mode, including clock dividers, serial audio interface format, master/slave, or speed modes, it is recommended to reset the device following the change by holding
the RST pin low for a minimum of one MCLK cycle and then restoring the pin to a logic-high condition.
4.8.1 Power-Down Mode
The CS5364 features a Power-Down Mode in which power is temporarily withheld from the modulators, the
crystal oscillator driver, the digital core, and the serial port. The user can access Power-Down Mode by
holding the device in reset and holding all clock lines at a static, valid logic level (either logic-high or logiclow). “DC Power” on page 11 shows the power-saving associated with Power-Down Mode.
4.9
Overflow Detection
4.9.1 Overflow in Stand-Alone Mode
The CS5364 includes overflow detection on all input channels. In Stand-Alone Mode, this information is
presented as open drain, active low on the OVFL pin. The pin will go to a logical low as soon as an overrange condition in any channel is detected. The data will remain low, then time-out as specified in Section
"Overflow Timeout" on page 14. After the time-out, the OVFL pin will return to a logical high if there has not
been any other over-range condition detected. Note that an over-range condition on any channel will restart
the time-out period.
4.9.2 Overflow in Control Port Mode
In Control Port Mode, the Overflow Status Register interacts with the Overflow Mask Register to provide
interrupt capability for each individual channel. See Section 5.4 "02h (OVFL) Overflow Status Register" on
page 33 for details on these two registers.
DS625F2
27
CS5364
4.10
Analog Connections
The analog modulator samples the input at half of the internal Master Clock frequency, or 6.144 MHz nominally. The digital filter will reject signals within the stopband of the filter. However, there is no rejection of
input signals that are at (N X 6.144 MHz) the digital passband frequency, where n=0,1,2.... Refer to
Figure 15, which shows the suggested filter that will attenuate any noise energy at 6.144 MHz in addition to
providing the optimum source impedance for the modulators. The use of capacitors that have a large voltage coefficient (such as general-purpose ceramics) must be avoided since these can degrade signal linearity. COG capacitors are recommended for this application. For additional configurations, refer to Cirrus
Application Note AN241.
634 Ω
470 pF
COG
-
91 Ω
10 uF
ADC AIN+
+
AIN+
100kΩ
10 k Ω
COG
VQ
2700 pF
10 k Ω
10 uF
AIN-
+
100kΩ
-
91 Ω
ADC AIN-
470 pF
COG
634 Ω
Figure 15. Recommended Analog Input Buffer
28
DS625F2
CS5364
4.11
Optimizing Performance in TDM Mode
Noise Management is a design technique that is utilized in the majority of audio A/D converters. Noise management is relatively simple conceptually. The goal of noise management is to interleave the on-chip digital
activity with the analog sampling processes to ensure that the noise generated by the digital activity is minimized (ideally non-existant) when the analog sampling occurs. Noise management, when implemented
properly, minimizes the on-chip interference between the analog and digital sections of the device. This
technique has proven to be very effective and has simplified the process of implementing an A/D converter
into a systems design. The dominate source of interference (and most difficult to control) is the activity on
the serial audio interface (SAI). However, noise management becomes more difficult to implement as audio
sample rates increase simply due to the fact that there is less time between transitions on the SAI.
The CS5364 A/D converter supports a multi-channel Time-Division-Multiplexed interface for Single, Double
and Quad-Speed sampling modes. In Single-Speed Mode, sample rates below 50 kHz, the required frequencies of the audio serial ports are sufficiently low that it is possible to implement noise-management. In
this mode, the performance of the devices are relatively immune to activity on the audio ports.
However, in Double-Speed and Quad-Speed modes there is insufficient time to implement noise management due to the required frequencies of the audio ports. Therefore, analog performance, both dynamic
range and THD+N, can be degraded if the serial port transitions occurr concurrently with the analog sampling. The magnitude of the interference is not only related to the timing of the transition but also the di/dt or
transient currents associated with the activity on the serial ports. Even though there is insufficient time to
properly implement noise management, the interference effects can be minimized by controlling the transient currents required of the serial ports in Double- and Quad-Speed TDM Modes.
In addition to standard mixed-signal design techniques, system performance can be maximized by following
several guidelines during design.
– Operate the serial audio port at 3.3 V and not 5 V. The lower serial port voltage lowers transent
currents.
– Operate the A/D converter as a system clock Slave. The serial clock and Left/Right clock become highimpedence inputs in this mode and do not generate significant transient currents.
– Place a buffer on the serial data output very near the A/D converter. Minimizing the stray capacitance
of the printed circuit board trace and the loading presented by other devices on the serial data line will
minimize the transient current.
– Place a resistor, near the converter, beween the A/D serial data output and the buffer. This resistor will
reduce the instantaneous switching currents into the capacitive loads on the nets, resulting in a slower
edge rate. The value of the resistor should be as high as possible without causing timing problems
elsewhere in the system.
4.12
DC Offset Control
The CS5364 includes a dedicated high-pass filter for each channel to remove input DC offset at the system
level. A DC level may result in audible “clicks” when switching between devices in a multi-channel system.
In Stand-Alone Mode, all of the high-pass filters remain enabled. In Control Port Mode, the high-pass filters
default to enabled, but may be controlled by writing to the HPF register. If any HPF bit is taken low, the respective high-pass filter is enabled, and it continuously subtracts a measure of the DC offset from the output
of the decimation filter. If any HPF bit is taken high during device operation, the value of the DC offset register is frozen, and this DC offset will continue to be subtracted from the conversion result.
DS625F2
29
CS5364
4.13
Control Port Operation
The Control Port is used to read and write the internal device registers. It supports two industry standard
formats, I²C and SPI. The part is in I²C format by default. SPI Mode is selected if there is ever a high-to-low
transition on the AD0/CS pin after the RST pin has been restored high.
In Control Port Mode, all features of the CS5364 are available. Four multi-use configuration pins become
software pins that support the I²C or SPI bus protocol. To initiate Control Port Mode, a controller that supports I²C or SPI must be used to enable the internal register functionality. This is done by setting the
CP-EN bit (Bit 7 of the Global Control Port Register). Once CP-EN is set, all of the device configuration pins
are ignored, and the internal register settings determine the operating modes of the part.
4.13.1 SPI Mode
In SPI Mode, CS is the CS5364 chip select signal; CCLK is the control port bit clock (input into the CS5364
from a controller); CDIN is the input data line from a controller; CDOUT is the output data line to a controller.
Data is clocked in on the rising edge of CCLK and is supplied on the falling edge of CCLK.
To write to a register, bring CS low. The first seven bits on CDIN form the chip address and must be
1001111. The eighth bit is a read/write indicator (R/W), which should be low to write. The next eight bits
form the Memory Address Pointer (MAP), which is set to the address of the register that is to be updated.
The next eight bits are the data that will be placed into the register designated by the MAP. During writes,
the CDOUT output stays in the Hi-Z state. It may be externally pulled high or low with a 47 kΩ resistor, if
desired.
There is a MAP auto-increment capability, which is enabled by the INCR bit in the MAP register. If INCR is
a zero, the MAP will stay constant for successive read or writes. If INCR is set to a 1, the MAP will autoincrement after each byte is read or written, allowing block reads or writes of successive registers.
To read a register, the MAP has to be set to the correct address by executing a partial write cycle that finishes (CS high) immediately after the MAP byte. The MAP auto-increment bit (INCR) may be set or not, as
desired. To begin a read, bring CS low, send out the chip address and set the read/write bit (R/W) high.
The next falling edge of CCLK will clock out the MSB of the addressed register (CDOUT will leave the high
impedance state). If the MAP auto-increment bit is set to 1, the data for successive registers will appear
consecutively
.
CS
CC LK
C H IP
ADDRESS
C D IN
1001111
MAP
R/W
C H IP
ADDRESS
DATA
MSB
b y te 1
LSB
1001111
R/W
b y te n
High Impedance
MSB
CDOUT
LSB MSB
LSB
MAP = Memory Address Pointer, 8 bits, MSB first
Figure 16. SPI Format
30
DS625F2
CS5364
4.13.2 I²C Mode
In I²C Mode, SDA is a bidirectional data line. Data is clocked into and out of the part by the clock, SCL.
There is no CS pin. Pins AD0 and AD1 form the two least-significant bits of the chip address and should
be connected through a resistor to VLC or DGND, as desired. The state of the pins is latched when the
CS5364 is being released from RST.
A Start condition is defined as a falling transition of SDA while SCL is high. A Stop condition is a rising transition of SDA while SCL is high. All other transitions of SDA occur while SCL is low. The first byte sent to
the CS5364 after a Start condition consists of a 7-bit chip address field and a R/W bit (high for a read, low
for a write). The upper five bits of the 7-bit address field are fixed at 10011. To communicate with a CS5364,
the chip address field, which is the first byte sent to the CS5364, should match 10011 and be followed by
the settings of the AD1 and AD0. The eighth bit of the address is the R/W bit. If the operation is a write, the
next byte is the Memory Address Pointer (MAP), which selects the register to be read or written. If the operation is a read, the contents of the register pointed to by the MAP will be output. Setting the auto-increment bit in MAP allows successive reads or writes of consecutive registers. Each byte is separated by an
acknowledge bit. The ACK bit is output from the CS5364 after each input byte is read and is input to the
CS5364 from the microcontroller after each transmitted byte.
Since the read operation cannot set the MAP, an aborted write operation is used as a preamble. The write
operation is aborted after the acknowledge for the MAP byte by sending a Stop condition. The following
pseudocode illustrates an aborted write operation followed by a read operation.
Send start condition.
Send 10011xx0 (chip address & write operation).
Receive acknowledge bit.
Send MAP byte, auto increment off.
Receive acknowledge bit.
Send stop condition, aborting write.
Send start condition.
Send 10011xx1 (chip address & read operation).
Receive acknowledge bit.
Receive byte, contents of selected register.
Send acknowledge bit.
Send stop condition.
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18
19
24 25 26 27 28
SCL
CHIP ADDRESS (WRITE)
1
SDA
0
0
1
MAP BYTE
1 AD1 AD0 0
INCR
6
5
4
3
1
ACK
0
7
6
ACK
1
DATA +n
DATA +1
DATA
2
0
7
6
1
0
7
6
1
0
ACK
ACK
STOP
START
Figure 17. I²C Write Format
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
SCL
CHIP ADDRESS (WRITE)
SDA
1
0 0
MAP BYTE
1 1 AD1 AD0 0
INCR
ACK
START
6
5
4
STOP
CHIP ADDRESS (READ)
1
3 2 1 0
0 0
DATA
1 1 AD1 AD0 1
ACK
START
7
ACK
DATA +1
0
7
ACK
0
DATA + n
7
0
NO
ACK
STOP
Figure 18. I²C Read Format
DS625F2
31
CS5364
5. REGISTER MAP
In Control Port Mode, the bits in these registers are used to control all of the programmable features of the ADC. All
registers above 0Ah are RESERVED.
5.1
Register Quick Reference
Adr
Name
7
6
5
4
3
2
CHIP-ID[3:0]
1
0
00
REVI
01
GCTL
02
OVFL
RESERVED RESERVED RESERVED RESERVED
OVFL4
OVFL3
OVFL2
OVFL1
03
OVFM
RESERVED RESERVED RESERVED RESERVED
OVFM4
OVFM3
OVFM2
OVFM1
04
HPF
RESERVED RESERVED RESERVED RESERVED
HPF4
HPF3
HPF2
HPF1
05
RESERVED
-
-
06
PDNE
07
RESERVED
CP-EN
CLKMODE
-
MDIV[1:0]
RESERVED
-
REVISION[3:0]
DIF[1:0]
-
-
PDN-BG
PDN-OSC
-
-
-
08
MUTE
09
RESERVED
0A
SDEN
5.2
00h (REVI) Chip ID Code & Revision Register
R/W
R
RESERVED RESERVED RESERVED RESERVED
-
-
-
7
6
5
RESERVED RESERVED
PDN21
-
-
-
MUTE4
MUTE3
MUTE2
MUTE1
-
-
-
-
SDEN2
SDEN1
RESERVED RESERVED
4
PDN43
-
-
RESERVED
MODE[1:0]
3
2
1
REVISION[3:0]
CHIP-ID[3:0]
0
Default: See description
The Chip ID Code & Revision Register is used to store the ID and revision of the chip.
Bits[7:4] contain the chip ID, where the CS5364 is represented with a value of 0x4.
Bits[3:0] contain the revision of the chip, where revision A is represented as 0x0, revision B is represented
as 0x1, etc.
5.3
01h (GCTL) Global Mode Control Register
R/W
R/W
7
CP-EN
6
CLKMODE
5
4
MDIV[1:0]
3
2
DIF[1:0]
1
0
MODE[1:0]
Default: 0x00
The Global Mode Control Register is used to control the Master/Slave Speed modes, the serial audio data
format and the Master clock dividers for all channels. It also contains a Control Port enable bit.
Bit[7] CP-EN manages the Control Port Mode. Until this bit is asserted, all pins behave as if in Stand-Alone
Mode. When this bit is asserted, all pins used in Stand-Alone Mode are ignored, and the corresponding register values become functional.
Bit[6] CLKMODE Setting this bit puts the part in 384X mode (divides XTI by 1.5), and clearing the bit invokes 256X mode (divide XTI by 1.0 - pass through).
32
DS625F2
CS5364
Bits[5:4] MDIV[1:0] Each bit selects an XTI divider. When either bit is low, an XTI divide-by-1 function is
selected. When either bit is HIGH, an XTI divide-by-2 function is selected. With both bits HIGH, XTI is divided by 4.
The table below shows the composite XTI division using both CLKMODE and MDIV[1:0].
CLKMODE,MDIV[1],MDIV[0]
000
100
001 or 010
101 or 110
011
111
DESCRIPTION
Divide-by-1
Divide-by-1.5
Divide-by-2
Divide-by-3
Divide-by-4
Reserved
Bits[3:2] DIF[1:0] Determine which data format the serial audio interface is using to clock-out data.
DIF[1:0]
0x00 Left-Justified format
0x01 I²S format
0x02 TDM
0x03 Reserved
Bits[1:0] MODE[1:0] This bit field determines the device sample rate range and whether it is operating as
an audio clocking Master or Slave.
MODE[1:0]
0x00 Single-Speed Mode Master
0x01 Double-Speed Mode Master
0x02 Quad-Speed Mode Master
0x03 Slave Mode all speeds
5.4
02h (OVFL) Overflow Status Register
R/W
R
7
6
5
4
RESERVED RESERVED RESERVED RESERVED
3
2
1
0
OVFL4
OVFL3
OVFL2
OVFL1
Default: 0xFF, no overflows have occurred.
Note:
This register interacts with Register 03h, the Overflow Mask Register.
The Overflow Status Register is used to indicate an individual overflow in a channel. If an overflow condition
on any channel is detected, the corresponding bit in this register is asserted (low) in addition to the open
drain active low OVFL pin going low. Each overflow status bit is sticky and is cleared only when read, providing full interrupt capability.
5.5
03h (OVFM) Overflow Mask Register
R/W
R/W
7
6
5
4
RESERVED RESERVED RESERVED RESERVED
3
OVFM4
2
OVFM3
1
OVFM2
0
OVFM1
Default: 0xFF, all overflow interrupts enabled.
The Overflow Mask Register is used to allow or prevent individual channel overflow events from creating
activity on the OVFL pin. When a particular bit is set low in the Mask register, the corresponding overflow
bit in the Overflow Status register is prevented from causing any activity on the OVFL pin.
DS625F2
33
CS5364
5.6
04h (HPF) High-Pass Filter Register
R/W
R/W
7
6
5
4
RESERVED RESERVED RESERVED RESERVED
3
2
1
0
HPF4
HPF3
HPF2
HPF1
Default: 0x00, all high-pass filters enabled.
The High-Pass Filter Register is used to enable or disable a high-pass filter that exists for each channel.
These filters are used to perform DC offset calibration, a procedure that is detailed in “DC Offset Control”
on page 29.
5.7
05h Reserved
R/W
RESERVED
5.8
7
-
6
-
5
-
4
-
3
-
2
-
1
-
0
-
1
PDN43
0
PDN21
06h (PDN) Power Down Register
R/W
R/W
7
6
RESERVED
5
PDN-BG
4
PDN-OSC
3
2
RESERVED RESERVED
Default: 0x00 - everything powered up
The Power Down Register is used as needed to reduce the chip’s power consumption.
Bit[7] RESERVED
Bit[6] RESERVED
Bit[5] PDN-BG When set, this bit powers-down the bandgap reference.
Bit[4] PDN-OSC controls power to the internal oscillator core. When asserted, the internal oscillator core is
shut down, and no clock is supplied to the chip. If the chip is running off an externally supplied clock at the
MCLK pin, it is also prevented from clocking the device internally.
Bit[1:0] PDN When any bit is set, all clocks going to a channel pair are turned off, and the serial data outputs
are forced to all zeroes.
5.9
07h Reserved
R/W
RESERVED
5.10
7
-
6
-
5
-
4
-
3
-
2
-
1
-
0
-
3
MUTE4
2
MUTE3
1
MUTE2
0
MUTE1
08h (MUTE) Mute Control Register
R/W
R/W
7
6
5
4
RESERVED RESERVED RESERVED RESERVED
Default: 0x00, no channels are muted.
The Mute Control Register is used to mute or unmute the serial audio data output of individual channels.
When a bit is set, that channel’s serial data is muted by forcing the output to all zeroes.
34
DS625F2
CS5364
5.11
09h Reserved
R/W
RESERVED
5.12
7
-
6
-
5
-
4
-
3
-
2
-
1
-
0
-
1
SDEN2
0
SDEN1
0Ah (SDEN) SDOUT Enable Control Register
R/W
R/W
7
6
5
RESERVED
4
3
2
RESERVED RESERVED
Default: 0x00, all SDOUT pins enabled.
The SDOUT Enable Control Register is used to tri-state the serial audio data output pins. Each bit, when
set, tri-states the associated SDOUT pin.
DS625F2
35
CS5364
6. FILTER PLOTS
0.1
0.08
0.06
Amplitude (dB)
0.04
0.02
0
−0.02
−0.04
−0.06
−0.08
−0.1
0
0.05
0.1
0.15
0.2
0.25
0.3
Frequency (normalized to Fs)
0.35
0.4
0.45
0.5
0.35
0.4
0.45
0.5
Figure 19. SSM Passband
0.1
0.08
0.06
Amplitude (dB)
0.04
0.02
0
−0.02
−0.04
−0.06
−0.08
−0.1
0
0.05
0.1
0.15
0.2
0.25
0.3
Frequency (normalized to Fs)
Figure 20. DSM Passband
0.1
0.08
0.06
Amplitude (dB)
0.04
0.02
0
−0.02
−0.04
−0.06
−0.08
−0.1
0
0.05
0.1
0.15
Frequency (normalized to Fs)
0.2
0.25
Figure 21. QSM Passband
36
DS625F2
CS5364
0
−20
Amplitude (dB)
−40
−60
−80
−100
−120
−140
0
0.1
0.2
0.3
0.4
0.5
0.6
Frequency (normalized to Fs)
0.7
0.8
0.9
1
0.7
0.8
0.9
1
0.7
0.8
0.9
1
Figure 22. SSM Stopband
0
−20
Amplitude (dB)
−40
−60
−80
−100
−120
−140
0
0.1
0.2
0.3
0.4
0.5
0.6
Frequency (normalized to Fs)
Figure 23. DSM Stopband
0
−20
Amplitude (dB)
−40
−60
−80
−100
−120
0
0.1
0.2
0.3
0.4
0.5
0.6
Frequency (normalized to Fs)
Figure 24. QSM Stopband
DS625F2
37
CS5364
0
−0.2
−0.4
Amplitude (dB)
−0.6
−0.8
−1
−1.2
−1.4
−1.6
−1.8
−2
0.4
0.42
0.44
0.46
0.48
0.5
0.52
Frequency (normalized to Fs)
0.54
0.56
0.58
0.6
0.54
0.56
0.58
0.6
0.34
0.36
0.38
0.4
Figure 25. SSM -1 dB Cutoff
0
−0.2
−0.4
Amplitude (dB)
−0.6
−0.8
−1
−1.2
−1.4
−1.6
−1.8
−2
0.4
0.42
0.44
0.46
0.48
0.5
0.52
Frequency (normalized to Fs)
Figure 26. DSM -1 dB Cutoff
0
−0.2
−0.4
Amplitude (dB)
−0.6
−0.8
−1
−1.2
−1.4
−1.6
−1.8
−2
0.2
0.22
0.24
0.26
0.28
0.3
0.32
Frequency (normalized to Fs)
Figure 27. QSM -1 dB Cutoff
38
DS625F2
CS5364
7. PARAMETER DEFINITIONS
Dynamic Range
The ratio of the rms value of the signal to the rms sum of all other spectral components over the specified
bandwidth. Dynamic Range is a signal-to-noise ratio measurement over the specified bandwidth made with
a -60 dBFS signal. 60 dB is added to resulting measurement to refer the measurement to full scale. This
technique ensures that the distortion components are below the noise level and do not affect the measurement. This measurement technique has been accepted by the Audio Engineering Society, AES17-199, and
the Electronic Industries Association of Japan, EIAJ CP-307. Expressed in decibels. The dynamic range is
specified with and without an A-weighting filter.
Total Harmonic Distortion + Noise
The ratio of the rms value of the signal to the rms sum of all other spectral components over the specified
bandwidth (typically 10 Hz to 20 kHz), including distortion components. Expressed in decibels. Measured
at -1 and -20 dBFS as suggested in AES17-1991 Annex A. Specified using an A-weighting filter.
Frequency Response
A measure of the amplitude response variation from 10 Hz to 20 kHz relative to the amplitude response at
1 kHz. Units in decibels.
Interchannel Isolation
A measure of crosstalk between one channel and all remaining channels, measured for each channel at the
converter's output with no signal to the input under test and a full-scale signal applied to all other channels.
Units in decibels.
Interchannel Gain Mismatch
The gain difference between left and right channels. Units in decibels.
Gain Error
The deviation from the nominal full-scale analog output for a full-scale digital input.
Gain Drift
The change in gain value with temperature. Units in ppm/°C.
Offset Error
The deviation of the mid-scale transition (111...111 to 000...000) from the ideal. Units in mV.
Intrachannel Phase Deviation
The deviation from linear phase within a given channel.
Interchannel Phase Deviation
The difference in phase response between channels.
DS625F2
39
CS5364
8. PACKAGE DIMENSIONS
48L LQFP PACKAGE DRAWING
E
E1
D D1
1
e
B
∝
A
A1
L
DIM
A
A1
B
D
D1
E
E1
e*
L
∝
MIN
--0.002
0.007
0.343
0.272
0.343
0.272
0.016
0.018
0.000°
INCHES
NOM
0.055
0.004
0.009
0.354
0.28
0.354
0.28
0.020
0.24
4°
MAX
0.063
0.006
0.011
0.366
0.280
0.366
0.280
0.024
0.030
7.000°
MIN
--0.05
0.17
8.70
6.90
8.70
6.90
0.40
0.45
0.00°
MILLIMETERS
NOM
1.40
0.10
0.22
9.0 BSC
7.0 BSC
9.0 BSC
7.0 BSC
0.50 BSC
0.60
4°
MAX
1.60
0.15
0.27
9.30
7.10
9.30
7.10
0.60
0.75
7.00°
* Nominal pin pitch is 0.50 mm
Controlling dimension is mm. JEDEC Designation: MS026
THERMAL CHARACTERISTICS
Parameter
Symbol
Allowable Junction Temperature
Package Thermal Resistance
40
θJA
θJC
Min
Typ
Max
Unit
-
-
135
°C
-
48
-
-
15
-
°C/W
DS625F2
CS5364
9. ORDERING INFORMATION
Product
Description
CS5364
114 dB, 192 kHz,
4-channel A/D
Converter
Package Pb-Free
48-pin
LQFP
YES
Grade
Temp Range
Container
Tray
Commercial -40° to +85°C
Tape & Reel
Tray
Automotive -40° to +105°C
Tape & Reel
CDB5364 Evaluation Board for CS5364
Order #
CS5364-CQZ
CS5364-CQZR
CS5364-DQZ
CS5364-DQZR
CDB5364
10.REVISION HISTORY
Revision
A1
Changes
Initial Release
PP1
Updated table under “DC Power” on page 11.
Updated Gain Error specification under “Analog Characteristics (Commercial)” on page 12
Added Master Mode specifications under “Serial Audio Interface - I²S/LJ Timing” on page 15
Added Master Mode specifications under “Serial Audio Interface - TDM Timing” on page 16
PP2
Updated “DC Power” on page 11.
PP3
Updated TDM Timing Specifications. See “Serial Audio Interface - TDM Timing” on page 16.
F1
Final Release
Added Section 4.11 “Optimizing Performance in TDM Mode” on page 29.
F2
Updated the wording of pin 24, LRCK/FS, in the pin description table on page 7 to correctly reflect the
high/low clocking state for odd-channel selection in I²S and LJ Modes.
Contacting Cirrus Logic Support
For all product questions and inquiries, contact a Cirrus Logic Sales Representative.
To find the one nearest you, go to www.cirrus.com.
IMPORTANT NOTICE
Cirrus Logic, Inc. and its subsidiaries ("Cirrus") believe that the information contained in this document is accurate and reliable. However, the information is subject
to change without notice and is provided "AS IS" without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant
information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale
supplied at the time of order acknowledgment, including those pertaining to warranty, indemnification, and limitation of liability. No responsibility is assumed by Cirrus
for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third
parties. This document is the property of Cirrus and by furnishing this information, Cirrus grants no license, express or implied under any patents, mask work rights,
copyrights, trademarks, trade secrets or other intellectual property rights. Cirrus owns the copyrights associated with the information contained herein and gives consent for copies to be made of the information only for use within your organization with respect to Cirrus integrated circuits or other products of Cirrus. This consent
does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL APPLICATIONS”). CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED OR WARRANTED FOR USE
IN AIRCRAFT SYSTEMS, MILITARY APPLICATIONS, PRODUCTS SURGICALLY IMPLANTED INTO THE BODY, AUTOMOTIVE SAFETY OR SECURITY DEVICES, LIFE SUPPORT PRODUCTS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF CIRRUS PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER’S RISK AND CIRRUS DISCLAIMS AND MAKES NO WARRANTY, EXPRESS, STATUTORY OR IMPLIED,
INCLUDING THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR PARTICULAR PURPOSE, WITH REGARD TO ANY CIRRUS PRODUCT
THAT IS USED IN SUCH A MANNER. IF THE CUSTOMER OR CUSTOMER’S CUSTOMER USES OR PERMITS THE USE OF CIRRUS PRODUCTS IN CRITICAL
APPLICATIONS, CUSTOMER AGREES, BY SUCH USE, TO FULLY INDEMNIFY CIRRUS, ITS OFFICERS, DIRECTORS, EMPLOYEES, DISTRIBUTORS AND
OTHER AGENTS FROM ANY AND ALL LIABILITY, INCLUDING ATTORNEYS’ FEES AND COSTS, THAT MAY RESULT FROM OR ARISE IN CONNECTION
WITH THESE USES.
Cirrus Logic, Cirrus, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks
or service marks of their respective owners.
I²C is a registered trademark of Philips Semiconductor.
SPI is a trademark of Motorola, Inc.
DS625F2
41