Revised December 2000 GTLP17T616 17-Bit LVTTL/GTLP Bus Transceiver with Buffered Clock General Description Features The GTLP17T616 is a 17-bit registered bus transceiver that provides LVTTL to GTLP signal level translation. It allows for transparent, latched and clocked modes of data flow and provides a buffered GTLP (CLKOUT) clock output from the LVTTL CLKAB. The device provides a high speed interface between cards operating at LVTTL logic levels and a backplane operating at GTLP logic levels. High speed backplane operation is a direct result of GTLP’s reduced output swing (<1V), reduced input threshold levels and output edge rate control. The edge rate control minimizes bus settling time. GTLP is a Fairchild Semiconductor derivative of the Gunning Transistor logic (GTL) JEDEC standard JESD8-3. ■ Bidirectional interface between GTLP and LVTTL logic levels Fairchild's GTLP has internal edge-rate control and is Process, Voltage, and Temperature (PVT) compensated. Its function is similar to BTL or GTL but with different output levels and receiver thresholds. GTLP output LOW level is typically less than 0.5V, the output level HIGH is 1.5V and the receiver threshold is 1.0V. ■ Designed with edge rate control circuitry to reduce output noise on the GTLP port ■ VREF pin provides external supply reference voltage for receiver threshold adjustibility ■ Special PVT compensation circuitry to provide consistent performance over variations of process, supply voltage and temperature ■ TTL compatible driver and control inputs ■ Designed using Fairchild advanced BiCMOS technology ■ Bushold data inputs on A port to eliminate the need for external pull-up resistors for unused inputs ■ Power up/down and power off high impedance for live insertion ■ Open drain on GTLP to support wired-or connection ■ Flow through pinout optimizes PCB layout ■ D-type flip-flop, latch and transparent data paths ■ A Port source/sink −24mA/+24mA ■ B Port sink +50mA ■ GTLP buffered CLKAB signal available (CLKOUT) Ordering Code: Order Number Package Number GTLP17T616MEA MS56A 56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300 Wide Package Description GTLP17T616MTD MTD56 56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. © 2000 Fairchild Semiconductor Corporation DS500327 www.fairchildsemi.com GTLP17T616 17-Bit LVTTL/GTLP Bus Transceiver with Buffered Clock January 2000 GTLP17T616 Pin Descriptions Pin Names Connection Diagram Description OEAB A-to-B Output Enable (Active LOW) (LVTTL levels) OEBA B-to-A Output Enable (Active LOW) (LVTTL levels) CEAB A-to-B Clock/LE Enable (Active LOW) (LVTTL levels) CEBA B-to-A Clock/LE Enable (Active LOW) (LVTTL levels) LEAB A-to-B Latch Enable (Transparent HIGH) (LVTTL levels) LEBA B-to-A Latch Enable (Transparent HIGH) (LVTTL levels) VREF GTLP Input Threshold Reference Voltage CLKAB A-to-B Clock (LVTTL levels) CLKBA B-to-A Clock (LVTTL levels) A1–A17 A-to-B Data Inputs or B-to-A 3-STATE Outputs B1–B17 B-to-A Data Inputs or A-to-B Open Drain Outputs (GTLP Levels) CLKIN B-to-A Buffered Clock Output (LVTTL levels) CLKOUT GTLP Buffered Clock Input/Output of CLKAB (GTLP Levels) Truth Table (Note 1) Inputs Output CEAB OEAB LEAB CLKAB A B X H X X X Z Mode Latched L L L H X B0 (Note 2) storage L L L L X B0 (Note 3) of A data Transparent X L H X L L X L H X H H L L L ↑ L L Clocked L L L ↑ H H storage H L L X X B0 (Note 3) Clock inhibit of A data Note 1: A-to-B data flow is shown. B-to-A data flow is similar but uses OEBA, LEBA, CLKBA, and CEBA. Note 2: Output level before the indicated steady state input conditions were established, provided that CLKAB was HIGH before LEAB went LOW. Note 3: Output level before the indicated steady-state input conditions were established. www.fairchildsemi.com 2 The GTLP17T616 is a 17 bit registered transceiver containing D-type flip-flop, latch and transparent modes of operation for the data path and a GTLP translation of the CLKAB signal (CLKOUT). Data flow in each direction is controlled by the clock enables (CEAB and CEBA), latch enables (LEAB and LEBA), clock (CLKAB and CLKBA) and output enables (OEAB and OEBA). The clock enables (CEAB and CEBA) enable all 17 bits. The output enables (OEAB and OEBA) control the 17 bits of data and the CLKOUT/CLKIN buffered clock path. For A-to-B data flow, when CEAB is low, the device operates on the LOW-to-HIGH transition of CLKAB for the flip-flop and on the HIGH-to-LOW transition of LEAB for the latch path. That is, if CEAB is LOW and LEAB is LOW the A data is latched regardless as to the state of CLKAB (HIGH or LOW) and if LEAB is HIGH the device is in transparent mode. When OEAB is LOW the outputs are active. When OEAB is HIGH the outputs are high impedance. The data flow of B-to-A is similar except that CEAB, OEBA, LEBA and CLKBA are used. Logic Diagram 3 www.fairchildsemi.com GTLP17T616 Functional Description GTLP17T616 Absolute Maximum Ratings(Note 4) Supply Voltage (VCC ) −0.5V to +4.6V DC Input Voltage (VI) −0.5V to +4.6V Recommended Operating Conditions Supply Voltage VCC /VCCQ DC Output Voltage (VO) Outputs 3-STATE −0.5V to +4.6V Outputs Active (Note 5) −0.5V to +4.6V 3.15V to 3.45V Bus Termination Voltage (VTT) DC Output Sink Current into GTLP 1.47V to 1.53V VREF 0.98V to 1.02V Input Voltage (VI) A Port IOL 48 mA DC Output Source Current from A Port IOH on A Port and Control Pins 0.0V to VCC on B Port 0.0V to VCC −48 mA HIGH Level Output Current (IOH) 100 mA LOW Level Output Current (IOL) DC Output Sink Current into −24 mA A Port B Port in the LOW State, IOL DC Input Diode Current (IIK) +24 mA A Port VI < 0V −50 mA DC Output Diode Current (IOK) VO < 0V −50 mA ESD Rating >2000V −40°C to +85°C Operating Temperature (TA) Note 4: Absolute Maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation under absolute maximum rated conditions in not implied. −65°C to +150 °C Storage Temperature (TSTG) +50 mA B Port Note 5: IO Absolute Maximum Rating must be observed. DC Electrical Characteristics Over Recommended Operating Free-Air Temperature Range, VREF = 1.0V (unless otherwise noted). Symbol VIH VIL Min Test Conditions Typ B Port VREF + 0.05 Others 2.0 B Port 0.0 VTT VREF − 0.05 Others VREF B Port VTT B Port VIK VOH VOL II A Port Max Units (Note 6) 0.8 VTT > VREF + 50 mV VTT > VREF + 50 mV 0.25 1.0 VREF + 50 mV 1.5 VCC = 3.15V II = −18 mA VCC = Min to Max (Note 7) IOH = −100 µA VCC = 3.15V IOH = −18 mA 2.4 IOH = -24mA 2.2 VCC − 1.2V V V V VCC −1.2 V VCC –0.2 V VCC = Min to Max (Note 7) IOL = 100 µA 0.2 VCC = 3.15V IOL = 24mA 0.5 B Port VCC = 3.15V IOL = 40 mA 0.4 IOL = 50 mA 0.55 Control Pins VCC = Min to Max (Note 7) VI = 3.45V or 0V ±5 µA A Port V V A Port VCC = 3.45V VI = 3.45V or 0V ±10 µA B Port VCC = 3.45V VI = 0 to 3.45V ±5 µA IPU/PD All Ports VCC = 0 to 1.5V VI/VO = 0 to 3.45V ±30 µA IOFF All Ports VCC = 0 VI or VO = 0 to 3.45V 30 µA II(hold) A Port VCC = 3.15V VI = 0.8V IOZH A Port VCC = 3.45V B Port IOZL A Port VCC = 3.45V B Port ICC A or B Ports (VCC/VCCQ) VI = 2.0V −75 VO = 3.45V 10 VO = 1.5V 5 VO = 0V −10 VO = 0.55V −5 VCC = 3.45V Outputs HIGH 45 IO = 0 Outputs LOW 45 VI = VCC or GND Outputs Disabled 45 One Input at 2.7V ∆ICC A Port and VCC = 3.45V, (Note 8) Control Pins A or Control Inputs at VCC or GND www.fairchildsemi.com 75 4 0 2 µA µA µA mA mA Symbol Ci (Continued) Min Test Conditions Typ Max Units (Note 6) Control Pins VI = VCC or 0 5.0 A Port VI = VCC or 0 7.0 B Port VI = VCC or 0 9.0 pF Note 6: All typical values are at VCC = 3.3V, VCCQ = 3.3V, and TA = 25°C. Note 7: For conditions shown as Min or Max, use the appropriate value specified under recommended operating conditions. Note 8: This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND. AC Operating Requirements Over recommended ranges of supply voltage and operating free-air temperature, VREF = 1.0V (unless otherwise noted). Symbol Test Conditions Min fTOGGLE Maximum Toggle Frequency Transparent Mode 125 fMAX Maximum Clock Frequency Registered Mode 125 tWIDTH Pulse Duration LEAB or LEBA HIGH 3.0 CLKAB or CLKBA HIGH or LOW 3.0 tSU tHOLD Setup Time Hold Time A before CLKAB↑ 0.6 B before CLKBA↑ 1.2 A before LEAB↑ 0.5 B before LEBA↑ 1.3 CEAB before CLKAB↑ 1.4 CEBA before CLKBA↑ 1.2 A after CLKAB↑ 0 B after CLKBA↑ 0.2 A after LEAB↑ 0.2 B after LEBA↑ 0 CEAB after CLKAB↑ 0.5 CEBA after CLKBA↑ 0.6 5 Max Unit MHz ns ns ns www.fairchildsemi.com GTLP17T616 DC Electrical Characteristics GTLP17T616 AC Electrical Characteristics Over recommended range of supply voltage and operating free-air temperature, VREF = 1.0V (unless otherwise noted). CL = 30 pF for B Port and CL = 50 pF for A Port. Symbol tPLH From To (Input) (Output) A B tPHL tPLH LEAB B tPHL tPLH CLKAB B tPHL tPLH CLKAB CLKOUT tPHL tPLH OEAB B or CLKOUT tPHL Min Typ 1.6 4.0 6.3 1.0 2.5 4.4 1.5 3.9 6.3 0.9 2.3 4.2 1.6 4.0 6.3 1.0 2.4 4.0 2.6 5.2 7.7 1.7 3.4 6.0 1.1 4.3 6.5 1.0 2.0 4.3 tRISE Transition time, B outputs (20% to 80%) 2.3 tFALL Transition time, B outputs (80% to 20%) 1.6 tRISE Transition Time, A outputs (10% to 90%) 2.3 tFALL Transition Time, A outputs (90% to 10%) 2.3 tPLH B A tPHL tPLH LEBA A tPHL tPLH CLKBA A tPHL tPLH CLKOUT CLKIN tPHL tPZH, tPZL OEBA A or CLKIN tPHZ, tPLZ Note 9: All typical values are at VCC = 3.3V, and TA = 25°C. www.fairchildsemi.com 6 Max Unit (Note 9) ns ns ns ns ns ns ns 1.7 2.9 4.5 1.7 3.2 5.8 0.3 2.5 4.6 0.4 2.5 4.6 0.5 2.6 4.6 0.6 2.8 4.6 1.2 2.4 5.3 2.2 3.5 5.3 0.3 2.8 5.2 0.3 2.5 5.2 ns ns ns ns ns Over recommended ranges of supply voltage and operating free-air temperature VREF = 1.0V (unless otherwise noted). CL = 30 pF for B Port and CL = 50 pF for A Port. Symbol tOSLH (Note 11) From To (Input) (Output) Min (Note 10) A B tOSHL (Note 11) tPVHL (Note 12)(Note 13) Typ Max Unit 0.3 1.0 ns 0.3 0.6 2.5 ns 0.3 1.0 ns 0.3 0.6 2.5 ns 0.5 ns A B CLKAB B CLKAB B B A 0.3 0.3 0.5 tOST (Note 11) B A 0.5 1.2 tPV (Note 12) B A CLKBA A 0.3 0.3 0.5 tOST (Note 11) CLKBA A 0.5 1.2 tPV (Note 12) CLKBA A 2.5 ns tPVHL (Note 11)(Note 12) CLKAB CLKOUT 2.8 ns B CLKOUT 0 1.7 ns 0 1.5 tOSLH (Note 11) tOSHL (Note 11) tPVHL (Note 12)(Note 13) tOSLH (Note 11) tOSHL (Note 11) tOSLH (Note 11) tOSHL (Note 11) tPDELLH (Note 14) tPDELHL (Note 14) ns 2.5 ns 0.5 ns ns Note 10: All typical values are at VCC = 3.3V, and TA = 25°C. Note 11: tOSHL/tOSLH and tOST - Output to output skew is defined as the absolute value of the difference between the actual propagation delay for all outputs within the same packaged device. The specifications are given for specific worst case VCC and temperature and apply to any outputs switching in the same direction either HIGH-to-LOW (tOSHL) or LOW-to-HIGH (tOSLH) or in opposite directions both HL and LH (tOST). This parameter is guaranteed by design and statistical process distribution. Actual skew values between the GTLP outputs could vary on the backplane due to the loading and impedance seen by the device. Note 12: tPV - Part to part skew is defined as the absolute value of the difference between the actual propagation delay for all outputs from device to device. The parameter is specified for a specific worst case VCC and temperature. This parameter is guaranteed by design and statistical process distribution. Actual skew values between the GTLP outputs could vary on the backplane due to the loading and impedance seen by the device. Note 13: Due to the open drain structure on GTLP outputs tOST and tPV(LH) in the A-to-B direction are not specified. Skew on these paths is dependent on the VTT and RT values on the backplane. Note 14: tPDELLH and tPDELHL -B to CLKOUT propagation delay delta is defined as the difference between the CLKAB to CLKOUT propagation delay and the CLKAB to B propagation delays. This parameter is for a given device and is not meant to guarantee the delta between the CLKAB to CLKOUT propagation delays of one device and the CLKAB to B propagation delays of other devices. This parameter is guaranteed by design and statistical process distribution. 7 www.fairchildsemi.com GTLP17T616 AC Extended Electrical Characteristics GTLP17T616 Test Circuits and Timing Waveforms Test Circuit for A Outputs Test Test Circuit for B Outputs S tPLH/tPHL OPEN tPLZ/tPZL 6V tPHZ/tPZH GND Note A: CL includes probes and Jig capacitance. Note B: For B Port, C L = 30 pF is used for worst case. Voltage Waveform - Propagation Delay Times Voltage Waveform - Pulse Width Voltage Waveform - Setup and Hold Times Voltage Waveform Enable and Disable Times Output Waveform 1 is for an output with internal conditions such that the output is LOW except when disabled by the control output. Output Waveform 2 is for an output with internal conditions such that the output is HIGH except when disabled by the control output. Input and Measure Conditions A or LVTTL Pins B or GTLP Pins VinHIGH VCC 1.5 VinLOW 0.0 0.0 VM VCC/2 1.0 VX VOL + 0.3V N/A VY VOH − 0.3V N/A All input pulses have the following characteristics: Frequency = 10MHz, tRISE = tFALL = 2 ns (10% to 90%), ZO = 50Ω The outputs are measured one at a time with one transition per measurement. www.fairchildsemi.com 8 GTLP17T616 Physical Dimensions inches (millimeters) unless otherwise noted 56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300 Wide Package Number MS56A 9 www.fairchildsemi.com GTLP17T616 17-Bit LVTTL/GTLP Bus Transceiver with Buffered Clock Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Package Number MTD56 Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com www.fairchildsemi.com 10