NSC ADC08D1020

ADC08D1020
Low Power, 8-Bit, Dual 1.0 GSPS or Single 2.0 GSPS A/D
Converter
General Description
Features
The ADC08D1020 is a dual, low power, high performance,
CMOS analog-to-digital converter that builds upon the ADC08D1000 platform. The ADC08D1020 digitizes signals to 8
bits of resolution at sample rates up to 1.3 GSPS. It has expanded features compared to the ADC08D1000, which include a test pattern output for system debug, a clock phase
adjust, and selectable output demultiplexer modes. Consuming a typical 1.6 Watts in non-demultiplex mode at 1 GSPS
from a single 1.9 Volt supply, this device is guaranteed to have
no missing codes over the full operating temperature range.
The unique folding and interpolating architecture, the fully differential comparator design, the innovative design of the internal sample-and-hold amplifier and the calibration schemes
enable a very flat response of all dynamic parameters beyond
Nyquist, producing a high 7.4 Effective Number of Bits
(ENOB) with a 498 MHz input signal and a 1 GHz sample rate
while providing a 10−18 Code Error Rate (C.E.R.) Output formatting is offset binary and the Low Voltage Differential Signaling (LVDS) digital outputs are compatible with IEEE
1596.3-1996, with the exception of an adjustable common
mode voltage between 0.8V and 1.2V.
Each converter has a selectable output demultiplexer which
feeds two LVDS buses. If the 1:2 demultiplexed mode is selected, the output data rate is reduced to half the input sample
rate on each bus. When non-demultiplexed mode is selected,
that output data rate on channels DI and DQ are at the same
rate as the input sample clock. The two converters can be
interleaved and used as a single 2 GSPS ADC.
The converter typically consumes less than 3.5 mW in the
Power Down Mode and is available in a leaded or lead-free
128-lead, thermally enhanced, exposed pad, LQFP and operates over the Industrial (-40°C ≤ TA ≤ +85°C) temperature
range.
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Single +1.9V ±0.1V Operation
Interleave Mode for 2x Sample Rate
Multiple ADC Synchronization Capability
Adjustment of Input Full-Scale Range, Offset, and Clock
Phase Adjust
Choice of SDR or DDR output clocking
1:1 or 1:2 Selectable Output Demux
Second DCLK output
Duty Cycle Corrected Sample Clock
Test pattern
Key Specifications
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Resolution
8 Bits
Max Conversion Rate
1 GSPS (min)
Code Error Rate
10−18 (typ)
ENOB @ 498 MHz Input (Normal Mode)
7.4 Bits (typ)
DNL
±0.15 LSB (typ)
Power Consumption
1.6 W (typ)
— Operating in Non-demux Output
1.7 W (typ)
— Operating in 1:2 Demux Output
3.5 mW (typ)
— Power Down Mode
Applications
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Direct RF Down Conversion
Digital Oscilloscopes
Satellite Set-top boxes
Communications Systems
Test Instrumentation
Ordering Information
Industrial Temperature Range (-40°C < TA < +85°C)
NS Package
ADC08D1020CIYB
Leaded 128-Pin Exposed Pad LQFP
ADC08D1020CIYB/NOPB
Lead-free 128-Pin Exposed Pad LQFP
ADC08D1020DEV
Development Board
© 2007 National Semiconductor Corporation
202062
www.national.com
ADC08D1020 Low Power, 8-Bit, Dual 1.0 GSPS or Single 2.0 GSPS A/D Converter
November 20, 2007
ADC08D1020
Block Diagram
20206253
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2
ADC08D1020
Pin Configuration
20206201
Note: The exposed pad on the bottom of the package must be soldered to a ground plane to ensure rated performance.
3
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ADC08D1020
Pin Descriptions and Equivalent Circuits
Pin Functions
Pin No.
Symbol
Equivalent Circuit
Description
3
OutV / SCLK
Output Voltage Amplitude and Serial Interface Clock. Tie this
pin high for normal differential DCLK and data amplitude.
Ground this pin for a reduced differential output amplitude
and reduced power consumption. See 1.1.6 The LVDS
Outputs. When the extended control mode is enabled, this
pin functions as the SCLK input which clocks in the serial
data. See 1.2 NORMAL/EXTENDED CONTROL for details
on the extended control mode. See 1.3 THE SERIAL
INTERFACE for description of the serial interface.
29
PDQ
Power Down Pins. A logic high on the PD pin puts the entire
device into the Power Down Mode.
OutEdge / DDR /
SDATA
DCLK Edge Select, Double Data Rate Enable and Serial
Data Input. This input sets the output edge of DCLK+ at
which the output data transitions. (See 1.1.5.2 OutEdge and
Demultiplex Control Setting). When this pin is floating or
connected to 1/2 the supply voltage, DDR clocking is
enabled. When the extended control mode is enabled, this
pin functions as the SDATA input. See 1.2 NORMAL/
EXTENDED CONTROL for details on the extended control
mode. See 1.3 THE SERIAL INTERFACE for description of
the serial interface.
15
DCLK_RST /
DCLK_RST+
DCLK Reset. When single-ended DCLK_RST is selected by
floating or setting pin 52 logic high, a positive pulse on this
pin is used to reset and synchronize the DCLK outputs of
multiple converters. See 1.5 MULTIPLE ADC
SYNCHRONIZATION for detailed description. When
differential DCLK_RST is selected by setting pin 52 logic low,
this pin receives the positive polarity of a differential pulse
signal used to reset and synchronize the DCLK outputs of
multiple converters.
26
PD
A logic high on the PDQ pin puts only the "Q" ADC into the
Power Down mode.
CAL
Calibration Cycle Initiate. A minimum 1280 input clock cycles
logic low followed by a minimum of 1280 input clock cycles
high on this pin initiates the calibration sequence. See 2.4.2
Calibration for an overview of calibration and 2.4.2.2 OnCommand Calibration for a description of on-command
calibration.
4
30
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4
Pin No.
14
127
18
19
Symbol
Equivalent Circuit
Description
FSR/ALT_ECE/
DCLK_RST-
Full Scale Range Select, Alternate Extended Control Enable
and DCLK_RST-. This pin has three functions. It can
conditionally control the ADC full-scale voltage, enable the
extended control mode, or become the negative polarity
signal of a differential pair in differential DCLK_RST mode.
If pin 52 and pin 41 are floating or at logic high, this pin can
be used to set the full-scale-range or can be used as an
alternate extended control enable pin . When used as the
FSR pin, a logic low on this pin sets the full-scale differential
input range to a reduced VIN input level. A logic high on this
pin sets the full-scale differential input range to a higher VIN
input level. See Converter Electrical Characteristics. To
enable the extended control mode, whereby the serial
interface and control registers are employed, allow this pin
to float or connect it to a voltage equal to VA/2. See 1.2
NORMAL/EXTENDED CONTROL for information on the
extended control mode. Note that pin 41 overrides the
extended control enable of this pin. When pin 52 is held at
logic low, this pin acts as the DCLK_RST- pin. When in
differential DCLK_RST mode, there is no pin-controlled FSR
and the full-scale-range is defaulted to the higher VIN input
level.
CalDly / DES / SCS
Calibration Delay, Dual Edge Sampling and Serial Interface
Chip Select. With a logic high or low on pin 14, this pin
functions as Calibration Delay and sets the number of input
clock cycles after power up before calibration begins (See
1.1.1 Calibration). With pin 14 floating, this pin acts as the
enable pin for the serial interface input and the CalDly value
becomes "0" (short delay with no provision for a long powerup calibration delay). When this pin is floating or connected
to a voltage equal to VA/2, DES (Dual Edge Sampling) mode
is selected where the "I" input is sampled at twice the input
clock rate and the "Q" input is ignored. See 1.1.5.1 DualEdge Sampling.
CLK+
CLK−
LVDS Clock input pins for the ADC. The differential clock
signal must be a.c. coupled to these pins. The input signal is
sampled on the falling edge of CLK+. See 1.1.2 Acquiring
the Input for a description of acquiring the input and 2.3 THE
CLOCK INPUTS for an overview of the clock inputs.
VINI+
VINI−
11
10
22
23
Analog signal inputs to the ADC. The differential full-scale
input range of this input is programmable using the FSR pin
14 in normal mode and the Input Full-Scale Voltage Adjust
register in the extended control mode. Refer to the VIN
specification in the Converter Electrical Characteristics for
the full-scale input range in the normal mode. Refer to 1.4
REGISTER DESCRIPTION for the full-scale input range in
the extended control mode.
VINQ+
VINQ−
5
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ADC08D1020
Pin Functions
ADC08D1020
Pin Functions
Pin No.
Symbol
Equivalent Circuit
Description
7
VCMO
Common Mode Voltage. This pin is the common mode
output in d.c. coupling mode and also serves as the a.c.
coupling mode select pin. When d.c. coupling is used, the
voltage output at this pin is required to be the common mode
input voltage at VIN+ and VIN− when d.c. coupling is used.
This pin should be grounded when a.c. coupling is used at
the analog inputs. This pin is capable of sourcing or sinking
100 μA. See 2.2 THE ANALOG INPUT.
31
VBG
Bandgap output voltage capable of 100 μA source/sink and
can drive a load up to 80 pF.
126
CalRun
32
REXT
34
35
Tdiode_P
Tdiode_N
41
52
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Calibration Running indication. This pin is at a logic high
when calibration is running.
External bias resistor connection. Nominal value is 3.3 kΩ
(±0.1%) to ground. See 1.1.1 Calibration.
Temperature Diode Positive (Anode) and Negative
(Cathode) for die temperature measurements. See 2.6.2
Thermal Management.
ECE
Extended Control Enable. This pin always enables and
disables Extended Control Enable. When this pin is set logic
high, the extended control mode is inactive and all control of
the device must be through control pins only . When it is set
logic low, the extended control mode is active. This pin
overrides the Extended Control Enable signal set using pin
14.
DRST_SEL
DCLK_RST select. This pin selects whether the DCLK is
reset using a single-ended or differential signal. When this
pin is floating or logic high, the DCLK_RST operation is
single-ended and pin 14 functions as FSR/ALT_ECE. When
this pin is logic low, the DCLK_RST operation becomes
differential with functionality on pin 15 (DCLK_RST+) and pin
14 (DCLK_RST-). When in differential DCLK_RST mode,
there is no pin-controlled FSR and the full-scale-range is
defaulted to the higher VIN input level. When pin 41 is set
logic low, the extended control mode is active and the FullScale Voltage Adjust registers can be programmed.
6
ADC08D1020
Pin Functions
Pin No.
Symbol
83 / 78
84 / 77
85 / 76
86 / 75
89 / 72
90 / 71
91 / 70
92 / 69
93 / 68
94 / 67
95 / 66
96 / 65
100 / 61
101 / 60
102 / 59
103 / 58
DI7− / DQ7−
DI7+ / DQ7+
DI6− / DQ6−
DI6+ / DQ6+
DI5− / DQ5−
DI5+ / DQ5+
DI4− / DQ4−
DI4+ / DQ4+
DI3− / DQ3−
DI3+ / DQ3+
DI2− / DQ2−
DI2+ / DQ2+
DI1− / DQ1−
DI1+ / DQ1+
DI0− / DQ0−
DI0+ / DQ0+
I and Q channel LVDS Data Outputs that are not delayed in
the output demultiplexer. Compared with the DId and DQd
outputs, these outputs represent the later time samples.
These outputs should always be terminated with a 100 Ω
differential resistor.
104 / 57
105 / 56
106 / 55
107 / 54
111 / 50
112 / 49
113 / 48
114 / 47
115 / 46
116 / 45
117 / 44
118 / 43
122 / 39
123 / 38
124 / 37
125 / 36
DId7− / DQd7−
DId7+ / DQd7+
DId6− / DQd6−
DId6+ / DQd6+
DId5− / DQd5−
DId5+ / DQd5+
DId4− / DQd4−
DId4+ / DQd4+
DId3− / DQd3−
DId3+ / DQd3+
DId2− / DQd2−
DId2+ / DQd2+
DId1− / DQd1−
DId1+ / DQd1+
DId0− / DQd0−
DId0+ / DQd0+
I and Q channel LVDS Data Outputs that are delayed by one
CLK cycle in the output demultiplexer. Compared with the
DI/DQ outputs, these outputs represent the earlier time
sample. These outputs should be terminated with a 100 Ω
differential resistor when enabled. In non-demultiplexed
mode, these outputs are disabled and are high impedance
when enabled. When disabled, these outputs must be left
floating.
OR+/DCLK2+
OR-/DCLK2-
Out Of Range output. A differential high at these pins
indicates that the differential input is out of range (outside the
range ±VIN/2 as programmed by the FSR pin in nonextended control mode or the Input Full-Scale Voltage Adjust
register setting in the extended control mode). DCLK2 is the
exact mirror of DCLK and should output the same signal at
the same rate.
DCLK+
DCLK-
Data Clock. Differential Clock outputs used to latch the
output data. Delayed and non-delayed data outputs are
supplied synchronous to this signal. In 1:2 demultiplexed
mode, this signal is at 1/2 the input clock rate in SDR mode
and at 1/4 the input clock rate in the DDR mode. By default,
the DCLK outputs are not active during the termination
resistor trim section of the calibration cycle. If a system
requires DCLK to run continuously during a calibration cycle,
the termination resistor trim portion of the cycle can be
disabled by setting the Resistor Trim Disable (RTD) bit to
logic high in the Extended Configuration Register (address
9h). This disables all subsequent termination resistor trims
after the initial trim which occurs during the power on
calibration. Therefore, this output is not recommended as a
system clock unless the resistor trim is disabled. When the
device is in the non-demultiplexed mode, DCLK can only be
in DDR mode and the signal is at 1/2 the input clock rate.
79
80
82
81
Equivalent Circuit
Description
7
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ADC08D1020
Pin Functions
Pin No.
Symbol
2, 5, 8, 13,
16, 17, 20,
25, 28, 33,
128
VA
Analog power supply pins. Bypass these pins to ground.
40, 51, 62,
73, 88, 99,
110, 121
VDR
Output Driver power supply pins. Bypass these pins to DR
GND.
1, 6, 9, 12,
21, 24, 27
GND
Ground return for VA.
42, 53, 64,
74, 87, 97,
108, 119
DR GND
Ground return for VDR.
63, 98, 109,
120
NC
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Equivalent Circuit
Description
No Connection. Make no connection to these pins.
8
Operating Ratings
(Notes 1, 2)
(Notes 1, 2)
Ambient Temperature Range
−40°C ≤ TA ≤ +85°C
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage (VA)
Driver Supply Voltage (VDR)
Common Mode Input Voltage
VIN+, VIN− Voltage Range
(Maintaining Common Mode)
Ground Difference
(|GND − DR GND|)
CLK Pins Voltage Range
Differential CLK Amplitude
+1.8V to +2.0V
+1.8V to VA
VCMO ± 50 mV
Supply Voltage (VA, VDR)
Supply Difference
VDR - VA
Voltage on Any Input Pin
Ground Difference
|GND - DR GND|
Input Current at Any Pin (Note
3)
Package Input Current (Note 3)
2.2V
0V to 100 mV
−0.15V to (VA +0.15V)
Power Dissipation at TA ≤ 85°C
ESD Susceptibility (Note 4)
Human Body Model
Machine Model
Charged Device Model
Storage Temperature
0V to 100 mV
200 mV to VA
0V
0V to VA
0.4VP-P to 2.0VP-P
Package Thermal Resistance
±25 mA
±50 mA
2.3 W
2500V
250V
1000V
−65°C to +150°C
Package
θJA
θJC
Top of
Package
θJC
Thermal
Pad
128-Lead,
Exposed Pad
LQFP
26°C / W
10°C / W
2.8°C / W
Soldering
process
must
comply
with
National
Semiconductor’s Reflow Temperature Profile specifications.
Refer to www.national.com/packaging. (Note 5)
Converter Electrical Characteristics
The following specifications apply after calibration for VA = VDR = 1.9V; OutV = 1.9V; VIN FSR (a.c. coupled) = differential 870
mVP-P; CL = 10 pF; Differential, a.c. coupled Sine Wave Input Clock, fCLK = 1 GHz at 0.5 VP-P with 50% duty cycle; VBG = Floating;
Non-Extended Control Mode; SDR Mode; REXT = 3300 Ω ±0.1%; Analog Signal Source Impedance = 100 Ω Differential; 1:2 Output
Demultiplex; Duty Cycle Stabilizer on. Boldface limits apply for TA = TMIN to TMAX. All other limits TA = 25°C, unless otherwise
noted. (Notes 6, 7)
Symbol
Parameter
Conditions
Typical
(Note 8)
Limits
(Note 8)
Units
(Limits)
STATIC CONVERTER CHARACTERISTICS
INL
Integral Non-Linearity
(Best fit)
DC Coupled, 1 MHz Sine Wave Overanged
±0.3
±0.9
LSB (max)
DNL
Differential Non-Linearity
DC Coupled, 1 MHz Sine Wave Overanged
±0.15
±0.6
LSB (max)
8
Bits
Resolution with No Missing
Codes
−0.45
LSB (min)
LSB (max)
±45
mV
VOFF
Offset Error
VOFF_ADJ
Input Offset Adjustment Range Extended Control Mode
PFSE
Positive Full-Scale Error
(Note 9)
±25
mV (max)
NFSE
Negative Full-Scale Error
(Note 9)
±25
mV (max)
FS_ADJ
Full-Scale Adjustment Range
Extended Control Mode
±15
%FS
±20
NORMAL MODE (Non DES) DYNAMIC CONVERTER CHARACTERISTICS, 1:2 DEMUX MODE
FPBW
Full Power Bandwidth
C.E.R.
Code Error Rate
Gain Flatness
Normal Mode
2.0
GHz
10−18
Error/Sample
d.c. to 498 MHz
d.c. to 1 GHz
±0.8
±1.0
dBFS
dBFS
fIN = 248 MHz, VIN = FSR − 0.5 dB
7.4
7.0
Bits (min)
7.4
7.0
Bits (min)
46.5
43.9
dB (min)
46.5
43.9
dB (min)
fIN = 248 MHz, VIN = FSR − 0.5 dB
46.8
45.1
dB (min)
fIN = 498 MHz, VIN = FSR − 0.5 dB
46.8
45.1
dB (min)
ENOB
Effective Number of Bits
fIN = 498 MHz, VIN = FSR − 0.5 dB
SINAD
Signal-to-Noise Plus Distortion fIN = 248 MHz, VIN = FSR − 0.5 dB
Ratio
fIN = 498 MHz, VIN = FSR − 0.5 dB
SNR
Signal-to-Noise Ratio
9
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ADC08D1020
Absolute Maximum Ratings
ADC08D1020
Symbol
THD
2nd Harm
3rd Harm
Typical
(Note 8)
Limits
(Note 8)
Units
(Limits)
fIN = 248 MHz, VIN = FSR − 0.5 dB
−58
-50
dB (max)
fIN = 498 MHz, VIN = FSR − 0.5 dB
−58
-50
dB (max)
fIN = 248 MHz, VIN = FSR − 0.5 dB
−63
dB
fIN = 498 MHz, VIN = FSR − 0.5 dB
−63
dB
fIN = 248 MHz, VIN = FSR − 0.5 dB
−65
dB
fIN = 498 MHz, VIN = FSR − 0.5 dB
−65
fIN = 248 MHz, VIN = FSR − 0.5 dB
58
50
dB (min)
fIN = 498 MHz, VIN = FSR − 0.5 dB
58
50
dB (min)
fIN1 = 321 MHz, VIN = FSR − 7 dB
fIN2 = 326 MHz, VIN = FSR − 7 dB
-50
Parameter
Total Harmonic Distortion
Second Harmonic Distortion
Third Harmonic Distortion
SFDR
Spurious-Free dynamic Range
IMD
Intermodulation Distortion
Conditions
(VIN+) − (VIN−) > + Full Scale
Out of Range Output Code
(In addition to OR Output high) (VIN+) − (VIN−) < − Full Scale
dB
dB
255
0
NORMAL MODE (Non DES) DYNAMIC CONVERTER CHARACTERISTICS, 1:1 DEMUX MODE
fIN = 248 MHz, VIN = FSR − 0.5 dB
7.3
Bits
fIN = 498 MHz, VIN = FSR − 0.5 dB
7.3
Bits
Signal-to-Noise Plus Distortion fIN = 248 MHz, VIN = FSR − 0.5 dB
Ratio
fIN = 498 MHz, VIN = FSR − 0.5 dB
45.7
dB
45.7
dB
46
dB
fIN = 498 MHz, VIN = FSR − 0.5 dB
46
dB
fIN = 248 MHz, VIN = FSR − 0.5 dB
-57
dB
fIN = 498 MHz, VIN = FSR − 0.5 dB
-57
dB
fIN = 248 MHz, VIN = FSR − 0.5 dB
-63
dB
fIN = 498 MHz, VIN = FSR − 0.5 dB
-63
dB
fIN = 248 MHz, VIN = FSR − 0.5 dB
-64
dB
fIN = 498 MHz, VIN = FSR − 0.5 dB
-64
dB
fIN = 248 MHz, VIN = FSR − 0.5 dB
57
dB
fIN = 498 MHz, VIN = FSR − 0.5 dB
57
dB
ENOB
Effective Number of Bits
SINAD
SNR
Signal-to-Noise Ratio
THD
Total Harmonic Distortion
2nd Harm
Second Harmonic Distortion
3rd Harm
Third Harmonic Distortion
SFDR
Spurious-Free dynamic Range
fIN = 248 MHz, VIN = FSR − 0.5 dB
INTERLEAVE MODE (DES Pin 127=Float) - DYNAMIC CONVERTER CHARACTERISTICS, 1:4 DEMUX MODE
FPBW
Full Power Bandwidth
Dual Edge Sampling Mode
1.3
GHz
ENOB
Effective Number of Bits
fIN = 498 MHz, VIN = FSR − 0.5 dB
7.3
6.7
Bits (min)
SINAD
Signal to Noise Plus Distortion
fIN = 498 MHz, VIN = FSR − 0.5 dB
Ratio
46
42.1
dB
SNR
Signal to Noise Ratio
fIN = 498 MHz, VIN = FSR − 0.5 dB
46.3
43.8
dB (min)
THD
Total Harmonic Distortion
fIN = 498 MHz, VIN = FSR − 0.5 dB
−58
-47
dB (max)
2nd Harm
Second Harmonic Distortion
fIN = 498 MHz, VIN = FSR − 0.5 dB
−58
3rd Harm
Third Harmonic Distortion
fIN = 498 MHz, VIN = FSR − 0.5 dB
−66
SFDR
Spurious Free Dynamic Range fIN = 498 MHz, VIN = FSR − 0.5 dB
57
dB
dB
47
dB (min)
580
mVP-P (min)
720
mVP-P (max)
800
mVP-P (min)
ANALOG INPUT AND REFERENCE CHARACTERISTICS
FSR pin 14 Low
VIN
650
Full Scale Analog Differential
Input Range
FSR pin 14 High
VCMI
870
VCMO
Common Mode Input Voltage
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10
940
mVP-P (max)
VCMO − 0.05
V (min)
VCMO + 0.05
V (max)
CIN
RIN
Parameter
Conditions
Typical
(Note 8)
Limits
(Note 8)
Units
(Limits)
Analog Input Capacitance,
Normal operation
(Notes 10, 11)
Differential
0.02
pF
Each input pin to ground
1.6
pF
Analog Input Capacitance,
DES Mode (Notes 10, 11)
Differential
0.08
pF
Each input pin to ground
2.2
Differential Input Resistance
pF
Ω (min)
100
Ω (max)
ANALOG OUTPUT CHARACTERISTICS
0.95
V (min)
1.45
V (max)
VCMO
Common Mode Output
Voltage
ICMO = ±100 µA
1.26
TC VCMO
Common Mode Output
Voltage Temperature
Coefficient
TA = −40°C to +85°C
118
ppm/°C
VCMO_LVL
VCMO input threshold to set DC VA = 1.8V
Coupling mode
VA = 2.0V
0.60
V
0.66
V
CLOAD VCMO
Maximum VCMO load
Capacitance
VBG
Bandgap Reference Output
Voltage
IBG = ±100 µA
TC VBG
Bandgap Reference Voltage
Temperature Coefficient
TA = −40°C to +85°C,
IBG = ±100 µA
CLOAD VBG
Maximum Bandgap Reference
load Capacitance
80
1.26
pF
1.20
V (min)
1.33
V (max)
28
ppm/°C
80
pF
CHANNEL-TO-CHANNEL CHARACTERISTICS
Offset Match
Positive Full-Scale Match
Zero offset selected in Control Register
Negative Full-Scale Match
Zero offset selected in Control Register
Phase Matching (I, Q)
fIN = 1.0 GHz
1
LSB
1
LSB
1
LSB
<1
Degree
X-TALK
Crosstalk from I (Aggressor) to Aggressor = 867 MHz F.S.
Q (Victim) Channel
Victim = 100 MHz F.S.
−65
dB
X-TALK
Crosstalk from Q (Aggressor) Aggressor = 867 MHz F.S.
to I (Victim) Channel
Victim = 100 MHz F.S.
−65
dB
LVDS CLK Input Characteristics (Typical specs also apply to DCLK_RST)
Sine Wave Clock
VID
0.6
Differential Clock Input Level
Square Wave Clock
VOSI
Input Offset Voltage
CIN
Input Capacitance
(Notes 10, 11)
0.6
0.4
VP-P (min)
2.0
VP-P (max)
0.4
VP-P (min)
2.0
VP-P (max)
1.2
V
Differential
0.02
pF
Each input to ground
1.5
pF
DIGITAL CONTROL PIN CHARACTERISTICS
VIH
Logic High Input Voltage
VIL
Logic Low Input Voltage
CIN
Input Capacitance
(Notes 11, 13)
OutV, DCLK_RST, PD, PDQ, CAL
0.69 x VA
OutEdge, FSR, CalDly
0.79 x VA
OutV, DCLK_RST, PD, PDQ, CAL
0.28 x VA
OutEdge, FSR, CalDly
0.21 x VA
Each input to ground
11
1.2
V (min)
V (max)
pF
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ADC08D1020
Symbol
ADC08D1020
Symbol
Parameter
Conditions
Typical
(Note 8)
Limits
(Note 8)
Units
(Limits)
DIGITAL OUTPUT CHARACTERISTICS
VOD
LVDS Differential Output
Voltage
Measured differentially, OutV = VA,
VBG = Floating (Note 15)
740
Measured differentially, OutV = GND, VBG
= Floating (Note 15)
560
480
mVP-P (min)
950
mVP-P (max)
320
mVP-P (min)
720
mVP-P (max)
ΔVO DIFF
Change in LVDS Output Swing
Between Logic Levels
VOS
Output Offset Voltage
See Figure 1
VOS
Output Offset Voltage
See Figure 1
ΔVOS
Output Offset Voltage Change
Between Logic Levels
IOS
Output Short Circuit Current
ZO
Differential Output Impedance
VOH
CalRun H level output
IOH = −400 µA (Note 12)
1.65
1.5
V
VOL
CalRun L level output
IOH = 400 µA (Note 12)
0.15
0.3
V
1:2 Demux Output
PD = PDQ = Low
PD = Low, PDQ = High
PD = PDQ = High
697
460
1.7
788
523
mA (max)
mA (max)
mA
Non-demux Output
PD = PDQ = Low
PD = Low, PDQ = High
PD = PDQ = High
712
464
1.5
803
530
mA (max)
mA (max)
mA
1:2 Demux Output
PD = PDQ = Low
PD = Low, PDQ = High
PD = PDQ = High
212
117
0.054
300
161
mA (max)
mA (max)
mA
Non-demux Output
PD = PDQ = Low
PD = Low, PDQ = High
PD = PDQ = High
136
83.5
0.047
212
120
mA (max)
mA (max)
mA
1:2 Demux Output
PD = PDQ = Low
PD = Low, PDQ = High
PD = PDQ = High
1.7
1.0
3.3
2.06
1.3
W (max)
W (max)
mW
Non-demux Output
PD = PDQ = Low
PD = Low, PDQ = High
PD = PDQ = High
1.6
1.04
2.76
1.92
1.235
W (max)
W (max)
mW
±1
mV
VBG = Floating
800
mV
VBG = VA (Note 15)
1175
mV
±1
mV
±4
mA
Output+ & Output−
connected to 0.8V
Ω
100
POWER SUPPLY CHARACTERISTICS
IA
IDR
Analog Supply Current
Output Driver Supply Current
PD
Power Consumption
PSRR1
D.C. Power Supply Rejection
Ratio
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Change in Full Scale Error with change in
VA from 1.8V to 2.0V
12
30
dB
Conditions
Typical
(Note 8)
Limits
(Note 8)
Units
(Limits)
Normal Mode (non DES) or DES Mode in
1:2 Demux Output
1.3
1.0
GHz (min)
1.0
GHz (max)
Parameter
AC ELECTRICAL CHARACTERISTICS
fCLK (max)
fCLK (min)
Maximum Input Clock
Frequency
Minimum Input Clock
Frequency
Input Clock Duty Cycle
Normal Mode (non DES) or DES Mode in
Non-demux Output
Normal Mode (non DES)
200
MHz
DES Mode
500
MHz
200 MHz ≤ fCLK ≤ 1 GHz
(Normal Mode) (Note 12)
50
500 MHz ≤ fCLK ≤ 1 GHz
(DES Mode) (Note 12)
50
20
% (min)
80
% (max)
20
% (min)
80
% (max)
tCL
Input Clock Low Time
(Note 11)
500
200
ps (min)
tCH
Input Clock High Time
(Note 11)
500
200
ps (min)
45
% (min)
55
% (max)
DCLK Duty Cycle
(Note 11)
50
tSR
Setup Time DCLK_RST±
(Note 12) Differential DCLK_RST
90
tHR
Hold Time DCLK_RST±
(Note 12) Differential DCLK_RST
30
ps
ps
CLK± Cycles
(min)
tPWR
Pulse Width DCLK_RST±
(Note 11)
tLHT
Differential Low-to-High
Transition Time
10% to 90%, CL = 2.5 pF
150
ps
tHLT
Differential High-to-Low
Transition Time
10% to 90%, CL = 2.5 pF
150
ps
tOSK
DCLK-to-Data Output Skew
50% of DCLK transition to 50% of Data
transition, SDR Mode
and DDR Mode, 0° DCLK (Note 11)
±50
ps (max)
tSU
Data-to-DCLK Set-Up Time
DDR Mode, 90° DCLK (Note 11)
750
ps
tH
DCLK-to-Data Hold Time
DDR Mode, 90° DCLK (Note 11)
890
ps
tAD
Sampling (Aperture) Delay
Input CLK+ Fall to Acquisition of Data
1.6
ns
tAJ
Aperture Jitter
0.4
ps (rms)
tOD
Input Clock-to Data Output
Delay (in addition to Pipeline
Delay)
4.0
ns
4
50% of Input Clock transition to 50% of
Data transition
DI Outputs
13
DId Outputs
Pipeline Delay (Latency) in 1:2
Demux Mode
DQ Outputs
(Notes 11, 14)
14
Normal Mode
Over Range Recovery Time
13.5
Normal Mode
DQd Outputs
Pipeline Delay (Latency) in
Non-Demux Mode
(Notes 11, 14)
13
DES Mode
14
DES Mode
14.5
DI Outputs
13
Normal Mode
DQ Outputs
13
DES Mode
Differential VIN step from ±1.2V to 0V to get
accurate conversion
Input Clock
Cycles
13.5
Input Clock
Cycles
1
Input Clock
Cycle
500
ns
tWU
PD low to Rated Accuracy
Conversion (Wake-Up Time)
Normal Mode (Note 11)
DES Mode (Note 11)
1
µs
fSCLK
Serial Clock Frequency
(Note 11)
15
MHz
tSSU
Serial Data to Serial Clock
Rising Setup Time
(Note 11)
2.5
ns (min)
13
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ADC08D1020
Symbol
ADC08D1020
Symbol
Parameter
tSH
Serial Data to Serial Clock
Rising Hold Time
tSCS
tHCS
Typical
(Note 8)
Conditions
(Note 11)
Limits
(Note 8)
Units
(Limits)
1
ns (min)
CS to Serial Clock Rising
Setup Time
2.5
ns
CS to Serial Clock Falling Hold
Time
1.5
ns
Serial Clock Low Time
26
ns (min)
Serial Clock High Time
26
ns (min)
tCAL
Calibration Cycle Time
tCAL_L
CAL Pin Low Time
See Figure 10 (Note 11)
1280
Clock Cycles
(min)
tCAL_H
CAL Pin High Time
See Figure 10 (Note 11)
1280
Clock Cycles
(min)
CalDly = Low
See 1.1.1 Calibration, Figure 10,
(Note 11)
226
Clock Cycles
(max)
CalDly = High
See 1.1.1 Calibration, Figure 10,
(Note 11)
232
Clock Cycles
(max)
tCalDly
Calibration delay determined
by pin 127
1.4 x
106
Clock Cycles
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. There is no guarantee of operation at the Absolute Maximum
Ratings. Operating Ratings indicate conditions for which the device is functional, but do not guarantee specific performance limits. For guaranteed specifications
and test conditions, see the Electrical Characteristics. The guaranteed specifications apply only for the test conditions listed. Some performance characteristics
may degrade when the device is not operated under the listed test conditions.
Note 2: All voltages are measured with respect to GND = DR GND = 0V, unless otherwise specified.
Note 3: When the input voltage at any pin exceeds the power supply limits (that is, less than GND or greater than VA), the current at that pin should be limited to
25 mA. The 50 mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input current of 25 mA to
two. This limit is not placed upon the power, ground and digital output pins.
Note 4: Human body model is 100 pF capacitor discharged through a 1.5 kΩ resistor. Machine model is 220 pF discharged through ZERO Ohms. Charged device
model simulates a pin slowly acquiring charge (such as from a device sliding down the feeder in an automated assembler) then rapidly being discharged.
Note 5: Reflow temperature profiles are different for lead-free and non-lead-free packages.
Note 6: The analog inputs are protected as shown below. Input voltage magnitudes beyond the Absolute Maximum Ratings may damage this device.
20206204
Note 7: To guarantee accuracy, it is required that VA and VDR be well bypassed. Each supply pin must be decoupled with separate bypass capacitors. Additionally,
achieving rated performance requires that the backside exposed pad be well grounded.
Note 8: Typical figures are at TA = 25°C, and represent most likely parametric norms. Test limits are guaranteed to National's AOQL (Average Outgoing Quality
Level).
Note 9: Calculation of Full-Scale Error for this device assumes that the actual reference voltage is exactly its nominal value. Full-Scale Error for this device,
therefore, is a combination of Full-Scale Error and Reference Voltage Error. See Figure 2. For relationship between Gain Error and Full-Scale Error, see
Specification Definitions for Gain Error.
Note 10: The analog and clock input capacitances are die capacitances only. Additional package capacitances of 0.65 pF differential and 0.95 pF each pin to
ground are isolated from the die capacitances by lead and bond wire inductances.
Note 11: This parameter is guaranteed by design and is not tested in production.
Note 12: This parameter is guaranteed by design and/or characterization and is not tested in production.
Note 13: The digital control pin capacitances are die capacitances only. Additional package capacitance of 1.6 pF each pin to ground are isolated from the die
capacitances by lead and bond wire inductances.
Note 14: Each of the two converters of the ADC08D1020 has two LVDS output buses, which each clock data out at one half the sample rate. The data at each
bus is clocked out at one half the sample rate. The second bus (D0 through D7) has a pipeline latency that is one Input Clock cycle less than the latency of the
first bus (Dd0 through Dd7) in 1:2 demux mode.
Note 15: Tying VBG to the supply rail will increase the output offset voltage (VOS) by 400 mV (typical), as shown in the VOS specification above. Tying VBG to the
supply rail will also affect the differential LVDS output voltage (VOD), causing it to increase by 40 mV (typical).
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14
ADC08D1020
Specification Definitions
APERTURE (SAMPLING) DELAY is the amount of delay,
measured from the sampling edge of the Clock input, after
which the signal present at the input pin is sampled inside the
device.
APERTURE JITTER (tAJ) is the variation in aperture delay
from sample to sample. Aperture jitter shows up as input
noise.
CODE ERROR RATE (C.E.R.) is the probability of error and
is defined as the probable number of word errors on the ADC
output per unit of time divided by the number of words seen
in that amount of time. A C.E.R. of 10-18 corresponds to a
statistical error in one word about every four (4) years.
CLOCK DUTY CYCLE is the ratio of the time that the clock
waveform is at a logic high to the total time of one clock period.
DIFFERENTIAL NON-LINEARITY (DNL) is the measure of
the maximum deviation from the ideal step size of 1 LSB.
Measured at sample rate = 500 MSPS with a 1MHz input
sinewave.
EFFECTIVE NUMBER OF BITS (ENOB, or EFFECTIVE
BITS) is another method of specifying Signal-to-Noise and
Distortion Ratio, or SINAD. ENOB is defined as
(SINAD − 1.76) / 6.02 and says that the converter is equivalent to a perfect ADC of this (ENOB) number of bits.
FULL POWER BANDWIDTH (FPBW) is a measure of the
frequency at which the reconstructed output fundamental
drops 3 dB below its low frequency value for a full-scale input.
GAIN ERROR is the deviation from the ideal slope of the
transfer function. It can be calculated from Offset and FullScale Errors:
Positive Gain Error = Offset Error − Positive Full-Scale
Error
Negative Gain Error = −(Offset Error − Negative FullScale Error)
Gain Error = Negative Full-Scale Error − Positive FullScale Error = Positive Gain Error + Negative Gain Error
INTEGRAL NON-LINEARITY (INL) is a measure of worst
case deviation of the ADC transfer function from an ideal
straight line drawn through the ADC transfer function. The
deviation of any given code from this straight line is measured
from the center of that code value step. The best fit method
is used
INTERMODULATION DISTORTION (IMD) is the creation of
additional spectral components as a result of two sinusoidal
frequencies being applied to the ADC input at the same time.
It is defined as the ratio of the power in the second and third
order intermodulation products to the power in one of the
original frequencies. IMD is usually expressed in dBFS.
LSB (LEAST SIGNIFICANT BIT) is the bit that has the smallest value or weight of all bits. This value is
20206246
FIGURE 1.
LVDS OUTPUT OFFSET VOLTAGE (VOS) is the midpoint
between the D+ and D− pins output voltage with respect to
ground, i.e., [(VD+) + ( VD−)] / 2.
MISSING CODES are those output codes that are skipped
and will never appear at the ADC outputs. These codes cannot be reached with any input value.
MSB (MOST SIGNIFICANT BIT) is the bit that has the largest
value or weight. Its value is one half of full scale.
NEGATIVE FULL-SCALE ERROR (NFSE) is a measure of
how far the first code transition is from the ideal 1/2 LSB above
a differential −VIN/2. For the ADC08D1020 the reference voltage is assumed to be ideal, so this error is a combination of
full-scale error and reference voltage error.
OFFSET ERROR (VOFF) is a measure of how far the midscale point is from the ideal zero voltage differential input.
Offset Error = Actual Input causing average of 8k samples to
result in an average code of 127.5.
OUTPUT DELAY (tOD) is the time delay (in addition to
Pipeline Delay) after the falling edge of CLK+ before the data
update is present at the output pins.
OVER-RANGE RECOVERY TIME is the time required after
the differential input voltages goes from ±1.2V to 0V for the
converter to recover and make a conversion with its rated accuracy.
PIPELINE DELAY (LATENCY) is the number of input clock
cycles between initiation of conversion and when that data is
presented to the output driver stage. New data is available at
every clock cycle, but the data lags the conversion by the
Pipeline Delay plus the tOD.
POSITIVE FULL-SCALE ERROR (PFSE) is a measure of
how far the last code transition is from the ideal 1-1/2 LSB
below a differential +VIN/2. For the ADC08D1020 the reference voltage is assumed to be ideal, so this error is a combination of full-scale error and reference voltage error.
POWER SUPPLY REJECTION RATIO (PSRR) can be one
of two specifications. PSRR1 (DC PSRR) is the ratio of the
change in full-scale error that results from a power supply
voltage change from 1.8V to 2.0V. PSRR2 (AC PSRR) is a
measure of how well an a.c. signal injected on the power supply is rejected from the output and is measured with a 248
MHz, 50 mVP-P signal riding upon the power supply. It is the
ratio of the output amplitude of that signal at the output to its
amplitude on the power supply pin. PSRR is expressed in dB.
SIGNAL TO NOISE RATIO (SNR) is the ratio, expressed in
dB, of the rms value of the input signal at the output to the rms
value of the sum of all other spectral components below onehalf the sampling frequency, not including harmonics or d.c.
SIGNAL TO NOISE PLUS DISTORTION (S/(N+D) or
SINAD) is the ratio, expressed in dB, of the rms value of the
input signal at the output to the rms value of all of the other
VFS / 2N
where VFS is the differential full-scale amplitude VIN as set by
the FSR input and "n" is the ADC resolution in bits, and which
is 8 for the ADC08D1020.
LOW VOLTAGE DIFFERENTIAL SIGNALING (LVDS)
DIFFERENTIAL VOLTAGE (VID and VOD) is two times the
absolute value of the difference between the VD+ and VD −
signals; each measured with respect to Ground.
15
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ADC08D1020
spectral components below half the input clock frequency, including harmonics but excluding d.c.
SPURIOUS-FREE DYNAMIC RANGE (SFDR) is the difference, expressed in dB, between the rms values of the input
signal at the output and the peak spurious signal, where a
spurious signal is any signal present in the output spectrum
that is not present at the input, excluding d.c.
TOTAL HARMONIC DISTORTION (THD) is the ratio expressed in dB, of the rms total of the first nine harmonic levels
at the output to the level of the fundamental at the output. THD
is calculated as
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where Af1 is the RMS power of the fundamental (output) frequency and Af2 through Af10 are the RMS power of the first 9
harmonic frequencies in the output spectrum.
– Second Harmonic Distortion (2nd Harm) is the difference, expressed in dB, between the RMS power in the input
frequency seen at the output and the power in its 2nd harmonic level at the output.
– Third Harmonic Distortion (3rd Harm) is the difference
expressed in dB between the RMS power in the input frequency seen at the output and the power in its 3rd harmonic
level at the output.
16
ADC08D1020
Transfer Characteristic
20206222
FIGURE 2. Input / Output Transfer Characteristic
17
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ADC08D1020
Timing Diagrams
20206214
FIGURE 3. ADC08D1020 Timing — SDR Clocking in 1:2 Demultiplexed Mode
20206259
FIGURE 4. ADC08D1020 Timing — DDR Clocking in 1:2 Demultiplexed and Normal Mode
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18
ADC08D1020
20206260
FIGURE 5. ADC08D1020 Timing — DDR Clocking in Non-Demultiplexed and Normal Mode
20206219
FIGURE 6. Serial Interface Timing
20206220
FIGURE 7. Clock Reset Timing in DDR Mode
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ADC08D1020
20206223
FIGURE 8. Clock Reset Timing in SDR Mode with OUTEDGE Low
20206224
FIGURE 9. Clock Reset Timing in SDR Mode with OUTEDGE High
20206225
FIGURE 10. Power-up Calibration and On-Command Calibration Timing
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20
INL vs. CODE
INL vs. AMBIENT TEMPERATURE
20206264
20206265
DNL vs. CODE
DNL vs. AMBIENT TEMPERATURE
20206266
20206267
POWER CONSUMPTION vs. CLOCK FREQUENCY
ENOB vs. AMBIENT TEMPERATURE
20206281
20206276
21
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ADC08D1020
Typical Performance Characteristics VA = VDR = 1.9V, fCLK = 1000 MHz, fIN = 498 MHz, TA= 25°C, I
channel, 1:2 Demux Mode (1:1 Demux Mode has similar performance), unless otherwise stated.
ADC08D1020
ENOB vs. DIE TEMPERATURE
ENOB vs. SUPPLY VOLTAGE
20206291
20206277
ENOB vs. CLOCK FREQUENCY
ENOB vs. INPUT FREQUENCY
20206278
20206279
SNR vs. AMBIENT TEMPERATURE
SNR vs. DIE TEMPERATURE
20206268
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20206293
22
ADC08D1020
SNR vs. SUPPLY VOLTAGE
SNR vs. CLOCK FREQUENCY
20206269
20206270
SNR vs. INPUT FREQUENCY
THD vs. AMBIENT TEMPERATURE
20206271
20206272
THD vs. DIE TEMPERATURE
THD vs. SUPPLY VOLTAGE
20206294
20206273
23
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ADC08D1020
THD vs. CLOCK FREQUENCY
THD vs. INPUT FREQUENCY
20206274
20206275
SFDR vs. AMBIENT TEMPERATURE
SFDR vs. DIE TEMPERATURE
20206285
20206292
SFDR vs. SUPPLY VOLTAGE
SFDR vs. CLOCK FREQUENCY
20206284
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20206282
24
GAIN STABILITY vs. DIE TEMPERATURE
20206283
20206295
SIGNAL GAIN vs. INPUT FREQUENCY
CROSSTALK vs. SOURCE FREQUENCY
20206298
20206263
SPECTRAL RESPONSE AT fIN = 248 MHz
SPECTRAL RESPONSE AT fIN = 498 MHz
20206287
20206288
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ADC08D1020
SFDR vs. INPUT FREQUENCY
ADC08D1020
information on the interaction between Power Down and Calibration.
In normal operation, calibration is performed just after application of power and whenever a valid calibration command is
given, which is holding the CAL pin low for at least tCAL_L clock
cycles, then hold it high for at least another tCAL_H clock cycles
as defined in the Converter Electrical Characteristics. The
time taken by the calibration procedure is specified as tCALin
Converter Electrical Characteristics. Holding the CAL pin high
upon power up will prevent the calibration process from running until the CAL pin experiences the above-mentioned
tCAL_L clock cycles followed by tCAL_H clock cycles.
CalDly (pin 127) is used to select one of two delay times that
apply from the application of power to the start of calibration.
This calibration delay time is depedent on the setting of the
CalDly pin and is specified as tCalDly in the Converter Electrical
Characteristics. These delay values allow the power supply
to come up and stabilize before calibration takes place. If the
PD pin is high upon power-up, the calibration delay counter
will be disabled until the PD pin is brought low. Therefore,
holding the PD pin high during power up will further delay the
start of the power-up calibration cycle. The best setting of the
CalDly pin depends upon the power-on settling time of the
power supply.
1.0 Functional Description
The ADC08D1020 is a versatile A/D Converter with an innovative architecture permitting very high speed operation. The
controls available ease the application of the device to circuit
solutions. Optimum performance requires adherence to the
provisions discussed here and in the Applications Information
Section.
While it is generally poor practice to allow an active pin to float,
pins 4, 14 and 127 of the ADC08D1020 are designed to be
left floating without jeopardy. In all discussions throughout this
data sheet, whenever a function is called by allowing a control
pin to float, connecting that pin to a potential of one half the
VA supply voltage will have the same effect as allowing it to
float.
1.1 OVERVIEW
The ADC08D1020 uses a calibrated folding and interpolating
architecture that achieves 7.4 effective bits. The use of folding
amplifiers greatly reduces the number of comparators and
power consumption. Interpolation reduces the number of
front-end amplifiers required, minimizing the load on the input
signal and further reducing power requirements. In addition
to other things, on-chip calibration reduces the INL bow often
seen with folding architectures. The result is an extremely
fast, high performance, low power converter.
The analog input signal that is within the converter's input
voltage range is digitized to eight bits at speeds of 200 MSPS
to 1.3 GSPS, typical. Differential input voltages below negative full-scale will cause the output word to consist of all
zeroes. Differential input voltages above positive full-scale
will cause the output word to consist of all ones. Either of
these conditions at either the "I" or "Q" input will cause the OR
(Out of Range) output to be activated. This single OR output
indicates when the output code from one or both of the channels is below negative full scale or above positive full scale.
Each converter has a selectable output demultiplexer which
feeds two LVDS buses. If the 1:2 demultiplexed mode is selected, the output data rate is reduced to half the input sample
rate on each bus. When non-demultiplexed mode is selected,
that output data rate on channels DI and DQ are at the same
rate as the input sample clock.
The output levels may be selected to be normal or reduced.
Using reduced levels saves power but could result in erroneous data capture of some or all of the bits, especially at
higher sample rates and in marginally designed systems.
1.1.2 Acquiring the Input
In 1:2 demux mode, data is acquired at the falling edge of CLK
+ (pin 18) and the digital equivalent of that data is available
at the digital outputs 13 input clock cycles later for the DI and
DQ output buses and 14 input clock cycles later for the DId
and DQd output buses. There is an additional internal delay
called tOD before the data is available at the outputs. See the
Timing Diagram. The ADC08D1020 will convert as long as
the input clock signal is present. The fully differential comparator design and the innovative design of the sample-andhold amplifier, together with calibration, enables a very flat
SINAD/ENOB response beyond 1 GHz. The ADC08D1020
output data signaling is LVDS and the output format is offset
binary.
1.1.3 Control Modes
Much of the user control can be accomplished with several
control pins that are provided. Examples include initiation of
the calibration cycle, power down mode and full scale range
setting. However, the ADC08D1020 also provides an Extended Control mode whereby a serial interface is used to access
register-based control of several advanced features. The Extended Control mode is not intended to be enabled and
disabled dynamically. Rather, the user is expected to employ
either the normal control mode or the Extended Control mode
at all times. When the device is in the Extended Control mode,
pin-based control of several features is replaced with registerbased control and those pin-based controls are disabled.
These pins are OutV (pin 3), OutEdge/DDR (pin 4), FSR (pin
14) and CalDly/DES (pin 127). See 1.2 NORMAL/EXTENDED CONTROL for details on the Extended Control mode.
1.1.1 Calibration
A calibration is performed upon power-up and can also be
invoked by the user upon command. Calibration trims the 100
Ω analog input differential termination resistor and minimizes
full-scale error, offset error, DNL and INL, resulting in maximizing SNR, THD, SINAD (SNDR) and ENOB. Internal bias
currents are also set with the calibration process. All of this is
true whether the calibration is performed upon power up or is
performed upon command. Running the calibration is an important part of this chip's functionality and is required in order
to obtain adequate performance. In addition to the requirement to be run at power-up, an on-command calibration must
be run whenever the sense of the FSR pin is changed. For
best performance, we recommend that an on-command calibration be run 20 seconds or more after application of power
and whenever the operating temperature changes significantly relative to the specific system performance requirements. See 2.4.2.2 On-Command Calibration for more
information. Calibration can not be initiated or run while the
device is in the power-down mode. See 1.1.7 Power Down for
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1.1.4 The Analog Inputs
The ADC08D1020 must be driven with a differential input signal. Operation with a single-ended signal is not recommended. It is important that the inputs either be a.c. coupled to the
inputs with the VCMO pin grounded, or d.c. coupled with the
VCMO pin left floating. An input common mode voltage equal
to the VCMO output must be provided when d.c. coupling is
used.
Two full-scale range settings are provided with pin 14 (FSR).
A high on pin 14 causes an input full-scale range setting of a
26
the input on the positive edge of the input clock and the other
ADC samples the same input on the falling edge of the input
clock. A single input is thus sampled twice per input clock cycle, resulting in an overall sample rate of twice the input clock
frequency, or 2 GSPS with a 1 GHz input clock.
In this mode, the outputs must be carefully interleaved to reconstruct the sampled signal. If the device is programmed into
the 1:2 demultiplex mode while in DES mode, the data is effectively demultiplexed 1:4. If the input clock is 1 GHz, the
effective sampling rate is doubled to 2 GSPS and each of the
4 output buses have a 500 MHz output rate. All data is available in parallel. To properly reconstruct the sampled waveform, the four bytes of parallel data that are output with each
clock are in the following sampling order from the earliest to
the latest and must be interleaved as such: DQd, DId, DQ, DI.
See Table 1 indicates what the outputs represent for the various sampling possibilities. If the device is programmed into
the non-demultiplex mode, two bytes of parallel data are output with each edge of the clock in the following sampling
order, from the earliest to the latest: DQ, DI. See Table 2.
In the non-extended mode of operation only the "I" input can
be sampled in the DES mode. In the extended mode of operation, the user can select which input is sampled.
The ADC08D1020 includes an automatic clock phase background adjustment which is used in DES mode to automatically and continuously adjust the clock phase of the I and Q
channel. This feature provides optimal Dual-Edge Sampling
performance.
1.1.5 Clocking
The ADC08D1020 must be driven with an a.c. coupled, differential clock signal. 2.3 THE CLOCK INPUTS describes the
use of the clock input pins. A differential LVDS output clock is
available for use in latching the ADC output data into whatever
device is used to receive the data.
The ADC08D1020 offers input and output clocking options.
These options include a choice of Dual Edge Sampling (DES)
or "interleaved mode" where the ADC08D1020 performs as a
single device converting at twice the input clock rate, a choice
of which DCLK edge the output data transitions on, and a
choice of Single Data Rate (SDR) or Double Data Rate (DDR)
outputs.
The ADC08D1020 also has the option to use a duty cycle
corrected clock receiver as part of the input clock circuit. This
feature is enabled by default and provides improved ADC
clocking especially in the Dual-Edge Sampling mode (DES).
This circuitry allows the ADC to be clocked with a signal
source having a duty cycle ratio of 20% / 80% (worst case)
for both the normal and the Dual Edge Sampling modes.
1.1.5.1 Dual-Edge Sampling
The DES mode allows one of the ADC08D1020's inputs (I or
Q Channel) to be sampled by both ADCs. One ADC samples
TABLE 1. Input Channel Samples Produced at Data Outputs in 1:2 Demultiplexed Mode**
Data Outputs
(Always sourced with
respect to fall of DCLK
+)
Dual-Edge Sampling Mode (DES)
Normal Sampling Mode
I-Channel Selected
Q-Channel Selected *
DI
"I" Input Sampled with Fall of CLK 13
cycles earlier.
"I" Input Sampled with Fall of "Q" Input Sampled with Fall
CLK 13 cycles earlier.
of CLK 13 cycles earlier.
DId
"I" Input Sampled with Fall of CLK 14
cycles earlier.
"I" Input Sampled with Fall of "Q" Input Sampled with Fall
CLK 14 cycles earlier.
of CLK 14 cycles earlier.
DQ
"Q" Input Sampled with Fall of CLK 13 "I" Input Sampled with Rise "Q" Input Sampled with Rise
cycles earlier.
of CLK 13.5 cycles earlier. of CLK 13.5 cycles earlier.
DQd
"Q" Input Sampled with Fall of CLK 14 "I" Input Sampled with Rise "Q" Input Sampled with Rise
cycles after being sampled.
of CLK 14.5 cycles earlier. of CLK 14.5 cycles earlier.
* Note that, in DES + normal mode, only the I Channel is sampled. In DES + extended control mode, I or Q channel can be sampled.
** Note that, in the non-demultiplexed mode, the DId and DQd outputs are disabled and are high impedance.
TABLE 2. Input Channel Samples Produced at Data Outputs in Non-Demultiplexed Mode
Data Outputs
(Sourced with
respect to fall
of DCLK+)
Normal Mode
DES Mode
DI
"I" Input Sampled with Fall of CLK 13 cycles earlier.
Selected input sampled 13 cycles earlier.
DId
No output.
No output.
DQ
"Q" Input Sampled with Fall of CLK 13 cycles earlier.
Selected input sampled 13.5 cycles earlier.
DQd
No output.
No output.
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ADC08D1020
higher VIN input level, while grounding pin 14 causes an input
full-scale range setting of a reduced VIN input level. The fullscale range setting operates equally on both ADCs.
In the Extended Control mode, programming the Input FullScale Voltage Adjust register allows the input full-scale range
to be adjusted as described in 1.4 REGISTER DESCRIPTION and 2.2 THE ANALOG INPUT.
ADC08D1020
1.1.5.2 OutEdge and Demultiplex Control Setting
To help ease data capture in the SDR mode, the output data
may be caused to transition on either the positive or the negative edge of the output data clock (DCLK). In the nonextended control mode, this is chosen with the OutEdge input
(pin 4). A high on the OutEdge input pin causes the output
data to transition on the rising edge of DCLK+, while grounding this input causes the output to transition on the falling edge
of DCLK+. See 2.4.3 Output Edge Synchronization. When in
the extended control mode, the OutEdge is selected using the
OED bit in the Configuration Register. This bit has two functions. In the single data rate (SDR) mode, the bit functions as
OutEdge and selects the DCLK edge with which the data
transitions. In the Double Data Rate (DDR) mode, this bit selects whether the device is in non-demultiplex or 1:2 demultiplex mode. In the DDR case, the DCLK has a 0° phase
relationship with the output data independent of the demultiplexer selection.
1.1.7 Power Down
The ADC08D1020 is in the active state when the Power Down
pin (PD) is low. When the PD pin is high, the device is in the
power down mode. In this power down mode the data output
pins (positive and negative) are put into a high impedance
state and the devices power consumption is reduced to a
minimal level. The DCLK+/- and OR +/- are not tri-stated, they
are weakly pulled down to ground internally. Therefore when
both I and Q are powered down the DCLK +/- and OR +/should not be terminated to a DC voltage.
A high on the PDQ pin will power down the "Q" channel and
leave the "I" channel active. There is no provision to power
down the "I" channel independently of the "Q" channel. Upon
return to normal operation, the pipeline will contain meaningless information.
If the PD input is brought high while a calibration is running,
the device will not go into power down until the calibration
sequence is complete. However, if power is applied and PD
is already high, the device will not begin the calibration sequence until the PD input goes low. If a manual calibration is
requested while the device is powered down, the calibration
will not begin at all. That is, the manual calibration input is
completely ignored in the power down state. Calibration will
function with the "Q" channel powered down, but that channel
will not be calibrated if PDQ is high. If the "Q" channel is subsequently to be used, it is necessary to perform a calibration
after PDQ is brought low.
1.1.5.3 Double Data Rate
A choice of single data rate (SDR) or double data rate (DDR)
output is offered. With single data rate the output clock
(DCLK) frequency is the same as the data rate of the two output buses. With double data rate the DCLK frequency is half
the data rate and data is sent to the outputs on both edges of
DCLK. DDR clocking is enabled in non-Extended Control
mode by allowing pin 4 to float.
1.1.6 The LVDS Outputs
The data outputs, the Out Of Range (OR) and DCLK, are
LVDS. The electrical specifications of the LVDS outputs are
compatible with typical LVDS receivers available on ASIC and
FPGA chips; but they are not IEEE or ANSI communications
standards compliant due to the low +1.9V supply used this
chip. User is given the choice of a lower signal amplitude
mode with OutV control pin or the OV control register bit. For
short LVDS lines and low noise systems, satisfactory performance may be realized with the OutV input low, which results
in lower power consumption. If the LVDS lines are long and/
or the system in which the ADC08D1020 is used is noisy, it
may be necessary to tie the OutV pin high.
The LVDS data output have a typical common mode voltage
of 800 mV when the VBG pin is unconnected and floating. This
common mode voltage can be increased to 1.175V by tying
the VBG pin to VA if a higher common mode is required.
IMPORTANT NOTE: Tying the VBG pin to VA will also increase the differential LVDS output voltage by up to 40 mV.
1.2 NORMAL/EXTENDED CONTROL
The ADC08D1020 may be operated in one of two modes. In
the simpler standard control mode, the user affects available
configuration and control of the device through several control
pins. The "extended control mode" provides additional configuration and control options through a serial interface and a
set of 9 registers. Extended control mode is selected by setting pin 41 to logic low. If pin 41 is floating and pin 52 is floating
or logic high, pin 14 can be used to enable the extended control mode. The choice of control modes is required to be a
fixed selection and is not intended to be switched dynamically
while the device is operational.
Table 3 shows how several of the device features are affected
by the control mode chosen.
TABLE 3. Features and Modes
Feature
Normal Control Mode
Extended Control Mode
SDR or DDR Clocking
Selected with pin 4
Selected with nDE in the Configuration Register
(Addr-1h; bit-10).
DDR Clock Phase
Not Selectable (0° Phase Only)
Selected with DCP in the Configuration Register
(Addr-1h; bit-11).
SDR Data transitions with rising
SDR Data transitions with rising
edge of DCLK+ when pin 4 is high
or falling DCLK edge
and on falling edge when low.
LVDS output level
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Normal differential data and DCLK
amplitude selected when pin 3 is
high and reduced amplitude
selected when low.
28
Selected with OED in the Configuration Register
(Addr-1h; bit-8).
Selected with OV in the Configuration Register
(Addr-1h; bit-9).
Short delay selected when pin 127 is
low and longer delay selected when Short delay only.
high.
Full-Scale Range
Normal input full-scale range
selected when pin 14 is high and
reduced range when low. Selected
range applies to both channels.
Up to 512 step adjustments over a nominal range
specified in 1.4 REGISTER DESCRIPTION. Separate
range selected for I- and Q-Channels. Selected using
Full Range Registers (Addr-3h and Bh; bit-7 thru 15).
Not possible
512 steps of adjustment using the Input Offset register
specified in 1.4 REGISTER DESCRIPTION for each
channel using Input Offset Registers (Addr-2h and Ah;
bit-7 thru 15).
Input Offset Adjust
Dual Edge Sampling Selection Enabled with pin 127 floating
Enabled by programming DES in the Extended
Configuration Register (Addr-9h; bit-13).
Dual Edge Sampling
Input Channel Selection
Only I-Channel Input can be used
Either I- or Q-Channel input may be sampled by both
ADCs.
Test Pattern
Not possible
A test pattern can be made present at the data outputs
by setting TPO to 1b in Extended Configuration
Register (Addr-9h; bit-15).
Resistor Trim Disable
Not possible
The DCLK outputs will continuously be present when
RTD is set to 1b in Extended Configuration Register
(Addr-9h; bit-14 to 7).
Selectable Output
Demultiplexer
Not possible
If the device is set in DDR, the output can be
programmed to be non-demultiplex. When OED in
Configuration Register is set 1b (Addr-1h; bit-8), this
selects non-demultiplex. If OED is set 0b, this selects
1:2 demultiplex.
Second DCLK Output
Not possible
The OR outputs can be programmed to become a
second DCLK output when nSD is set 0b in
Configuration Register (Addr-1h; bit-13).
Sampling Clock Phase Adjust
Not possible
The sampling clock phase can be manually adjusted
through the Coarse and Intermediate Register (AddrFh; bit-15–7) and Fine Register (Addr-Eh; bit-15 to 8).
The default state of the Extended Control Mode is set upon
power-on reset (internally performed by the device) and is
shown in Table 4.
TABLE 4. Extended Control Mode Operation (Pin 41 Logic Low or Pin 14 Floating)
Feature
Extended Control Mode Default State
SDR or DDR Clocking
DDR Clocking
DDR Clock Phase
Data changes with DCLK edge (0° phase)
LVDS Output Amplitude
Higher value indicated in Electrical Table
Calibration Delay
Short Delay
Full-Scale Range
700 mV nominal for both channels
Input Offset Adjust
No adjustment for either channel
Dual Edge Sampling (DES)
Not enabled
Test Pattern
Not present at output
Resistor Trim Disable
Trim enabled, DCLK not continuously present at output
Selectable Output Demultiplexer
1:2 demultiplex
Second DCLK Output
Not present, pins 79 and 80
function as OR+ and OR-
Sampling Clock Phase Adjust
No adjustment for fine, intermediate or coarse
Serial Clock (SCLK), Serial Data (SDATA) and Serial Interface Chip Select (SCS). Nine write only registers are accessible through this serial interface.
1.3 THE SERIAL INTERFACE
The 3-pin serial interface is enabled only when the device is
in the Extended Control mode. The pins of this interface are
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ADC08D1020
Power-On Calibration Delay
ADC08D1020
SCS: This signal should be asserted low while accessing a
register through the serial interface. Setup and hold times with
respect to the SCLK must be observed.
SCLK: Serial data input is accepted at the rising edge of this
signal. There is no minimum frequency requirement for SCLK.
SDATA: Each register access requires a specific 32-bit pattern at this input. This pattern consists of a header, register
address and register value. The data is shifted in MSB first.
Setup and hold times with respect to the SCLK must be observed. See the Timing Diagram.
Each Register access consists of 32 bits, as shown in Figure
6 of the Timing Diagrams. The fixed header pattern is 0000
0000 0001 (eleven zeros followed by a 1). The loading sequence is such that a "0" is loaded first. These 12 bits form
the header. The next 4 bits are the address of the register that
is to be written to and the last 16 bits are the data written to
the addressed register. The addresses of the various registers are indicated in Table 5.
Refer to the Register Description (1.4 REGISTER DESCRIPTION) for information on the data to be written to the registers.
Subsequent register accesses may be performed immediately, starting with the 33rd SCLK. This means that the SCS input
does not have to be de-asserted and asserted again between
register addresses. It is possible, although not recommended,
to keep the SCS input permanently enabled (at a logic low)
when using extended control.
Control register contents are retained when the device is put
into power-down mode.
IMPORTANT NOTE: Do not write to the Serial Interface when
calibrating the ADC. Doing so will impair the performance of
the device until it is re-calibrated correctly. Programming the
serial registers will also reduce dynamic performance of the
ADC for the duration of the register access time.
1
1
0
Eh
Sampling Clock Phase
Fine Adjust
1
1
1
1
Fh
Sample Clock Phase
Intermediate and Coarse
Adjust
1.4 REGISTER DESCRIPTION
Nine write-only registers provide several control and configuration options in the Extended Control Mode. These registers have no effect when the device is in the Normal Control
Mode. Each register description below also shows the PowerOn Reset (POR) state of each control bit.
Calibration Register
Addr: 0h (0000b)
Write only (0x7FFF)
D15
D14
D13
D12
D11
D10
D9
D8
CAL
1
1
1
1
1
1
1
D7
D6
D5
D4
D3
D2
D1
D0
1
1
1
1
1
1
1
1
Bit 15
CAL: Calibration Enable. When this bit is set
1b, an on-command calibration cycle is
initiated. This function is exactly the same as
issuing an on-command calibration using the
CAL pin.
POR State: 0b
Must be set to 1b
Bits 14:0
Configuration Register
Addr: 1h (0001b)
Write only (0xB2FF)
TABLE 5. Register Addresses
D15
D14
D13
D12
D11
D10
D9
D8
4-Bit Address
1
0
nSD
DCS DCP
nDE
OV
OED
Loading Sequence:
A3 loaded after H0, A0 loaded last
D7
D6
D5
D4
D3
D2
D1
D0
1
1
1
1
1
1
1
1
A3 A2 A1
A0 Hex
Register Addressed
0
0
0
0
0h
Calibration
0
0
0
1
1h
Configuration
0
0
1
0
2h
"I" Ch Offset
0
0
1
1
3h
"I" Ch Full-Scale Voltage
Adjust
0
1
0
0
4h
Reserved
0
1
0
1
5h
Reserved
0
1
1
0
6h
Reserved
0
1
1
1
7h
Reserved
1
0
0
0
8h
Reserved
1
0
0
1
9h
Extended Configuration
1
0
1
0
Ah
"Q" Ch Offset
1
0
1
1
Bh
"Q" Ch Full-Scale Voltage
Adjust
1
1
0
0
Ch
Reserved
1
1
0
1
Dh
Reserved
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1
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
30
Must be set to 1b
Must be set to 0b
nSD: Second DCLK Output Enable. When
this bit is 1b, the device only has one DCLK
output and one OR output. When this bit is
0b, the device has two identical DCLK
outputs and no OR output.
POR State: 1b
DCS: Duty Cycle Stabilizer. When this bit is
set to 1b, a duty cycle stabilization circuit is
applied to the clock input. When this bit is set
to 0b the stabilization circuit is disabled.
POR State: 1b
DCP: DDR Clock Phase. This bit only has an
effect in the DDR mode. When this bit is set
to 0b, the DCLK edges are time-aligned with
the data bus edges ("0° Phase"). When this
bit is set to 1b, the DCLK edges are placed
in the middle of the data bit-cells ("90°
Phase"), using the one-half speed DCLK
shown in Figure 4 as the phase reference.
POR State: 0b
nDE: DDR Enable. When this bit is set to 0b,
data bus clocking follows the DDR (Double
Data Rate) mode whereby a data word is
output with each rising and falling edge of
DCLK. When this bit is set to a 1b, data bus
clocking follows the SDR (single data rate)
mode whereby each data word is output with
either the rising or falling edge of DCLK , as
determined by the OutEdge bit.
POR State: 0b
OV: Output Voltage. This bit determines the
LVDS outputs' voltage amplitude and has the
same function as the OutV pin that is used in
the normal control mode. When this bit is set
to 1b, the standard output amplitude of 710
mVP-P is used. When this bit is set to 0b, the
reduced output amplitude of 510 mVP-P is
used.
POR State: 1b
OED: Output Edge and Demultiplex Control.
This bit has two functions. When the device
is in SDR mode, this bit selects the DCLK
edge with which the data words transition in
the SDR mode and has the same effect as
the OutEdge pin in the normal control mode.
When this bit is set to 1b, the data outputs
change with the rising edge of DCLK+. When
this bit is set to 0b, the data output changes
with the falling edge of DCLK+. When the
device is in DDR mode, this bit selects the
non-demultiplexed mode when set to 1b.
When the bit set to 0b, the device is
programmed into the 1:2 demultiplexed
mode. The 1:2 demultiplexed mode is the
default mode. In DDR mode, DCLK has a 0°
phase relationship with the data.
POR State: 0b
Must be set to 1b
Bit 9
Bit 8
Bits 7:0
Bits 15:8
Bit 7
Bits 6:0
I-Channel Full-Scale Voltage Adjust
Addr: 3h (0011b)
D15
D15
D14
D13
D12
D11
D10
D9
D12
D11
D10
D9
D8
Adjust Value
D7
D6
D5
D4
D3
D2
D1
D0
1
1
1
1
1
1
1
Bits 6:0
Full Scale Voltage Adjust Value. The input fullscale voltage or gain of the I-Channel ADC is
adjusted linearly and monotonically with a 9 bit
data value. The adjustment range is ±20% of the
nominal 700 mVP-P differential value.
0000 0000 0
560 mVP-P
1000 0000 0
Default Value
1111 1111 1
700 mVP-P
840 mVP-P
For best performance, it is recommended that the
value in this field be limited to the range of 0110
0000 0b to 1110 0000 0b. i.e., limit the amount of
adjustment to ±15%. The remaining ±5%
headroom allows for the ADC's own full scale
variation. A gain adjustment does not require ADC
re-calibration.
POR State: 1000 0000 0b (no adjustment)
Must be set to 1b
Extended Configuration Register
Addr: 9h (1001b)
Write only (0x007F)
Offset Value
D13
(LSB)
Bits 15:7
I-Channel Offset
(MSB)
D14
Write only (0x807F)
(MSB)
IMPORTANT NOTE: It is recommended that this register
should only be written upon power-up initialization as writing
it may cause disturbance on the DCLK output as this signal's
basic configuration is changed.
Addr: 2h (0010b)
Offset Value. The input offset of the IChannel ADC is adjusted linearly and
monotonically by the value in this field. 00h
provides a nominal zero offset, while FFh
provides a nominal 45 mV of offset. Thus,
each code step provides 0.176 mV of offset.
POR State: 0000 0000 b
Sign bit. 0b gives positive offset, 1b gives
negative offset, resulting in total offset
adjustment of ±45 mV.
POR State: 0b
Must be set to 1b
Write only (0x03FF)
D15
D14
D13
D12
D11
D10
D9
D8
TPO
RTD
DES
IS
0
DLF
1
1
D8
D7
D6
D5
D4
D3
D2
D1
D0
(LSB)
1
1
1
1
1
1
1
1
Bit 15
D7
D6
D5
D4
D3
D2
D1
D0
Sign
1
1
1
1
1
1
1
TPO: Test Pattern Output. When this bit is set
1b, the ADC is disengaged and a test pattern
generator is connected to the outputs
including OR. This test pattern will work with
the device in the SDR, DDR and the nondemultiplex output modes.
POR State: 0b
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ADC08D1020
Bit 10
ADC08D1020
Bit 14
Bits 15:7
RTD: Resistor Trim Disable. When this bit is
set to 1b, the input termination resistor is not
trimmed during the calibration cycle and the
DCLK output remains enabled. Note that the
ADC is calibrated regardless of this setting.
POR State: 0b
Bit 13
DES: DES Enable. Setting this bit to 1b
enables the Dual Edge Sampling mode. In
this mode the ADCs in this device are used
to sample and convert the same analog input
in a time-interleaved manner, accomplishing
a sample rate of twice the input clock rate.
When this bit is set to 0b, the device operates
in the normal dual channel mode.
POR State: 0b
Bit 12
IS: Input Select. When this bit is set to 0b the
"I" input is operated upon by both ADCs.
When this bit is set to 1b the "Q" input is
operated on by both ADCs.
POR State: 0b
Bits 6:0
Bit 11
Must be set to 0b
Bit 10
DLF: Low Frequency. When this bit is set 1b,
the dynamic performance of the device is
improved when the input clock is less than
900MHz.
POR State: 0b
Bits 9:0
Must be set to 1b
Q-Channel Offset
Addr: Ah (1010b)
D15
D14
D13
(MSB)
Write only (0x007F)
D12
D11
D10
D9
Offset Value
D8
(LSB)
D7
D6
D5
D4
D3
D2
D1
D0
Sign
1
1
1
1
1
1
1
Bits 15:8
Offset Value. The input offset of the QChannel ADC is adjusted linearly and
monotonically by the value in this field. 00h
provides a nominal zero offset, while FFh
provides a nominal 45 mV of offset. Thus,
each code step provides about 0.176 mV of
offset.
POR State: 0000 0000 b
Sign bit. 0b gives positive offset, 1b gives
negative offset.
POR State: 0b
Must be set to 1b
Bit 7
Bits 6:0
Q-Channel Full-Scale Voltage Adjust
Addr: Bh (1011b)
D15
D14
D13
(MSB)
Write only (0x807F)
D12
D11
D10
D9
D8
Adjust Value
D7
D6
D5
D4
D3
D2
D1
D0
(LSB)
1
1
1
1
1
1
1
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32
Full Scale Voltage Adjust Value. The input
full-scale voltage or gain of the I-Channel
ADC is adjusted linearly and monotonically
with a 9 bit data value. The adjustment range
is ±20% of the nominal 700 mVP-P differential
value.
0000 0000 0
560 mVP-P
1000 0000 0
700 mVP-P
1111 1111 1
840 mVP-P
For best performance, it is recommended
that the value in this field be limited to the
range of 0110 0000 0b to 1110 0000 0b. i.e.,
limit the amount of adjustment to ±15%. The
remaining ±5% headroom allows for the
ADC's own full scale variation. A gain
adjustment does not require ADC recalibration.
POR State: 1000 0000 0b (no adjustment)
Must be set to 1b
ADC08D1020
Sample Clock Phase Fine Adjust
Addr: 1110
D15
D14
Write only (0x00FF)
D13
(MSB)
D12
D11
D10
D9
Fine Phase Adjust
D8
(LSB)
D7
D6
D5
D4
D3
D2
D1
D0
1
1
1
1
1
1
1
1
Bits 15:8
Fine Phase Adjust. The phase of the ADC
sampling clock is adjusted monotonically by
the value in this field. 00h provides a nominal
zero phase adjustment, while FFh provides a
nominal 50 ps of delay. Thus, each code step
provides approximately 0.2 ps of delay.
20206230
FIGURE 11. Extended Mode Offset Behavior
POR State: 0000 0000b
Bits 7:0
1.5 MULTIPLE ADC SYNCHRONIZATION
The ADC08D1020 has the capability to precisely reset its
sampling clock input to DCLK output relationship as determined by the user-supplied DCLK_RST pulse. This allows
multiple ADCs in a system to have their DCLK (and data) outputs transition at the same time with respect to the shared
CLK input that all the ADCs use for sampling.
The DCLK_RST signal must observe some timing requirements that are shown in Figure 7, Figure 8 and Figure 9 of the
Timing Diagrams. The DCLK_RST pulse must be of a minimum width and its deassertion edge must observe setup and
hold times with respect to the CLK input rising edge. The duration of the DCLK_RST pulse affects the length of time that
the digital output will take before providing valid data again
after the end of the reset condition. Therefore, the DCLK_RST
pulse width should be made reasonably short within the system application constraints. These timing specifications are
listed as tRH, tRS, and tRPW in the Converter Electrical Characteristics.
The DCLK_RST signal can be asserted asynchronous to the
input clock. If DCLK_RST is asserted, the DCLK output is held
in a designated state. The state in which DCLK is held during
the reset period is determined by the mode of operation (SDR/
DDR) and the setting of the Output Edge configuration pin or
bit. (Refer to Figure 7, Figure 8 and Figure 9 for the DCLK
reset state conditions). Therefore, depending upon when the
DCLK_RST signal is asserted, there may be a narrow pulse
on the DCLK line during this reset event. When the
DCLK_RST signal is de-asserted in synchronization with the
CLK rising edge, the next CLK falling edge synchronizes the
DCLK output with those of other ADC08D1020s in the system. The DCLK output is enabled again after a constant delay
(relative to the input clock frequency) which is equal to the
CLK input to DCLK output delay (tOD). The device always exhibits this delay characteristic in normal operation. The user
has the option of using a single-ended DCLK_RST signal, but
a differential DCLK_RST is strongly recommended due to its
superior timing specifications.
If the device is not programmed to allow DCLK to run continuously, DCLK will become inactive during a calibration cycle.
Therefore, it is strongly recommended that DCLK only be
used as a data capture clock and not as a system clock.
The DCLK_RST pin should NOT be brought high while the
calibration process is running (while CalRun is high). Doing
so could cause a digital glitch in the digital circuitry, resulting
in corruption and invalidation of the calibration.
Must be set to 1b
Sample Clock Phase Intermediate/Coarse Adjust
Addr: Fh (1111b)
D15
POL
D14
D13
Write only (0x007F)
D12
D11
D10
D9
(MSB) Coarse Phase Adjust
D8
IPA
D7
D6
D5
D4
D3
D2
D1
D0
(LSB)
1
1
1
1
1
1
1
Bit 15
Polarity Select. When this bit is selected, the
polarity of the ADC sampling clock is
inverted.
POR State: 0b
Bits 14:10 Coarse Phase Adjust. Each code value in
this field delays the sample clock by
approximately 65 ps. A value of 00000b in
this field causes zero adjustment.
POR State: 00000b
Bits 9:7
Intermediate Phase Adjust. Each code value
in this field delays the sample clock by
approximately 11 ps. A value of 000b in this
field causes zero adjustment. Maximum
combined adjustment using Coarse Phase
Adjust and Intermediate Phase adjust is
approximately 2.1ns.
POR State: 000b
Bits 6:0
Must be set to 1b
1.4.1 Note Regarding Clock Phase Adjust
This is a feature intended to help the system designer remove
small imbalances in clock distribution traces at the board level
when multiple ADCs are used. Please note, however, that
enabling this feature will reduce the dynamic performance
(ENOB, SNR, SFDR) some finite amount. The amount of
degradation increases with the amount of adjustment applied.
The user is strongly advised to (a) use the minimal amount of
adjustment; and (b) verify the net benefit of this feature in his
system before relying on it.
1.4.2 Note Regarding Extended Mode Offset Correction
When using the I or Q channel Offset Adjust registers, the
following information should be noted.
For offset values of +0000 0000 and −0000 0000, the actual
offset is not the same. By changing only the sign bit in this
case, an offset step in the digital output code of about 1/10th
of an LSB is experienced. This is shown more clearly in the
Figure below.
1.6 ADC TEST PATTERN
To aid in system debug, the ADC08D1020 has the capability
of providing a test pattern at the four output ports completely
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ADC08D1020
independent of the input signal. The ADC is disengaged and
a test pattern generator is connected to the outputs including
OR. The test pattern output is the same in DES mode and
non-DES mode. Each port is given a unique 8-bit word, alternating between 1's and 0's as described in Table 6 and Table
7.
Time
T13
TABLE 6. Test Pattern by Output Port in
1:2 Demultiplex Mode
T14
T15
...
Time
Qd
Id
Q
I
OR
T0
01h
02h
03h
04h
0
T1
FEh
FDh
FCh
FBh
1
T2
01h
02h
03h
04h
0
T3
FEh
FDh
FCh
FBh
1
T4
01h
02h
03h
04h
0
T5
01h
02h
03h
04h
0
T6
FEh
FDh
FCh
FBh
1
T7
01h
02h
03h
04h
0
T8
FEh
FDh
FCh
FBh
1
T9
01h
02h
03h
04h
0
T10
01h
02h
03h
04h
0
T11
...
...
...
...
...
Comments
Pattern
Sequence
n
Pattern
Sequence
n+1
Pattern
Sequence n
+2
TABLE 7. Test Pattern by Output Port in
Non-demultiplex Mode
Q
I
OR
T0
01h
02h
0
T1
FEh
FDh
1
T2
01h
02h
0
T3
01h
02h
0
T4
FEh
FDh
1
T5
FEh
FDh
1
T6
01h
02h
0
T7
01h
02h
0
T8
FEh
FDh
1
T9
01h
02h
0
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I
OR
T10
01h
02h
0
T11
FEh
FDh
1
T12
01h
02h
0
01h
02h
0
FEh
FDh
1
...
...
Comments
Pattern
Sequence
n+1
It is possible for the I and the Q channels' test patterns to be
not synchronized. Either I and Id or Q and Qd patterns may
be slipped by one DCLK.
To ensure that the test pattern starts synchronously in each
port, set DCLK_RST while writing the Test Pattern Output bit
in the Extended Configuration Register. The pattern appears
at the data output ports when DCLK_RST is cleared low. The
test pattern will work at speed and will work with the device in
the SDR, DDR and the non-demultiplex output modes.
With the part programmed into the non-demultiplex mode, the
test pattern’s order will be as described in Table 7.
Time
Q
Comments
Pattern
Sequence
n
34
2.1 THE REFERENCE VOLTAGE
The voltage reference for the ADC08D1020 is derived from a
1.254V bandgap reference, a buffered version of which is
made available at pin 31, VBG, for user convenience.
This output has an output current capability of ±100 μA and
should be buffered if more current than this is required.
The internal bandgap-derived reference voltage has a nominal value of 650 mV or 870 mV, as determined by the FSR
pin and described in 1.1.4 The Analog Inputs.
There is no provision for the use of an external reference voltage, but the full-scale input voltage can be adjusted through
a Configuration Register in the Extended Control mode, as
explained in 1.2 NORMAL/EXTENDED CONTROL.
Differential input signals up to the chosen full-scale level will
be digitized to 8 bits. Signal excursions beyond the full-scale
range will be clipped at the output. These large signal excursions will also activate the OR output for the time that the
signal is out of range. See 2.2.2 Out Of Range (OR) Indication.
One extra feature of the VBG pin is that it can be used to raise
the common mode voltage level of the LVDS outputs. The
output offset voltage (V OS) is typically 800 mV when the VBG
pin is used as an output or left unconnected. To raise the
LVDS offset voltage to a typical value of 1175 mV the VBG pin
can be connected directly to the supply rails.
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FIGURE 12. Differential Input Drive
When the d.c. coupled mode is used, a common mode voltage must be provided at the differential inputs. This common
mode voltage should track the VCMO output pin. Note that the
VCMO output potential will change with temperature. The common mode output of the driving device should track this
change.
IMPORTANT NOTE: An analog input channel that is not used
(e.g. in DES Mode) should be tied to the VCMO voltage when
the inputs are d.c. coupled. Do not connect unused analog
inputs to ground.
Full-scale distortion performance falls off rapidly as the
input common mode voltage deviates from VCMO. This is
a direct result of using a very low supply voltage to minimize power. Keep the input common voltage within 50
mV of VCMO.
Performance is as good in the d.c. coupled mode as it is in
the a.c. coupled mode, provided the input common mode
voltage at both analog inputs remain within 50 mV of VCMO.
2.2 THE ANALOG INPUT
The analog input is a differential one to which the signal
source may be a.c. coupled or d.c. coupled. In the normal
mode, the full-scale input range is selected using the FSR pin
as specified in the Converter Electrical Characteristics. In the
Extended Control mode, the full-scale input range is selected
by programming the Full-Scale Voltage Adjust register
through the Serial Interface. For best performance when adjusting the input full-scale range in the Extended Control, refer
to 1.4 REGISTER DESCRIPTION for guidelines on limiting
the amount of adjustment
Table 8 gives the input to output relationship with the FSR pin
high when the normal (non-extended) mode is used. With the
FSR pin grounded, the millivolt values in Table 8 are reduced
to 75% of the values indicated. In the Enhanced Control
Mode, these values will be determined by the full scale range
and offset settings in the Control Registers.
2.2.1 Handling Single-Ended Input Signals
There is no provision for the ADC08D1020 to adequately process single-ended input signals. The best way to handle
single-ended signals is to convert them to differential signals
before presenting them to the ADC. The easiest way to accomplish single-ended to differential signal conversion is with
an appropriate balun-connected transformer, as shown in
Figure 13.
TABLE 8. Differential Input To Output Relationship
(Non-Extended Control Mode, FSR High)
VIN+
VIN−
Output Code
VCM − 217.5 mV
VCM + 217.5 mV
0000 0000
VCM − 109 mV
VCM + 109 mV
0100 0000
VCM
VCM
0111 1111 /
1000 0000
VCM + 109 mV
VCM − 109 mV
1100 0000
VCM + 217.5 mV
VCM − 217.5 mV
1111 1111
2.2.1.1. a.c. Coupled Input
The easiest way to accomplish single-ended a.c. input to differential a.c. signal is by using an appropriate balun, as shown
inFigure 13.
The buffered analog inputs simplify the task of driving these
inputs and the RC pole that is generally used at sampling ADC
inputs is not required. If it is desired to use an amplifier circuit
before the ADC, use care in choosing an amplifier with adequate noise and distortion performance and adequate gain at
the frequencies used for the application.
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ADC08D1020
Note that a precise d.c. common mode voltage must be
present at the ADC inputs. This common mode voltage,
VCMO, is provided on-chip when a.c. input coupling is used
and the input signal is a.c. coupled to the ADC.
When the inputs are a.c. coupled, the VCMO output must be
grounded, as shown in Figure 12. This causes the on-chip
VCMO voltage to be connected to the inputs through on-chip
50 kΩ resistors.
IMPORTANT NOTE: An Analog input channel that is not used
(e.g. in DES Mode) should be connected to ac-ground (ie,
capacitors to ground) when the inputs are a.c. coupled. Do
not connect an unused analog input directly to ground.
2.0 Applications Information
ADC08D1020
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FIGURE 13. Single-Ended to Differential Signal
Conversion Using a Balun
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Figure 13 is a generic depiction of a single-ended to differential signal conversion using a balun. The circuitry specific to
the balun will depend upon the type of balun selected and the
overall board layout. It is recommended that the system designer contact the manufacturer of the balun they have selected to aid in designing the best performing single-ended to
differential conversion circuit using that particular balun.
When selecting a balun, it is important to understand the input
architecture of the ADC. There are specific balun parameters
of which the system designer should be mindful. A designer
should match the impedance of their analog source to the
ADC081020's on-chip 100Ω differential input termination resistor. The range of this termination resistor is described in
the electrical table as the specification RIN.
Also, the phase and amplitude balance are important. The
lowest possible phase and amplitude imbalance is desired
when selecting a balun. The phase imbalance should be no
more than ±2.5° and the amplitude imbalance should be limited to less than 1dB at the desired input frequency range.
Finally, when selecting a balun, the VSWR (Voltage Standing
Wave Ratio), bandwidth and insertion loss of the balun should
also be considered. The VSWR aids in determining the overall
transmission line termination capability of the balun when interfacing to the ADC input. The insertion loss should be
considered so that the signal at the balun output is within the
specified input range of the ADC as described in the Converter Electrical Characteristics as the specification VIN.
FIGURE 14. Example of Servoing the Analog Input with
VCMO
In Figure 14, RADJ- and RADJ+ are used to adjust the differential
offset that can be measured at the ADC inputs VIN+ / VIN- with
LMH6555's input terminated to ground as shown but not driven and with no RADJ resistors applied. An unadjusted positive
offset with reference to VIN- greater than |15mV| should be
reduced with a resistor in the RADJ- position. Likewise, an unadjusted negative offset with reference to VIN- greater than
|15mV| should be reduced with a resistor in the RADJ+ position.
Table 9 gives suggested RADJ- and RADJ+ values for various
unadjusted differential offsets to bring the VIN+ / VIN- offset
back to within |15mV|.
TABLE 9. D.C. Coupled Offset Adjustment
Unadjusted Offset Reading
Resistor Value
0mV to 10mV
no resistor needed
11mV to 30mV
20.0kΩ
31mV to 50mV
10.0kΩ
51mV to 70mV
6.81kΩ
71mV to 90mV
4.75kΩ
91mV to 110mV
3.92kΩ
2.2.2 Out Of Range (OR) Indication
When the conversion result is clipped the Out of Range output
is activated such that OR+ goes high and OR- goes low. This
output is active as long as accurate data on either or both of
the buses would be outside the range of 00h to FFh. Note that
when the device is programmed to provide a second DCLK
output, the OR signals become DCLK2. Refer to 1.4 REGISTER DESCRIPTION
2.2.1.2. d.c. Coupled Input
When d.c. coupling to the ADC08D1020 analog inputs is required, single-ended to differential conversion may be easily
accomplished with the LMH6555, as shown inFigure 14. In
such applications, the LMH6555 performs the task of singleended to differential conversion while delivering low distortion
and noise, as well as output balance, that supports the operation of the ADC08D1020. Connecting the ADC08D1020
VCMO pin to the VCM_REF pin of the LMH6555, through an appropriate buffer, will ensure that the common mode input
voltage is as needed for optimum performance of the ADC08D1020. The LMV321 was chosen to buffer VCMD for its
low voltage operation and reasonable offset voltage.
Be sure to limit output current from the ADC08D1020 VCMO
pin to 100 μA
2.2.3 Full-Scale Input Range
As with all A/D Converters, the input range is determined by
the value of the ADC's reference voltage. The reference voltage of the ADC08D1020 is derived from an internal band-gap
reference. The FSR pin controls the effective reference voltage of the ADC08D1020 such that the differential full-scale
input range at the analog inputs is a normal amplitude with
the FSR pin high, or a reduced amplitude with FSR pin low as
defined by the specification VIN in the Converter Electrical
Characteristics. Best SNR is obtained with FSR high, but better distortion and SFDR are obtained with the FSR pin low.
The LMH6555 of is Figure 14 suitable for any Full Scale
Range.
2.3 THE CLOCK INPUTS
The ADC08D1020 has differential LVDS clock inputs, CLK+
and CLK−, which must be driven with an a.c. coupled, differential clock signal. Although the ADC08D1020 is tested and
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2.4 CONTROL PINS
Six control pins (without the use of the serial interface) provide
a wide range of possibilities in the operation of the ADC08D1020 and facilitate its use. These control pins provide
Full-Scale Input Range setting, Calibration, Calibration Delay,
Output Edge Synchronization choice, LVDS Output Level
choice and a Power Down feature.
2.4.1 Full-Scale Input Range Setting
The input full-scale range can be selected with the FSR control input (pin 14) in the normal mode of operation. The input
full-scale range is specified as VIN in the Converter Electrical
Characteristics. In the extended control mode, the input fullscale range may be programmed using the Full-Scale Adjust
Voltage register. See 2.2 THE ANALOG INPUT for more information.
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2.4.2 Calibration
The ADC08D1020 calibration must be run to achieve specified performance. The calibration procedure is run upon power-up and can be run any time on command. The calibration
procedure is exactly the same whether there is an input clock
present upon power up or if the clock begins some time after
application of power. The CalRun output indicator is high
while a calibration is in progress. Note that the DCLK outputs
are not active during a calibration cycle by default and therefore are not recommended as system clock unless the Resistor Trim Disable feature is used (Reg.9h). The DCLK
outputs are continuously present at the output only when the
Resistor Trim Disable is active.
FIGURE 15. Differential (LVDS) Input Clock Connection
The differential input clock line pair should have a characteristic impedance of 100 Ω and (when using a balun), be
terminated at the clock source in that (100 Ω) characteristic
impedance. The input clock line should be as short and as
direct as possible. The ADC08D1020 clock input is internally
terminated with an untrimmed 100 Ω resistor.
Insufficient input clock levels will result in poor dynamic performance. Excessively high clock levels could cause a
change in the analog input offset voltage. To avoid these
problems, keep the clock level within the range specified as
VID in the Converter Electrical Characteristics.
The low and high times of the input clock signal can affect the
performance of any A/D Converter. The ADC08D1020 features a duty cycle clock correction circuit which can maintain
performance over temperature even in DES mode. The ADC
will meet its performance specification if the input clock high
and low times are maintained within the duty cycle range as
specified in the Converter Electrical Characteristics.
High speed, high performance ADCs such as the ADC08D1020 require a very stable input clock signal with minimum phase noise or jitter. ADC jitter requirements are defined
by the ADC resolution (number of bits), maximum ADC input
frequency and the input signal amplitude relative to the ADC
input full scale range. The maximum jitter (the sum of the jitter
from all sources) allowed to prevent a jitter-induced reduction
in SNR is found to be
2.4.2.1 Power-On Calibration
Power-on calibration begins after a time delay following the
application of power. This time delay is determined by the
setting of CalDly, as described in the Calibration Delay Section, below.
The calibration process will be not be performed if the CAL
pin is high at power up. In this case, the calibration cycle will
not begin until the on-command calibration conditions are
met. The ADC08D1020 will function with the CAL pin held
high at power up, but no calibration will be done and performance will be impaired. A manual calibration, however, may
be performed after powering up with the CAL pin high. See
On-Command Calibration 2.4.2.2 On-Command Calibration.
The internal power-on calibration circuitry comes up in an unknown logic state. If the input clock is not running at power up
and the power on calibration circuitry is active, it will hold the
analog circuitry in power down and the power consumption
will typically be less than 200 mW. The power consumption
will be normal after the clock starts.
tJ(MAX) = (VINFSR / VIN(P-P)) x (1/(2(N+1) x π x fIN))
where tJ(MAX) is the rms total of all jitter sources in seconds,
VIN(P-P) is the peak-to-peak analog input signal, VINFSR is the
full-scale range of the ADC, "N" is the ADC resolution in bits
and fIN is the maximum input frequency, in Hertz, at the ADC
analog input.
Note that the maximum jitter described above is the RSS sum
of the jitter from all sources, including that in the ADC input
clock, that added by the system to the ADC input clock and
2.4.2.2 On-Command Calibration
To initiate an on-command calibration, bring the CAL pin high
for a minimum of tCAL_H input clock cycles after it has been
low for a minimum of tCAL_L input clock cycles. Holding the
CAL pin high upon power up will prevent execution of power37
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ADC08D1020
input signals and that added by the ADC itself. Since the effective jitter added by the ADC is beyond user control, the best
the user can do is to keep the sum of the externally added
input clock jitter and the jitter added by the analog circuitry to
the analog signal to a minimum.
Input clock amplitudes above those specified in the Converter
Electrical Characteristics may result in increased input offset
voltage. This would cause the converter to produce an output
code other than the expected 127/128 when both input pins
are at the same potential.
its performance is guaranteed with a differential 1 GHz clock,
it typically will function well with input clock frequencies indicated in the Converter Electrical Characteristics. The clock
inputs are internally terminated and biased. The input clock
signal must be capacitively coupled to the clock pins as indicated in Figure 15.
Operation up to the sample rates indicated in the Converter
Electrical Characteristics is typically possible if the maximum
ambient temperatures indicated are not exceeded. Operating
at higher sample rates than indicated for the given ambient
temperature may result in reduced device reliability and product lifetime. This is because of the higher power consumption
and die temperatures at high sample rates. Important also for
reliability is proper thermal management . See 2.6.2 Thermal
Management.
ADC08D1020
on calibration until the CAL pin is low for a minimum of
tCAL_L input clock cycles, then brought high for a minimum of
another tCAL_H input clock cycles. The calibration cycle will
begin tCAL_H input clock cycles after the CAL pin is thus
brought high. The CalRun signal should be monitored to determine when the calibration cycle has completed.
The minimum tCAL_L and tCAL_H input clock cycle sequence is
required to ensure that random noise does not cause a calibration to begin when it is not desired. As mentioned for best
performance, a calibration should be performed 20 seconds
or more after power up and repeated when the operating
temperature changes significantly relative to the specific system design performance requirements.
By default, On-Command calibration also includes calibrating
the input termination resistance and the ADC. However, since
the input termination resistance, once trimmed at power-up,
changes marginally with temperature, the user has the option
to disable the input termination resistor trim, which will guarantee that the DCLK is continuously present at the output
during subsequent calibration. The Resistor Trim Disable can
be programmed in register (address: 1h, bit 13) when in the
Extended Control mode. Refer to for register programming
information.
With OutV low there is less power consumption in the output
drivers, but the lower output level means decreased noise
immunity.
For short LVDS lines and low noise systems, satisfactory performance may be realized with the OutV input low. If the LVDS
lines are long and/or the system in which the ADC08D1020
is used is noisy, it may be necessary to tie the OutV pin high.
2.4.5 Dual Edge Sampling
The Dual Edge Sampling (DES) feature causes one of the two
input pairs to be routed to both ADCs. The other input pair is
deactivated. One of the ADCs samples the input signal on one
input clock edge (duty cycle corrected), the other samples the
input signal on the other input clock edge (duty cycle corrected). If the device is in the 1:2 output demultiplex mode, the
result is an output data rate 1/4 that of the interleaved sample
rate which is twice the input clock frequency. Data is presented in parallel on all four output buses in the following order:
DQd, DId, DQ, DI. If the device is the non-demultiplex output
mode, the result is an output data rate 1/2 that of the interleaved sample rate. Data is presented in parallel on two
output buses in the following order: DQ, DI.
To use this feature in the non-extended control mode, allow
pin 127 to float and the signal at the "I" channel input will be
sampled by both converters. The Calibration Delay will then
only be a short delay.
In the extended control mode, either input may be used for
dual edge sampling. See 1.1.5.1 Dual-Edge Sampling.
2.4.2.3 Calibration Delay
The CalDly input (pin 127) is used to select one of two delay
times after the application of power to the start of calibration,
as described in 1.1.1 Calibration. The calibration delay values
allow the power supply to come up and stabilize before calibration takes place. With no delay or insufficient delay, calibration would begin before the power supply is stabilized at
its operating value and result in non-optimal calibration coefficients. If the PD pin is high upon power-up, the calibration
delay counter will be disabled until the PD pin is brought low.
Therefore, holding the PD pin high during power up will further
delay the start of the power-up calibration cycle. The best
setting of the CalDly pin depends upon the power-on settling
time of the power supply.
Note that the calibration delay selection is not possible in the
Extended Control mode and the short delay time is used.
2.4.6 Power Down Feature
The Power Down pins (PD and PDQ) allow the ADC08D1020
to be entirely powered down (PD) or the "Q" channel to be
powered down and the "I" channel to remain active. See 1.1.7
Power Down for details on the power down feature.
The digital data (+/-) output pins are put into a high impedance
state when the PD pin for the respective channel is high. Upon
return to normal operation, the pipeline will contain meaningless information and must be flushed.
If the PD input is brought high while a calibration is running,
the device will not go into power down until the calibration
sequence is complete. However, if power is applied and PD
is already high, the device will not begin the calibration sequence until the PD input goes low. If a manual calibration is
requested while the device is powered down, the calibration
will not begin at all. That is, the manual calibration input is
completely ignored in the power down state.
2.4.3 Output Edge Synchronization
DCLK signals are available to help latch the converter output
data into external circuitry. The output data can be synchronized with either edge of these DCLK signals. That is, the
output data transition can be set to occur with either the rising
edge or the falling edge of the DCLK signal, so that either
edge of that DCLK signal can be used to latch the output data
into the receiving circuit.
When OutEdge (pin 4) is high, the output data is synchronized
with (changes with) the rising edge of the DCLK+ (pin 82).
When OutEdge is low, the output data is synchronized with
the falling edge of DCLK+.
At the very high speeds of which the ADC08D1020 is capable,
slight differences in the lengths of the DCLK and data lines
can mean the difference between successful and erroneous
data capture. The OutEdge pin is used to capture data on the
DCLK edge that best suits the application circuit and layout.
Reliable data capture can be achieved by using just one
DCLK+/- signal for the full 32 signal data bus. However, if desired, the user may configure the OR+/- output as the second
DCLK+/- output instead.
2.5 THE DIGITAL OUTPUTS
The ADC08D1020 normally demultiplexes the output data of
each of the two ADCs on the die onto two LVDS output buses
(total of four buses, two for each ADC). For each of the two
converters, the results of successive conversions started on
the odd falling edges of the CLK+ pin are available on one of
the two LVDS buses, while the results of conversions started
on the even falling edges of the CLK+ pin are available on the
other LVDS bus. This means that, the word rate at each LVDS
bus is 1/2 the ADC08D1020 input clock rate and the two buses must be multiplexed to obtain the entire 1 GSPS conversion result.
Since the minimum recommended input clock rate for this
device is 200 MSPS (normal non-DES mode), the effective
rate can be reduced to as low as 100 MSPS by using the
results available on just one of the the two LVDS buses and
a 200 MHz input clock, decimating the 200 MSPS data by two.
There is one LVDS output clock pair (DCLK+/−) available for
use to latch the LVDS outputs on all buses. However, the user
2.4.4 LVDS Output Level Control
The output level can be set to one of two levels with OutV (pin
3). The strength of the output drivers is greater with OutV high.
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In the circuit of Figure 16, an LM317 linear regulator is satisfactory if its input supply voltage is 4V to 5V . If a 3.3V supply
is used, an LM1086 linear regulator is recommended.
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FIGURE 16. Non-Spiking Power Supply
The output drivers should have a supply voltage, VDR, that is
within the range specified in the Operating Ratings table. This
voltage should not exceed the VA supply voltage.
If the power is applied to the device without an input clock
signal present, the current drawn by the device might be below 200 mA. This is because the ADC08D1020 gets reset
through clocked logic and its initial state is unknown. If the
reset logic comes up in the "on" state, it will cause most of the
analog circuitry to be powered down, resulting in less than
100 mA of current draw. This current is greater than the power
down current because not all of the ADC is powered down.
The device current will be normal after the input clock is established.
2.6 POWER CONSIDERATIONS
A/D converters draw sufficient transient current to corrupt
their own power supplies if not adequately bypassed. A
33 µF capacitor should be placed within an inch (2.5 cm) of
the A/D converter power pins. A 0.1 µF capacitor should be
placed as close as possible to each VA pin, preferably within
one-half centimeter. Leadless chip capacitors are preferred
because they have low lead inductance.
The VA and VDR supply pins should be isolated from each
other to prevent any digital noise from being coupled into the
analog portions of the ADC. A ferrite choke, such as the JW
Miller FB20009-3B, is recommended between these supply
lines when a common source is used for them.
As is the case with all high speed converters, the ADC08D1020 should be assumed to have little power supply
noise rejection. Any power supply used for digital circuitry in
a system where a lot of digital power is being consumed
should not be used to supply power to the ADC08D1020. The
ADC supplies should be the same supply used for other analog circuitry, if not a dedicated supply.
2.6.2 Thermal Management
The ADC08D1020 is capable of impressive speeds and performance at very low power levels for its speed. However, the
power consumption is still high enough to require attention to
thermal management. For reliability reasons, the die temperature should be kept to a maximum of 130°C. That is, TA
(ambient temperature) plus ADC power consumption times
θJA (junction to ambient thermal resistance) should not exceed 130°C. This is not a problem if the ambient temperature
is kept to a maximum of +85°C as specified in the Operating
Ratings section.
Please note that the following are general recommendations
for mounting exposed pad devices onto a PCB. This should
be considered the starting point in PCB and assembly process development. It is recommended that the process be
developed based upon past experience in package mounting.
The package of the ADC08D1020 has an exposed pad on its
back that provides the primary heat removal path as well as
excellent electrical grounding to the printed circuit board. The
land pattern design for lead attachment to the PCB should be
the same as for a conventional LQFP, but the exposed pad
must be attached to the board to remove the maximum
amount of heat from the package, as well as to ensure best
product parametric performance.
To maximize the removal of heat from the package, a thermal
land pattern must be incorporated on the PC board within the
footprint of the package. The exposed pad of the device must
be soldered down to ensure adequate heat conduction out of
the package. The land pattern for this exposed pad should be
at least as large as the 5 x 5 mm of the exposed pad of the
package and be located such that the exposed pad of the
device is entirely over that thermal land pattern. This thermal
land pattern should be electrically connected to ground. A
clearance of at least 0.5 mm should separate this land pattern
from the mounting pads for the package pins.
2.6.1 Supply Voltage
The ADC08D1020 is specified to operate with a supply voltage of 1.9V ±0.1V. It is very important to note that, while this
device will function with slightly higher supply voltages, these
higher supply voltages may reduce product lifetime.
No pin should ever have a voltage on it that is in excess of the
supply voltage or below ground by more than 150 mV, not
even on a transient basis. This can be a problem upon application of power and power shut-down. Be sure that the supplies to circuits driving any of the input pins, analog or digital,
do not come up any faster than does the voltage at the ADC08D1020 power pins.
The Absolute Maximum Ratings should be strictly observed,
even during power up and power down. A power supply that
produces a voltage spike at turn-on and/or turn-off of power
can destroy the ADC08D1020. The circuit of Figure 16 will
provide supply overshoot protection.
Many linear regulators will produce output spiking at poweron unless there is a minimum load provided. Active devices
draw very little current until their supply voltages reach a few
hundred millivolts. The result can be a turn-on spike that can
destroy the ADC08D1020, unless a minimum load is provided
for the supply. The 100 Ω resistor at the regulator output provides a minimum output current during power-up to ensure
there is no turn-on spiking.
39
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ADC08D1020
has the option to configure the OR+/- output as a second
DCLK+/- pair. Whether the data is sent at the rising or falling
edge of DCLK is determined by the sense of the OutEdge pin,
as described in 2.4.3 Output Edge Synchronization.
DDR (Double Data Rate) clocking can also be used. In this
mode a word of data is presented with each edge of DCLK,
reducing the DCLK frequency to 1/4 the input clock frequency.
See the Timing Diagram section for details.
The OutV pin is used to set the LVDS differential output levels.
See 2.4.4 LVDS Output Level Control.
The output format is Offset Binary. Accordingly, a full-scale
input level with VIN+ positive with respect to VIN− will produce
an output code of all ones, a full-scale input level with VIN−
positive with respect to VIN+ will produce an output code of all
zeros and when VIN+ and VIN− are equal, the output code will
vary between codes 127 and 128. A non-multiplexed mode of
operation is available for those cases where the digital ASIC
is capable of higher speed operation.
ADC08D1020
isolate and remedy. The solution is to keep the analog circuitry well separated from the digital circuitry.
High power digital components should not be located on or
near any linear component or power supply trace or plane that
services analog or mixed signal components as the resulting
common return current path could cause fluctuation in the
analog input “ground” return of the ADC, causing excessive
noise in the conversion result.
Generally, we assume that analog and digital lines should
cross each other at 90° to avoid getting digital noise into the
analog path. In high frequency systems, however, avoid
crossing analog and digital lines altogether. The input clock
lines should be isolated from ALL other lines, analog AND
digital. The generally-accepted 90° crossing should be avoided as even a little coupling can cause problems at high
frequencies. Best performance at high frequencies is obtained with a straight signal path.
The analog input should be isolated from noisy signal traces
to avoid coupling of spurious signals into the input. This is
especially important with the low level drive required of the
ADC08D1020. Any external component (e.g., a filter capacitor) connected between the converter's input and ground
should be connected to a very clean point in the analog
ground plane. All analog circuitry (input amplifiers, filters, etc.)
should be separated from any digital components.
20206221
FIGURE 17. Recommended Package Land Pattern
Since a large aperture opening may result in poor release, the
aperture opening should be subdivided into an array of smaller openings, similar to the land pattern of Figure 17.
To minimize junction temperature, it is recommended that a
simple heat sink be built into the PCB. This is done by including a copper area of about 2 square inches (6.5 square cm)
on the opposite side of the PCB. This copper area may be
plated or solder coated to prevent corrosion, but should not
have a conformal coating, which could provide some thermal
insulation. Thermal vias should be used to connect these top
and bottom copper areas. These thermal vias act as "heat
pipes" to carry the thermal energy from the device side of the
board to the opposite side of the board where it can be more
effectively dissipated. The use of 9 to 16 thermal vias is recommended.
The thermal vias should be placed on a 1.2 mm grid spacing
and have a diameter of 0.30 to 0.33 mm. These vias should
be barrel plated to avoid solder wicking into the vias during
the soldering process as this wicking could cause voids in the
solder between the package exposed pad and the thermal
land on the PCB. Such voids could increase the thermal resistance between the device and the thermal land on the
board, which would cause the device to run hotter.
If it is desired to monitor die temperature, a temperature sensor may be mounted on the heat sink area of the board near
the thermal vias. Allow for a thermal gradient between the
temperature sensor and the ADC08D1020 die of θJC (Thermal
Pad) times typical power consumption = 2.8 x 1.8 = 5°C. Allowing for 6°C, including some margin for temperature drop
from the pad to the temperature sensor, then, would mean
that maintaining a maximum pad temperature reading of 124°
C will ensure that the die temperature does not exceed 130°
C, assuming that the exposed pad of the ADC08D1020 is
properly soldered down and the thermal vias are adequate.
(The inaccuracy of the temperature sensor is in addition to the
above calculation).
2.8 DYNAMIC PERFORMANCE
The ADC08D1020 is a.c. tested and its dynamic performance
is guaranteed. To meet the published specifications and avoid
jitter-induced noise, the clock source driving the CLK input
must exhibit low rms jitter. The allowable jitter is a function of
the input frequency and the input signal level, as described in
2.3 THE CLOCK INPUTS.
It is good practice to keep the ADC input clock line as short
as possible, to keep it well away from any other signals and
to treat it as a transmission line. Other signals can introduce
jitter into the input clock signal. The clock signal can also introduce noise into the analog path if not isolated from that
path.
Best dynamic performance is obtained when the exposed pad
at the back of the package has a good connection to ground.
This is because this path from the die to ground is a lower
impedance than offered by the package pins.
2.9 USING THE SERIAL INTERFACE
The ADC08D1020 may be operated in the non-extended control (non-Serial Interface) mode or in the extended control
mode. Table 10 and Table 11 describe the functions of pins
3, 4, 14 and 127 in the non-extended control mode and the
extended control mode, respectively.
2.9.1 Non-Extended Control Mode Operation
Non-extended control mode operation means that the Serial
Interface is not active and all controllable functions are controlled with various pin settings. Pin 41 is the primary control
of the extended control enable function. When pin 41 is logic
high, the device is in the non-extended control mode. If pin 41
is floating and pin 52 is floating or logic high, the extended
control enable function is controlled by pin 14. The device has
functions which are pin programmable when in the non-extended control mode. An example is the full-scale range is
controlled in the non-extended control mode by setting pin 14
high or low. Table 10 indicates the pin functions of the ADC08D1020 in the non-extended control mode.
2.7 LAYOUT AND GROUNDING
Proper grounding and proper routing of all signals are essential to ensure accurate conversion. A single ground plane
should be used, instead of splitting the ground plane into analog and digital areas.
Since digital switching transients are composed largely of
high frequency components, the skin effect tells us that total
ground plane copper weight will have little effect upon the
logic-generated noise. Total surface area is more important
than is total ground plane volume. Coupling between the typically noisy digital circuitry and the sensitive analog circuitry
can lead to poor performance that may seem impossible to
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40
Pin
Low
High
Floating
3
Reduced VOD
Normal VOD
n/a
4
OutEdge = Neg
OutEdge = Pos
DDR
127
CalDly Short
CalDly Long
DES
Normal VIN
Extended
Control
Mode
Reduced VIN
14
Pin 3 can be either high or low in the non-extended control
mode. See 1.2 NORMAL/EXTENDED CONTROL for more
information.
Pin 4 can be high or low or can be left floating in the nonextended control mode. In the non-extended control mode,
pin 4 high or low defines the edge at which the output data
transitions. See 2.4.3 Output Edge Synchronization for more
information. If this pin is floating, the output clock (DCLK) is a
DDR (Double Data Rate) clock (see 1.1.5.3 Double Data
Rate) and the output edge synchronization is irrelevant since
data is clocked out on both DCLK edges.
Pin 127, if it is high or low in the non-extended control mode,
sets the calibration delay. If pin 127 is floating, the calibration
delay is the same as it would be with this pin low and the
converter performs dual edge sampling (DES).
TABLE 11. Extended Control Mode Operation
(Pin 41 Logic Low or Pin 14 Floating and Pin 52 Floating
or Logic High)
Pin
Function
3
SCLK (Serial Clock)
4
SDATA (Serial Data)
127
SCS (Serial Interface Chip Select)
2.10 COMMON APPLICATION PITFALLS
Driving the inputs (analog or digital) beyond the power
supply rails. For device reliability, no input should go more
than 150 mV below the ground pins or 150 mV above the
supply pins. Exceeding these limits on even a transient basis
may not only cause faulty or erratic operation, but may impair
device reliability. It is not uncommon for high speed digital
circuits to exhibit undershoot that goes more than a volt below
41
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ADC08D1020
ground. Controlling the impedance of high speed lines and
terminating these lines in their characteristic impedance
should control overshoot.
Care should be taken not to overdrive the inputs of the ADC08D1020. Such practice may lead to conversion inaccuracies and even to device damage.
Incorrect analog input common mode voltage in the d.c.
coupled mode. As discussed in 1.1.4 The Analog Inputs and
2.2 THE ANALOG INPUT, the Input common mode voltage
must remain within 50 mV of the VCMO output , which has a
variability with temperature that must also be tracked. Distortion performance will be degraded if the input common mode
voltage is more than 50 mV from VCMO .
Using an inadequate amplifier to drive the analog input.
Use care when choosing a high frequency amplifier to drive
the ADC08D1020 as many high speed amplifiers will have
higher distortion than will the ADC08D1020, resulting in overall system performance degradation.
Driving the VBG pin to change the reference voltage. As
mentioned in 2.1 THE REFERENCE VOLTAGE, the reference voltage is intended to be fixed by FSR pin or Full-Scale
Voltage Adjust register settings. Over driving this pin will not
change the full scale value, but can otherwise upset operation.
Driving the clock input with an excessively high level
signal. The ADC input clock level should not exceed the level
described in the Operating Ratings Table or the input offset
could change.
Inadequate input clock levels. As described in 2.3 THE
CLOCK INPUTS, insufficient input clock levels can result in
poor performance. Excessive input clock levels could result
in the introduction of an input offset.
Using a clock source with excessive jitter, using an excessively long input clock signal trace, or having other
signals coupled to the input clock signal trace. This will
cause the sampling interval to vary, causing excessive output
noise and a reduction in SNR performance.
Failure to provide adequate heat removal. As described in
2.6.2 Thermal Management, it is important to provide adequate heat removal to ensure device reliability. This can be
done either with adequate air flow or the use of a simple heat
sink built into the board. The backside pad should be grounded for best performance.
TABLE 10. Non-Extended Control Mode Operation
(Pin 41 Floating and Pin 52 Floating or Logic High)
ADC08D1020
Physical Dimensions inches (millimeters) unless otherwise noted
NOTES: UNLESS OTHERWISE SPECIFIED
REFERENCE JEDEC REGISTRATION MS-026, VARIATION BFB.
128-Lead, Exposed Pad, Low Profile, Quad, Flatpack (LQFP)
Order Number ADC08D1020CIYB
NS Package Number VNX128A
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ADC08D1020
Notes
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ADC08D1020 Low Power, 8-Bit, Dual 1.0 GSPS or Single 2.0 GSPS A/D Converter
Notes
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