MOTOROLA Order this document by MCM8A10/D SEMICONDUCTOR TECHNICAL DATA Advance Information 1M x 8 Bit Fast Static RAM Module The MCM8A10 is an 8M bit static random access memory module organized as 1,048,576 words of 8 bits. The module is offered in a 72–lead single in–line memory module (SIMM). Eight MCM6227B fast static RAMs, packaged in 28–lead SOJ packages are mounted on a printed circuit board along with eight decoupling capacitors. The MCM6227B is organized as 1,048,576 words of 1 bit. Static design eliminates the need for external clocks or timing strobes, while CMOS circuitry reduces power consumption and provides for greater reliability. The MCM8A10 is equipped with a chip enable (E) and eight separate write enable (W0 – W7) inputs, allowing for greater system flexibility. • • • • • • • Single 5 V ± 5% Power Supply Fast Access Times: 15 ns Three–State Outputs Fully TTL Compatible High Board Density SIMM Package Bit Operation: Eight Separate Write Enables, One for Each Bit High Quality Six–Layer FR4 PWB with Separate Internal Power and Ground Planes MCM8A10 PIN ASSIGNMENT TOP VIEW 72-LEAD SIMM – CASE TBD A1 2 1 A0 VSS A3 4 3 A2 6 5 A5 8 7 VCC A4 A7 10 9 A6 VCC A9 12 11 14 13 VSS A8 D0 16 15 Q0 18 17 W0 20 19 VCC D1 VSS W1 Q1 22 21 A11 24 23 A10 VCC DAISY 26 25 28 27 VSS DAISY D2 30 29 Q2 32 31 W2 34 33 Q3 36 35 VCC D3 PD1 38 37 PD0 VCC Q4 40 39 42 41 VSS PD2 W4 44 43 D4 45 VSS 48 47 W5 50 49 Q5 A19 52 51 A20 VCC A17 54 53 56 55 VSS A18 A15 58 57 A16 59 A14 61 VCC VSS W3 PIN NAMES A0 – A19 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Address Inputs W0 – W7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Write Enables E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Chip Enable D0 – D7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data Inputs Q0 – Q7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data Outputs PD0 – PD2 . . . . . . . . . . . . . . . . . . . . . . . . . Package Density DAISY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pins Single Net VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . + 5 V Power Supply VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ground For proper operation of the device, VSS must be connected to ground. VCC D5 A21 46 VSS A13 60 Q6 64 63 A12 W6 66 65 D6 VCC D7 68 67 69 VSS W7 E 72 71 Q7 62 70 This document contains information on a new product. Specifications and information herein are subject to change without notice. 10/30/96 Motorola, Inc. 1996 MOTOROLA FAST SRAM MCM8A10 1 FUNCTIONAL BLOCK DIAGRAM 1M x 8 MEMORY MODULE A0 – A19 A0 – A19 A0 – A19 A0 – A19 A0 – A19 E E E E E W0 W W1 W W2 W W3 W D0 D D1 D D2 D D3 D Q0 Q Q1 Q Q2 Q Q3 Q 1M x 1 1M x 1 1M x 1 1M x 1 A0 – A19 A0 – A19 A0 – A19 A0 – A19 E E E E W4 W W5 W W6 W W7 W D4 D D5 D D6 D D7 D Q4 Q Q5 Q Q6 Q Q7 Q 1M x 1 1M x 1 1M x 1 1M x 1 PD0 — Open PD1 — VSS PD2 — Open MCM8A10 2 MOTOROLA FAST SRAM TRUTH TABLE E W Mode I/O Pin Cycle Current H X Not Selected High–Z — ISB1, ISB2 L H Read Dout Read ICCA L L Write High–Z Write ICCA NOTE: H = High, L = Low, X = Don’t Care ABSOLUTE MAXIMUM RATINGS (See Note) Rating Symbol Value Unit VCC – 0.5 to 7.0 V Vin, Vout – 0.5 to VCC + 0.5 V Output Current Iout ± 20 mA Power Dissipation PD 8.8 W Temperature Under Bias Tbias – 10 to + 85 °C Operating Temperature TA 0 to + 70 °C Tstg – 55 to + 150 °C Power Supply Voltage Relative to VSS Voltage Relative to VSS for Any Pin Except VCC Storage Temperature This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields; however, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to these high–impedance circuits. This CMOS memory circuit has been designed to meet the dc and ac specifications shown in the tables, after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow of at least 500 linear feet per minute is maintained. NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to RECOMMENDED OPERATING CONDITIONS. Exposure to higher than recommended voltages for extended periods of time could affect device reliability. DC OPERATING CONDITIONS AND CHARACTERISTICS (VCC = 5.0 V ± 5%, TA = 0 to 70°C, Unless Otherwise Noted) RECOMMENDED OPERATING CONDITIONS Parameter Symbol Min Max Unit Supply Voltage (Operating Voltage Range) VCC 4.75 5.25 V Input High Voltage VIH 2.2 VCC +0.3** V Input Low Voltage VIL – 0.5* 0.8 V Symbol Min Max Unit Input Leakage Current (All Inputs, Vin = 0 to VCC) Ilkg(I) — ±1 µA Output Leakage Current (E = VIH, Vout = 0 to VCC) Ilkg(O) — ±1 µA AC Active Supply Current (Iout = 0 mA, VCC = max) ICCA — 920 mA AC Standby Current (VCC = max, E = VIH, f ≤ fmax) ISB1 — 320 mA CMOS Standby Current (E ≥ VCC – 0.2 V, Vin ≤ VSS + 0.2 V or ≥ VCC – 0.2 V, VCC = max, f = 0 MHz) ISB2 — 40 mA Output Low Voltage (IOL = + 8.0 mA) VOL — 0.4 V Output High Voltage (IOH = – 4.0 mA) VOH 2.4 — V Symbol Typ Max Unit Cin 42 50 10 58 74 13 pF Cin, Cout 10 13 pF * VIL (min) = – 0.5 V dc; VIL (min) = – 2.0 V ac (pulse width ≤ 20 ns). ** VIH (max) = VCC + 0.3 V dc; VIH (max) = VCC + 2 V ac (pulse width ≤ 20 ns). DC CHARACTERISTICS AND SUPPLY CURRENTS Parameter CAPACITANCE (f = 1.0 MHz, dV = 3.0 V, TA = 25°C, Periodically Sampled Rather Than 100% Tested) Characteristic Input Capacitance Input and Output Capacitance MOTOROLA FAST SRAM Address Inputs E W D, Q MCM8A10 3 AC OPERATING CONDITIONS AND CHARACTERISTICS (VCC = 5.0 V ± 5%, TA = 0 to + 70°C, Unless Otherwise Noted) Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to 3.0 V Input Rise/Fall Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 ns Input Timing Measurement Reference Level . . . . . . . . . . . . . . . 1.5 V Output Timing Measurement Reference Level . . . . . . . . . . . . . 1.5 V Output Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Figure 1a READ CYCLE TIMING (See Notes 1 and 2) MCM8A10–15 P Parameter S b l Symbol Min Max U i Unit N Notes Read Cycle Time tAVAV 15 — ns 2, 3 Address Access Time tAVQV — 15 ns Enable Access Time tELQV — 15 ns Output Hold from Address Change tAXQX 5 — ns Enable Low to Output Active tELQX 5 — ns 5, 6, 7 Enable High to Output High–Z tEHQZ 0 6 ns 5, 6, 7 4 NOTES: 1. W is high for read cycle. 2. Product sensitivities to noise require proper grounding and decoupling of power supplies as well as minimization or elimination of bus contention conditions during read and write cycles. 3. All timings are referenced from the last valid address to the first transitioning address. 4. Addresses valid prior to or coincident with E going low. 5. At any given voltage and temperature, tEHQZ max is less than tELQX min, both for a given device and from device to device. 6. Transition is measured ± 500 mV from steady–state voltage with load of Figure 1b. 7. This parameter is sampled and not 100% tested. 8. Device is continuously selected (E ≤ VIL). TIMING LIMITS +5V RL = 50 Ω OUTPUT 480 Ω OUTPUT 255 Ω Z0 = 50 Ω 5 pF VL = 1.5 V (a) (b) The table of timing values shows either a minimum or a maximum limit for each parameter. Input requirements are specified from the external system point of view. Thus, address setup time is shown as a minimum since the system must supply at least that much time. On the other hand, responses from the memory are specified from the device point of view. Thus, the access time is shown as a maximum since the device never provides data later than that time. Figure 1. AC Test Loads MCM8A10 4 MOTOROLA FAST SRAM READ CYCLE 1 (See Notes 1, 2, and 8) tAVAV A (ADDRESS) tAXQX Q (DATA OUT) PREVIOUS DATA VALID DATA VALID tAVQV READ CYCLE 2 (See Note 4) tAVAV A (ADDRESS) tELQV E (CHIP ENABLE) tEHQZ tELQX Q (DATA OUT) HIGH–Z ICC SUPPLY CURRENT ISB MOTOROLA FAST SRAM DATA VALID tAVQV tELICCH tEHICCL MCM8A10 5 WRITE CYCLE 1 (W Controlled, See Notes 1 and 2) MCM8A10–15 P Parameter S b l Symbol Min Max U i Unit N Notes Write Cycle Time tAVAV 15 — ns 3 Address Setup Time tAVWL 0 — ns Address Valid to End of Write tAVWH 12 — ns Write Pulse Width tWLWH, tWLEH 12 — ns Data Valid to End of Write tDVWH 7 — ns Data Hold TIme tWHDX 0 — ns Write Low to Data High–Z tWLQZ 0 6 ns 4, 5, 6 Write High to Output Active tWHQX 5 — ns 4, 5, 6 Write Recovery Time tWHAX 0 — ns NOTES: 1. A write occurs during the overlap of E low and W low. 2. Product sensitivities to noise require proper grounding and decoupling of power supplies as well as minimization or elimination of bus contention conditions during read and write cycles. 3. All timings are referenced from the last valid address to the first transitioning address. 4. Transition is measured ± 500 mV from steady–state voltage with load of Figure 1b. 5. This parameter is sampled and not 100% tested. 6. At any given voltage and temperature, tWLQZ max is less than tWHQX min both for a given device and from device to device. WRITE CYCLE 1 (W Controlled See Notes 1 and 2) tAVAV A (ADDRESS) tWHAX tAVWH E (CHIP ENABLE) tWLWH tWLEH W (WRITE ENABLE) tAVWL tDVWH D (DATA IN) DATA VALID tWHQX tWLQZ Q (DATA OUT) MCM8A10 6 tWHDX HIGH–Z HIGH–Z MOTOROLA FAST SRAM WRITE CYCLE 2 (E Controlled, See Notes 1 and 2) MCM8A10–15 P Parameter S b l Symbol Min Max U i Unit N Notes Write Cycle Time tAVAV 15 — ns 3 Address Setup Time tAVEL 0 — ns Address Valid to End of Write tAVEH 12 — ns Enable to End of Write tELEH, tELWH 10 — ns Write Pulse Width tWLEH 12 — ns Data Valid to End of Write tDVEH 7 — ns Data Hold Time tEHDX 0 — ns Write Recovery Time tEHAX 0 — ns 4, 5 NOTES: 1. A write occurs during the overlap of E low and W low. 2. Product sensitivities to noise require proper grounding and decoupling of power supplies as well as minimization or elimination of bus contention conditions during read and write cycles. 3. All timings are referenced from the last valid address to the first transitioning address. 4. If E goes low coincident with or after W goes low, the output will remain in a high–impedance state. 5. If E goes high coincident with or before W goes high, the output will remain in a high–impedance state. WRITE CYCLE 2 (E Controlled See Notes 1 and 2) tAVAV A (ADDRESS) tAVEH tELEH E (CHIP ENABLE) tAVEL tELWH tEHAX tWLEH W (WRITE ENABLE) tDVEH D (DATA IN) DATA VALID tEHDX HIGH–Z Q (DATA OUT) ORDERING INFORMATION (Order by Full Part Number) MCM 8A10 XX XX Motorola Memory Prefix Speed (15 = 15 ns) Part Number Package (SG = Gold Pad SIMM) Full Part Number — MCM8A10SG15 MOTOROLA FAST SRAM MCM8A10 7 PACKAGE DIMENSIONS 72–LEAD SIMM CASE TBD Motorola reserves the right to make changes without further notice to any products herein. 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