QL4036 - QuickRAMTM 36,000 Usable PLD Gate QuickRAM ESP Combining Performance, Density, and Embedded RAM QL4036 - QuickRAM DEVICE HIGHLIGHTS Device Highlights High Performance & High Density ■ 36,000 Usable PLD Gates with 204 I/Os ■ 300 MHz 16-bit Counters, 400 MHz Datapaths, 160+ MHz FIFOs ■ 14 RAM Blocks 0.35µm four-layer metal non-volatile CMOS process for smallest die sizes High Speed Embedded SRAM ■ 14 dual-port RAM modules, organized in user-configurable 1,152 bit blocks ■ 5ns access times, each port independently accessible ■ Fast and effecient for FIFO, RAM, and ROM functions Easy to Use / Fast Development Cycles ■ 100% routable with 100% utilization and complete pin-out stability ■ Variable-grain logic cells provide high performance and 100% utilization ■ Comprehensive design tools include high quality Verilog/VHDL synthesis Advanced I/O Capabilities ■ Interfaces with both 3.3V and 5.0V devices ■ PCI compliant with 3.3V and 5.0V busses for -1/-2/-3/-4 speed grades ■ Full JTAG boundary scan ■ Registered I/O cells with individually controlled clocks and output enables } 672 High Speed Logic Cells Interface FIGURE 1. QuickRAM Block Diagram ARCHITECTURE OVERVIEW Architecture Overview The QuickRAM family of ESPs (Embedded Standard Products) offers FPGA logic in combination with DualPort SRAM modules. The QL4036 is a 36,000 usable PLD gate member of the QuickRAM family of ESPs. QuickRAM ESPs are fabricated on a 0.35mm four-layer metal process using QuickLogic’s patented ViaLinkTM technology to provide a unique combination of high performance, high density, low cost, and extreme ease-of-use. The QL4036 contains 672 logic cells and 14 dual port RAM modules (see Figure 1). Each RAM module has 1,152 RAM bits, for a total of 16,128 bits. RAM Modules are Dual Port (one read port, one write port) and can be configured into one of four modes: 64 (deep) x18 (wide), 128x9, 256x4, or 512x2 (see Figure 2). With a maximum of 204 I/Os, the QL4036 is available in 144-pin TQFP, 208-pin PQFP and 256pin PBGA packages. Designers can cascade multiple RAM modules to increase the depth or width allowed in single modules by connecting corresponding address lines together and dividing the words between modules (see Figure 3). This approach allows up to 512-deep configurations as large as 16 bits wide in the smallest QuickRAM device and 44 bits wide in the largest device. 6-31 QL4036 Rev F QL4036 - QuickRAMTM PRODUCT SUMMARY Product Summary Product Summary Total of 204 I/O Pins ■ 196 bi-directional input/output pins, PCI-compliant for 5.0 volt and 3.3 volt buses for -1/-2/-3/-4 speed grades ■ 8 high-drive input/distributed network pins Eight Low-Skew Distributed Networks ■ Two array clock/controlnetworks available to the logic cell flip-flop clock, set and reset inputs - each driven by and input-only pin ■ Six global clock/control networks available to the logic cell F1, clock, set and reset inputs and the input and I/O register clock, reset and enable inputs as well as the output enable control - each driven by an input-only or I/O pin, or any logic cell output or I/O cell feedback FIGURE 2. QuickRAM Module Software support for the complete QuickRAM family, including the QL4016, is available through two basic packages. The turnkey QuickWorksTM package provides the most complete ESP software solution from design entry to logic synthesis, to place and route, to simulation. The QuickToolsTM packages provides a solution for designers who use Cadence, Exemplar, Mentor, Syn-opsys, Synplicity, Viewlogic, Veribest, or other third-party tools for design entry, synthesis, or simulation. High Performance ■ Input + logic cell + output total delays under 6 ns ■ Data path speeds over 400 MHz ■ Counter speeds over 300 MHz ■ FIFO speeds over 160+ MHz The QuickLogic variable grain logic cell features up to 16 simultaneous inputs and 5 outs within a cell that can be fragmented into 5 independent cells. Each cell has a fan-in of 29 including register and control lines (see Figure 4). WDATA WADDR RAM Module (1,152 bits) QS RDATA RADDR A1 A2 A3 A4 A5 A6 AZ OS OP B1 B2 C1 C2 MP MS OZ QZ D1 D2 E1 E2 NP NS NZ F1 F2 F3 F4 F5 F6 RAM Module WDATA (1,152 bits) QC QR RDATA FIGURE 3. QuickRAM Module bits 6-32 32 FZ Preliminary FIGURE 4. Logic Cell QL4036 - QuickRAMTM Pin #109 Pin #1 QuickRAM QL4036-1PF144C Pin #73 Pin #37 144 Pin TQFP Pinout Diagram Pin #157 Pin #1 QuickRAM QL4036-1PQ208C Pin #105 Pin #53 208 Pin PQFP/CQFP Pinout Diagram 6-33 QL4036 - QuickRAMTM 208 PQFP & 144 TQFP PINOUT TABLE 208 PQFP and 144 TQFP Pinout Table 208 144 PQFP TQFP Function 208 144 PQFP TQFP Function 208 144 PQFP TQFP Function 208 144 PQFP TQFP Function Function 1 2 NC 1 I/O I/O 43 44 30 31 GND I/O 85 86 60 61 I/O I/O 127 128 87 88 GND I/O 169 170 117 118 I/O I/O 3 4 2 3 I/O I/O 45 46 NC 32 I/O I/O 87 88 NC 62 I/O I/O 129 130 89 90 GCLK / I ACLK / I 171 172 119 120 I/O I/O 5 6 NC 4 I/O I/O 47 48 NC 33 I/O I/O 89 90 63 NC I/O I/O 131 132 91 92 VCC GCLK / I 173 174 NC NC I/O I/O 7 8 9 10 5 NC 6 7 I/O I/O I/O VCC 49 50 51 52 NC 34 35 36 I/O I/O I/O I/O 91 92 93 94 NC 64 NC 65 I/O I/O I/O I/O 133 134 135 136 93 94 95 NC GCLK / I VCC I/O I/O 175 176 177 178 121 NC 122 123 I/O I/O GND I/O 11 12 13 14 NC NC 8 NC I/O GND I/O I/O 53 54 55 56 37 38 39 NC I/O TDI I/O I/O 95 96 97 98 66 67 NC NC GND I/O VCC I/O 137 138 139 140 96 NC 97 98 I/O I/O I/O I/O 179 180 181 182 124 NC 125 126 I/O I/O I/O GND 15 16 17 18 9 NC 10 11 I/O I/O I/O I/O 57 58 59 60 40 NC NC 41 I/O I/O GND I/O 99 100 101 102 68 69 NC 70 I/O I/O I/O I/O 141 142 143 144 NC 99 NC 100 I/O I/O I/O I/O 183 184 185 186 127 128 129 NC I/O I/O I/O I/O 19 20 21 22 12 13 NC 14 I/O I/O I/O I/O 61 62 63 64 42 43 NC 44 VCC I/O I/O I/O 103 104 105 106 71 72 NC 73 TRSTB TMS I/O I/O 145 146 147 148 NC 101 102 103 VCC I/O GND I/O 187 188 189 190 130 131 132 NC VCCIO I/O I/O I/O 23 24 15 16 GND I/O 65 66 45 NC I/O I/O 107 108 NC 74 I/O I/O 149 150 104 NC I/O I/O 191 192 133 134 I/O I/O 25 26 17 18 GCLK / I ACLK / I 67 68 46 47 I/O I/O 109 110 75 76 I/O I/O 151 152 105 106 I/O I/O 193 194 NC 135 I/O I/O 27 28 19 20 VCC GCLK / I 69 70 48 NC I/O I/O 111 112 77 NC I/O I/O 153 154 NC 107 I/O I/O 195 196 136 NC I/O I/O 29 30 21 22 GCLK / I VCC 71 72 49 NC I/O I/O 113 114 78 79 I/O VCC 155 156 NC 108 I/O I/O 197 198 137 NC I/O I/O 31 32 33 34 23 NC 24 NC I/O I/O I/O I/O 73 74 75 76 50 51 52 NC GND I/O I/O I/O 115 116 117 118 80 NC 81 82 I/O GND I/O I/O 157 158 159 160 109 110 111 NC TCK STM I/O I/O 199 200 201 202 138 139 NC 140 GND I/O VCC I/O 35 36 37 38 25 NC 26 27 I/O I/O I/O I/O 77 78 79 80 53 54 55 56 I/O GND I/O I/O 119 120 121 122 NC 83 NC 84 I/O I/O I/O I/O 161 162 163 164 112 113 NC NC I/O I/O GND I/O 203 204 205 206 NC 141 142 NC I/O I/O I/O I/O 39 40 28 NC I/O I/O 81 82 NC 57 I/O I/O 123 124 85 NC I/O I/O 165 166 114 115 VCC I/O 207 208 143 144 TDO I/O 41 42 NC 29 VCC I/O 83 84 58 59 VCCIO I/O 125 126 86 NC I/O I/O 167 168 116 NC I/O I/O TABLE 1: 208 PQFP and 144 TQFP Pinout Table 6-34 34 208 144 PQFP TQFP Preliminary QL4036 - QuickRAMTM PINOUT DIAGRAM Pinout Diagram QuickRAM QL4036-1PB256C 256 Pin PBGA TOP Pin A1 Corner 20 18 16 14 12 10 8 6 4 19 17 15 13 11 9 7 5 3 2 1 A B C D E F G H J K L M N P R T U V W Y Bottom PBGA 256 Pinout Table 6-35 QL4036 - QuickRAMTM PBGA 256 PINOUT TABLE 256 PBGA Function 256 PBGA Function 256 PBGA Function 256 PBGA Function 256 PBGA Function 256 PBGA Function A1 A2 VSS I/O C4 C5 I/O I/O E19 E20 I/O I/O L2 L3 ACLK / I GCLK / I T17 T18 I/O I/O V20 W1 I/O I/O A3 I/O C6 I/O F1 I/O L4 GCLK / I T19 NC W2 I/O A4 I/O C7 I/O F2 I/O L17 VCC T20 I/O W3 TDI A5 I/O C8 I/O F3 I/O L18 I/O U1 I/O W4 I/O A6 I/O C9 VCCIO F4 VCC L19 I/O U2 I/O W5 I/O A7 I/O C10 I/O F17 VCC L20 I/O U3 I/O W6 I/O A8 A9 I/O I/O C11 C12 I/O I/O F18 F19 NC I/O M1 M2 I/O I/O U4 U5 VSS I/O W7 W8 I/O I/O A10 I/O C13 I/O F20 I/O M3 I/O U6 VCC W9 I/O A11 A12 A13 I/O I/O I/O C14 C15 C16 I/O I/O I/O G1 G2 G3 I/O NC I/O M4 M17 M18 NC NC I/O U7 U8 U9 I/O VSS I/O W10 W11 W12 I/O I/O I/O A14 I/O C17 I/O G4 I/O M19 I/O U10 VCC W13 I/O A15 A16 A17 I/O I/O I/O C18 C19 C20 I/O I/O I/O G17 G18 G19 I/O I/O NC M20 N1 N2 I/O I/O I/O U11 U12 U13 I/O I/O VSS W14 W15 W16 I/O I/O I/O A18 I/O D1 I/O G20 I/O N3 I/O U14 I/O W17 I/O A19 A20 B1 TCK I/O TDO D2 D3 D4 I/O I/O VSS H1 H2 H3 I/O I/O I/O N4 N17 N18 VSS VSS I/O U15 U16 U17 VCC I/O VSS W18 W19 W20 I/O I/O TRSTB B2 I/O D5 I/O H4 VSS N19 I/O U18 I/O Y1 I/O B3 B4 B5 I/O I/O I/O D6 D7 D8 VCC I/O VSS H17 H18 H19 VSS I/O I/O N20 P1 P2 I/O I/O I/O U19 U20 V1 I/O I/O I/O Y2 Y3 Y4 NC I/O I/O B6 I/O D9 I/O H20 I/O P3 I/O V2 NC Y5 I/O B7 B8 B9 I/O I/O I/O D10 D11 D12 I/O VCC I/O J1 J2 J3 I/O I/O NC P4 P17 P18 I/O I/O I/O V3 V4 V5 I/O I/O I/O Y6 Y7 Y8 I/O I/O I/O B10 I/O D13 VSS J4 I/O P19 NC V6 I/O Y9 I/O B11 B12 B13 B14 I/O I/O I/O I/O D14 D15 D16 D17 I/O VCC I/O VSS J17 J18 J19 J20 NC I/O I/O GCLK / I P20 R1 R2 R3 I/O NC I/O I/O V7 V8 V9 V10 I/O I/O I/O I/O Y10 Y11 Y12 Y13 I/O I/O I/O I/O B15 B16 B17 B18 I/O I/O NC STM D18 D19 D20 E1 I/O I/O I/O NC K1 K2 K3 K4 I/O I/O I/O VCC R4 R17 R18 R19 VCC VCC I/O I/O V11 V12 V13 V14 I/O VCCIO I/O I/O Y14 Y15 Y16 Y17 I/O I/O I/O I/O B19 B20 C1 NC I/O I/O E2 E3 E4 I/O I/O I/O K17 K18 K19 GCLK / I ACLK / I GCLK / I R20 T1 T2 I/O NC I/O V15 V16 V17 I/O I/O I/O Y18 Y19 Y20 I/O I/O NC C2 C3 I/O I/O E17 E18 I/O I/O K20 L1 NC GCLK / I T3 T4 I/O NC V18 V19 I/O TMS 6-36 36 Preliminary QL4036 - QuickRAMTM PIN DESCRIPTION Pin Description Pin TDI/RSI Function Test Data In for JTAG / RAM init. Serial Data In TRSTB/RRO Active low Reset for JTAG / RAM init. reset out TMS Test Mode Select for JTAG TCK Test Clock for JTAG TDO/RCO Test data out for JTAG / RAM init. clock out STM Special Test Mode I/ACLK Can be configured as either or both. I High-drive input and/or array network driver High-drive input and/or global network driver High-drive input I/O Input/Output pin Can be configured as an input and/or output. VCC Power supply pin Connect to 3.3V supply. VCCIO Input voltage tolerance pin GND Ground pin Connect to 5.0 volt supply if 5 volt input tolerance is required, otherwise connect to 3.3V supply. Connect to ground. GND/THERM Ground/Thermal pin I/GCLK Description Hold HIGH during normal operation. Connects to serial PROM data in for RAM initialization. Connect to VCC if unused. Hold LOW during normal operation. Connects to serial PROM reset for RAM initialization. Connect to GND if unused. Hold HIGH during normal operation. Connect to VCC if not used for JTAG. Hold HIGH or LOW during normal operation. Connect to VCC or ground if not used for JTAG. Connect to serial PROM clock for RAM initialization. Must be left unconnected if not used for JTAG or RAM initialization. Must be grounded during normal operation. Can be configured as either or both. Use for input signals with high fanout. Available on 456-PBGA only. Connect to ground plane on PCB if heat sinking desired. Otherwise may be left unconnected. Ordering Information QL 4036 - 1 PQ208 C QuickLogic device QuickRAM device part number Speed Grade 0 = quick 1 = fast 2 = faster 3 = faster *4 = wow Operating Range C = Commercial I = Industrial M = Military Package Code PF144 = 144-pin TQFP CF208 = 208-pin CQFP PQ208 = 208-pin PQFP PB256 = 256-pin PBGA * Contact QuickLogic regarding availability. 6-37 QL4036 - QuickRAMTM Absolute Maximum Ratings VCC Voltage..................................-0.5 to 4.6V VCCIO Voltage ...................................-0.5 to 7.0V Input Voltage ......................... -0.5 to VCCIO+0.5V Latch-up Immunity .................................. ±200mA DC Input Current.................................. ±20 mA ESD Pad Protection .............................. ±2000V Storage Temperature .............. -65°C to +150°C Lead Temperature ........................... .......300°C Operating Range Symbol Parameter VCC VCCIO TA TC Supply Voltage I/O Input Tolerance Voltage Ambient Temperature Case Temperature -0 Speed Grade Delay Factor -1 Speed Grade -2 Speed Grade -3 Speed Grade -4 Speed Grade K Military Min Max 3.0 3.6 3.0 5.5 -55 125 0.42 2.03 0.42 1.64 0.42 1.37 N/A N/A N/A N/A Industrial Min Max 3.0 3.6 3.0 5.5 -40 85 Commercial Min Max 3.0 3.6 3.0 5.25 0 70 0.43 0.43 0.43 0.43 0.43 0.46 0.46 0.46 0.46 0.46 1.90 1.54 1.28 0.90 0.82 Unit V V °C °C 1.85 1.50 1.25 0.88 0.80 DC Characteristics Symbol VIH VIL VOH Parameter Input HIGH Voltage Input LOW Voltage Output HIGH Voltage Conditions VOL Output LOW Voltage II IOZ CI IOS I or I/O Input Leakage Current 3-State Output Leakage Current Input Capacitance [2] Output Short Circuit Current [3] ICC ICCIO D.C. Supply Current [4] D.C. Supply Current on VCCIO Min Max Unit 0.5VCC VCCIO+0.5 V -0.5 0.3VCC V IOH = -12 mA 2.4 V 0.9VCC V IOH = -500 µA IOL = 16 mA [1] 0.45 V IOL = 1.5 mA 0.1VCC V VI = VCCIO or GND -10 10 µA VI = VCCIO or GND -10 10 µA 10 pF VO = GND -15 -180 mA VO = VCC 40 210 mA VI, VIO = VCCIO or GND 0.50 (typ) 2 mA 0 100 µA Notes: [1] Applies only to -1/-2/-3/-4 commercial grade devices. These speed grades are also PCI-compliant. All other devices have 8 mA IOL specifications. [2]Capacitance is sample tested only. Clock pins are 12 pF maximum. [3]Only one output at a time. Duration should not exceed 30 seconds. [4]For -1/-2/-3/-4 commercial grade devices only. Maximum ICC is 3 mA for -0 commercial grade and all industrial grade devices, and 5 mA for all military grade devices. For AC conditions, contact QuickLogic customer engineering. 6-38 38 Preliminary QL4036 - QuickRAMTM AC CHARACTERISTICS at VCC = 3.3V, TA = 25°C (K = 1.00) (To calculate delays, multiply the appropriate K factor in the "Operating Range" section by the following numbers.) Logic Cells Symbol tPD tSU tH tCLK tCWHI tCWLO tSET tRESET tSW tRW Parameter Combinatorial Delay [6] Setup Time [6] Hold Time Clock to Q Delay Clock High Time Clock Low Time Set Delay Reset Delay Set Width Reset Width 1 1.4 1.7 0.0 0.7 1.2 1.2 1.0 0.8 1.9 1.8 Propagation Delays (ns) Fanout [5] 2 3 4 1.7 1.9 2.2 1.7 1.7 1.7 0.0 0.0 0.0 1.0 1.2 1.5 1.2 1.2 1.2 1.2 1.2 1.2 1.3 1.5 1.8 1.1 1.3 1.6 1.9 1.9 1.9 1.8 1.8 1.8 8 3.2 1.7 0.0 2.5 1.2 1.2 2.8 2.6 1.9 1.8 RAM Cell Synchronous Write Timing Symbol TSWA THWA TSWD THWD TSWE THWE TWCRD Parameter WA Setup Time to WCLK WA Hold Time to WCLK WD Setup Time to WCLK WD Hold Time to WCLK WE Setup Time to WCLK WE Hold Time to WCLK WCLK to RD (WA=RA) [5] 1 1.0 0.0 1.0 0.0 1.0 0.0 5.0 Propagation Delays (ns) Fanout 2 3 4 1.0 1.0 1.0 0.0 0.0 0.0 1.0 1.0 1.0 0.0 0.0 0.0 1.0 1.0 1.0 0.0 0.0 0.0 5.3 5.6 5.9 8 1.0 0.0 1.0 0.0 1.0 0.0 7.1 Notes: [5]Stated timing for worst case Propagation Delay over process variation at VCC=3.3V and TA=25°C. Multiply by the appropriate Delay Factor, K, for speed grade, voltage and temperature settings as specified in the Operating Range. [6]These limits are derived from a representative selection of the slowest paths through the QuickRAM logic cell including typical net delays. Worst case delay values for specific paths should be determined from timing analysis of your particular design. 6-39 QL4036 - QuickRAMTM RAM Cell Synchronous Read Timing Symbol TSRA THRA TSRE THRE TRCRD Propagation Delays (ns) Fanout 2 3 4 1.0 1.0 1.0 0.0 0.0 0.0 1.0 1.0 1.0 0.0 0.0 0.0 4.3 4.6 4.9 Parameter 1 1.0 0.0 1.0 0.0 4.0 RA Setup Time to RCLK RA Hold Time to RCLK RE Setup Time to RCLK RE Hold Time to RCLK RCLK to RD [5] 8 1.0 0.0 1.0 0.0 6.1 RAM Cell Asynchronous Read Timing Symbol RPDRD Propagation Delays (ns) Fanout 2 3 4 3.3 3.6 3.9 Parameter 1 3.0 RA to RD [5] 8 5.1 Input-Only/Clock Cells Symbol Propagation Delays (ns) Fanout [5] Parameter 1 2 3 4 8 12 24 TIN TINI TISU TIH TlCLK TlRST TlESU High Drive Input Delay High Drive Input, Inverting Delay Input Register Set-Up Time Input Register Hold Time Input Register Clock To Q Input Register Reset Delay Input Register Clock Enable Setup Time 1.5 1.6 3.1 0.0 0.7 0.6 2.3 1.6 1.7 3.1 0.0 0.8 0.7 2.3 1.8 1.9 3.1 0.0 1.0 0.9 2.3 1.9 2.0 3.1 0.0 1.1 1.0 2.3 2.4 2.5 3.1 0.0 1.6 1.5 2.3 2.9 3.0 3.1 0.0 2.1 2.0 2.3 4.4 4.5 3.1 0.0 3.6 3.5 2.3 TlEH Input Register Clock Enable Hold Time 0.0 0.0 0.0 0.0 0.0 0.0 0.0 Clock Cells Symbol tACK tGCKP tGCKB Parameter Array Clock Delay Global Clock Pin Delay Global Clock Buffer Delay 1 1.2 0.7 0.8 Propagation Delays (ns) Loads per Half Column [7] 2 3 4 8 10 1.2 1.3 1.3 1.5 1.6 0.7 0.7 0.7 0.7 0.7 0.8 0.9 0.9 1.1 1.2 11 1.7 0.7 1.3 Notes: [7]The array distributed networks consist of 40 half columns and the global distributed networks consist of 44 half columns, each driven by an independent buffer. The number of half columns used does not affect clock buffer delay. The array clock has up to 8 loads per half column. The global clock has up to 11 loads per half column. 6-40 40 Preliminary QL4036 - QuickRAMTM I/O Cell Input Delays Symbol tI/O TISU TIH TlOCLK TlORST TlESU TlEH Propagation Delays (ns) Fanout [5] Parameter Input Delay (bidirectional pad) Input Register Set-Up Time Input Register Hold Time Input Register Clock To Q Input Register Reset Delay Input Register clock Enable Set-Up Time Input Register Clock Enable Hold Time 1 2 3 4 8 10 1.3 3.1 0.0 0.7 0.6 2.3 0.0 1.6 3.1 0.0 1.0 0.9 2.3 0.0 1.8 3.1 0.0 1.2 1.1 2.3 0.0 2.1 3.1 0.0 1.5 1.4 2.3 0.0 3.1 3.1 0.0 2.5 2.4 2.3 0.0 3.6 3.1 0.0 3.0 2.9 2.3 0.0 I/O Cell Output Delays Symbol TOUTLH TOUTHL TPZH TPZL TPHZ TPLZ Propagation Delays (ns) Output Load Capacitance (pF) Parameter Output Delay Low to High Output Delay High to Low Output Delay Tri-state to High Output Delay Tri-state to Low Output Delay High to Tri-State [8] Output Delay Low to Tri-State [8] 30 50 75 100 150 2.1 2.2 1.2 1.6 2.0 1.2 2.5 2.6 1.7 2.0 3.1 3.2 2.2 2.6 3.6 3.7 2.8 3.1 4.7 4.8 3.9 4.2 Notes: [8]The following loads are used for tPXZ tPHZ 1KΩ 5 pF 1KΩ tPLZ 5 pF 6-41 QL4036 - QuickRAMTM This page is intentionally blank. 6-42 42 Preliminary