QL3025 - pASIC 3 FPGATM 25,000 Usable PLD Gate pASIC 3 FPGA Combining High Performance and High Density QL3025 - pASIC 3 FPGA DEVICE HIGHLIGHTS Device Highlights Device Highlights High Performance & High Density ■ 25,000 Usable PLD Gates with 204 I/Os ■ 16-bit counter speeds over 300 MHz, data path speeds over 400 MHz ■ 0.35um four-layer metal non-volatile CMOS process for smallest die sizes Easy to Use / Fast Development Cycles ■ 100% routable with 100% utilization and complete pin-out stability ■ Variable-grain logic cells provide high performance and 100% utilization ■ Comprehensive design tools include high quality Verilog/VHDL synthesis FIGURE 1. 672 Logic Cells Advanced I/O Capabilites ■ Interfaces with both 3.3 volt and 5.0 volt devices ■ PCI compliant with 3.3V and 5.0V buses for -1/-2/-3/-4 speed grades ■ Full JTAG boundary scan ■ Registered I/O cells with individually controlled clocks and output enables Total of 204 I/O Pins ■ 196 bidirectional input/output pins, PCI-compliant for 5.0 volt and 3.3 volt buses for -1/-2/-3/-4 speed grades ■ 4 high-drive input-only pins PRODUCT SUMMARY Product Summary The QL3025 is a 25,000 usable PLD gate member of the pASIC 3 family of FPGAs. pASIC 3 FPGAs are fabricated on a 0.35mm four-layer metal process using QuickLogic’s patented ViaLink technology to provide a unique combination of high performance, high density, low cost, and extreme ease-of-use. ■ 4 high-drive input/distributed network pins Four Low-Skew Distributed Networks ■ Two array clock/control networks available to the logic cell flip- flop clock, set and reset inputs - each driven by an input-only pin ■ Six global clock/control networks available to the logic cell F1, clock set and reset inputs and the input and I/O register clock, reset and enable inputs as well as the output enable control - each driven by an input-only or I/O pin, or any logic cell output or I/O cell feedback High Performance ■ Input + logic cell + output total delays under 6 ns ■ Data path speeds over 400 MHz ■ Counter speeds over 300 MHz QL3025 Rev C The QL3025 contains 672 logic cells. With a maximum of 204 I/Os, the QL3025 is available in 144-pin TQFP, 208-PQFP, and 256-pin PBGA packages. Software support for the complete pASIC 3 family, including the QL3025, is available through three basic packages. The turnkey QuickWorks“ package provides the most complete FPGA software solution from design entry to logic synthesis, to place and route, to simulation. The QuickToolsTM for Workstations package provides a solution for designers who use Cadence, Exemplar, Mentor, Synopsys, Synplicity, Viewlogic, Veribest, or other third-party tools for design entry, synthesis, or simulation. 7-27 QL3025 - pASIC 3 FPGATM QL3025 PASIC P PINOUT INOUT D DIAGRAM IAGRAMS QL3025 Pinout Diagrams Pin #109 Pin #1 pASIC QL3025-1PF144C Pin #73 Pin #37 FIGURE 2. 144-Pin TQFP pASIC Pinout Table Pin #157 Pin #1 pASIC QL3025-1PQ208C Pin #53 Pin #105 FIGURE 3. 208-Pin PQFP 7-28 28 Preliminary QL3025 - pASIC 3 FPGATM 144 TQFP & 208 PQFP PINOUT TABLE 144 TQFP & 208 PQFP Pinout Table 208 144 PQFP TQFP Function 208 144 PQFP TQFP Function 208 144 PQFP TQFP Function 208 144 PQFP TQFP Function 208 144 PQFP TQFP Function 1 2 NC 1 I/O I/O 43 44 30 31 GND I/O 85 86 60 61 I/O I/O 127 128 87 88 GND I/O 169 170 117 118 I/O I/O 3 4 2 3 I/O I/O 45 46 NC 32 I/O I/O 87 88 NC 62 I/O I/O 129 130 89 90 I ACLK / I 171 172 119 120 I/O I/O 5 NC I/O 47 NC I/O 89 63 I/O 131 91 VCC 173 NC I/O 6 4 I/O 48 33 I/O 90 NC I/O 132 92 I 174 NC I/O 7 8 5 NC I/O I/O 49 50 NC 34 I/O I/O 91 92 NC 64 I/O I/O 133 134 93 94 GCLK / I VCC 175 176 121 NC I/O I/O 9 10 6 7 I/O VCC 51 52 35 36 I/O I/O 93 94 NC 65 I/O I/O 135 136 95 NC I/O I/O 177 178 122 123 GND I/O 11 12 NC NC I/O GND 53 54 37 38 I/O TDI 95 96 66 67 GND I/O 137 138 96 NC I/O I/O 179 180 124 NC I/O I/O 13 14 8 NC I/O I/O 55 56 39 NC I/O I/O 97 98 NC NC VCC I/O 139 140 97 98 I/O I/O 181 182 125 126 I/O GND 15 16 17 18 9 NC 10 11 I/O I/O I/O I/O 57 58 59 60 40 NC NC 41 I/O I/O GND I/O 99 100 101 102 68 69 NC 70 I/O I/O I/O I/O 141 142 143 144 NC 99 NC 100 I/O I/O I/O I/O 183 184 185 186 127 128 129 NC I/O I/O I/O I/O 19 20 21 22 12 13 NC 14 I/O I/O I/O I/O 61 62 63 64 42 43 NC 44 VCC I/O I/O I/O 103 104 105 106 71 72 NC 73 TRSTB TMS I/O I/O 145 146 147 148 NC 101 102 103 VCC I/O GND I/O 187 188 189 190 130 131 132 NC VCCIO I/O I/O I/O 23 24 25 26 15 16 17 18 GND I/O I ACLK / I 65 66 67 68 45 NC 46 47 I/O I/O I/O I/O 107 108 109 110 NC 74 75 76 I/O I/O I/O I/O 149 150 151 152 104 NC 105 106 I/O I/O I/O I/O 191 192 193 194 133 134 NC 135 I/O I/O I/O I/O 27 28 29 30 19 20 21 22 VCC I GCLK / I VCC 69 70 71 72 48 NC 49 NC I/O I/O I/O I/O 111 112 113 114 77 NC 78 79 I/O I/O I/O VCC 153 154 155 156 NC 107 NC 108 I/O I/O I/O I/O 195 196 197 198 136 NC 137 NC I/O I/O I/O I/O 31 32 33 34 23 NC 24 NC I/O I/O I/O I/O 73 74 75 76 50 51 52 NC GND I/O I/O I/O 115 116 117 118 80 NC 81 82 I/O GND I/O I/O 157 158 159 160 109 110 111 NC TCK STM I/O I/O 199 200 201 202 138 139 NC 140 GND I/O VCC I/O 35 36 37 38 25 NC 26 27 I/O I/O I/O I/O 77 78 79 80 53 54 55 56 I/O GND I/O I/O 119 120 121 122 NC 83 NC 84 I/O I/O I/O I/O 161 162 163 164 112 113 NC NC I/O I/O GND I/O 203 204 205 206 NC 141 142 NC I/O I/O I/O I/O 39 40 28 NC I/O I/O 81 82 NC 57 I/O I/O 123 124 85 NC I/O I/O 165 166 114 115 VCC I/O 207 208 143 144 TDO I/O 41 42 NC 29 VCC I/O 83 84 58 59 VCCIO I/O 125 126 86 NC I/O I/O 167 168 116 NC I/O I/O 7-29 QL3025 - pASIC 3 FPGATM 256-PIN PBGA PINOUT DIAGRAM 256-Pin PBGA Pinout Diagram pASIC QL3025-1PB256C TOP Pin A1 Corner 20 18 16 14 12 10 8 6 4 19 17 15 13 11 9 7 5 3 2 1 A B C D E F G H J K L M N P R T U V W Y BOTTOM 7-30 30 Preliminary QL3025 - pASIC 3 FPGATM PBGA 256 PINOUT TABLE PBGA 256 Pinout Table 256 PBGA Function 256 PBGA Function 256 PBGA Function 256 PBGA Function 256 PBGA Function 256 PBGA Function A1 A2 VSS I/O C4 C5 I/O I/O E19 E20 I/O I/O L2 L3 ACLK / I I T17 T18 I/O I/O V20 W1 I/O I/O A3 A4 A5 A6 I/O I/O I/O I/O C6 C7 C8 C9 I/O I/O I/O VCCIO F1 F2 F3 F4 I/O I/O I/O VCC L4 L17 L18 L19 GCLK / I VCC I/O I/O T19 T20 U1 U2 NC I/O I/O I/O W2 W3 W4 W5 I/O TDI I/O I/O A7 A8 A9 A10 I/O I/O I/O I/O C10 C11 C12 C13 I/O I/O I/O I/O F17 F18 F19 F20 VCC NC I/O I/O L20 M1 M2 M3 I/O I/O I/O I/O U3 U4 U5 U6 I/O VSS I/O VCC W6 W7 W8 W9 I/O I/O I/O I/O A11 A12 A13 A14 I/O I/O I/O I/O C14 C15 C16 C17 I/O I/O I/O I/O G1 G2 G3 G4 I/O NC I/O I/O M4 M17 M18 M19 NC NC I/O I/O U7 U8 U9 U10 I/O VSS I/O VCC W10 W11 W12 W13 I/O I/O I/O I/O A15 A16 A17 A18 I/O I/O I/O I/O C18 C19 C20 D1 I/O I/O I/O I/O G17 G18 G19 G20 I/O I/O NC I/O M20 N1 N2 N3 I/O I/O I/O I/O U11 U12 U13 U14 I/O I/O VSS I/O W14 W15 W16 W17 I/O I/O I/O I/O A19 A20 TCK I/O D2 D3 I/O I/O H1 H2 I/O I/O N4 N17 VSS VSS U15 U16 VCC I/O W18 W19 I/O I/O B1 B2 TDO I/O D4 D5 VSS I/O H3 H4 I/O VSS N18 N19 I/O I/O U17 U18 VSS I/O W20 Y1 TRSTB I/O B3 B4 B5 B6 I/O I/O I/O I/O D6 D7 D8 D9 VCC I/O VSS I/O H17 H18 H19 H20 VSS I/O I/O I/O N20 P1 P2 P3 I/O I/O I/O I/O U19 U20 V1 V2 I/O I/O I/O NC Y2 Y3 Y4 Y5 NC I/O I/O I/O B7 B8 B9 B10 I/O I/O I/O I/O D10 D11 D12 D13 I/O VCC I/O VSS J1 J2 J3 J4 I/O I/O NC I/O P4 P17 P18 P19 I/O I/O I/O NC V3 V4 V5 V6 I/O I/O I/O I/O Y6 Y7 Y8 Y9 I/O I/O I/O I/O B11 B12 B13 B14 I/O I/O I/O I/O D14 D15 D16 D17 I/O VCC I/O VSS J17 J18 J19 J20 NC I/O I/O GCLK / I P20 R1 R2 R3 I/O NC I/O I/O V7 V8 V9 V10 I/O I/O I/O I/O Y10 Y11 Y12 Y13 I/O I/O I/O I/O B15 B16 B17 B18 I/O I/O NC STM D18 D19 D20 E1 I/O I/O I/O NC K1 K2 K3 K4 I/O I/O I/O VCC R4 R17 R18 R19 VCC VCC I/O I/O V11 V12 V13 V14 I/O VCCIO I/O I/O Y14 Y15 Y16 Y17 I/O I/O I/O I/O B19 B20 C1 NC I/O I/O E2 E3 E4 I/O I/O I/O K17 K18 K19 I ACLK / I I R20 T1 T2 I/O NC I/O V15 V16 V17 I/O I/O I/O Y18 Y19 Y20 I/O I/O NC C2 C3 I/O I/O E17 E18 I/O I/O K20 L1 NC I T3 T4 I/O NC V18 V19 I/O TMS 7-31 QL3025 - pASIC 3 FPGATM Pin Descriptions PIN DESCRIPTIONS Pin Descriptions Pin TDI Function Test Data In for JTAG TRSTB Active low Reset for JTAG TMS Test Mode Select for JTAG TCK Test Clock for JTAG TDO Test data out for JTAG STM Special Test Mode I/ACLK I High-drive input and/or array network driver High-drive input and/or global network driver High-drive input I/O Input/Output pin Can be configured as an input and/or output. VCC Power supply pin Connect to 3.3V supply. VCCIO Input voltage tolerance pin GND Ground pin Connect to 5.0 volt supply if 5 volt input tolerance is required, otherwise connect to 3.3V supply. Connect to ground. I/GCLK Description Hold HIGH during normal operation. Connect to VCC if not used for JTAG. Hold LOW during normal operation. Connect to ground if not used for JTAG. Hold HIGH during normal operation. Connect to VCC if not used for JTAG. Hold HIGH or LOW during normal operation. Connect to VCC or ground if not used for JTAG. Output that must be left unconnected if not used for JTAG. Must be grounded during normal operation. Can be configured as either or both. Can be configured as either or both. Use for input signals with high fanout. Ordering Information QL 3025 - 1 PQ208 C QuickLogic pASIC device Operating Range C = Commercial I = Industrial M = Military pASIC 3 device part number Package Code PF144 = 144-pin TQFP PQ208 = 208-pin PQFP PB256 = 256-pin PBGA Speed Grade 0 = quick 1 = fast 2 = faster 3 = faster *4 = fastest * Contact QuickLogic regarding availability 7-32 32 Preliminary QL3025 - pASIC 3 FPGATM Absolute Maximum Ratings VCC Voltage . . . . . . . . . . . . . . . . . . . -0.5 to 4.6V DC Input Current . . . . . . . . . . . . . . . . . . . ±20 mA VCCIO Voltage . . . . . . . . . . . . . . . . . -0.5 to 7.0V ESD Pad Protection . . . . . . . . . . . . . . . . . ±2000V Input Voltage . . . . . . . . . . . . -0.5 to VCCIO +0.5V Storage Temperature . . . . . . . . . -65°C to +150°C Latch-up Immunity . . . . . . . . . . . . . . . . . ±200 mA Lead Temperature . . . . . . . . . . . . . . . . . . . 300°C Operating Range Symbol Parameter VCC VCCIO TA TC Supply Voltage I/O Input Tolerance Voltage Ambient Temperature Case Temperature -0 Speed Grade Delay Factor -1 Speed Grade -2 Speed Grade -3 Speed Grade -4 Speed Grade K Military Min Max 3.0 3.6 3.0 5.5 -55 125 0.42 0.42 N/A N/A 1.64 1.37 N/A N/A Industrial Min Max 3.0 3.6 3.0 5.5 -40 85 Commercial Min Max 3.0 3.6 3.0 5.25 0 70 0.43 0.43 0.43 0.43 0.43 0.46 0.46 0.46 0.46 0.46 1.90 1.54 1.28 0.90 0.82 Unit V V °C °C 1.85 1.50 1.25 0.88 0.80 DC Characteristics Symbol VIH VIL VOH Parameter Input HIGH Voltage Input LOW Voltage Output HIGH Voltage VOL Output LOW Voltage II IOZ CI IOS I or I/O Input Leakage Current 3-State Output Leakage Current Input Capacitance [2] Output Short Circuit Current [3] ICC ICCIO D.C. Supply Current [4] D.C. Supply Current on VCCIO Conditions Min Max Unit 0.5VCC VCCIO+0.5 V -0.5 0.3VCC V IOH = -12 mA 2.4 V 0.9VCC V IOH = -500 µA IOL = 16 mA [1] 0.45 V IOL = 1.5 mA 0.1VCC V VI = VCCIO or GND -10 10 µA VI = VCCIO or GND -10 10 µA 10 pF VO = GND -15 -180 mA VO = VCC 40 210 mA VI, VIO = VCCIO or GND 0.50 (typ) 2 mA 0 100 µA Notes: [1] Applies only to -1/-2/-3/-4 commercial grade devices. These speed grades are also PCI-compliant. All other devices have 8 mA IOL specifications. [2] Capacitance is sample tested only. Clock pins are 12 pF maximum. [3] Only one output at a time. Duration should not exceed 30 seconds. [4] For -1/-2/-3/-4 commercial grade devices only. Maximum ICC is 3 mA for -0 commercial grade and all industrial grade devices, and 5 mA for all military grade devices. For AC conditions, contact QuickLogic customer engineering. 7-33 QL3025 - pASIC 3 FPGATM AC Characteristics at VCC = 3.3V, TA = 25°C (K = 1.00) (To calculate delays, multiply the appropriate K factor in the "Operating Range" section by the following numbers.) Logic Cells Symbol tPD tSU tH tCLK tCWHI tCWLO tSET tRESET tSW tRW Propagation Delays (ns) Fanout [5] 2 3 4 1.7 1.9 2.2 1.7 1.7 1.7 0.0 0.0 0.0 1.0 1.2 1.5 1.2 1.2 1.2 1.2 1.2 1.2 1.3 1.5 1.8 1.1 1.3 1.6 1.9 1.9 1.9 1.8 1.8 1.8 Parameter Combinatorial Delay [6] Setup Time [6] Hold Time Clock to Q Delay Clock High Time Clock Low Time Set Delay Reset Delay Set Width Reset Width 1 1.4 1.7 0.0 0.7 1.2 1.2 1.0 0.8 1.9 1.8 8 3.2 1.7 0.0 2.5 1.2 1.2 2.8 2.6 1.9 1.8 Input-Only/Clock Cells Symbol tIN tINI tISU tIH tlCLK tlRST tlESU tlEH Parameter High Drive Input Delay High Drive Input, Inverting Delay Input Register Set-Up Time Input Register Hold Time Input Register Clock To Q Input Register Reset Delay Input Register clock Enable Set-Up Time Input Register Clock Enable Hold Time 1 1.5 1.6 3.1 0.0 0.7 0.6 2.3 0.0 Propagation Delays (ns) Fanout [5] 2 3 4 8 12 1.6 1.8 1.9 2.4 2.9 1.7 1.9 2.0 2.5 3.0 3.1 3.1 3.1 3.1 3.1 0.0 0.0 0.0 0.0 0.0 0.8 1.0 1.1 1.6 2.1 0.7 0.9 1.0 1.5 2.0 2.3 2.3 2.3 2.3 2.3 0.0 0.0 0.0 0.0 0.0 24 4.4 4.5 3.1 0.0 3.6 3.5 2.3 0.0 Notes: [5] Stated timing for worst case Propagation Delay over process variation at VCC=3.3V and TA=25°C. Multiply by the appropriate Delay Factor, K, for speed grade, voltage and temperature settings as specified in the Operating Range. [6] These limits are derived from a representative selection of the slowest paths through the pASIC 3 logic cell including typical net delays. Worst case delay values for specific paths should be determined from timing analysis of your particular design. 7-34 34 Preliminary QL3025 - pASIC 3 FPGATM Clock Cells Symbol tACK tGCKP tGCKB Parameter 1 1.2 0.7 0.8 Array Clock Delay Global Clock Pin Delay Global Clock Buffer Delay Propagation Delays (ns) Loads per Half Column [7] 2 3 4 8 10 1.2 1.3 1.3 1.5 1.6 0.7 0.7 0.7 0.7 0.7 0.8 0.9 0.9 1.1 1.2 11 1.7 0.7 1.3 I/O Cells Symbol Parameter tI/O tISU tIH tlOCLK tlORST tlESU tlEH Input Delay (bidirectional pad) Input Register Set-Up Time Input Register Hold Time Input Register Clock To Q Input Register Reset Delay Input Register clock Enable Set-Up Time Input Register Clock Enable Hold Time Symbol Parameter tOUTLH tOUTHL tPZH tPZL tPHZ tPLZ Output Delay Low to High Output Delay High to Low Output Delay Tri-state to High Output Delay Tri-state to Low Output Delay High to Tri-State [8] Output Delay Low to Tri-State [8] 1 1.3 3.1 0.0 0.7 0.6 2.3 0.0 30 2.1 2.2 1.2 1.6 2.0 1.2 Propagation Delays (ns) Fanout [5] 2 3 4 8 1.6 1.8 2.1 3.1 3.1 3.1 3.1 3.1 0.0 0.0 0.0 0.0 1.0 1.2 1.5 2.5 0.9 1.1 1.4 2.4 2.3 2.3 2.3 2.3 0.0 0.0 0.0 0.0 10 3.6 3.1 0.0 3.0 2.9 2.3 0.0 Propagation Delays (ns) Output Load Capacitance (pF) 50 75 100 2.5 3.1 3.6 2.6 3.2 3.7 1.7 2.2 2.8 2.0 2.6 3.1 150 4.7 4.8 3.9 4.2 Notes: [7] The array distributed networks consist of 40 half columns and the global distributed networks consist of 44 half columns, each driven by an independent buffer. The number of half columns used does not affect clock buffer delay. The array clock has up to 8 loads per half column. The global clock has up to 11 loads per half column. [8] The following loads are used for tPXZ: tPHZ 1KΩ 5 pF 1KΩ tPLZ 5 pF 7-35 QL3025 - pASIC 3 FPGATM 7-36 36 Preliminary