3.3V, 2.5Gbps ANY INPUT-to-LVPECL DUAL TRANSLATOR DESCRIPTION FEATURES ■ Input accepts virtually all logic standards • Single-ended: SSTL, TTL, CMOS • Differential: LVDS, HSTL, CML ■ Guaranteed AC parameters over temperature: • fMAX > 2.5Gbps (2.5GHz toggle) • tr / tf < 200ps • Within-device skew < 50ps • Propagation delay < 400ps ■ Low power: 46mW/channel (typ) ■ 3.0V to 3.6V power supply ■ 100K LVPECL outputs ■ Flow-through pinout and fully differential design ■ Two channels in a 10-pin (3mm × 3mm) MSOP package The SY55857L is a fully differential, high-speed dual translator optimized to accept any logic standard from single-ended TTL/CMOS to differential LVDS, HSTL, or CML and translate it to LVPECL. Translation is guaranteed for speeds up to 2.5Gbps (2.5GHz toggle frequency). The SY55857L does not internally terminate its inputs, as different interfacing standards have different termination requirements. PIN CONFIGURATION APPLICATIONS D0 1 10 VCC /D0 2 9 Q0 D1 3 SuperLite™ SY55857L MSOP ■ ■ ■ ■ 8 /Q0 /D1 4 7 Q1 GND 5 6 /Q1 High-speed logic Data communications systems Wireless communications systems Telecom systems FUNCTIONAL BLOCK DIAGRAM D0 Any IN Q0 CH0 /D0 LVPECL OUT /Q0 D1 Q1 Any IN CH1 /D1 LVPECL OUT /Q1 SuperLite is a trademark of Micrel, Inc. Rev.: A 1 Amendment: /3 Issue Date: November 2001 SuperLite™ SY55857L Micrel PIN DESCRIPTIONS Pin Number Pin Name Description D0, /D0 1, 2 Channel 0 differential inputs (clock or data). See Figure 1 for input structure. See “Input Interface” section for typical interface recommendations. D1, /D1 3, 4 Channel 1 differential inputs (clock or data). See Figure 1 for input structure. See “Input Interface” section for typical interface recommendations. Q0, /Q0 9, 8 Channel 0 differential 100k compatible LVPECL outputs. Terminate to VCC – 2V. See “LVPECL Output Termination” section. Outputs are low impedance, emitter-followers. For AC-coupled applications, a pull-down resistor is required on Q and /Q to ensure a DC current path to GND. Q1, /Q1 7, 6 Channel 1 differential 100k compatible LVPECL outputs. Terminate to VCC – 2V. See “LVPECL Output Termination” section. Outputs are low impedance, emitter-followers. For AC-coupled applications, a pull-down resistor is required on Q and /Q to ensure a DC current path to GND. GND 5 Device ground. Typically connected to Logic ground. VCC 10 Supply Voltage. Typically connect to +3.3V ± 10% supply. Bypass with 0.01µF//0.1µF low ESR capacitors. FUNCTIONAL DESCRIPTION Establishing Static Logic Inputs Do not leave unused inputs floating. Tie either the true or complement inputs to ground, but not both. A logic zero is achieved by connecting the complement input to ground with the true input floating. For a TTL input, tie a 2.5kΩ resistor between the complement input and ground. See “Input Interface” section. Input Levels LVDS, CML and HSTL differential signals may be connected directly to the D inputs. Depending on the actual worst case voltage seen, performance of SY55857L varies as per the following table: Input Voltage Range Minimum Voltage Swing Maximum Translation Speed 0 to 2.4V 100mV 2.5Gbps 0 to VCC +0.3 200mV 1.25Gbps VCC R2 1.5k R2 1.5k DIN R1 1.05k /DIN R1 1.05k GND Figure 1. Simplified Input Structure 2 SuperLite™ SY55857L Micrel ABSOLUTE MAXIMUM RATINGS(1) Symbol Rating Value Unit –0.5 to +6.0 V –0.5 to VCC +0.5 V 50 100 mA VCC Power Supply Voltage VIN Input Voltage IOUT Output Current TA Operating Temperature Range –40 to +85 °C Tstore Storage Temperature Range –65 to +150 °C θJA Package Thermal Resistance (Junction-to-Ambient) 113 96 °C/W °C/W θJC Package Thermal Resistance (Junction-to-Case) 42 °C/W –Continuous –Surge –Still-Air –500lfpm NOTE: 1. Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. This is a stress rating only and functional operation is not implied at conditions other than those detailed in the operational sections of this data sheet. Exposure to ABSOLUTE MAXIMUM RATlNG conditions for extended periods may affect device reliability. DC ELECTRICAL CHARACTERISTICS TA = –40°C to +85°C Symbol VCC ICC Parameter Min. Typ. Max. Unit Power Supply Voltage(1) Condition 3.0 3.3 3.6 V Power Supply Current(1) — 28 45 mA Inputs/Outputs Open NOTE: 1. The specifications shown above are valid after thermal equilibrium has been established. INPUT ELECTRICAL CHARACTERISTICS(1) VCC = 3.0V to 3.6V; GND = 0V; TA = –40°C to +85°C Symbol Parameter Min. Typ. Max. Unit Condition VID Differential Input Voltage 100 200 — — — — mV mV VIN < 2.4V VIN < VCC+0.3V VIH Input HIGH Voltage — — VCC+0.3V mV VIL Input LOW Voltage –0.3 — — mV NOTE: 1. The specifications shown above are valid after thermal equilibrium has been established. (100K) LVPECL OUTPUT CHARACTERISTICS(1) VCC = 3.0V to 3.6V; GND = 0V; TA = –40°C to +85°C Symbol Min. Typ. Max. Unit Condition VOL Output LOW Voltage Parameter 1355 1480 1605 mV 50Ω to VCC–2V VOH Output HIGH Voltage 2155 2280 2405 mV 50Ω to VCC–2V VSWING Output Voltage Swing 600 700 — mVpk-pk 50Ω to VCC–2V NOTES: 1. 100K circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been establised. The circuit is in a test socket or mounted on a printed circuit board and traverse airflow greater than 500lfpm is maintained. Input and output parameters are at VCC = 3.3V. They vary 1:1 with VCC. 3 SuperLite™ SY55857L Micrel AC ELECTRICAL CHARACTERISTICS(1) VCC = 3.0V to 3.6V; GND = 0V; TA = –40°C to +85°C Symbol fMAX Parameter Min. Typ. Max. Unit Condition Maximum Frequency NRZ Data Clock(2) 2.5 2.5 — — — — Gbps GHz small signal, VIN < 2.4V NRZ Data Clock(2) 1.25 1.25 — — — — Gbps GHz large signal, VIN < VCC+0.3V tPLH tPHL Propagation Delay (Differential) D0 to Q0, D1 to Q1 — — 400 ps tSKEW(3) Within-Device Skew (Diff.) Part-to-Part Skew (Diff.) — — — — 50 200 ps tJITTER Jitter Generation tr , tf PECL Output Rise/Fall Times (20% to 80%) (rms) <1 — — ps (rms) 200 ps NOTES: 1. Performance is guaranteed as shown in the above table after thermal equilibrium has been established. 2. Clock frequency is defined as the maximum toggle frequency, and guaranteed for functionality only. Measured with a 750mV signal, 50% duty cycle. All loading is with a 50Ω to VCC – 2V. 3. Skew is measured between outputs under identical transitions. PRODUCT ORDERING CODE Ordering Code Package Type Operating Range Package Marking SY55857LKI K10-1 Industrial 857L SY55857LKITR* K10-1 Industrial 857L *Tape and Reel 4 SuperLite™ SY55857L Micrel INPUT INTERFACE VCC(857) ≥ VCC(DRIVER) VCC(DRIVER) VCC(857) ≥ VCC(DRIVER) VCC(DRIVER) TTL LVTTL D D /D SY55857 CML 2.5k 1% 102Ω 1% /D SY55857 Figure 2. CML-DC Coupled Figure 1. 5V, 3.3V "TTL" VCC(857) ≥ VCC(DRIVER) VCC(DRIVER) D 2.3V to 2.7V VCC PECL /D 2.5V LVTTL SY55857 D 51Ω 1% /D SY55857 51Ω 1% 2.5k 1% VCC—2V Figure 3. 2.5V "TTL" Figure 4. PECL-DC Coupled VCC VCC(DRIVER) VCC D CML D HSTL /D 50Ω 102Ω 1% /D SY55857 SY55857 3.92kΩ 1% 50Ω 3.92kΩ 1% Figure 6. CML-AC Coupled - Short lines Figure 5. HSTL 5 SuperLite™ SY55857L Micrel INPUT INTERFACE (CONT.) VCC VCC(DRIVER) 82Ω 1% 82Ω 1% VCC D CML /D VCC SY55857 130Ω 1% 130Ω 1% D LVDS Figure 7. CML-AC Coupled - Long lines 102Ω 1% /D SY55857 Figure 8. LVDS VDDQ VDDQ 105Ω 1% 105Ω 1% 110Ω 1% VCC /D /D 100Ω 1% 100Ω 1% VCC D SSTL_3 D SSTL_2 110Ω 1% SY55857 90.9Ω 1% 90.9Ω 1% Figure 10. SSTL_3 Figure 9. SSTL_2 6 SY55857 SuperLite™ SY55857L Micrel 10 LEAD MSOP (K10-1) Rev. 00 MICREL-SYNERGY TEL + 1 (408) 980-9191 FAX 3250 SCOTT BOULEVARD SANTA CLARA CA 95054 + 1 (408) 914-7878 WEB USA http://www.synergysemi.com http://www.micrel.com This information is believed to be accurate and reliable, however no responsibility is assumed by Micrel for its use nor for any infringement of patents or other rights of third parties resulting from its use. No license is granted by implication or otherwise under any patent or patent right of Micrel Inc. © 2001 Micrel Incorporated 7