SuperLite™ SY55852U D FLIP-FLOP DESCRIPTION FEATURES ■ ■ ■ ■ ■ ■ ■ ■ ■ 2.5GHz min. fMAX 2.3V to 5.7V power supply Single bit register memory Synchronizes 1 bit of data to a clock Optimized to work with SuperLite™ family Fully differential Accepts CML, PECL, LVPECL input logic levels Source terminated CML outputs for fast edge rates Available in a tiny 10-pin MSOP The SY55852U is a flip-flop used to synchronize data to a clock. Its differential output will reproduce and remember the value on its input at the rising edge of the clock. In addition, an asynchronous, level sensitive reset is provided. For a synchonous reset, the SY55851U AnyGate™ can be used. SY55852U inputs can be terminated with a single resistor between the true and complement pins of a given input. The SY55852U is a member of Micrel's SuperLite™ family of high-speed CML logic. This family features very small packaging and 2.3V to 5.7V operation. PIN CONFIGURATION VCC /R 9 10 APPLICATIONS R 8 Q 7 ■ High-speed logic ■ OC-48 communication systems /Q 6 Top View MSOP 1 D 4 5 2 3 /D CLK /CLK GND PIN NAMES FUNCTIONAL BLOCK DIAGRAM Pin DATA D Q OUT CLOCK R RESET Function D, /D CML/PECL/LVPECL Data Input CLK, /CLK CML/PECL/LVPECL Clock Input R, /R CML/PECL/LVPECL Reset Input Q, /Q CML Data Output GND Ground VCC VCC SuperLite is a trademark of Micrel, Inc. Rev.: A 1 Amendment: /0 Issue Date: January 2001 SuperLite™ SY55852U Micrel PIN DESCRIPTIONS D, /D – CML/PECL/LVPECL Input (Differential) This is the single bit of data that gets clocked in and remembered. R, /R – CML/PECL/LVPECL Input (Differential) This is an asynchronous active high level reset, that forces the flip-flop into a known state, namely zero. CLK, /CLK – CML/PECL/LVPECL Input (Differential) The rising edge of this signal is the clock signal that determines when the Boolean value at the data input gets stored. Q, /Q – CML Output (Differential) This is the output of the flip-flop. FUNCTIONAL DESCRIPTION inputs unconnected. For V CC ≤ 3.0V, connect the complement inputs to VCC and leave the true inputs unconnected. To make an input static logic one, connect the true input to V CC , leave the complement input unconnected. These are the only safe ways to cause inputs to be at a static value. In particular, no input pin should be directly connected to ground. All NC (no connect) pins should be unconnected. Establishing Static Logic Inputs The true pin of an input pair is internally biased to ground through a 75kΩ resistor. The complement pin of an input pair is internally biased halfway between VCC and ground by a voltage divider consisting of two 75kΩ resistors. To keep an input at static logic zero at VCC > 3.0V, leave both VCC X NC X NC /X NC /X VCC > 3.0V Figure 1. Hard Wiring a Logic “1” (1) NOTE: 1. X is either D, CLK, R input. /X is either /D, /CLK, /R input. NC X VCC /X VCC ≤ 3.0V TRUTH TABLE Figure 2. Hard Wiring a Logic “0” (1) D CLK R Q /Q X X 1 0 1 X 0 0 QN-1 /QN-1 X 1 0 QN-1 /QN-1 0 0 0 1 1 0 1 0 2 SuperLite™ SY55852U Micrel ABSOLUTE MAXIMUM RATINGS(1) Symbol Rating Value Unit –0.5 to +6.0 V –0.5 to VCC +0.5 V VCC –1.0 to VCC +0.5 V Operating Temperature Range –40 to +85 °C Storage Temperature Range –65 to +150 °C VCC Power Supply Voltage VI Input Voltage VO CML Output Voltage TA Tstore NOTE: 1. Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. This is a stress rating only and functional operation is not implied at conditions other than those detailed in the operational sections of this data sheet. Exposure to ABSOLUTE MAXIMUM RATlNG conditions for extended periods may affect device reliability. CML TERMINATION All inputs accept the output from any other member of this family. All outputs are source terminated 100Ω CML differential drivers as shown in Figures 3 and 4. SY55852U expects the inputs to be terminated, and that good high vcc 100Ω speed design practices be adhered to. SY55852U inputs are designed to accept a termination resistor between the true and complement inputs of a differential pair. 0402 form factor chip resistors will fit with some trace fanout. vcc vcc 100Ω 100Ω 100Ω 50Ω 100Ω 100Ω 100Ω 50Ω 100Ω 100Ω 50Ω 50Ω 50Ω 8mA 8mA SY55852U SY55852U Figure 3a. Differentially Terminated (50Ω Load CML Output) Figure 3b. Individually Terminated (50Ω Load CML Output) VCC 100Ω 100Ω 100Ω 200Ω 100Ω 8mA SY55852U Figure 4. 100Ω Load CML Output 3 50Ω SuperLite™ SY55852U Micrel DC ELECTRICAL CHARACTERISTICS VCC = 2.3V to 5.7V; GND = 0V TA = –40°C Symbol Parameter TA = 0°C TA = +25°C TA = +85°C Min. Max. Min. Max. Min. Max. Min. Max. Unit VCC Power Supply Voltage 2.3 5.7 2.3 5.7 2.3 5.7 2.3 5.7 V ICC Power Supply Current — 36 — 36 — 36 — 36 mA CML DC ELECTRICAL CHARACTERISTICS VCC = 2.3V to 5.7V; GND = 0V; TA = –40°C to +85°C(1) Symbol Parameter Min. Typ. Max. Unit VID Differential Input Voltage 100 — — mV VIH Input HIGH Voltage(5) 1.6 — VCC V VIL Input LOW Voltage(5) 1.5 — VCC – 0.1 V VOH Output HIGH Voltage VCC – 0.020 VCC – 0.010 VCC V No Load VOL Output LOW Voltage VCC – 0.97 VCC – 0.825 VCC – 0.660 V No Load 0.660 0.800 0.400 0.200 0.950 V No Load 100Ω Environment(4) 50Ω Environment(3) 80 100 120 Ω Swing(2) VOS Output Voltage RDRIVE Output Source Impedance Condition NOTES: 1. Equilibrium temperature. 2. Actual voltage levels and differential swing will depend on customer termination scheme. Typically, a 400mV swing is available in the 100Ω environment and a 200mV swing in the 50Ω environment. Refer to the “CML Termination” diagram for more details. 3. See Figure 3a and 3b. 4. See Figure 4. 5. Inputs must be biased to logic LOW or HIGH when VCC is less than 3.0V. AC ELECTRICAL CHARACTERISTICS VCC = 2.3V to 5.7V; GND = 0V; TA = –40°C to +85°C Symbol Parameter Min. Typ. Max. Unit fMAX Max. Operating Frequency 2.5 — — GHz tPLH tPHL Propagation Delay, — — — — 400 500 ps tS Set-Up Time 40 — — ps tH Hold Time 40 — — ps tRR Reset Recovery 400 — — ps tPW Minimum Pulse Width CLK to Q 160 140 250 — — — — — — ps 35 — 150 ps R to Q tr tf CLK to Q R to Q VCC < 3V VCC ≥ 3V CML Output Rise/Fall Times (20% to 80%) NOTE: 1. Tested using environment of Figure 3b, 50Ω load CML output. 4 Condition(1) SuperLite™ SY55852U Micrel TIMING DIAGRAMS CLK tH 50% 50% DATA tS tRR RESET 50% Q 50% tPHL tPLH PRODUCT ORDERING CODE Ordering Code Package Type Operating Range SY55852UKC K10-1 Commercial 5 SuperLite™ SY55852U Micrel 10 LEAD MSOP (K10-1) Rev. 00 MICREL-SYNERGY TEL + 1 (408) 980-9191 FAX 3250 SCOTT BOULEVARD + 1 (408) 914-7878 WEB SANTA CLARA CA 95054 USA http://www.synergysemi.com http://www.micrel.com This information is believed to be accurate and reliable, however no responsibility is assumed by Micrel for its use nor for any infringement of patents or other rights of third parties resulting from its use. No license is granted by implication or otherwise under any patent or patent right of Micrel Inc. © 2001 Micrel Incorporated 6