74ACT299 8 BIT PIPO SHIFT REGISTER WITH ASYNCHRONOUS CLEAR PRELIMINARY DATA ■ ■ ■ ■ ■ ■ ■ ■ ■ HIGH SPEED: fMAX = 170 MHz (TYP.) at VCC = 5V LOW POWER DISSIPATION: ICC = 8 µA (MAX.) at TA = 25 oC COMPATIBLE WITH TTL OUTPUTS VIH = 2V (MIN), VIL = 0.8V (MAX) 50Ω TRANSMISSION LINE DRIVING CAPABILITY SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 24 mA (MIN) BALANCED PROPAGATION DELAYS: tPLH ≅ tPHL OPERATING VOLTAGE RANGE: VCC (OPR) = 4.5V to 5.5V PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 299 IMPROVED LATCH-UP IMMUNITY DESCRIPTION The ACT299 is an high-speed CMOS 8-BIT PIPO SHIFT REGISTERS (3-STATE) fabricated with sub-micron silicon gate and double-layer metal 2 wiring C MOS technology. It is ideal for low power applications mantaining high speed operation similar to equivalent Bipolar Schottky TTL. B M (Plastic Package) (Micro Package) ORDER CODES : 74ACT299B 74ACT299M These devices have four modes (HOLD, SHIFT LEFT, SHIFT RIGHT and LOAD DATA). Each mode is chosen by two function select inputs (S0, S1) as shown in the Truth Table. When one or both enable inputs, (G1, G2) are high, the eight input/output terminals are in the high-impedance state ; however sequential operation or clearing of the register is not affected. Clear function is synchronous to clock. The device is designed to interface directly High Speed CMOS systems with TTL, NMOS and CMOS output voltage levels. All inputs and outputs are equipped with protection circuits against static discharge, giving them 2KV ESD immunity and transient excess voltage. PIN CONNECTION AND IEC LOGIC SYMBOLS April 1999 1/13 74ACT299 INPUT AND OUTPUT EQUIVALENT CIRCUIT PIN DESCRIPTION PIN No 1, 19 SYMBOL S0, S1 NAME AND F UNCTION Mode Select Inputs 3 State Output Enable Inputs (Active LOW) 2, 3 G1, G2 7, 13, 6, 14, 5, 15, 4, 16 A/QA to H/QH 8, 17 QA’ to QH’ 9 CLEAR 11 SR 12 CLOCK Parallel Data Inputs or 3 State Parallel Outputs (Bus Driver) Serial Outputs (Standard Output) Asynchronous Master Reset Input (Active LOW) Serial Data Shift Right Input Clock Input (LOW to HIGH, Edge-triggered) 18 SL 10 GND Serial Data Shift Left Input Ground (0V) 20 VCC Positive Supply Voltage TRUTH TABLE MO DE CLEAR INPUTS F UNCTIO N OUTPUT SELECTED CONTRO L S1 S0 G1* G2* CLO CK INPUTS/OUTPUTS SERIAL A/Q A H/Q H O UT PUT S QA’ QH’ SL SR Z L H H X X X X X Z Z L L CLEAR L L L X X L L L L L X X X X X X L L L L L L L L HOLD SHIFT RIGHT H H L L L H L L L L X X X X H QA0 H QH0 QGn QA0 H QH0 QGn H H L H H L L L L L X H L X L QBn QGn H L QBn QGn H H H H H L H L X L X L X X X QBn a L h QBn a L h SHIFT LEFT LOAD * When one or both output controls are high, the eight, input/output terminals arethe high impedanc e state: howewer sequential operation or clearing of the register is not affected. Z : HIGH IMPEDANCE Qn0 : THE LEVELOF An BEFORE THE INDICATED STEADYSTATEINPUTCONDITIONS WERE ESTABLISED. Qnn : THE LEVELOF Qn BEFORETHE MOST RECENTACTIVETRANSITIONINDICATEDBY OR a,h : THE LEVELOF THE STEADYSTATEINPUTSA, H, RESPECTIVELY. X : DON’T CARE 2/13 74ACT299 LOGIC DIAGRAM 3/13 74ACT299 TIMING CHART 4/13 74ACT299 ABSOLUTE MAXIMUM RATINGS Symbol VCC Parameter Supply Voltage Value Unit -0.5 to +7 V VI DC Input Voltage -0.5 to VCC + 0.5 V VO DC Output Voltage -0.5 to VCC + 0.5 V IIK DC Input Diode Current ± 20 mA IOK DC Output Diode Current ± 20 mA IO DC Output Current ± 50 mA ± 400 mA ICC or IGND DC VCC or Ground Current Tstg Storage Temperature TL Lead Temperature (10 sec) -65 to +150 o 300 o C C Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these condition is not implied. RECOMMENDED OPERATING CONDITIONS Symbol Value Unit Supply Voltage 4.5 to 5.5 V VI Input Voltage 0 to VCC V VO Output Voltage 0 to VCC VCC Top dt/dv Parameter Operating Temperature: Input Rise and Fall Time VCC = 4.5 to 5.5V (note 1) -40 to +85 8 V o C ns/V 1) VIN from 0.8 V to 2.0 V 5/13 74ACT299 DC SPECIFICATIONS Symb ol Parameter Test Co nditions VIH High Level Input Voltage 4.5 5.5 VIL Low Level Input Voltage 4.5 5.5 VOH High Level Output Voltage 4.5 5.5 Low Level Output Voltage VO = 0.1 V or VCC - 0.1 V Min. T yp. 2.0 1.5 2.0 2.0 1.5 2.0 VO = 0.1 V or VCC - 0.1 V V I (* ) = V IH or V IL Un it -40 to 85 o C Max. Min. Max. V 1.5 0.8 0.8 1.5 0.8 0.8 IO=-50 µA 4.4 4.49 4.4 IO=-50 µA 5.4 5.49 5.4 IO=-24 mA 3.86 IO=-24 mA 4.86 4.5 IO=50 µA 0.001 0.1 0.1 IO=50 mA 0.001 0.1 0.1 IO=24 mA 0.36 0.44 IO=24 mA 0.36 0.44 5.5 4.5 5.5 (* ) VI = V IH or V IL V V 5.5 4.5 VOL Valu e T A = 25 oC V CC (V) 3.76 4.76 V Input Leakage Current 5.5 VI = VCC or GND ±0.1 ±1 µA IOZ 3 State Output Leakage Current 5.5 VI = VIH or VIL VO = VCC or GND ±0.5 ±5 µA ICCT Max ICC /Input 5.5 VI = VCC -2.1 V 1.5 mA ICC Quiescent Supply Current 5.5 VI = VCC or GND 80 µA IOLD Dynamic Output Current (note 1, 2) 5.5 VOLD = 1.65 V max 75 mA VOHD = 3.85 V min -75 mA II IOHD 1) Maximum test duration 2ms, one output loaded attime 2) Incident wave switching is guaranteed on transmission lines with impedances as low as 50 Ω. (*) All outputs loaded. 6/13 0.6 8 74ACT299 AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, RL = 500 Ω, Input tr = tf =3 ns) Symb ol Parameter T est Con ditio n V CC (V) tPLH tPHL tPLH tPHL tPHL tPHL tPZL tPZH Propagation Delay Time CLOCK to Q’A, Q’H 5.0(*) Propagation Delay Time CLOCK to QA - QH (*) Propagation Delay Time CLEAR to Q’A, Q’ H Propagation Delay Time CLEAR to QA - QH Output Enable Time Valu e T A = 25 oC -40 to 85 o C Min. T yp. Max. Min. Max. 7.2 10.5 1.0 12.0 5.0 (*) 5.0 (*) 5.0 (*) 5.0 (*) 7.4 11.4 1.0 13.0 6.0 10.0 1.0 11.5 6.3 10.5 1.0 12.0 7.4 11.4 1.0 13.0 7.2 9.6 1.0 11.0 tPLZ tPHZ tw Output Disable Time 5.0 CLEAR pulse Width, LOW 5.0(*) 5.0 5.0 tw CLOCK pulse Width 5.0(*) 5.0 5.0 ts Setup Time HIGH or LOW (S0 or S1 to CK) 5.0(*) 6.0 6.5 (*) th Hold Time HIGH or LOW (S0 or S1 to CK) 5.0 0.0 0.0 ts Setup Time HIGH or LOW (SR or SL to CK) 5.0(*) 3.5 3.5 th Hold Time HIGH or LOW (SR or SL to CK) 5.0(*) 2.0 2.0 tREM Recovery Time CLR to Q 5.0(*) fMAX Maximum Clock Frequency 5.0(*) 2.0 80 120 2.0 80 Un it ns ns ns ns ns ns ns ns ns ns ns ns ns MHz *) Voltage range is 5V ± 0.5V CAPACITIVE CHARACTERISTICS Symb ol Parameter Test Co nditions Valu e T A = 25 oC V CC (V) Min. T yp. Max. 10 C IN Input Capacitance 5.0 5 CI/O Bus Input Capacitance 5.0 13 CPD Power Dissipation Capacitance (note 1) 5.0 fIN = 10 MHz 160 Un it -40 to 85 o C Min. Max. 10 pF pF 1) CPD isdefined as the value of the IC’sinternal equivalent capacitance which is calculated fromthe operating current consumption without load. (Referto 7/13 74ACT299 TEST CIRCUIT T EST tPLH , tPHL SW IT CH Open tPZL , tPLZ 2VCC tPZH , tPHZ Open CL = 50 pF or equivalent (includes jigand probe capacitance) RL = R1 = 500Ω orequivalent RT = ZOUT of pulse generator (typically 50Ω) WAVEFORM 1: PROPAGATION DELAYS (f=1MHz; 50% duty cycle) 8/13 74ACT299 WAVEFORM 2: PROPAGATION DELAYS (f=1MHz; 50% duty cycle) WAVEFORM 3: PROPAGATION DELAYS (f=1MHz; 50% duty cycle) 9/13 74ACT299 WAVEFORM 4: PROPAGATION DELAYS (f=1MHz; 50% duty cycle) 10/13 74ACT299 Plastic DIP-20 (0.25) MECHANICAL DATA mm DIM. MIN. a1 0.254 B 1.39 TYP. inch MAX. MIN. TYP. MAX. 0.010 1.65 0.055 0.065 b 0.45 0.018 b1 0.25 0.010 D 25.4 1.000 E 8.5 0.335 e 2.54 0.100 e3 22.86 0.900 F 7.1 0.280 I 3.93 0.155 L Z 3.3 0.130 1.34 0.053 P001J 11/13 74ACT299 SO-20 MECHANICAL DATA mm DIM. MIN. TYP. A a1 inch MAX. MIN. TYP. 2.65 0.10 0.104 0.20 a2 MAX. 0.004 0.007 2.45 0.096 b 0.35 0.49 0.013 0.019 b1 0.23 0.32 0.009 0.012 C 0.50 0.020 c1 45 (typ.) D 12.60 13.00 0.496 0.512 E 10.00 10.65 0.393 0.419 e 1.27 0.050 e3 11.43 0.450 F 7.40 7.60 0.291 0.299 L 0.50 1.27 0.19 0.050 M S 0.75 0.029 8 (max.) P013L 12/13 74ACT299 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specification mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. 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