Micrel, Inc. SuperLite™ SY55857L SuperLite™ 3.3V, 2.5Gbps ANY INPUT-to-LVPECL DUAL TRANSLATOR SY55857L FEATURES ■ Input accepts virtually all logic standards: • Single-ended: SSTL, TTL, CMOS • Differential: LVDS, HSTL, CML ■ Guaranteed AC parameters over temperature: • fMAX > 2.5Gbps (2.5GHz toggle) • tr / tf < 200ps • Within-device skew < 50ps • Propagation delay < 400ps ■ Low power: 46mW/channel (typ) ■ 3.0V to 3.6V power supply ■ 100K LVPECL outputs ■ Flow-through pinout and fully differential design ■ Two channels in a 10-pin (3mm × 3mm) MSOP package SuperLite™ DESCRIPTION The SY55857L is a fully differential, high-speed dual translator optimized to accept any logic standard from single-ended TTL/CMOS to differential LVDS, HSTL, or CML and translate it to LVPECL. Translation is guaranteed for speeds up to 2.5Gbps (2.5GHz toggle frequency). The SY55857L does not internally terminate its inputs, as different interfacing standards have different termination requirements. All support documentation can be found on Micrel’s web site at www.micrel.com. FUNCTIONAL BLOCK DIAGRAM APPLICATIONS ■ ■ ■ ■ High-speed logic Data communications systems Wireless communications systems Telecom systems D0 Any IN Q0 CH0 /D0 /Q0 Q1 D1 Any IN CH1 /D1 LVPECL OUT LVPECL OUT /Q1 SuperLite is a trademark of Micrel, Inc. M9999-082306 [email protected] or (408) 955-1690 Rev.: E 1 Amendment: /0 Issue Date: August 2006 SuperLite™ SY55857L Micrel, Inc. PACKAGE/ORDERING INFORMATION Ordering Information(1) D0 1 Part Number Package Type Operating Range Package Marking Lead Finish SY55857LKI K10-1 Industrial 857L Sn-Pb 7 Q1 SY55857LKITR(2) K10-1 Industrial 857L Sn-Pb 6 /Q1 SY55857LKG(3) K10-1 Industrial 857L with NiPdAu Pb-Free bar line indicator Pb-Free SY55857LKGTR(2, 3) K10-1 Industrial 857L with NiPdAu Pb-Free bar line indicator Pb-Free 10 VCC /D0 2 9 Q0 D1 3 8 /Q0 /D1 4 GND 5 10-Pin MSOP (K10-1) Notes: 1. Contact factory for die availability. Dice are guaranteed at TA = 25°C, DC Electricals only. 2. Tape and Reel. 3. Pb-Free package recommended for new designs. PIN DESCRIPTIONS Pin Number Pin Name D0, /D0 1, 2 Channel 0 Differential Inputs (clock or data). See Figure 2 for input structure. See “Input Interface” section for typical interface recommendations. D1, /D1 3, 4 Channel 1 Differential Inputs (clock or data). See Figure 2 for input structure. See “Input Interface” section for typical interface recommendations. Q0, /Q0 9, 8 Channel 0 Differential 100k-compatible LVPECL Outputs. Terminate to VCC – 2V. See “LVPECL Output Termination” section. Outputs are low impedance, emitter-followers. For AC-coupled applications, a pull-down resistor is required on Q and /Q to ensure a DC current path to GND. Q1, /Q1 7, 6 Channel 1 Differential 100k-compatible LVPECL Outputs. Terminate to VCC – 2V. See “LVPECL Output Termination” section. Outputs are low impedance, emitter-followers. For AC-coupled applications, a pull-down resistor is required on Q and /Q to ensure a DC current path to GND. GND 5 Device Ground. Typically connected to Logic ground. VCC 10 Supply Voltage. Typically connect to +3.3V ±10% supply. Bypass with 0.01µF0.1µF low ESR capacitors. M9999-082306 [email protected] or (408) 955-1690 Description 2 SuperLite™ SY55857L Micrel, Inc. Absolute Maximum Ratings(1) Operating Ratings(2) Power Supply Voltage (VCC ) ...................... –0.5V to +6.0V Input Voltage (VIN) ............................... –0.5V to VCC +0.5V Output Current (IOUT) Continuous ............................................................. 50mA Surge .................................................................... 100mA Lead Temperature (soldering, 20 sec.) ................... +260°C Storage Temperature Range (TS ) ........... –65°C to +150°C Power Supply Voltage (VCC) ....................... +3.0V to +3.6V Ambient Temperature Range (TA) ............. –40°C to +85°C Package Thermal Resistance(3) MSOP (θJA) Still-Air ........................................................... 113°C/W 500lpfm ............................................................ 96°C/W MSOP (θJC) Junction-to-Case ............................................. 42°C/W DC ELECTRICAL CHARACTERISTICS(4) TA = –40°C to +85°C; unless noted. Symbol Parameter VCC Power Supply Voltage ICC Power Supply Current Condition Min Typ Max Units 3.0 3.3 3.6 V 28 45 mA Inputs/outputs open INPUT ELECTRICAL CHARACTERISTICS(4) VCC = +3.0V to +3.6V; GND = 0V; TA = –40°C to +85°C; unless noted. Symbol Parameter Condition Min VID Input Voltage Swing See Figure 1a, VIN < 2.4V. 100 mV VIN < VCC+0.3V 200 mV VIH Input HIGH Voltage VIL Input LOW Voltage Typ Max VCC+0.3 –0.3 Units V V (100K) LVPECL OUTPUT CHARACTERISTICS(5) VCC = +3.0V to +3.6V; GND = 0V; TA = –40°C to +85°C; RL = 50Ω to VCC –2V, unless otherwise stated. Symbol Parameter Condition Min Typ Max Units VOL Output LOW Voltage Q, /Q VCC–1.945 VCC–1.820 VCC–1.695 V VOH Output HIGH Voltage Q, /Q VCC–1.145 VCC–1.020 VCC–0.895 V VOUT Output Voltage Swing Q, /Q See Figure 1a. 550 800 mV VDIFF_OUT Differential Output Voltage Swing Q, /Q See Figure 1b. 1100 1600 mVpp Notes: 1. Permanent device damage may occur if the ratings in “Absolute Maximum Ratings” section are exceeded. This is a stress rating only and functional operation is not implied at conditions other than those detailed in the operational sections of this data sheet. Exposure to absolute maximum ratings conditions for extended periods may affect device reliability. 2. The data sheet limits are not guaranteed if the device is operated beyond the operating ratings. 3. Package thermal resistance assumes exposed pad is soldered (or equivalent) to the device’s most negative potential (GND) on the PCB. ψJB uses 4-layer θJA in still air unless otherwise stated. 4. The specifications shown are valid after thermal equilibrium has been established. 5. 100K circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. M9999-082306 [email protected] or (408) 955-1690 3 SuperLite™ SY55857L Micrel, Inc. AC ELECTRICAL CHARACTERISTICS VCC = 3.3V ±10%; TA= –40°C to +85°C; RL = 50Ω to VCC –2V, unless otherwise stated. Symbol Parameter Condition fMAX Maximum Operating Frequency Note 6 VIN < 2.4V NRZ Data 2.5 Gbps VIN < 2.4V Clock 2.5 GHz VIN < VCC +0.3V NRZ Data 1.25 Gbps VIN < VCC +0.3V Clock 1.25 GHz tPD Propagation Delay tSKEW Within-Device-Skew (Differential) Part-to-Part Skew (Differential) tJITTER tr, tf Min Typ D-to-Q Max Units 400 ps Note 7 50 ps Note 8 200 ps Note 9 1 psRMS Deterministic Jitter (DJ) Note 10 10 psPP Total Jitter (TJ) Note 11 10 psPP 200 ps Random Jitter (RJ) Output Rise/Fall Time 20% to 80% 1 At full output swing Notes: 6. Clock frequency is defined as the maximum toggle frequency, and guaranteed for functionality only. Measured with a 750mV signal, 50% duty cycle and VOUT swing ≥ 400mV. High -frequency AC-parameters are guaranteed by design and characterization. 7. Within-device skew is measured between two different outputs under identical transitions. 8. Part-to-part skew is defined for two parts with identical power supply voltages at the same temperature and with no skew of the edges at the respective inputs. 9. Random jitter is measured with a K28.7 comma detect character pattern, measured at 2.5Gbps. 10. Deterministic jitter is measured at 2.5Gbps with both K28.5 and 223–1 PRBS pattern. 11. Total jitter definition: with an ideal differential clock input of frequency ≤ fMAX, no more than one output edge in 1012 output edges will deviate by more than the specified peak-to-peak jitter value. SINGLE-ENDED AND DIFFERENTIAL SWINGS VDIFF_IN, VDIFF_OUT 1600mV (Typ.) VID, VOUT 800mV (Typ.) Figure 1a. Single-Ended Voltage Swing M9999-082306 [email protected] or (408) 955-1690 Figure 1b. Differential Voltage Swing 4 SuperLite™ SY55857L Micrel, Inc. FUNCTIONAL DESCRIPTION Establishing Static Logic Inputs Do not leave unused inputs floating. Tie either the true or complement inputs to ground, but not both. A logic zero is achieved by connecting the complement input to ground with the true input floating. For a TTL input, tie a 2.5kΩ resistor between the complement input and ground. See “Input Interface” section. For LVDS applications, only point-to-point interfaces are supported. Due to the current required by the input structure shown in Figure 2, mutli-drop and multi-point architectures are not supported. VCC Input Levels LVDS, CML and HSTL differential signals may be connected directly to the D inputs. Depending on the actual worst case voltage seen, performance of SY55857L varies as per the following table: R2 1.5k R2 1.5k DIN R1 1.05k /DIN Input Voltage Range Minimum Voltage Swing Maximum Translation Speed 0 to 2.4V 100mV 2.5Gbps 0 to VCC +0.3 200mV 1.25Gbps R1 1.05k Figure 2. Simplified Input Structure Table 1. Input Voltage Swings M9999-082306 [email protected] or (408) 955-1690 GND 5 SuperLite™ SY55857L Micrel, Inc. INPUT INTERFACE VCC(DRIVER) VCC(857) 2.3V to 2.7V VCC(DRIVER) VCC(857) VCC(DRIVER) TTL LVTTL VCC(DRIVER) 2.5V LVTTL D D D /D SY55857L 102Ω 1% CML 2.5kΩ 1% Figure 3. 3.3V “TTL” VCC(857) VCC(DRIVER) VCC /D /D SY55857L SY55857L 2.5kΩ 1% Figure 4. CML-DC Coupled Figure 5. 2.5V “TTL” VCC(DRIVER) VCC VCC(DRIVER) D VCC PECL D /D SY55857L 51Ω 1% 51Ω 1% CML D HSTL /D 50Ω 102Ω 1% /D SY55857L SY55857L 3.92kΩ 1% 50Ω 3.92kΩ 1% VCC—2V Figure 6. PECL-DC Coupled Figure 7. HSTL VCC Figure 8. CML-AC Coupled Short Lines VDDQ 82Ω 1% VCC(DRIVER) 82Ω 1% VCC VCC 105Ω 1% D 105Ω 1% D VCC CML /D SY55857L 130Ω 1% 130Ω 1% D LVDS Figure 9. CML-AC Coupled Long Lines 102Ω 1% /D SY55857L Figure 10. LVDS VDDQ VCC 110Ω 1% 110Ω 1% D SSTL_3 /D 90.9Ω 1% 90.9Ω 1% SY55857L Figure 12. SSTL_3 M9999-082306 [email protected] or (408) 955-1690 6 /D SSTL_2 100Ω 1% 100Ω 1% Figure 11. SSTL_2 SY55857L SuperLite™ SY55857L Micrel, Inc. LVPECL OUTPUT TERMINATION LVPECL output have very low output impedance (open emitter), and small signal swing which results in low EMI. LVPECL is ideal for driving 50Ω and 100Ω-controlled impedance transmission lines. There are several techniques in terminating the LVPECL output, as shown in Figures 13 through 15. +3.3V* +3.3V* SY58021U ZO = 50Ω R1 130Ω R1 130Ω R2 82Ω R2 82Ω +3.3V* ZO = 50Ω +3.3V* +3.3V* SY58021U ZO = 50Ω R1 130Ω R1 130Ω *Note: For +2.5V systems, R1 = 250Ω, R2 = 62.5Ω +3.3V* VT = VCC –2V Figure 15. Terminating Unused I/O ZO = 50Ω Notes: *Note. For +2.5V systems, R1 = 250Ω, R2 = 62.5Ω R2 82Ω R2 82Ω 1. Unused output (/Q) must be terminated to balance the output. VT = VCC –2V 2. For +2.5V systems: R1 = 250Ω, R2 = 62.5Ω, R3 = 1.25kΩ, R4 = 1.2kΩ. For +3.3V systems: R1 = 130Ω, R2 = 82Ω, R3 = 1kΩ, R4 = 1.6kΩ. 3. Unused output pairs (Q and /Q) may be left floating. Figure 13. Parallel Termination-Thevenin Equivalent Notes: 1. For +2.5V systems: R1 = 250Ω, R2 = 62.5Ω. 2. For +3.3V systems: R1 = 130Ω, R2 = 82Ω. +3.3V SY58021U +3.3V Z = 50Ω Z = 50Ω 50Ω 50Ω “destination” “source” 50Ω VDD Rb* C1 (optional) 0.01µF * For +2.5V, Rb = 19Ω Notes: * For +3.3V, Rb = 46Ω to 50Ω 1. Power saving alternative to Thevenin termination. 2. Place termination resistors as close to destination inputs as possible. 3. Rb resistor sets the DC bias voltage, equal to VT. Figure 14. Three-Resistor “Y-Termination” Notes: 1. Power-saving alternatives to Thevenin termination. 2. Place termination resistors as close to destination inputs as possible. 3. Rb resistor sets the DC bias voltage, equal to VT. For +2.5V systems: Rb = 19Ω. For +3.3V systems: Rb = 46Ω to 50Ω. 4. C1 is an optional bypass capacitor intended to compensate for any tr/tf mismatches. M9999-082306 [email protected] or (408) 955-1690 7 SuperLite™ SY55857L Micrel, Inc. 10-PIN MSOP (K10-1) Rev. 00 MICREL, INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131 TEL + 1 (408) 944-0800 FAX + 1 (408) 474-1000 WEB USA http://www.micrel.com The information furnished by Micrel in this data sheet is believed to be accurate and reliable. However, no responsibility is assumed by Micrel for its use. Micrel reserves the right to change circuitry and specifications at any time without notification to the customer. Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a product can reasonably be expected to result in personal injury. Life support devices or systems are devices or systems that (a) are intended for surgical implant into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant injury to the user. A Purchaser’s use or sale of Micrel Products for use in life support appliances, devices or systems is at Purchaser’s own risk and Purchaser agrees to fully indemnify Micrel for any damages resulting from such use or sale. © 2005 Micrel, Incorporated. M9999-082306 [email protected] or (408) 955-1690 8