SLUS395E - FEBRUARY 2000 - REVISED APRIL 2001 D Controls Boost Preregulator to Near-Unity D, DW, and N PACKAGES (TOP VIEW) Power Factor Limits Line Distortion World Wide Line Operation Over-Voltage Protection Accurate Power Limiting Average Current Mode Control Improved Noise Immunity Improved Feed-Forward Line Regulation Leading Edge Modulation 150-µA Typical Start-Up Current Low-Power BiCMOS Operation 12-V to 17-V Operation D D D D D D D D D D D GND PKLMT CAOUT CAI MOUT IAC VAOUT VFF 1 16 2 15 3 14 4 13 5 12 6 11 7 10 8 9 DRVOUT VCC CT SS RT VSENSE OVP/EN VREF description The UCCx817/18 family provides all the functions necessary for active power factor corrected preregulators. The controller achieves near unity power factor by shaping the ac input line current waveform to correspond to that of the ac input line voltage. Average current mode control maintains stable, low distortion sinusoidal line current. block diagram VCC 15 OVP/EN 10 16 V (FOR UCC2817 ONLY) SS 13 VAOUT 7 1.9 V + 11 – 7.5 V VFF 0.33 V VOLTAGE ERROR AMP + 16 DRVOUT 1 GND 2 PKLMT VCC – + X ÷ MULT X CURRENT AMP 8.0 V + OVP – – – + PWM S + X2 8 VREF 16 V/10 V (UCC2817) 10.5 V/10 V (UCC2818) ZERO POWER VSENSE 9 UVLO ENABLE – 7.5 V REFERENCE PWM LATCH OSC R CLK MIRROR 2:1 Q R CLK IAC OSCILLATOR 6 – + MOUT 5 4 3 12 14 CAI CAOUT RT CT UDG-98182 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright 2001, Texas Instruments Incorporated !" # $%&" !# '%()$!" *!"&+ *%$"# $ " #'&$$!"# '& ",& "& # &-!# #"% &"# #"!*!* .!!"/+ *%$" '$&##0 *&# " &$&##!)/ $)%*& "&#"0 !)) '!! &"&#+ POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SLUS395E - FEBRUARY 2000 - REVISED APRIL 2001 description (continued) Designed in Texas Instrument’s BiCMOS process, the UCC2817/UCC2818 offers new features such as lower start-up current, lower power dissipation, overvoltage protection, a shunt UVLO detect circuitry, a leading-edge modulation technique to reduce ripple current in the bulk capacitor and an improved, low-offset (±2 mV) current amplifier to reduce distortion at light load conditions. UCC2817 offers an on-chip shunt regulator with low start-up current, suitable for applications utilizing a bootstrap supply. UCC2818 is intended for applications with a fixed supply (VCC). Available in the 16-pin D, DW, and N packages. absolute maximum ratings over operating free-air temperature (unless otherwise noted)† Supply voltage VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 V Gate drive current, continuous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.2 A Gate drive current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2 A Input voltage, CAI, MOUT, SS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 V Input voltage, PKLMT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 V Input voltage, VSENSE, OVP/EN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 V Input current, RT, IAC, PKLMT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 mA Input current, VCC (no switching) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA Maximum negative voltage, DRVOUT, PKLMT, MOUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V Power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 W † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. AVAILABLE OPTIONS PACKAGE DEVICES D PACKAGE 2 DW PACKAGE N PACKAGE TJ ON-CHIP SHUNT REGULATOR FIXED SUPPLY (VCC) ON-CHIP SHUNT REGULATOR FIXED SUPPLY (VCC) ON-CHIP SHUNT REGULATOR FIXED SUPPLY (VCC) –40°C to 85°C UCC2817D UCC2818D UCC2817DW UCC2818DW UCC2817N UCC2818N 0°C to 70°C UCC3817D UCC3818D UCC3817DW UCC3818DW UCC3817N UCC3818N POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SLUS395E - FEBRUARY 2000 - REVISED APRIL 2001 electrical characteristics, TA = 0°C to 70°C for the UCC3817 and TA = –40°C to 85°C for the UCC2817, TA = TJ, VCC = 12 V, RT = 22 kΩ, CT = 270 pF, (unless otherwise noted) supply current section PARAMETER TEST CONDITIONS Supply current, off VCC = (VCC turn-on threshold –0.3 V) Supply current, on VCC = 12 V, No load on DRVOUT MIN TYP MAX 150 300 UNITS µA 2 4 6 mA UVLO section PARAMETER TEST CONDITIONS VCC turn-on threshold (UCCx817) UVLO hysteresis (UCCx817) Maximum shunt voltage (UCCx817) IVCC = 10 mA MIN TYP MAX UNITS 15.4 16 16.6 V 5.8 6.3 V 15.4 17 17.5 V VCC turnon threshold (UCCx818) 9.7 10.2 10.8 V VCC turnoff threshold (UCCx818) 9.4 9.7 V UVLO hysteresis (UCCx818) 0.3 0.5 V voltage amplifier section PARAMETER TEST CONDITIONS Inp t voltage Input oltage TA = 0°C to 70°C TA = –40°C to 85°C VSENSE bias current Open loop gain VSENSE = VREF, VAOUT = 2 V to 5 V High-level output voltage IL = –150 µA IL = 150 µA MIN TYP MAX UNITS 7.387 7.5 7.613 V 7.369 7.5 7.631 V 50 200 nA VAOUT = 2.5 V 50 90 5.3 5.5 5.6 V 0 50 150 mV MIN TYP MAX UNITS VREF +0.48 VREF +0.50 VREF +0.52 V Hysteresis 300 500 600 mV Enable threshold 1.7 1.9 2.1 V Enable hysteresis 0.1 0.2 0.3 V MIN TYP MAX –2 0 2 mV –50 –100 nA 25 100 nA Low-level output voltage dB over voltage protection and enable section PARAMETER TEST CONDITIONS Over voltage reference current amplifier section PARAMETER Input offset voltage Input bias current Input offset current Open loop gain Common-mode rejection ratio High-level output voltage Low-level output voltage Gain bandwidth product TEST CONDITIONS UNITS VCM = 0 V, VCM = 0 V, VCAOUT = 3 V VCAOUT = 3 V VCM = 0 V, VCM = 0 V, VCAOUT = 3 V VCAOUT = 2 V to 5 V 90 VCM = 0 V to 1.5 V, IL = –120 µA VCAOUT = 3 V 60 80 5.6 6.5 6.8 V 0.1 0.2 0.5 V IL = 1 mA See Note 1 dB 2.5 dB MHz NOTES: 1. Ensured by design, not production tested. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 SLUS395E - FEBRUARY 2000 - REVISED APRIL 2001 electrical characteristics, TA = 0°C to 70°C for the UCC3817 and TA = –40°C to 85°C for the UCC2817, TA = TJ, VCC = 12 V, RT = 22 kΩ, CT = 270 pF, (unless otherwise noted) voltage reference section PARAMETER Inp t voltage Input oltage Load regulation Line regulation TEST CONDITIONS TA = 0°C to 70°C TA = –40°C to 85°C IREF = 1 mA to 2 mA VCC = 10.8 V to 15 V, See Note 2 Short-circuit current VREF = 0 V NOTES: 2. Reference variation for VCC < 10.8 V is shown in Figure 8. MIN TYP MAX UNITS 7.387 7.5 7.613 V 7.369 7.5 7.631 V 0 10 mV 0 10 mV –20 –25 –50 mA UNITS oscillator section PARAMETER MIN TYP MAX 85 100 115 Voltage stability TA = 25°C VCC = 10.8 V to 15 V –1 1 Total variation Line, temp 80 120 kHz Initial accuracy TEST CONDITIONS kHz % Ramp peak voltage 4.5 5 5.5 V Ramp amplitude voltage (peak to peak) 3.5 4 4.5 V MIN TYP MAX peak current limit section PARAMETER TEST CONDITIONS UNITS PKLMT reference voltage –15 15 mV PKLMT propagation delay 150 350 500 ns MIN TYP MAX UNITS multiplier section PARAMETER TEST CONDITIONS IMOUT, high line, low power output current, (0°C to 85°C) IAC = 500 µA, VFF = 4.7 V, VAOUT = 1.25 V 0 –6 –20 µA IMOUT, high line, low power output current, (–40°C to 85°C) IAC = 500 µA, VFF = 4.7 V, VAOUT = 1.25 V 0 –6 –23 µA IMOUT, high line, high power output current IAC = 500 µA, VFF = 4.7 V, VAOUT = 5 V –70 –90 –105 µA IMOUT, low line, low power output current IAC = 150 µA, VFF = 1.4 V, VAOUT = 1.25 V –10 –19 –50 µA IMOUT, low line, high power output current IAC = 150 µA, VFF = 1.4 V, VAOUT = 5 V –268 –300 –345 µA IMOUT, IAC limited output current Gain constant (K) IAC = 150 µA, IAC = 300 µA, VFF = 1.3 V, VFF = 3 V, VAOUT = 5 V –250 –300 –400 µA VAOUT = 2.5 V 0.5 1 1.5 1/V IAC = 150 µA, IAC = 500 µA, VFF = 1.4 V, VFF = 4.7 V, VAOUT = 0.25 V 0 –2 IMOUT, zero current µA VAOUT = 0.25 V 0 –2 µA IMOUT, zero current, (0°C to 85°C) IMOUT, zero current, (–40°C to 85°C) IAC = 500 µA, IAC = 500 µA, VFF = 4.7 V, VFF = 4.7 V, VAOUT = 0.5 V 0 –3 µA Power limit (IMOUT x VFF) IAC = 150 µA, VFF = 1.4 V, VAOUT = 5 V 4 POST OFFICE BOX 655303 VAOUT = 0.5 V • DALLAS, TEXAS 75265 –375 0 –3.5 µA –420 –485 µW SLUS395E - FEBRUARY 2000 - REVISED APRIL 2001 electrical characteristics, TA = 0°C to 70°C for the UCC3817 and TA = –40°C to 85°C for the UCC2817, TA = TJ, VCC = 12 V, RT = 22 kΩ, CT = 270 pF, (unless otherwise noted) feed-forward section PARAMETER VFF output current TEST CONDITIONS IAC = 300 µA MIN TYP MAX UNITS –140 –150 –160 µA MIN TYP MAX UNITS –6 –10 –16 µA MIN TYP MAX UNITS 5 12 Ω 2 10 Ω 25 50 ns 10 50 ns 95 100 % 2 % soft start section PARAMETER TEST CONDITIONS SS charge current gate driver section PARAMETER Pullup resistance TEST CONDITIONS Pulldown resistance IO = –100 mA to –200 mA IO = 100 mA Output rise time CL = 1 nF, RL = 10 Ω, Output fall time CL = 1 nF, RL = 10 Ω, VDRVOUT = 0.7 V to 9.0 V VDRVOUT = 9.0 V to 0.7 V Maximum duty cycle Minimum controlled duty cycle 93 At 100 kHz zero power section PARAMETER Zero power comparator threshold TEST CONDITIONS Measured on VAOUT MIN TYP MAX UNITS 0.20 0.33 0.50 V pin descriptions CAI: (current amplifier noninverting input) Place a resistor between this pin and the GND side of current sense resistor. This input and the inverting input (MOUT) remain functional down to and below GND. CAOUT: (current amplifier output) This is the output of a wide bandwidth operational amplifier that senses line current and commands the PFC pulse-width modulator (PWM) to force the correct duty cycle. Compensation components are placed between CAOUT and MOUT. CT: (oscillator timing capacitor) A capacitor from CT to GND sets the PWM oscillator frequency according to: f[ ǒRT0.6CTǓ The lead from the oscillator timing capacitor to GND should be as short and direct as possible. DRVOUT: (gate drive) The output drive for the boost switch is a totem-pole MOSFET gate driver on DRVOUT. Use a series gate resistor to prevent interaction between the gate impedance and the output driver that might cause the DRVOUT to overshoot excessively. See characteristic curve (Figure 13) to determine minimum required gate resister value. Some overshoot of the DRVOUT output is always expected when driving a capacitive load. GND: (ground) All voltages measured with respect to ground. VCC and REF should be bypassed directly to GND with a 0.1-µF or larger ceramic capacitor. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 SLUS395E - FEBRUARY 2000 - REVISED APRIL 2001 pin descriptions (continued) IAC: (current proportional to input voltage) This input to the analog multiplier is a current proportional to instantaneous line voltage. The multiplier is tailored for very low distortion from this current input (IIAC) to multiplier output. The recommended maximum IIAC is 500 µA. MOUT: (multiplier output and current amplifier inverting input) The output of the analog multiplier and the inverting input of the current amplifier are connected together at MOUT. As the multiplier output is a current, this is a high-impedance input so the amplifier can be configured as a differential amplifier. This configuration improves noise immunity and allows for the leading-edge modulation operation. The multiplier output current ǒ is limited to 2 I Ǔ . The multiplier output current is given by the equation: IAC I (V * 1) VAOUT I + IAC MOUT 2 K V VFF where K + 1 is the multiplier gain constant. V OVP/EN: (over-voltage/enable) A window comparator input that disables the output driver if the boost output voltage is a programmed level above the nominal or disables both the PFC output driver and resets SS if pulled below 1.9 V (typ). PKLMT: (PFC peak current limit) The threshold for peak limit is 0 V. Use a resistor divider from the negative side of the current sense resistor to VREF to level shift this signal to a voltage level defined by the value of the sense resistor and the peak current limit. Peak current limit is reached when PKLMT voltage falls below 0 V. RT: (oscillator charging current) A resistor from RT to GND is used to program oscillator charging current. A resistor between 10 kΩ and 100 kΩ is recommended. Nominal voltage on this pin is 3 V. SS: (soft-start) VSS is discharged for VVCC low conditions. When enabled, SS charges an external capacitor with a current source. This voltage is used as the voltage error signal during start-up, enabling the PWM duty cycle to increase slowly. In the event of a VVCC dropout, the OVP/EN is forced below 1.9 V (typ), SS quickly discharges to disable the PWM. Note: In an open-loop test circuit, grounding the SS pin does not ensure 0% duty cycle. Please see the application section for details. VAOUT: (voltage amplifier output) This is the output of the operational amplifier that regulates output voltage. The voltage amplifier output is internally limited to approximately 5.5 V to prevent overshoot. VCC: (positive supply voltage) Connect to a stable source of at least 20 mA between 10 V and 17 V for normal operation. Bypass VCC directly to GND to absorb supply current spikes required to charge external MOSFET gate capacitances. To prevent inadequate gate drive signals, the output devices are inhibited unless VVCC exceeds the upper under-voltage lockout voltage threshold and remains above the lower threshold. VFF: (feed-forward voltage) The RMS voltage signal generated at this pin by mirroring 1/2 of the IIAC into a single pole external filter. At low line, the VFF voltage should be 1.4 V. VSENSE: (voltage amplifier inverting input) This is normally connected to a compensation network and to the boost converter output through a divider network. VREF: (voltage reference output) VREF is the output of an accurate 7.5-V voltage reference. This output is capable of delivering 20 mA to peripheral circuitry and is internally short-circuit current limited. VREF is disabled and remains at 0 V when VVCC is below the UVLO threshold. Bypass VREF to GND with a 0.1-µF or larger ceramic capacitor for best stability. Please refer to Figures 8 and 9 for VREF line and load regulation characteristics. 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SLUS395E - FEBRUARY 2000 - REVISED APRIL 2001 APPLICATION INFORMATION The UCC3817 is a BiCMOS average current mode boost controller for high power factor, high efficiency preregulator power supplies. Figure 1 shows the UCC3817 in a 250-W PFC preregulator circuit. Off-line switching power converters normally have an input current that is not sinusoidal. The input current waveform has a high harmonic content because current is drawn in pulses at the peaks of the input voltage waveform. An active power factor correction circuit programs the input current to follow the line voltage, forcing the converter to look like a resistive load to the line. A resistive load has 0° phase displacement between the current and voltage waveforms. Power factor can be defined in terms of the phase angle between two sinusoidal waveforms of the same frequency: PF + cos Q Therefore, a purely resistive load would have a power factor of 1. In practice, power factors of 0.999 with THD (total harmonic distortion) of less than 3% are possible with a well-designed circuit. Following guidelines are provided to design PFC boost converters using the UCC3817. C10 1 µF R16 100Ω C11 1 µF VCC R21 383k R15 24k R13 383k D7 IAC R18 24k AC2 L1 1mH VO D1 8A, 600V F1 + C14 1.5 µ F 400V VLINE 85–270 VAC D8 D2 6A, 600V C13 0.47 µ F 600V R14 0.25Ω 3W 6A 600V – R17 20Ω UCC3817 R9 4.02k R12 2k VOUT C12 385V–DC 220 µ F 450V Q1 IRFP450 D3 AC1 R10 4.02k 1 GND DRVOUT 16 D4 VCC 2 PKLIMIT 3 CAOUT 4 CAI 5 MOUT CT 14 6 IAC SS 13 RT 12 VSENSE 11 VCC D5 R11 10k VREF 15 C2 100µ F AI EI C1 560pF C9 1.2nF R8 12k C3 1µ F CER C4 0.01µ F C8 270pF R1 12k D6 C7 150nF R7 100k C15 2.2 µ F 7 VAOUT 8 VFF R3 20k R2 499k R19 499k C6 2.2µ F R20 274k OVP/EN 10 VREF 9 R6 30k C5 1µ F VO R4 249k R5 10k VREF UDG-98183 Figure 1. Typical Application Circuit POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 SLUS395E - FEBRUARY 2000 - REVISED APRIL 2001 APPLICATION INFORMATION power stage LBOOST : The boost inductor value is determined by: L BOOST + ǒVIN(min) (DI Ǔ D fs) where D is the duty cycle, ∆I is the inductor ripple current and fS is the switching frequency. For the example circuit a switching frequency of 100 kHz, a ripple current of 875 mA, a maximum duty cycle of 0.688 and a minimum input voltage of 85 VRMS gives us a boost inductor value of about 1 mH. The values used in this equation are at the peak of low line, where the inductor current and its ripple are at a maximum. COUT : Two main criteria, the capacitance and the voltage rating, dictate the selection of the output capacitor. The value of capacitance is determined by the holdup time required for supporting the load after input ac voltage is removed. Holdup is the amount of time that the output stays in regulation after the input has been removed. For this circuit, the desired holdup time is approximately 16 ms. Expressing the capacitor value in terms of output power, output voltage, and holdup time gives the equation: C OUT + ǒ2 P Ǔ Dt OUT ǒVOUT2 * VOUT(min)2Ǔ In practice, the calculated minimum capacitor value may be inadequate because output ripple voltage specifications limit the amount of allowable output capacitor ESR. Attaining a sufficiently low value of ESR often necessitates the use of a much larger capacitor value than calculated. The amount of output capacitor ESR allowed can be determined by dividing the maximum specified output ripple voltage by the inductor ripple current. In this design holdup time was the dominant determining factor and a 220-µF, 450-V capacitor was chosen for the output voltage level of 385 VDC at 250 W. Power switch selection: As in any power supply design, tradeoffs between performance, cost and size have to be made. When selecting a power switch, it can be useful to calculate the total power dissipation in the switch for several different devices at the switching frequencies being considered for the converter. Total power dissipation in the switch is the sum of switching loss and conduction loss. Switching losses are the combination of the gate charge loss, COSS loss and turnon and turnoff losses: P P P GATE +Q COSS +1 2 ON )P V GATE OFF C OSS +1 2 V fs GATE V2 OFF OFF I L fs ǒtON ) tOFFǓ fs where QGATE is the total gate charge, VGATE is the gate drive voltage, fS is the clock frequency, COSS is the drain source capacitance of the MOSFET, IL is the peak inductor current, tON and tOFF are the switching times (estimated using device parameters RGATE, QGD and VTH) and VOFF is the voltage across the switch during the off time, in this case VOFF = VOUT. 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SLUS395E - FEBRUARY 2000 - REVISED APRIL 2001 APPLICATION INFORMATION Conduction loss is calculated as the product of the RDS(on) of the switch (at the worst case junction temperature) and the square of RMS current: P COND +R DS(on) K I2 RMS where K is the temperature factor found in the manufacturer’s RDS(on) vs. junction temperature curves. Calculating these losses and plotting against frequency gives a curve that enables the designer to determine either which manufacturer’s device has the best performance at the desired switching frequency, or which switching frequency has the least total loss for a particular power switch. For this design example an IRFP450 HEXFET from International Rectifier was chosen because of its low RDS(on) and its VDSS rating. The IRFP450’s RDS(on) of 0.4 Ω and the maximum VDSS of 500 V made it an ideal choice. An excellent review of this procedure can be found in the Unitrode Power Supply Design Seminar SEM1200, Topic 6, Design Review: 140 W, [Multiple Output High Density DC/DC Converter]. softstart The softstart circuitry is used to prevent overshoot of the output voltage during start up. This is accomplished by bringing up the voltage amplifier’s output (VVAOUT) slowly which allows for the PWM duty cycle to increase slowly. Please use the following equation to select a capacitor for the softstart pin. In this example tDELAY is equal to 7.5 ms, which would yield a CSS of 10 nF. C SS + 10 mA t DELAY 7.5 V In an open-loop test circuit, shorting the softstart pin to ground does not ensure 0% duty cycle. This is due to the current amplifiers input offset voltage, which could force the current amplifier output high or low depending on the polarity of the offset voltage. However, in the typical application there is sufficient amount of inrush and bias current to overcome the current amplifier’s offset voltage. multiplier The output of the multiplier of the UCC3817 is a signal representing the desired input line current. It is an input to the current amplifier, which programs the current loop to control the input current to give high power factor operation. As such, the proper functioning of the multiplier is key to the success of the design. The inputs to the multiplier are VAOUT, the voltage amplifier error signal, IIAC, a representation of the input rectified ac line voltage, and an input voltage feedforward signal, VVFF. The output of the multiplier, IMOUT, can be expressed as: I MOUT +I ǒVVAOUT * 1Ǔ IAC K V 2 VFF where K is a constant typically equal to 1 . V The electrical characteristics table covers all the required operating conditions for designing with the multiplier. Additionally, curves in figures 10, 11, and 12 provide typical multiplier characteristics over its entire operating range. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 9 SLUS395E - FEBRUARY 2000 - REVISED APRIL 2001 APPLICATION INFORMATION multiplier (continued) The IIAC signal is obtained through a high-value resistor connected between the rectified ac line and the IAC pin of the UCC3817/18. This resistor (RIAC) is sized to give the maximum IIAC current at high line. For the UCC3817/18 the maximum IIAC current is about 500 µA. A higher current than this can drive the multiplier out of its linear range. A smaller current level is functional, but noise can become an issue, especially at low input line. Assuming a universal line operation of 85 VRMS to 265 VRMS gives a RIAC value of 750 kΩ. Because of voltage rating constraints of standard 1/4-W resistor, use a combination of lower value resistors connected in series to give the required resistance and distribute the high voltage amongst the resistors. For this design example two 383-kΩ resistors were used in series. The current into the IAC pin is mirrored internally to the VFF pin where it is filtered to produce a voltage feed forward signal proportional to line voltage. The VFF voltage is used to keep the power stage gain constant; and to provid input power limiting. Please refer to Texas Instruments application note SLUA196 for detailed explanation on how the VFF pin provides power limiting. The following equation can be used to size the VFF resistor (RVFF) to provide power limiting where VIN(min) is the minimum RMS input voltage and RIAC is the total resistance connected between the IAC pin and the rectified line voltage. R VFF + 1.4 V V IN(min) R IAC 0.9 [ 30 kW Because the VFF voltage is generated from line voltage it needs to be adequately filtered to reduce total harmonic distortion caused by the 120 Hz rectified line voltage. Refer to Unitrode Power Supply Design Seminar, SEM–700 Topic 7, [Optimizing the Design of a High Power Factor Preregulator.] A single pole filter was adequate for this design. Assuming that an allocation of 1.5% total harmonic distortion from this input is allowed, and that the second harmonic ripple is 66% of the input ac line voltage, the amount of attenuation required by this filter is: 1.5 % + 0.022 66 % With a ripple frequency (fR) of 120 Hz and an attenuation of 0.022 requires that the pole of the filter (fP) be placed at: f + 120 Hz P 0.022 [ 2.6 Hz The following equation can be used to select the filter capacitor (CVFF) required to produce the desired low pass filter. C VFF + 2 1 R VFF p f [ 2.2 mF P The RMOUT resistor is sized to match the maximum current through the sense resistor to the maximum multiplier current. The maximum multiplier current, or IMOUT(max), can be determined by the equation: I I 10 MOUT(max) + ǒVVAOUT(max) * 1VǓ @V IN(min) IAC K V 2 VFF (min) POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SLUS395E - FEBRUARY 2000 - REVISED APRIL 2001 APPLICATION INFORMATION multiplier (continued) IMOUT(max) for this design is approximately 315 µA. The RMOUT resistor can then be determined by: R MOUT + V I RSENSE MOUT(max) In this example VRSENSE was selected to give a dynamic operating range of 1.25 V, which gives an RMOUT of roughly 3.91 kΩ. voltage loop The second major source of harmonic distortion is the ripple on the output capacitor at the second harmonic of the line frequency. This ripple is fed back through the error amplifier and appears as a 3rd harmonic ripple at the input to the multiplier. The voltage loop must be compensated not just for stability but also to attenuate the contribution of this ripple to the total harmonic distortion of the system. (refer to Figure 2). Cf VOUT CZ Rf R IN – + RD VREF Figure 2. Voltage Amplifier Configuration The gain of the voltage amplifier, GVA, can be determined by first calculating the amount of ripple present on the output capacitor. The peak value of the second harmonic voltage is given by the equation: V OPK + P ǒ2 p f R C IN OUT V OUT Ǔ In this example VOPK is equal to 3.91 V. Assuming an allowable contribution of 0.75% (1.5% peak to peak) from the voltage loop to the total harmonic distortion budget we set the gain equal to: G VA + ǒDVVAOUTǓ(0.015) 2 V OPK where ∆VVAOUT is the effective output voltage range of the error amplifier (5 V for the UCC3817). The network needed to realize this filter is comprised of an input resistor, RIN, and feedback components Cf, CZ, and Rf. The value of RIN is already determined because of its function as one half of a resistor divider from VOUT feeding back to the voltage amplifier for output voltage regulation. In this case the value was chosen to be 1 MΩ. This high value was chosen to reduce power dissipation in the resistor. In practice, the resistor value would be realized by the use of two 500-kΩ resistors in series because of the voltage rating constraints of most standard 1/4-W resistors. The value of Cf is determined by the equation: POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 11 SLUS395E - FEBRUARY 2000 - REVISED APRIL 2001 APPLICATION INFORMATION voltage loop (continued) C + f 1 ǒ2 p f G R VA R Ǔ IN In this example Cf equals 150 nF. Resistor Rf sets the dc gain of the error amplifier and thus determines the frequency of the pole of the error amplifier. The location of the pole can be found by setting the gain of the loop equation to one and solving for the crossover frequency. The frequency, expressed in terms of input power, can be calculated by the equation: f 2 VI + P ǒ(2 p)2 DV V VAOUT IN OUT R IN C OUT C Ǔ f fVI for this converter is 10 Hz. A derivation of this equation can be found in the Unitrode Power Supply Design Seminar SEM1000, Topic 1, [A 250-kHz, 500-W Power Factor Correction Circuit Employing Zero Voltage Transitions]. Solving for Rf becomes: R + f 1 ǒ2 p f VI C Ǔ f or Rf equals 100 kΩ. Due to the low output impedance of the voltage amplifier, capacitor CZ was added in series with RF to reduce loading on the voltage divider. To ensure the voltage loop crossed over at fVI, CZ was selected to add a zero at a 10th of fVI. For this design a 2.2-µF capacitor was chosen for CZ. The following equation can be used to calculate CZ. C + Z 2 p 1 f VI 10 R f current loop The gain of the power stage is: G (s) + ID ǒVOUT RSENSEǓ ǒs LBOOST VPǓ RSENSE has been chosen to give the desired differential voltage for the current sense amplifier at the desired current limit point. In this example, a current limit of 4 A and a reasonable differential voltage to the current amp of 1 V gives a RSENSE value of 0.25 Ω. VP in this equation is the voltage swing of the oscillator ramp, 4 V for the UCC3817. Setting the crossover frequency of the system to 1/10th of the switching frequency, or 10 kHz, requires a power stage gain at that frequency of 0.383. In order for the system to have a gain of 1 at the crossover frequency, the current amplifier needs to have a gain of 1/GID at that frequency. GEA, the current amplifier gain is then: G 12 EA + 1 + 1 + 2.611 0.383 G ID POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SLUS395E - FEBRUARY 2000 - REVISED APRIL 2001 APPLICATION INFORMATION current loop (continued) RI is the RMOUT resistor, previously calculated to be 3.9 kΩ. (refer to Figure 3). The gain of the current amplifier is Rf/RI, so multiplying RI by GEA gives the value of Rf, in this case approximately 12 kΩ. Setting a zero at the crossover frequency and a pole at half the switching frequency completes the current loop compensation. C + Z 2 C + P p 1 R f f C 1 2 p R f fs 2 C P C Rf Z RI – CAOUT + Figure 3. Current Loop Compensation The UCC3817 current amplifier has the input from the multiplier applied to the inverting input. This change in architecture from previous Texas Instruments PFC controllers improves noise immunity in the current amplifier. It also adds a phase inversion into the control loop. The UCC3817 takes advantage of this phase inversion to implement leading-edge duty cycle modulation. Synchronizing a boost PFC controller to a downstream dc-to-dc controller reduces the ripple current seen by the bulk capacitor between stages, reducing capacitor size and cost and reducing EMI. This is explained in greater detail in a following section. The UCC3817 current amplifier configuration is shown in Figure 4. L BOOST V OUT – R SENSE Q BOOST + Zf MULT CA PWM COMPARATOR – + – + Figure 4. UCC3817 Current Amplifier Configuration POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 13 SLUS395E - FEBRUARY 2000 - REVISED APRIL 2001 APPLICATION INFORMATION start up The UCC3818 version of the device is intended to have VCC connected to a 12-V supply voltage. The UCC3817 has an internal shunt regulator enabling the device to be powered from bootstrap circuitry as shown in the typical application circuit of Figure 1. The current drawn by the UCC3817 during undervoltage lockout, or start-up current, is typically 150 µA. Once VCC is above the UVLO threshold, the device is enabled and draws 4 mA typically. A resistor connected between the rectified ac line voltage and the VCC pin provides current to the shunt regulator during power up. Once the circuit is operational, the bootstrap winding of the inductor provides the VCC voltage. Sizing of the start-up resistor is determined by the start-up time requirement of the system design. I + C DV C Dt V R + RMS I (0.9) C Where IC is the charge current, C is the total capacitance at the VCC pin, ∆V is the UVLO threshold and ∆t is the allowed start-up time. Assuming a 1 second allowed start-up time, a 16-V UVLO threshold, and a total VCC capacitance of 100 µF, a resistor value of 51 kΩ is required at a low line input voltage of 85 VRMS. The IC start-up current is sufficiently small as to be ignored in sizing the start-up resistor. capacitor ripple reduction For a power system where the PFC boost converter is followed by a dc-to-dc converter stage, there are benefits to synchronizing the two converters. In addition to the usual advantages such as noise reduction and stability, proper synchronization can significantly reduce the ripple currents in the boost circuit’s output capacitor. Figure 5 helps illustrate the impact of proper synchronization by showing a PFC boost converter together with the simplified input stage of a forward converter. The capacitor current during a single switching cycle depends on the status of the switches Q1 and Q2 and is shown in Figure 6. It can be seen that with a synchronization scheme that maintains conventional trailing-edge modulation on both converters, the capacitor current ripple is highest. The greatest ripple current cancellation is attained when the overlap of Q1 offtime and Q2 ontime is maximized. One method of achieving this is to synchronize the turnon of the boost diode (D1) with the turnon of Q2. This approach implies that the boost converter’s leading edge is pulse width modulated while the forward converter is modulated with traditional trailing edge PWM. The UCC3817 is designed as a leading edge modulator with easy synchronization to the downstream converter to facilitate this advantage. Table 1 compares the ICB(rms) for D1/Q2 synchronization as offered by UCC3817 vs. the ICB(rms) for the other extreme of synchronizing the turnon of Q1 and Q2 for a 200-W power system with a VBST of 385 V. UDG-97130-1 Figure 5. Simplified Representation of a 2-Stage PFC Power Supply 14 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SLUS395E - FEBRUARY 2000 - REVISED APRIL 2001 APPLICATION INFORMATION capacitor ripple reduction (continued) UDG-97131 Figure 6. Timing Waveforms for Synchronization Scheme Table 1. Effects of Synchronization on Boost Capacitor Current VIN = 85 V D1/Q2 VIN = 120 V D1/Q2 Q1/Q2 VIN = 240 V D1/Q2 D(Q2) Q1/Q2 Q1/Q2 0.35 1.491 A 0.835 A 1.341 A 0.663 A 1.024 A 0.731 A 0.45 1.432 A 0.93 A 1.276 A 0.664 A 0.897 A 0.614 A Table 1 illustrates that the boost capacitor ripple current can be reduced by about 50% at nominal line and about 30% at high line with the synchronization scheme facilitated by the UCC3817. Figure 7 shows the suggested technique for synchronizing the UCC3817 to the downstream converter. With this technique, maximum ripple reduction as shown in Figure 6 is achievable. The output capacitance value can be significantly reduced if its choice is dictated by ripple current or the capacitor life can be increased as a result. In cost sensitive designs where holdup time is not critical, this is a significant advantage. An alternative method of synchronization to achieve the same ripple reduction is possible. In this method, the turnon of Q1 is synchronized to the turnoff of Q2. While this method yields almost identical ripple reduction and maintains trailing edge modulation on both converters, the synchronization is much more difficult to achieve and the circuit can become susceptible to noise as the synchronizing edge itself is being modulated. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 15 SLUS395E - FEBRUARY 2000 - REVISED APRIL 2001 APPLICATION INFORMATION capacitor ripple reduction (continued) Gate Drive From Down Stream PWM C1 UCC3817 D2 CT CT RT D1 RT Figure 7. Synchronizing the UCC3817 to a Down-Stream Converter REFERENCE VOLTAGE vs REFERENCE CURRENT REFERENCE VOLTAGE vs SUPPLY VOLTAGE 7.510 VREF – Reference Voltage – V VREF – Reference Voltage – V 7.60 7.55 7.50 7.45 7.505 7.500 7.495 7.490 7.40 9 10 11 12 13 14 0 10 Figure 8 Figure 9 POST OFFICE BOX 655303 15 20 IVREF – Reference Current – mA VCC – Supply Voltage – V 16 5 • DALLAS, TEXAS 75265 25 SLUS395E - FEBRUARY 2000 - REVISED APRIL 2001 APPLICATION INFORMATION MULTIPLIER OUTPUT CURRENT vs VOLTAGE ERROR AMPLIFIER OUTPUT MULTIPLIER GAIN vs VOLTAGE ERROR AMPLIFIER OUTPUT 1.5 300 1.3 IAC = 150 µ A IAC = 150 µ A 250 Multiplier Gain – K IMOUT - Multiplier Output Current – µA 350 200 IAC = 300 µ A 150 100 1.1 0.9 IAC = 300 µ A IAC = 500 µ A 0.7 50 IAC = 500 µ A 0.5 0 0.0 1.0 2.0 3.0 4.0 1.0 5.0 2.0 Figure 10 (VFF × IMOUT) – µW 400 VAOUT = 5 V 300 VAOUT = 4 V 200 VAOUT = 3 V 100 VAOUT = 2 V 0 3.0 4.0 5.0 RGATE - Recommended Minimum Gate Resistance – Ω 500 2.0 5.0 Figure 11 MULTIPLIER CONSTANT POWER PERFORMANCE 1.0 4.0 VAOUT – Voltage Error Amplifier Output – V VAOUT – Voltage Error Amplifier Output – V 0.0 3.0 RECOMMENDED MINIMUM GATE RESISTANCE vs SUPPLY VOLTAGE 17 16 15 14 13 12 11 10 9 8 10 12 14 16 18 20 VCC – Supply Voltage – V VFF – Feedforward Voltage – V Figure 12 Figure 13 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 17 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. 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