ETC UPD45125421G5-A10-9JF

PRELIMINARY DATA SHEET
MOS INTEGRATED CIRCUIT
µPD45125421, 45125821, 45125161
128M-BIT VirtualChannelTM SDRAM
Description
The 128M-bit VirtualChannel (VC) SDRAM is implemented to be 100% pin and package compatible to the industry
standard SDRAM. It uses the same command protocol and interface as SDRAM. The VirtualChannel SDRAM
command set is a superset of the SDRAM. It also follows the same electrical and timing specifications of the
SDRAM, such that it is possible for one product platform to be used with the VirtualChannel SDRAM and nonVirtualChannel SDRAM part.
Features
• Fully Standard Synchronous Dynamic RAM, with all signals referenced to a positive clock edge
• Dual internal banks controlled by Bank Select Address
• Sixteen Channels controlled by Channel Select Address
• Quad segments controlled by Segment Select Address
• Byte control (x16) by LDQM and UDQM
• Programmable Wrap sequence (Sequential / Interleave)
• Programmable burst length (1, 2, 4, 8 and 16)
• Read latency (1, 2)
★
• Prefetch Read latency (2, 4) : For x4 bits organization(µPD45125421), prefetch read operation can not be used.
• Auto precharge and without auto precharge
• Auto refresh and Self refresh
• x4, x8, x16 organization
• Single 3.3 V ± 0.3 V power supply
• Interface: LVTTL
• Refresh cycle: 4 K cycles / 64 ms
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
Document No.
M14412EJ3V0DS00 (3rd edition)
Date Published November 1999 NS CP(K)
Printed in Japan
The mark • shows major revised points.
©
1999
µPD45125421, 45125821, 45125161
★
Ordering Information (Under development)
Part number
Organization
Clock
Read
Prefetch
Channel
(word x bit x bank)
frequency
latency
Read
and
Latency
Interface
MHz
(MAX.)
µPD45125421G5-A75-9JF
16M x 4 x 2
133
67
µPD45125421G5-A10-9JF
8M x 8 x 2
µPD45125821G5-A10-9JF
2
4M x 16 x 2
16 channels
54-pin Plastic
−
Note1
and
TSOP(II)
−
Note1
LVTTL
(10.16mm (400))
−
Note1
2
4
1
Note2
2
2
4
Note2
2
2
4
Note2
2
2
4
Note2
2
1
1
100
50
Note1
1
133
67
−
Note2
100
50
µPD45125161G5-A10-9JF
1
133
67
µPD45125161G5-A75-9JF
Note2
100
50
µPD45125821G5-A75-9JF
2
1
Notes 1. For x4 bits organization, prefetch read operation can not be used.
2. Under development.
2
Package
Preliminary Data Sheet M14412EJ3V0DS00
µPD45125421, 45125821, 45125161
Part Number
★
[ x4, x8 ]
µ PD4 5
125 8 2 1 G5 - A75
NEC Memory
Synchronous DRAM
Data rate
Minimum Cycle Time
75 :
RL=2 : 7.5 ns (133MHz)
RL=1 : 15 ns ( 67MHz)
10 :
RL=2 : 10 ns (100MHz)
RL=1 : 20 ns ( 50MHz)
No letter : Single Data Rate
Note
D : Double Data Rate
Memory Density
64
65
128
125
: 64M bits Standard SDRAM
: 64M bits VC SDRAM
: 128M bits Standard SDRAM
: 128M bits VC SDRAM
Low Voltage
A : 3.3 ± 0.3 V
Organization
Package
4 : x4
8 : x8
G5 : TSOP(II)
Number of Banks and Channel
Note
Note
Note
Note
Note
1 : 2 banks and 8 Channels
2 : 2 banks and 16 Channels
3 : 2 banks and 32 Channels
4 : 4 banks and 8 Channels
5 : 4 banks and 16 Channels
6 : 4 banks and 32 Channels
Interface
Note
1 : LVTTL
2 : SSTL
Note Reserved
Preliminary Data Sheet M14412EJ3V0DS00
3
µPD45125421, 45125821, 45125161
★
[ x16 ]
µ PD4 5
125 16 1 G5 - A75
NEC Memory
Synchronous DRAM
Data rate
Minimum Cycle Time
75 :
RL=2 : 7.5 ns (133MHz)
RL=1 : 15 ns ( 67MHz)
10 :
RL=2 : 10 ns (100MHz)
RL=1 : 20 ns ( 50MHz)
No letter : Single Data Rate
Note D : Double Data Rate
Memory Density
64
65
128
125
: 64M bits Standard SDRAM
: 64M bits VC SDRAM
: 128M bits Standard SDRAM
: 128M bits VC SDRAM
Low Voltage
A : 3.3 ± 0.3 V
Word and Number of Channel
Note
Note
15 : x16 bits and 8 Channels
16 : x16 bits and 16 Channels
17 : x16 bits and 32 Channels
Package
G5 : TSOP(II)
Number of Banks and Interface
Note
1 : 2 Banks and LVTTL
2 : 2 Banks and SSTL
Note Reserved
4
Preliminary Data Sheet M14412EJ3V0DS00
µPD45125421, 45125821, 45125161
Pin Configurations
/xxx indicates active low signal.
[µPD45125421]
54-pin Plastic TSOP (II) (10.16mm (400))
16M words x 4 bits x 2 banks
VCC
1
54
VSS
NC
2
53
NC
VCCQ
3
52
VSSQ
NC
4
51
NC
DQ0
5
50
DQ3
VSSQ
6
49
VCCQ
NC
7
48
NC
NC
8
47
NC
VCCQ
9
46
VSSQ
NC
10
45
NC
DQ1
11
44
DQ2
VSSQ
12
43
VCCQ
NC
13
42
NC
VCC
14
41
VSS
NC
15
40
NC
/WE
16
39
DQM
/CAS
17
38
CLK
/RAS
18
37
CKE
/CS
19
36
NC
Bank Address(A13)
20
35
A11
A12
21
34
A9
Auto Precharge(A10)
22
33
A8
A0
23
32
A7
A1
24
31
A6
A2
25
30
A5
A3
26
29
A4
VCC
27
28
VSS
A0 - A13
: Address inputs
DQM
: DQ mask enable
A0 - A12
: Row address inputs
CKE
: Clock enable
A0 - A7, A10
: Column address inputs
CLK
: System clock input
DQ0 - DQ3
: Data inputs/outputs
VCC
: Supply voltage
/CS
: Chip select
VSS
: Ground
/RAS
: Row address strobe
VCCQ
: Supply voltage for DQ
/CAS
: Column address strobe
VSSQ
: Ground for DQ
/WE
: Write enable
NC
: No connection
Remark Refer to 1. Input/ Output Pin Function for Bank address, Channel address and Segment address.
Preliminary Data Sheet M14412EJ3V0DS00
5
µPD45125421, 45125821, 45125161
[µPD45125821]
54-pin Plastic TSOP (II) (10.16mm (400))
8M words x 8 bits x 2 banks
VCC
1
54
VSS
DQ0
2
53
DQ7
VCCQ
3
52
VSSQ
NC
4
51
NC
DQ1
5
50
DQ6
VSSQ
6
49
VCCQ
NC
7
48
NC
DQ2
8
47
DQ5
VCCQ
9
46
VSSQ
NC
10
45
NC
DQ3
11
44
DQ4
VSSQ
12
43
VCCQ
NC
13
42
NC
VCC
14
41
VSS
NC
15
40
NC
/WE
16
39
DQM
/CAS
17
38
CLK
/RAS
18
37
CKE
/CS
19
36
NC
Bank Address(A13)
20
35
A11
A12
21
34
A9
Auto Precharge(A10)
22
33
A8
A0
23
32
A7
A1
24
31
A6
A2
25
30
A5
A3
26
29
A4
VCC
27
28
VSS
A0 - A13
: Address inputs
DQM
: DQ mask enable
A0 - A12
: Row address inputs
CKE
: Clock enable
A0 - A7
: Column address inputs
CLK
: System clock input
DQ0 - DQ7
: Data inputs/outputs
VCC
: Supply voltage
/CS
: Chip select
VSS
: Ground
/RAS
: Row address strobe
VCCQ
: Supply voltage for DQ
/CAS
: Column address strobe
VSSQ
: Ground for DQ
/WE
: Write enable
NC
: No connection
Remark Refer to 1. Input/ Output Pin Function for Bank address, Channel address and Segment address.
6
Preliminary Data Sheet M14412EJ3V0DS00
µPD45125421, 45125821, 45125161
[µPD45125161]
54-pin Plastic TSOP (II) (10.16mm (400))
4M words x 16 bits x 2 banks
VCC
1
54
VSS
DQ0
2
53
DQ15
VCCQ
3
52
VSSQ
DQ1
4
51
DQ14
DQ2
5
50
DQ13
VSSQ
6
49
VCCQ
DQ3
7
48
DQ12
DQ4
8
47
DQ11
VCCQ
9
46
VSSQ
DQ5
10
45
DQ10
DQ6
11
44
DQ9
VSSQ
12
43
VCCQ
DQ7
13
42
DQ8
VCC
14
41
VSS
LDQM
15
40
NC
/WE
16
39
UDQM
/CAS
17
38
CLK
/RAS
18
37
CKE
/CS
19
36
NC
Bank Address(A13)
20
35
A11
A12
21
34
A9
Auto Precharge(A10)
22
33
A8
A0
23
32
A7
A1
24
31
A6
A2
25
30
A5
A3
26
29
A4
VCC
27
28
VSS
A0 - A13
: Address inputs
UDQM
: Upper DQ mask enable
A0 - A12
: Row address inputs
LDQM
: Lower DQ mask enable
A0 - A6
: Column address inputs
CKE
: Clock enable
DQ0 - DQ15
: Data inputs/outputs
CLK
: System clock input
/CS
: Chip select
VCC
: Supply voltage
/RAS
: Row address strobe
VSS
: Ground
/CAS
: Column address strobe
VCCQ
: Supply voltage for DQ
/WE
: Write enable
VSSQ
: Ground for DQ
NC
: No connection
Remark Refer to 1. Input/ Output Pin Function for Bank address, Channel address and Segment address.
Preliminary Data Sheet M14412EJ3V0DS00
7
µPD45125421, 45125821, 45125161
VCMemoryTM Architecture
The VCMemory is a memory core technology designed to improve memory data throughput efficiency and initial
latency of memories. Intended for use in next generation memory systems, the VCMemory technology is ideal
memory for a wide range of application such as Multimedia PC, Game machine, Internet Server etc…. The slow core
operation memory such as DRAM, Flash Memory and Mask ROM can get very significant performance improvements
with VCMemory technology.
Today's memory subsystems are accessed by multiple tasks/sources (memory masters), working in multitasking
mode. Each memory master accesses memory with an address locality with a time locality, a block size and a
number of contiguous accesses.
VCMemory architecture is designed for this multitasking, multiple masters,
interleaving access scenarios. The VCMemory provides memory masters with VirtualChannels. Each channel is a
set of resources that constitute a fast dedicated path for each memory masters to access the memory.
The
VirtualChannels will minimize the overhead resulting from other memory master's accesses, reduce the access
latency and facilitate automatic data sharing.
Each channel is equipped with a data row buffer and its own independent operating modes. To the memory
masters, this looks like its own very fast memory. The system memory controller associates these channels to the
memory masters for their accesses. Thus, the channels are made to track the accesses of these memory masters.
The system memory controller has complete controls over the operations of the channels. It can schedule and issue
commands that causes segments of memory rows to be loaded into the channels or for data from the channels to be
written back to the memory rows. Any channels can store the data from any rows, can be written to any rows and
hence are fully associative. Then the Read and Write operations will be occurring as much as possible with these
high speed channels, minimizing all overheads associated with the DRAM bank operations.
The Read/Write operations of the channels (foreground operations) can operate independently with the DRAM bank
operations (background operations) of Activate, Precharge, Prefetch (Loading row data to channel) and Restore
(Writing channel data to row). Then VCMemory also further enhances performance by allowing the system memory
controller to schedule the foreground and background operations to operate concurrently.
VirtualChannel SDRAM architecture offers the following features and benefits:
1. Multiplies the effective data throughput performance of conventional DRAM core.
2. Achieving close to full data bus bandwidth with low latency, interleaved random row, random column Read/Write
through the channels.
3. Transparent DRAM bank operations through the concurrent foreground and Background Operations
4. Very wide (256 bytes wide) internal data transfer bus between Channel and memory core
5. Equivalence of tens of multiple memory banks by using only a fraction of the frequency of Row Activate and
Precharge of conventional DRAM core.
8
Preliminary Data Sheet M14412EJ3V0DS00
µPD45125421, 45125821, 45125161
Block Diagram
Address
Address
Channel Control
Address Buffer
and
Refresh counter
Channel Selector
Bank B
Mode
register
/CAS
Row Decoder
/WE
CKE
CLK
Column Decoder
Channel
Memory Cell Array
Sense Amp.
Segment Decoder
Control Logic
/RAS
Command Decoder
/CS
Bank A
DQM
Data Control Circuit
Clock Generator
Latch Circuit
Input and Output Buffer
DQ
Preliminary Data Sheet M14412EJ3V0DS00
DQ
9
µPD45125421, 45125821, 45125161
Conceptual Schematic 1
Background
Prefetch Operation
Restore Operation
Segment
DQ
Input and Output Buffer
Segment
Segment
Segment
Segment
Bank A
Read Operation
( from channel )
One segment : 1/4 Row
One segment means
one data transfer size
at the background
operations.
Segment
Segment
Bank B
16 Channels
Segment
Prefetch Operation
(from Segment of memory core
to channel)
Foreground
Read Operation
Write Operation
Row Decoder
Row Decoder
10
Restore Operation
(from Channel
to Segment of memory core)
Preliminary Data Sheet M14412EJ3V0DS00
Write Operation
( to channel )
DQ
µPD45125421, 45125821, 45125161
Conceptual Schematic 2
Prefetch Operation
The data is fetched from a segment to any channel buffer.
Segment
Segment
Bank A
Segment
Segment
Segment
Bank B
Segment
Row Decoder
Must select one channel
Segment
Segment
16 Channels
Row Decoder
Restore Operation
The data is transferred from a channel buffer to any segment.
Segment
Segment
Bank A
Segment
Segment
Segment
Bank B
Segment
Row Decoder
Must select one segment
Segment
Segment
16 Channels
Row Decoder
Preliminary Data Sheet M14412EJ3V0DS00
11
µPD45125421, 45125821, 45125161
Data size of segment and channel
8 K (8192) bits
1 Row
Memory cell
4 Segments
2 K (2048) bits
One segment means one data transfer size at the prefetch and restore operation.
16 Channels
2 K (2048) bits
2
1
3
4
5
x 4 bits organization
Column Selector
One channel density
512 bits
2048 (2K) bits
2048 (2K) bits / 4
Input and Output Buffer
1
0
3
2
x 8 bits organization
Column Selector
One channel density
256 bits
2048 (2K) bits
2048 (2K) bits / 8
Input and Output Buffer
0
1
2
3
4
5
6
7
x 16 bits organization
Column Selector
One channel density
2048 (2K) bits
128 bits
2048 (2K) bits / 16
Input and Output Buffer
0 1 2 3 4 5 6 7 8 9 10 1112 13 14 15
12
Preliminary Data Sheet M14412EJ3V0DS00
16
µPD45125421, 45125821, 45125161
1. Input / Output Pin Function
(1/3)
Pin name
CLK
Input/Output
Input
Function
CLK is the master clock input. Other inputs signals for all commands are
referenced to the CLK rising edge.
CKE
Input
CKE determine validity of the next CLK (clock). If CKE is high, the next CLK rising
edge is valid; otherwise it is invalid. If the CLK rising edge is invalid, the internal
clock is not issued and the VirtualChannel SDRAM suspends operation.
When the VirtualChannel SDRAM is not in burst mode and CKE is negated, the
device enters power down mode. During power down mode, CKE must remain low.
/CS
Input
Chip select.
/CS low starts the command input cycle, which occurs on rising edge of CLK.
During /CS high, commands are ignored but operations continue.
/RAS, /CAS, /WE
Input
Command Inputs.
The combination of these signals defines the command being entered.
For details, refer to the Command Table in Command Functions. The symbol
names (/RAS, /CAS, /WE) do not refer to the functional meanings used for
conventional DRAM.
DQM
Input
For x4, x8 devices
For x8,x4 devices
DQM controls I/O buffers.
UDQM LDQM
For x16 device
For x16 device
UDQM and LDQM control upper byte and lower byte I/O buffers, respectively.
In read mode
DQM controls the output buffers like a conventional /OE pin.
DQM high and DQM low turn the output buffers off and on, respectively.
The DQM latency for the read is two clocks.
In write mode
DQM controls the word mask. Input data is written to the memory cell if DQM is
low but not if DQM is high.
The DQM latency for the write is zero.
DQ0 - DQ3
Input / Output
DQ0 - DQ7
DQ pins have the same function as I/O pins on a Standard Synchronous DRAM.
DQ0 - DQ3 (for x 4 device)
DQ0 - DQ15
DQ0 - DQ7 (for x 8 device)
DQ0 - DQ15 (for x 16 device)
NC
VCC
−
No connect. Leave these pins unconnected.
(Power supply)
VCC and VSS are power supply pins for internal circuits.
(Power supply)
VCCQ and VSSQ are power supply pins for the output buffers.
VSS
VCCQ
VSSQ
Preliminary Data Sheet M14412EJ3V0DS00
13
µPD45125421, 45125821, 45125161
(2/3)
Pin name
A0 - A13
Input / Output
Input
Function
Address specification. These pins provide memory source and target addresses
(bank, row, column, etc.), and channel addresses.
Row Address
Row Address is determined by A0 - A12 at the CLK (clock) rising edge in the active
command cycle. It does not depend on the bit organization.
Column Address
Column Address is determined by A0 - A7 and A10 at the CLK rising edge in the
read or write command cycle. It depends on the bit organization.
: A0 - A7, A10 for x4 device
: A0 - A7 for x8 device
: A0 - A6 for x16 device.
Bank Address(A13)
A13 is the bank select signal.
In command cycle, A13 low select bank A, and A13 high select bank B.
14
Preliminary Data Sheet M14412EJ3V0DS00
µPD45125421, 45125821, 45125161
(3/3)
Pin name
A0 - A13
Input / Output
Input
Function
Channel Address(A8, A9, A10, A11, A12)
A8, A9, A11, A12 are the channel select signals.
In prefetch, restore, read and write operations, channel is determined by A8, A9, A11 and A12.
Channel number
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
A12
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
A11
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
A8
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
A9
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
In set register operation, channel is determined by A9, A10, A11 and A12.
Channel number A12
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
A11
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
A10
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
A9
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Segment Address(A0, A1, A10, A13)
A0, A1, A10, A13 are the segment select signals.
In prefetch and restore operations, column address in channel is determined by A0, A1.
In prefetch read operation, segment is determined by A10, A13.
Auto precharge Address(A10)
A10 defines the precharge mode.
In the precharge command cycle
High level: All banks are precharged.
Low level: Only the bank selected by A13 is precharged.
In the prefetch or restore command cycle
High level: Auto precharge
Low level: Without auto precharge
Preliminary Data Sheet M14412EJ3V0DS00
15
µPD45125421, 45125821, 45125161
2. Truth Table
2.1 Command Execution
All commands are executed with the signal combination at the rising edge of the clock (CLK), /CS (Chip Select)
must be low at the command input cycle. CKE (Clock Enable) must be high at one clock before the command input
cycle as shown in below. The state of the /RAS, /CAS, and /WE signals specifies the command function to be
executed. Some commands have the same signal combination for /RAS, /CAS, and /WE and are distinguished by
some of address Input signals. When /CS becomes high, operations continue as specified in the command, but
further commands (signal states that would specify a command) are not registered until /CS becomes low.
This state is Device deselect.
n-1
n
CLK
CKE
/CS
/RAS
/CAS
/WE
Address
16
H
L
Command
Preliminary Data Sheet M14412EJ3V0DS00
n+1
µPD45125421, 45125821, 45125161
2.2 Command Truth Table
Function
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
Device deselect
Symbol
DESL
H
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
No operation
NOP
L
H
H
H
x
x
x
x
x
x
x
x
x
x
x
x
x
x
Prefetch without auto precharge
PFC
L
H
H
L
BA Cha. Cha.
L
Cha. Cha.
L
L
L
x
x
x
PFCA
L
H
H
L
BA Cha. Cha.
H
Cha. Cha.
L
L
L
x
x
x
Seg. Seg.
RST
L
H
H
L
BA Cha. Cha.
L
Cha. Cha.
H
x
x
x
x
x
Seg. Seg.
Restore with auto precharge
RSTA
L
H
H
L
BA Cha. Cha.
H
Cha. Cha.
H
x
x
x
x
x
Seg. Seg.
Channel read
READ
L
H
L
H
Channel write
WRIT
L
H
L
L
Bank activate
ACT
L
L
H
H
BA Row Row Row Row Row Row Row Row Row Row Row Row Row
Prefetch read with auto precharge
PFR
L
L
H
L
Seg. Cha. Cha. Seg. Cha. Cha. Col. Col. Col. Col. Col. Col. Col. Col.
Precharge selected bank
PRE
L
L
L
L
BA
x
x
L
x
x
Precharge all banks
PALL
L
L
L
L
x
x
x
H
x
x
x
x
L
Set register operation
SCLR
L
L
L
L
L
L
L
L
L
L
L
L
H
SCCR
L
L
L
L
L
L
L
H
H
Prefetch with auto precharge
Restore without auto precharge
Note
/CS /RAS /CAS /WE A13 A12 A11 A10
Seg. Seg.
x
Cha. Cha. Col. Cha. Cha. Col. Col. Col. Col. Col. Col. Col. Col.
L
Cha. Cha. Col. Cha. Cha. Col. Col. Col. Col. Col. Col. Col. Col.
Cha. Cha. Cha. Cha.
x
x
L
x
x
x
x
PRL RL
x
x
x
x
x
x
x
x
RL
RL
WT
BL
BL
BL
Note For x4 bits organization, this command is illegal.
Remark
H
Abbreviations in the table mean as follows.
: High level
L
: Low level
X
Row : Row address
Col.
: Column address
BA : Bank Address
Cha. : Channel address
Seg. : Segment address
BL
: Burst length
RL
WT
: Wrap Type
: Read Latency
: High or Low level (Don' t care)
PRL : Prefetch Read Latency
Preliminary Data Sheet M14412EJ3V0DS00
17
µPD45125421, 45125821, 45125161
2.3 CKE Truth Table
Current state
Function
Symbol
CKE
/CS
/RAS
/CAS
/WE
Address
n–1
n
Activating
Clock suspend mode entry
–
H
L
x
x
x
x
x
Any
Clock suspend
–
L
L
x
x
x
x
x
Clock suspend
Clock suspend mode exit
–
L
H
x
x
x
x
x
Idle
Idle
Auto refresh command
REF
H
H
L
L
L
H
x
Self refresh entry
SELF
H
L
L
L
L
H
x
Self refresh
Self refresh exit
–
L
H
L
H
H
H
x
L
H
H
x
x
x
x
Idle
Power down entry
–
H
L
x
x
x
x
x
Power down
Power down exit
–
L
H
H
x
x
x
x
L
H
H
H
x
Remark H: High level, L: Low level, x: High or Low level (Don' t care)
18
Preliminary Data Sheet M14412EJ3V0DS00
µPD45125421, 45125821, 45125161
3. Commands
Device deselect (DESL)
/CS /RAS /CAS /WE
High
x
x
x
A13 A12 A11 A10 A9
x
x
x
x
x
A8
A7
A6
A5
A4
A3
A2
A1
A0
x
x
x
x
x
x
x
x
x
Remark x: High or Low level (Don' t care)
The device is deselected state by this command.
CLK
CKE
H
/CS
/RAS
/CAS
/WE
A0 to A13
Preliminary Data Sheet M14412EJ3V0DS00
19
µPD45125421, 45125821, 45125161
No operation (NOP)
/CS
/RAS /CAS
/WE
A13
Low
High
High
x
High
A12 A11
x
x
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
x
x
x
x
x
x
x
x
x
x
x
Remark x: High or Low level (Don' t care)
This command is not a execution command. No operations begin or terminate by this command.
CLK
CKE
H
/CS
/RAS
/CAS
/WE
A0 to A13
20
Preliminary Data Sheet M14412EJ3V0DS00
µPD45125421, 45125821, 45125161
Prefetch without auto precharge (PFC)
/CS
/RAS /CAS
/WE
A13
A12 A11
Low
High
Low
BA
Cha. Cha. Low Cha. Cha. Low Low Low
High
A10
A9
A8
A7
A6
A5
A4
A3
A2
x
x
x
A1
A0
Seg. Seg.
Remark BA: Bank address, Cha.: Channel address, x: High or Low level (Don' t care), Seg.: Segment address
This command needs to follow Bank activate (ACT) command. This command fetches data from a segment of the
activated row in a bank to a channel buffer which is chosen by channel address. The Segment and Bank fields
specify the source segment and bank. In addition, the Channel Address field specifies the destination channel.
A10 specify the optional precharge operation. In case of A10: low, without auto precharge operation occurs. In
case of A10: high, with auto precharge operation occurs after data fetch operation. (Please refer to PFCA
command.) (Bank precharge is necessary after data fetch.)
This fetched command can be issued continuously without any precharge operation. For instance, when the first
operation has been done from one of segment on activated row area to one of channel, if the second prefetch
operation is required from same activated row, but different channel, the second prefetch command can be issued
without any precharge operation. tPPD (PFC to PFC/PFCA command period) is required between first and second
prefetch command. When the new row address area need to be activated on same bank, bank precharge is
necessary after this PFC command. tPPL (PFC to PRE command period) is required between PFC and PRE.
Fetched data into the channel buffer remains available for Channel Read and Channel Write operations.
CLK
CKE
H
/CS
/RAS
/CAS
/WE
A13
Valid
A12
Valid
A11
Valid
Bank select
Channel address
A10
A9
Valid
A8
Valid
Channel address
A7
A6
A5
A2 to A4
A1
Valid
A0
Valid
Segment address
Preliminary Data Sheet M14412EJ3V0DS00
21
µPD45125421, 45125821, 45125161
Prefetch with auto precharge (PFCA)
/CS
/RAS /CAS
/WE
A13
A12 A11
Low
High
Low
BA
Cha. Cha. High Cha. Cha. Low Low Low
High
A10
A9
A8
A7
A6
A5
A4
A3
A2
x
x
x
A1
A0
Seg. Seg.
Remark BA: Bank address, Cha.: Channel address, x: High or Low level (Don' t care), Seg.: Segment address
This command needs to follow Bank activate (ACT) command. This command fetches data from a segment of the
activated row in a bank to a channel buffer, and precharge operation is performed automatically, which closes the
activated row after data fetch operation.
The Segment and Bank fields specify the source segment and bank.
In addition, the Channel Address field specifies the destination channel.
A10 specify the optional precharge operation.
In case of A10: low, without auto precharge operation occurs. (Please refer to PFC command.)
In case of A10: high, with auto precharge operation occurs after data fetch operation.
Fetched data into the channel buffer remains available for Channel Read and Channel Write operations.
CLK
CKE
H
/CS
/RAS
/CAS
/WE
A13
Valid
A12
Valid
A11
Valid
Bank select
Channel address
A10
A9
Valid
A8
Valid
Channel address
A7
A6
A5
A2 to A4
A1
Valid
A0
Valid
Segment address
22
Preliminary Data Sheet M14412EJ3V0DS00
µPD45125421, 45125821, 45125161
Restore without auto precharge (RST)
/CS
/RAS /CAS
/WE
A13
A12 A11
Low
High
Low
BA
Cha. Cha. Low Cha. Cha. High
High
A10
A9
A8
A7
A6
A5
A4
A3
A2
x
x
x
x
x
A1
A0
Seg. Seg.
Remark BA: Bank address, Cha.: Channel address, x: High or Low level (Don' t care), Seg.: Segment address
This command transfers data from a channel buffer to a segment of a row which is going to be activated by
following ACT command.
The command Bank Address field specifies the destination bank.
The Channel Address fields specify the source channel.
The Segment number field specifies the destination segment.
A10 specify the optional precharge operation.
In case of A10: low, without auto precharge operation occurs. (Please refer to RSTA command.)
In case of A10: high, with auto precharge operation occurs after data fetch operation.
CLK
CKE
H
/CS
/RAS
/CAS
/WE
A13
Valid
A12
Valid
A11
Valid
Bank select
Channel address
A10
A9
Valid
A8
Valid
Channel address
A7
A2 to A6
A1
Valid
A0
Valid
Segment address
Preliminary Data Sheet M14412EJ3V0DS00
23
µPD45125421, 45125821, 45125161
Restore with auto precharge (RSTA)
/CS
/RAS /CAS
/WE
A13
A12 A11
Low
High
Low
BA
Cha. Cha. High Cha. Cha. High
High
A10
A9
A8
A7
A6
A5
A4
A3
A2
x
x
x
x
x
A1
A0
Seg. Seg.
Remark BA: Bank address, Cha.: Channel address, x: High or Low level (Don' t care), Seg.: Segment address
This command transfers data from a channel buffer to a segment of a row which is going to be activated by
following ACT command.
In addition, precharge operation is performed automatically which closes the active row after data restore
operation.
The command Bank Address field specifies the destination bank.
The Channel Address fields specify the source channel.
The Segment number field specifies the destination segment.
A10 specify the optional precharge operation.
In case of A10: low, without auto precharge operation occurs. (Please refer to RSTA command.)
In case of A10: high, with auto precharge operation occurs after data fetch operation.
CLK
CKE
H
/CS
/RAS
/CAS
/WE
A13
Valid
A12
Valid
A11
Valid
Bank select
Channel address
A10
A9
Valid
A8
Valid
Channel address
A7
A2 to A6
A1
Valid
A0
Valid
Segment address
24
Preliminary Data Sheet M14412EJ3V0DS00
µPD45125421, 45125821, 45125161
Channel read (READ)
/CS
/RAS /CAS
/WE
A13
Low
High
High
x
Low
A12 A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
Cha. Cha. Col. Cha. Cha. Col.
Col.
Col.
Col.
Col.
Col.
Col.
Col.
Remark x: High or Low level (Don' t care), Cha.: Channel address, Col.: Column address
Channel Read (READ) reads data words from a channel buffer onto the data bus (DQ). The Channel Address field
specifies the source channel. The Column Address field specifies the starting location of the data word in the buffer
(Data words may be 4, 8, or 16 bits.). The burst-length field in the channel control register for the channel specifies
the number of data words to complete the read operation.
CLK
CKE
H
/CS
/RAS
/CAS
/WE
A13
A12
Valid
A11
Valid
A10
Valid
A9
Valid
A8
Valid
A0 to A7
Valid
Channel address
Column address
Channel address
Column address
Preliminary Data Sheet M14412EJ3V0DS00
25
µPD45125421, 45125821, 45125161
Channel write (WRIT)
/CS
/RAS /CAS
/WE
A13
A7
A6
A5
A4
A3
A2
A1
A0
Low
High
Low
Low Cha. Cha. Col. Cha. Cha. Col.
Col.
Col.
Col.
Col.
Col.
Col.
Col.
Low
A12 A11
A10
A9
A8
Remark x: High or Low level (Don' t care), Cha.: Channel address, Col.: Column address
Channel Write(WRIT) writes data from the data bus (DQ) into a channel buffer. The Channel Address field specifies
the destination channel. The Column Address field specifies the starting location of the data word in the buffer (Data
words may be 4, 8 or 16 bits.).
The burst-length field in the channel control register for the channel specifies the number of data words to complete
the write operation.
CLK
CKE
H
/CS
/RAS
/CAS
/WE
A13
A12
Valid
A11
Valid
A10
Valid
A9
Valid
A8
Valid
A0 to A7
Valid
Channel address
26
Column address
Channel address
Column address
Preliminary Data Sheet M14412EJ3V0DS00
µPD45125421, 45125821, 45125161
Bank activate (ACT)
/CS
/RAS /CAS
/WE
A13
A12 A11
Low
Low
High
BA
Row Row Row Row Row Row Row Row Row Row Row Row Row
High
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
Remark BA: Bank address, Row: Row address
Activation causes row contents to be placed into the bank's sense amplifier. The command Bank Address and
Row Address fields specify bank and row. This device has two banks, each with 8,192 rows. This command
activates the bank selected by bank address(A13) and a row address selected by A0 through A12. The row remains
active for access until a Precharge command is issued to the bank. A Precharge command must be issued before
another row can be activated in that bank. Each bank can have one row active. This command corresponds to a
conventional DRAM’s /RAS falling.
CLK
CKE
H
/CS
/RAS
/CAS
/WE
A13
Valid
Bank select
A0 to A12
Valid
Row address
Preliminary Data Sheet M14412EJ3V0DS00
27
µPD45125421, 45125821, 45125161
Prefetch read with auto precharge (PFR)
/CS
/RAS /CAS
/WE
A13
A7
A6
A5
A4
A3
A2
A1
A0
Low
Low
Low
Seg. Cha. Cha. Seg. Cha. Cha. Col.
Col.
Col.
Col.
Col.
Col.
Col.
Col.
High
A12 A11
A10
A9
A8
Remark Seg.: Segment address, Cha.: Channel address, Col.: Column address
This command needs to follow Bank activate (ACT) command. This command fetches data from a segment of the
activated row in a bank to a channel buffer, and reads data words from a channel buffer onto the data bus (DQ).
In addition, precharge operation is performed automatically, which closes the activated row after data fetch
operation.
The Segment fields specify the source segment. In addition, the Channel Address field specifies the destination
channel.
The Column Address field specifies the starting location of the data word in the buffer (Data words may be 4, 8, or
16 bits.). The burst-length field in the channel control register for the channel specifies the number of data words to
complete the read operation.
For x4 bits organization, this command is illegal.
CLK
CKE
H
/CS
/RAS
/CAS
/WE
A13
Valid
A12
Valid
A11
Valid
A10
Valid
A9
Valid
A8
Valid
A0 to A7
Valid
Segment address
Channel address
28
Segment address
Channel address
Column address
Preliminary Data Sheet M14412EJ3V0DS00
µPD45125421, 45125821, 45125161
Precharge selected bank (PRE)
/CS
/RAS /CAS
/WE
A13
Low
Low
Low
BA
Low
A12 A11
x
x
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
Low
x
x
x
x
Low
x
x
x
x
x
Remark BA: Bank address, x: High or Low level (Don' t care)
This command closes (deactivates) an activated row in a bank, in order to prepare the bank for an Activate or
Restore command to activate a new row. After precharging, a bank is in the Idle state.
The Bank field specifies the bank to precharge and A10 Low specifies the command.
After this command, tRP (precharge to activate command period) must be satisfied for next activate command to
precharging bank.
This command corresponds to a conventional DRAM’s /RAS rising.
CLK
CKE
H
/CS
/RAS
/CAS
/WE
A13
Valid
Bank select
A11,A12
A10
A6 to A9
A5
A0 to A4
Preliminary Data Sheet M14412EJ3V0DS00
29
µPD45125421, 45125821, 45125161
Precharge all banks (PALL)
/CS
/RAS /CAS
/WE
A13
Low
Low
Low
x
Low
A12 A11
x
x
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
High
x
x
x
x
Low
x
x
x
x
x
Remark x: High or Low level (Don' t care)
The signal combination is Reserved (with command modifier A10 High). The PALL command is typically used
during auto refresh operation and initialization. Replace with Precharge commands for each bank.
CLK
CKE
H
/CS
/RAS
/CAS
/WE
A11 to A13
A10
A6 to A9
A5
A0 to A4
30
Preliminary Data Sheet M14412EJ3V0DS00
µPD45125421, 45125821, 45125161
Set Channel Latency Register (SCLR)
/CS
/RAS /CAS
/WE
A13
Low
Low
Low
Low Low Low Low Low Low Low Low High PRL
Low
A12 A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
RL
RL
RL
WT
Remark PRL: Prefetch Read Latency, RL: Read Latency, WT: Wrap Type
This command sets the Read Latency value which specifies read delay time in channel read operation.
In addition, this command sets the Wrap type which specifies the order(Sequential or Interleave) in which the burst
data will be addressed.
Moreover, this command sets the Read Latency value which specifies read delay time in prefetch read operation.
The commands can only be executed with all memory banks idle and no burst operations in progress.
CLK
CKE
H
/CS
/RAS
/CAS
/WE
A6 to A13
A5
A4
Valid
A3
Valid
A2
Valid
A1
Valid
A0
Valid
Prefetch Read Latency
Read Latency
Wrap Type
Preliminary Data Sheet M14412EJ3V0DS00
31
µPD45125421, 45125821, 45125161
Set Channel Control Register (SCCR)
/CS /RAS /CAS
/WE
A13
Low Low
Low
Low Cha. Cha. Cha. Cha. Low Low High High
Low
A12 A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
x
x
BL
BL
BL
Remark Cha.: Channel address, BL: Burst Length, x: High or Low level (Don' t care)
This command sets Burst Length in channel address.
Burst Length for the 0-15 channels is the same.
This command is executed during Initialization.
The commands can only be executed with all memory banks idle and no burst operations in progress.
CLK
CKE
H
/CS
/RAS
/CAS
/WE
A13
A12
Valid
A11
Valid
A10
Valid
A9
Valid
Channel address
A7,A8
A5,A6
A3,A4
32
A2
Valid
A1
Valid
A0
Valid
Burst length
Preliminary Data Sheet M14412EJ3V0DS00
µPD45125421, 45125821, 45125161
Auto Refresh (REF)
CKE
n–1
/CS
/RAS
/CAS
/WE
Address
Low
Low
Low
High
High or Low level (Don' t care)
n
High High
This command is a request to begin the auto refresh operation. The refresh address is generated internally.
Before executing auto refresh, all banks must be in the idle state. After this cycle, all banks will be in the idle
(precharged) state and ready for a row activate command. During tRC period (from refresh command to refresh or
activate command), the VirtualChannel SDRAM cannot accept any other command.
n−1
n
H
H
CLK
CKE
/CS
/RAS
/CAS
/WE
A0 to A13
Preliminary Data Sheet M14412EJ3V0DS00
33
µPD45125421, 45125821, 45125161
Self Refresh (SELF)
CKE
n–1
/CS
/RAS
/CAS
/WE
Address
Low
Low
Low
High
High or Low level (Don' t care)
n
High Low
After the command execution, self refresh operation continues while CKE remains low. During self refresh mode,
the internal refresh controller takes care of refresh interval and refresh operation. There is no need for external
control. Before executing self refresh, both banks must be in the idle state.
During self refresh mode, both background and foreground operation can not be executed.
n−1
n
H
L
CLK
CKE
/CS
/RAS
/CAS
/WE
A0 to A13
34
Preliminary Data Sheet M14412EJ3V0DS00
µPD45125421, 45125821, 45125161
4. Simplified State Diagram
IDLE
Stand by
CKE:low
Power
Down
CKE:high
SELF
Self
Refresh
SELF exit
REF
CLR
S
Set
Channel Latency
Register
Auto
Refresh
CR
SC
Active
Power
Down
ACT
AD
RE
low
Write
Suspend
E:
CK
T
READ
READ
D
REA
AD
AD
RE
RE
READ
T
RI
W
WRIT
WRIT
Active
stand by
AD
IT
T
RE
WR
RI
Channel
Read
READ
AC
T
AC
WRIT
W
CK
IT
WR
Channel
Write
WRIT
AD
AC
T
IT
WR
CK
RE
ACT
igh
:low
E:h
CK
CKE
Row
Active
Read
Suspend
igh
h
E:
E:lo
w
CKE
:hig
h
Set
Channel Control
Register
PFR
E
PRE
PR
E
PR
RS
T
RST
RST
Auto Precharge
Precharge
PRE
without
Auto Precharge
PF
PFC
PFCA
CA
PF
Auto Precharge
Prefetch
Restore
without
PFC
with
PFC
Restore
TA
RS
C
PF
RSTA
RST
A
Prefetch
Read
CA
Prefetch
PFCA
with
Auto Precharge
Automatic sequence
Power ON
PRE
Manual input
foreground
operation
background
operation
Preliminary Data Sheet M14412EJ3V0DS00
35
µPD45125421, 45125821, 45125161
5. Prefetch Read Operation ( Optional )
This operation fetches data from a segment of the activated row in a bank to a channel buffer, and reads data words
from a channel buffer onto the data bus (DQ). In addition, precharge operation is performed automatically, which
closes the activated row after data fetch operation.
For x4 bits organization, prefetch read operation can not be used (PFR command is illegal).
Prefetch Operation
Segment
Input and Output Buffer
Segment
Segment
DQ
Prefetch Read Operation
Segment
Segment
Segment
Bank A
Read Operation
Segment
Segment
Bank B
16 Channels
Row Decoder
DQ
Row Decoder
( Burst length = 4 )
0
1
2
3
4
5
6
7
8
Q0
Q1
Q2
Q3
Q0
Q1
Q2
Q3
CLK
tAPD
Command
ACT
PFC
READ
Read latency = 2
DQ
Hi-Z
tAPRD
Command
DQ
ACT
Hi-Z
PFR
Prefetch read latency = 4
The relationship between clock frequency and read latency, prefetch read latency
Clock frequency MHz(MAX.)
133
100
67
50
36
Read latency
Prefetch read latency
2
4
1
2
Preliminary Data Sheet M14412EJ3V0DS00
µPD45125421, 45125821, 45125161
6. Write Operation and Restore Operation
Write command proceeds write operation to the channel. When the system needs to refill the channel with new
data, restore operation may be necessary. The restore operation needs both restore command and active command.
Restore command must be first command. Restore operation is also fully associative operation.
The data in the channel can be transferred to anywhere on memory core array. Another write and read operation to
another channel can proceed during this restore operation.
The another background operation is illegal while tRAD (RST/RSTA to ACT(R) command delay time).
In addition, the foreground operation to the same channel set by RST command is illegal too.
DQ
Segment
Input and Output Buffer
Segment
Segment
Segment
Segment
Bank A
Segment
Segment
Bank B
Segment
16 Channels
Row Decoder
Write Operation
( to channel )
Restore Operation
(from Channel to Segment)
Row Decoder
DQ
( Burst length = 2 )
0
1
2
3
4
5
6
7
8
READ
PRE
CLK
tRCD
Command
ACT (R)
RST
WRIT
tRAS
tRAD
Channel
Channel 1
Channel 1
Address
Col. 0
Segment
Row 0
Col. 1
A13
BankA
BankA
BankA
BankA
A10
without
Auto
Precharge
with
Auto
Precharge
L
Channel 1
DQM
DQ
Remark
D1-0
D1-1
Hi-Z
Q1-1
ACT(R) command is ACT command after RST command.
Preliminary Data Sheet M14412EJ3V0DS00
37
µPD45125421, 45125821, 45125161
7. Set Register Operation
JEDEC standard test set (Refresh counter test)
A13
0
A12
0
A11
0
0
A10
A9
0
A8
0
A7
1
A6
,
Don t
care
A5
A4
A3
A2
A1
A0
,
Don t care
1
Use in future
A13
A12
A11
A10
A9
A8
A7
A6
A4
A3
A2
A1
A0
A5
A4
A3
A2
A1
A0
A1
A0
1
0
1
A5
Vender specification
A13
A12
A11
A10
A9
,
Don t care
A8
1
A7
1
A6
Valid
data input
1
Valid data input
Mode register set
A13
A12
A11
Valid data input
A10
A9
A8
0
A7
0
A6
A5
1
A4
A3
A2
Valid data input
A6(0) Set Channel Latency Register (SCLR)
A6(1) Set Channel Control Register (SCCR)
38
Preliminary Data Sheet M14412EJ3V0DS00
µPD45125421, 45125821, 45125161
8. Set Channel Latency Register (SCLR)
CLK
CKE
H
/CS
/RAS
/CAS
/WE
A0
Valid
A1
Valid
A2
Valid
A3
Valid
A4
Valid
A5
A6
A7
A8
A9
A10
A11
A12
A13
A13
0
0
A12
0
A11
0
A10
0
A9
A8
0
A7
0
A6
0
A5
A4
A3
A2
A1
A0
1
Wrap type
A0
0
1
Wrap type
Sequential
Interleave
Read latency and Prefetch read latency
A4
A2
A1
Read latency
0
1
0
1
0
0
1
1
1
1
0
0
1
1
2
2
Prefetch
read latency
2
3
3
4
Remark
legal
illegal
illegal
legal
Remark For x4 bits organization, Prefetch read latency (A4) is don't care.
Preliminary Data Sheet M14412EJ3V0DS00
39
µPD45125421, 45125821, 45125161
9. Set Channel Control Register (SCCR)
CLK
CKE
H
/CS
/RAS
/CAS
/WE
A0
Valid
A1
Valid
A2
Valid
A3
A4
A5
A6
A7
A8
A9
Valid
A10
Valid
A11
Valid
A12
Valid
A13
A13
0
A12
A11
A10
A9
A8
0
Channel address
A7
0
A6
1
A5
1
A4
,
Don t care
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
40
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
A11
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
A10
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
A2
A1
Burst length
Burst length
Channel number
Channel number A12
A3
A9
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Sequential
1
2
4
8
16
Reserved
Reserved
Reserved
Preliminary Data Sheet M14412EJ3V0DS00
Interleave
1
2
4
8
16
Reserved
Reserved
Reserved
A2
0
0
0
0
1
1
1
1
A1
0
0
1
1
0
0
1
1
A0
0
1
0
1
0
1
0
1
A0
µPD45125421, 45125821, 45125161
10. Burst Length and Sequence
[Burst of Two]
Starting Address
Addressing Sequence
Addressing Sequence
(column address A0)
Sequential
Interleave
(binary)
(decimal)
(decimal)
0
0, 1
0, 1
1
1, 0
1, 0
[Burst of Four]
Starting Address
Addressing Sequence
Addressing Sequence
(column address A1,A0)
Sequential
Interleave
(binary)
(decimal)
(decimal)
00
0, 1, 2, 3
0, 1, 2, 3
01
1, 2, 3, 0
1, 0, 3, 2
10
2, 3, 0, 1
2, 3, 0, 1
11
3, 0, 1, 2
3, 2, 1, 0
Starting Address
Addressing Sequence
Addressing Sequence
(column address A2-A0)
Sequential
Interleave
(binary)
(decimal)
(decimal)
000
0, 1, 2, 3, 4, 5, 6, 7
0, 1, 2, 3, 4, 5, 6, 7
001
1, 2, 3, 4, 5, 6, 7, 0
1, 0, 3, 2, 5, 4, 7, 6
010
2, 3, 4, 5, 6, 7, 0, 1
2, 3, 0, 1, 6, 7, 4, 5
011
3, 4, 5, 6, 7, 0, 1, 2
3, 2, 1, 0, 7, 6, 5, 4
100
4, 5, 6, 7, 0, 1, 2, 3
4, 5, 6, 7, 0, 1, 2, 3
101
5, 6, 7, 0, 1, 2, 3, 4
5, 4, 7, 6, 1, 0, 3, 2
110
6, 7, 0, 1, 2, 3, 4, 5
6, 7, 4, 5, 2, 3, 0, 1
111
7, 0, 1, 2, 3, 4, 5, 6
7, 6, 5, 4, 3, 2, 1, 0
[Burst of Eight]
Preliminary Data Sheet M14412EJ3V0DS00
41
µPD45125421, 45125821, 45125161
[Burst of Sixteen]
42
Starting Address
Addressing Sequence
Addressing Sequence
(column address A3-A0)
Sequential
Interleave
(binary)
(decimal)
(decimal)
0000
0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15
0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15
0001
1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,0
1,0,3,2,5,4,7,6,9,8,11,10,13,12,15,14
0010
2,3,4,5,6,7,8,9,10,11,12,13,14,15,0,1
2,3,0,1,6,7,4,5,10,11,8,9,14,15,12,13
0011
3,4,5,6,7,8,9,10,11,12,13,14,15,0,1,2
3,2,1,0,7,6,5,4,11,10,9,8,15,14,13,12
0100
4,5,6,7,8,9,10,11,12,13,14,15,0,1,2,3
4,5,6,7,0,1,2,3,12,13,14,15,8,9,10,11
0101
5,6,7,8,9,10,11,12,13,14,15,0,1,2,3,4
5,4,7,6,1,0,3,2,13,12,15,14,9,8,11,10
0110
6,7,8,9,10,11,12,13,14,15,0,1,2,3,4,5
6,7,4,5,2,3,0,1,14,15,12,13,10,11,8,9
0111
7,8,9,10,11,12,13,14,15,0,1,2,3,4,5,6
7,6,5,4,3,2,1,0,15,14,13,12,11,10,9,8
1000
8,9,10,11,12,13,14,15,0,1,2,3,4,5,6,7
8,9,10,11,12,13,14,15,0,1,2,3,4,5,6,7
1001
9,10,11,12,13,14,15,0,1,2,3,4,5,6,7,8
9,8,11,10,13,12,15,14,1,0,3,2,5,4,7,6
1010
10,11,12,13,14,15,0,1,2,3,4,5,6,7,8,9
10,11,8,9,14,15,12,13,2,3,0,1,6,7,4,5
1011
11,12,13,14,15,0,1,2,3,4,5,6,7,8,9,10
11,10,9,8,15,14,13,12,3,2,1,0,7,6,5,4
1100
12,13,14,15,0,1,2,3,4,5,6,7,8,9,10,11
12,13,14,15,8,9,10,11,4,5,6,7,0,1,2,3
1101
13,14,15,0,1,2,3,4,5,6,7,8,9,10,11,12
13,12,15,14,9,8,11,10,5,4,7,6,1,0,3,2
1110
14,15,0,1,2,3,4,5,6,7,8,9,10,11,12,13
14,15,12,13,10,11,8,9,6,7,4,5,2,3,0,1
1111
15,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14
15,14,13,12,11,10,9,8,7,6,5,4,3,2,1,0
Preliminary Data Sheet M14412EJ3V0DS00
µPD45125421, 45125821, 45125161
11. Initialization
The VirtualChannel SDRAM is initialized in the power-on sequence according to the following.
(1) To stabilize internal circuits, when power is applied, a 100 µs or longer pause must precede any signal toggling.
(2) After the pause, both banks must be precharged using the Precharge command (The Precharge all banks
command is convenient).
(3) Once the precharge is completed and the minimum tRP is satisfied, the mode register can be programmed.
After the mode register set cycle, tRSC (2 CLK minimum) pause must be satisfied as well.
(4) Two or more auto refresh must be performed.
Remarks 1. The sequence of Mode register programming and Refresh above may be transposed.
2. CKE and DQM must be held high until the Precharge command is issued to ensure data-bus Hi-Z.
Preliminary Data Sheet M14412EJ3V0DS00
43
µPD45125421, 45125821, 45125161
12. Electrical Specifications (Target)
• All voltages are referenced to VSS (GND).
• After power up, wait more than 100 µs and then, execute Power on sequence and Auto Refresh before proper
device operation is achieved.
Absolute Maximum Ratings
Parameter
Symbol
Rating
Unit
VCC, VCCQ
–0.5 to +4.6
V
Voltage on input pin relative to GND
VT
–0.5 to +4.6
V
Short circuit output current
IO
50
mA
Power dissipation
PD
1
W
Operating ambient temperature
TA
0 to 70
°C
Storage temperature
Tstg
–55 to +125
°C
Voltage on power supply pin relative to GND
Caution
Condition
Exposing the device to stress above those listed in Absolute Maximum Ratings could cause
permanent damage. The device is not meant to be operated under conditions outside the limits
described in the operational section of this specification. Exposure to Absolute Maximum Rating
conditions for extended periods may affect device reliability.
Recommended Operating Conditions
Parameter
Symbol
Supply voltage
Condition
VCC, VCCQ
High level input voltage
VIH
MIN.
TYP.
MAX.
3.0
3.3
3.6
VCC + 0.3
2.0
Low level input voltage
VIL
–0.3
Operating ambient temperature
TA
0
Note2
Unit
V
Note1
V
+0.8
V
70
°C
Notes 1. VIH (MAX.) = VCC + 1.5 V (Pulse width ≤ 5 ns)
2. VIL (MIN.) = –1.5 V (Pulse width ≤ 5 ns)
★
Capacitance (TA = 25 °C, f = 1 MHz)
Parameter
Input capacitance
Data input/output capacitance
44
Symbol
Test condition
MIN.
MAX.
Unit
3.5
pF
CI1
CLK
-A10
2.5
4.0
CI2
A0 - A13,CKE, /CS,/RAS, /CAS,
-A75
2.5
3.8
/WE,DQM, UDQM, LDQM
-A10
2.5
4.0
4.0
6.5
CI/O
-A75
DQ
Preliminary Data Sheet M14412EJ3V0DS00
2.5
TYP.
pF
µPD45125421, 45125821, 45125161
★
DC Characteristics 1 (Recommended Operating Conditions unless otherwise noted)
Parameter
Symbol
Test condition
Grade
Read
Latency
Operating current
ICC1P
tRC ≥ tRC(MIN.)
( Prefetch mode at one
Prefetch is executed one time
bank active )
during tRC.
Operating current
ICC1R
tRC ≥ tRC(MIN.)
RL=1
RL=2
150
-A10
RL=1
TBD
RL=2
130
RL=1
TBD
RL=2
150
RL=1
TBD
RL=2
130
( Restore mode at one
Precharge standby current
-A10
ICC2P
1.2
ICC2PS CKE ≤ VIL(MAX.), tCK = ∞
Precharge standby current
in non power down mode
ICC2N CKE ≥ VIH(MIN.), tCK = 15 ns
/CS≥VIH(MIN.),
Input signals are changed one time during 30 ns.
CKE ≥ VIH(MIN.), tCK = ∞
ICC2NS
Input signals are stable.
ICC3P
ICC3N CKE ≥ VIH(MIN.), tCK = 15 ns
/CS ≥ VIH(MIN.)
Input signals are changed one time during 30 ns.
CKE≥VIH(MIN.),tCK=∞
ICC3NS
Input signals are stable.
(Burst mode)
IO = 0 mA,
ICC5
-A10
-A75
-A10
Self refresh current
ICC6
mA
30
mA
20
RL=1
RL=2
tRCF ≥ tRCF(MIN.)
1
10
TBD
60
65
RL=1
RL=2
Auto refresh current
mA
6
-A75
Background: precharge standby
1
mA
6
ICC3PS CKE ≤ VIL(MAX.), tCK = ∞
tCK ≥ tCK(MIN.),
mA
mA
20
CKE ≤ VIL(MAX.), tCK = 15 ns
Active standby current in
non power down mode
ICC4
Unit Notes
1.2
power down mode
Operating current
TBD
CKE ≤ VIL(MAX.), tCK = 15 ns
in power down mode
Active standby current in
Maximum.
x8
x16
-A75
-A75
bank active )
x4
mA
2
mA
3
75
TBD
45
50
75
RL=1
TBD
RL=2
230
RL=1
TBD
RL=2
220
CKE ≤ 0.2 V
2
mA
Notes 1. ICC1 depends on cycle rates. In addition to this, ICC1 is measured on condition that addresses are changed
only one time during tCK(MIN.).
2. ICC4 depends on output loading and cycle rates. Specified values are obtained with the output open. In
addition to this, ICC4 is measured on condition that addresses are changed only one time during tCK(MIN.).
3. ICC5 is measured on condition that addresses are changed only one time during tCK(MIN.).
DC Characteristics 2 (Recommended Operating Conditions unless otherwise noted)
Parameter
Input leakage current
Symbol
II(L)
Test condition
0 ≤ VI ≤ VCCQ, VCCQ = VCC
MIN.
TYP.
MAX.
Unit
– 1.0
–
+ 1.0
µA
– 1.5
–
+ 1.5
µA
Note
All other pins not under test = 0 V
Output leakage current
IO(L)
0 ≤ VO ≤ VCCQ, DOUT is disabled.
High level output voltage
VOH
IO = – 4 mA
2.4
–
–
V
Low level output voltage
VOL
IO = + 4 mA
–
–
0.4
V
Preliminary Data Sheet M14412EJ3V0DS00
45
µPD45125421, 45125821, 45125161
AC Characteristics (Recommended Operating Conditions unless otherwise noted)
Test Conditions
• AC measurements assume tT = 1 ns.
• Reference level for measuring timing of input signals is 1.4 V. Transition times are measured between VIH and VIL.
• If tT is longer than 1 ns, reference level for measuring timing of input signals is VIH(MIN.) and VIL(MAX.).
• An access time is measured at 1.4 V.
tCK2
tCK2
tCL
tCH
tCH
tCL
CLK
tCKH
tCKS
CKE
tS
Command
Address
DQM
(Input)
tH
Valid
tDS
Data (Input)
tDH
Valid
46
Hi-Z
tDH
Valid
tAC2
tAC2
tLZ
Data (Output)
tDS
tOH2
Valid
Preliminary Data Sheet M14412EJ3V0DS00
tHZ
Valid
Hi-Z
µPD45125421, 45125821, 45125161
AC characteristics(Target)
Parameter
★
★
★
Symbol
-A75
-A10
Unit
MIN.
MAX.
MIN.
MAX.
RL=1
tCK1
15
−
20
−
ns
RL=2
tCK2
7.5
−
10
−
ns
RL=1
tAC1
−
12
−
15
ns
RL=2
tAC2
−
5.4
−
6
ns
CLK high level width
tCH
2.5
−
3
−
ns
CLK low level width
tCL
2.5
−
3
−
ns
Data-out hold time
tOH
2.7
−
3
−
ns
Data-out low-impedance time
tLZ
0
−
0
−
ns
RL=1
tHZ1
2.5
12
3
15
ns
RL=2
tHZ2
2.5
5.4
3
6
ns
Data-in setup time
tDS
1.5
−
2
−
ns
Data-in hold time
tDH
0.8
−
1
−
ns
Address, Command, DQM setup time
tS
1.5
−
2
−
ns
Address, Command, DQM hold time
tH
0.8
−
1
−
ns
CKE setup time
tCKS
1.5
−
2
−
ns
CKE hold time
tCKH
0.8
−
1
−
ns
CKE setup time (Power down exit)
tCKSP
1.5
−
2
−
ns
tT
0.8
30
1
30
ns
Refresh time (4,096 refresh cycle)
tREF
−
64
−
64
ms
Mode register set cycle time
tRSC
2
−
2
−
CLK
Clock cycle time
Access time from CLK
Data-out high-impedance time
Transition time
Note
1
1
Note1 Output load.
Z = 50 Ω
Output
50 pF
Preliminary Data Sheet M14412EJ3V0DS00
47
µPD45125421, 45125821, 45125161
AC characteristics (Background to Background operation)
Parameter
Symbol
-A 75
-A10
Unit
Notes
MIN. MAX. MIN. MAX.
SAME BANK OPERATION
ACT to ACT/REF Command period
tRC
67.5
−
80
−
ns
REF to REF/ ACT Command period
tRCF
67.5
−
90
−
ns
ACT to PRE Command period
tRAS
52.5 120,000
60
120,000
ns
PRE to ACT / REF Command period
tRP
20
−
20
−
ns
ACT to PFC/PFCA Command delay time
tAPD
15
−
20
−
ns
ACT to PFR Command delay time
tAPRD
15
−
20
−
ns
PFC to PRE Command delay time
tPPL
22.5
−
30
−
ns
PFCA / PFR to ACT/REF Command delay time
tPAL
45
−
50
−
ns
tRAD
7.5
30
10
40
ns
tRPD
37.5
−
40
−
ns
tPPD
22.5
−
30
−
ns
tRRD
15
−
20
−
ns
ACT(R) to ACT(R) Command delay time
tRRDR
30
−
40
−
ns
PFC /PFCA to RST /RSTA Command delay time
tPRD
22.5
−
30
−
ns
3
(Prefetch Read Operation)
RST / RSTA to ACT(R)
Note1
Command delay time
2
SAME,OTHER BANK OPERATION
ACT(R)
Note1
to PFC/PFCA/PFR
Command delay time
PFC to PFC / PFCA Command delay time
OTHER BANK OPERATION
ACT to ACT/ACT(R) or ACT(R) to ACT
Command delay time
Notes 1 ACT(R) command is ACT command after RST command.
2 The another background operation and same channel foreground operation are illegal while tRAD period.
3 For x4 bits organization, prefetch read operation can not used.
48
Preliminary Data Sheet M14412EJ3V0DS00
µPD45125421, 45125821, 45125161
AC characteristics (Foreground to Foreground operation)
Parameter
READ/WRITE to READ/WRITE
Symbol
tCCD
-A75
-A 10
Unit
MIN.
MAX.
MIN.
MAX.
7.5
−
10
−
Note
ns
Command delay time
AC characteristics (Background to Foreground operation)
(after same channel Prefetch/Restore)
Parameter
PFC/PFCA to READ/WRITE
Symbol
-A75
-A 10
Unit
MIN.
MAX.
MIN.
MAX.
tPCD
15
−
20
−
ns
tRCD
30
−
40
−
ns
Note
Command delay time
ACT(R) to READ/WRITE
1
Command delay time
Note1 ACT(R) command is ACT command after RST command.
Preliminary Data Sheet M14412EJ3V0DS00
49
µPD45125421, 45125821, 45125161
Power on Sequence and Auto Refresh
0
1
2
3
4
5
6
7
8
16
17
25
26
CLK
Command
SCLR
PALL
tRSC
tRP
Address
A10
tRSC
tRSC
Read latency
Burst length
Burst length
Wrap type
Channel
Channel
tRCF
L
L
A6
L
H
H
L
It is necessary to input SCCR command 16 times
(16 channels)
to set burst length for channel.
DQM
Hi-Z
1st
SCCR
50
tRCF
Row 1
BankA
L
DQ
ACT
REF
H
A7, A8
A5
REF
SCCR
SCCR
2nd
SCCR
Preliminary Data Sheet M14412EJ3V0DS00
µPD45125421, 45125821, 45125161
/CS Function (Only /CS signal needs to be issued at minimum rate)
( Read latency = 2, Burst length = 2 )
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
CLK
CKE
H
/CS
/RAS
/CAS
/WE
A13
Bank
Bank
A8,A9,A11,A12
Row
Channel
A10
Row
A5,A6,A7
Channel
Channel
Row
Column
Column
A2,A3,A4
Row
Column
Column
A0,A1
Row
Column
Column
DQM
DQ
Command
Segment
L
Hi-Z
Q1-0
ACT
PFC
Q1-1
READ
Preliminary Data Sheet M14412EJ3V0DS00
D1-0
D1-1
WRIT
51
µPD45125421, 45125821, 45125161
Clock Suspension during Burst Read (using CKE Function)
( Read latency = 2, Burst length = 4 )
0
1
2
3
4
5
6
7
8
Q1-0
Q1-1
9
10
11
12
13
14
15
CLK
CKE
tPCD
tAPD
Command
ACT
Channel
PFC
READ
Channel
1
Channel
1
Col. 0
Address
Row 0
Segment
1
A13
BankA
BankA
without
Auto
Precharge
A10
DQM
DQ
L
Hi-Z
Q1-2
1 clock
suspend
52
Preliminary Data Sheet M14412EJ3V0DS00
Q1-3
2 clocks
suspend
3 clocks
suspend
16
µPD45125421, 45125821, 45125161
Clock Suspension during Burst Write (using CKE Function)
( Burst length = 4 )
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
CLK
CKE
tPCD
tAPD
Command
ACT
Channel
PFC
WRIT
Channel
1
Channel
1
Col. 0
Address
Row 0
Segment
1
A13
BankA
BankA
without
Auto
Precharge
A10
DQM
DQ
L
Hi-Z
1 clock
suspend
D1-3
D1-2
D1-1
D1-0
2 clocks
suspend
Preliminary Data Sheet M14412EJ3V0DS00
3 clocks
suspend
53
µPD45125421, 45125821, 45125161
Power Down Mode
( Read latency = 2, Burst length = 2 )
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
CLK
tCKSP
tCKSP
CKE
Command
PRE
PFC
READ
Channel
Channel
1
Channel
1
Address Row 0
Segment
1
Col. 0
A13 BankA
BankA
BankA
A10
without
Auto
Precharge
L
DQM
DQ
ACT
L
Hi-Z
Q1-0
Power down mode
entry
Power down mode
exit
Q1-1
Power down mode
entry
Active standby
54
Power down mode
exit
Precharge standby
Preliminary Data Sheet M14412EJ3V0DS00
µPD45125421, 45125821, 45125161
Set Register Operation
0
1
2
3
4
5
6
7
8
CLK
tRSC
Command
tRSC
SCLR
SCCR
SCLR
Read latency,
Channel,
Burst lenght
Read latency,
Wrap type
A6
L
H
L
A7 to A8
L
L
L
Channel
Address
DQM
DQ
Wrap type
L
Hi-Z
Preliminary Data Sheet M14412EJ3V0DS00
55
µPD45125421, 45125821, 45125161
Read Operation
( Burst length = 4 )
0
1
2
3
4
CLK
Command
READ
Read latency = 2
DQM
DQ
L
Hi-Z
Q1
Q0
Q2
Q3
Write Operation
0
1
3 ( Burst length = 4 )
2
CLK
WRIT
Command
Write latency = 0
DQM
DQ
56
L
D0
D1
D2
Preliminary Data Sheet M14412EJ3V0DS00
D3
µPD45125421, 45125821, 45125161
DQM Operation in READ
( Burst length = 4 )
CLK
DQM
Read mask latency = 2
DQ
Hi-Z
Mask
Q0
Q1
Hi-Z
Q3
DQM Operation in WRITE
( Burst length = 4 )
CLK
DQM
Write mask latency = 0
DQ
Mask
D1
Preliminary Data Sheet M14412EJ3V0DS00
Mask
D3
57
µPD45125421, 45125821, 45125161
Read to Read Operation
( Read latency = 2, Burst length = 4 )
0
1
2
3
4
5
6
7
8
Q1-3
Q3-0
Q3-1
Q3-2
CLK
Command
READ
READ
tCCD
Channel
Channel 1
Channel 3
Address
Col. 0
Col. 0
DQM
L
DQ
Hi-Z
Q1-0
Q1-1
Q1-2
Q3-3
Write to Write Operation
( Burst length = 4 )
0
1
2
3
4
5
6
7
8
D3-1
D3-2
D3-3
CLK
Command
WRIT
WRIT
tCCD
Channel
Channel 1
Channel 3
Address
Col. 0
Col. 0
DQM
DQ
★
58
L
Hi-Z
D1-0
D1-1
D1-2
D1-3
D3-0
Preliminary Data Sheet M14412EJ3V0DS00
µPD45125421, 45125821, 45125161
Read to Write Operation
( Burst length = 8 )
0
1
2
3
4
5
6
7
8
D3-1
D3-2
CLK
Command
READ
WRIT
tCCD
Channel
Channel 1
Channel 3
Address
Col. 0
Col. 0
DQM
L
Hi-Z
DQ
Q1-0
Q1-1
Q1-2
D3-0
D3-3
Write to Read Operation
( Burst length = 8 )
0
1
2
3
4
5
6
7
8
Q3-0
Q3-1
Q3-2
CLK
Command
WRIT
READ
tCCD
Channel
Channel 1
Channel 3
Address
Col. 0
Col. 0
DQM
DQ
L
Hi-Z
D1-0
D1-1
D1-2
Hi-Z
Preliminary Data Sheet M14412EJ3V0DS00
Q3-3
59
µPD45125421, 45125821, 45125161
Prefetch to Read Operation without Auto Precharge (Same Channel Read)
( Read latency = 2, Burst length = 4 )
0
1
2
3
4
5
6
7
8
CLK
tAPD
Command
ACT
tPCD
PFC
READ
PRE
ACT
tRAS
Channel
tRP
Channel 1
Channel 1
tRC
Address
Row 0
Segment
A13
BankA
BankA
BankA
without
Auto
Precharge
L
A10
DQM
Col. 0
Row 1
BankA
L
Hi-Z
DQ
Q1-0
Q1-1
Q1-2
Q1-3
Prefetch to Read Operation without Auto Precharge (Other Channel Read)
( Read latency = 2, Burst length = 4 )
0
1
2
3
4
5
6
7
PRE
READ
8
CLK
tPPL
Command
ACT
Channel
READ
Channel 1
Channel 4
Channel 5
Col. 0
Col. 7
Address
Row 0
Segment
A13
BankA
BankA
BankA
without
Auto
Precharge
L
A10
DQM
DQ
60
PFC
L
Hi-Z
Q4-0
Preliminary Data Sheet M14412EJ3V0DS00
Q4-1
Q4-2
Q5-7
µPD45125421, 45125821, 45125161
Prefetch to Write Operation without Auto Precharge (Same Channel Write)
( Burst length = 4 )
0
1
2
3
4
5
6
7
8
CLK
tAPD
Command
ACT
tPCD
PFC
WRIT
PRE
ACT
tRAS
Channel
tRP
Channel 1
Channel 1
tRC
Address
Row 0
Segment
A13
BankA
BankA
BankA
without
Auto
Precharge
L
A10
DQM
Col. 0
Row 1
BankA
L
Hi-Z
DQ
D1-0
D1-1
D1-2
D1-3
Prefetch to Write Operation without Auto Precharge (Other Channel Write)
( Burst length = 4 )
0
1
2
3
4
5
6
7
PRE
WRIT
8
CLK
tPPL
Command
ACT
Channel
PFC
WRIT
Channel 1
Channel 4
Channel 3
Col. 0
Col. 7
Address
Row 0
Segment
A13
BankA
BankA
BankA
without
Auto
Precharge
L
A10
DQM
DQ
L
Hi-Z
D4-0
D4-1
Preliminary Data Sheet M14412EJ3V0DS00
D4-2
D3-7
D3-8
D3-9
61
µPD45125421, 45125821, 45125161
Read to Prefetch to Read Operation without Auto Precharge (Same Channel Prefetch)
( Read latency = 2, Burst length = 8 )
0
1
2
3
4
5
6
7
READ
PRE
8
CLK
tAPD
Command
READ
ACT
tPPL
PFC
tPCD
Channel
Channel 1
Address
Col. 0
A13
Channel 1
Channel 1
Row 0
Segment
Col. 7
BankA
BankA
BankA
without
Auto
Precharge
L
A10
DQM
Hi-Z
DQ
Q1-0
Q1-1
Q1-2
Q1-3
Q1-7
Q1-8
Prefetch
Termination
Read to Prefetch to Write Operation without Auto Precharge (Same Channel Prefetch)
( Read latency = 2, Burst length = 8 )
0
1
2
3
4
5
6
7
WRIT
PRE
8
CLK
tAPD
Command
READ
ACT
tPPL
PFC
tPCD
Channel
Channel 1
Address
Col. 0
A13
Channel 1
Channel 1
Row 0
Segment
Col. 3
BankA
BankA
BankA
without
Auto
Precharge
L
A10
DQM
Prefetch Termination
DQ
62
Hi-Z
Q1-0
Q1-1
Q1-2
Preliminary Data Sheet M14412EJ3V0DS00
D1-3
D1-4
D1-5
D1-6
µPD45125421, 45125821, 45125161
Write to Prefetch to Write Operation without Auto Precharge (Same Channel Prefetch)
( Burst length = 8 )
0
1
2
3
4
5
6
7
8
WRIT
PRE
CLK
tAPD
Command
WRIT
ACT
tPPL
PFC
tPCD
Channel
Channel 1
Address
Col. 0
A13
Channel 1
Channel 1
Row 0
Segment
Col. 1
BankA
BankA
BankA
without
Auto
Precharge
L
A10
DQM
Hi-Z
DQ
D1-0
D1-1
D1-2
D1-3
MASK
Prefetch Termination
D1-4
D1-1
D1-2
D1-3
Write to Prefetch to Read Operation without Auto Precharge (Same Channel Prefetch)
( Read latency = 2, Burst length = 8 )
0
1
2
3
4
5
6
7
8
READ
PRE
CLK
tAPD
Command
WRIT
ACT
tPPL
PFC
tPCD
Channel
Channel 1
Address
Col. 0
Channel 1
A13
Channel 1
Row 0
Segment
BankA
BankA
BankA
without
Auto
Precharge
L
A10
Col. 1
DQM
MASK
DQ
Hi-Z
D1-0
D1-1
D1-2
D1-3
D1-4
Preliminary Data Sheet M14412EJ3V0DS00
Prefetch Termination
Q1-1
63
µPD45125421, 45125821, 45125161
Restore to Read Operation without Auto Precharge (Same Channel Read)
( Read latency = 2, Burst length = 4 )
0
1
2
3
4
5
6
READ
PRE
7
8
CLK
tRCD
Command
ACT (R)
RST
tRAD
tRAS
Channel
Channel 1
Address
Segment
Row 0
A13
BankA
BankA
A10
without
Auto
Precharge
DQM
L
DQ
Remark
Channel 1
Col. 0
BankA
L
Hi-Z
Q1-0
Q1-1
Q1-2
ACT(R) command is ACT command after RST command.
Restore to Read Operation without Auto Precharge (Other Channel Read)
( Read latency = 2, Burst length = 4 )
0
1
RST
ACT (R)
2
3
4
5
6
7
8
Q7-2
Q7-3
CLK
Command
READ
tRAD
Channel 1
Address
Segment
Row 0
A13
BankA
BankA
A10
without
Auto
Precharge
DQM
L
Remark
64
tRAS
Channel
DQ
PRE
Channel 7
Col. 0
BankA
L
Hi-Z
Q7-0
ACT(R) command is ACT command after RST command.
Preliminary Data Sheet M14412EJ3V0DS00
Q7-1
µPD45125421, 45125821, 45125161
Restore to Write Operation without Auto Precharge (Same Channel Write)
( Burst length = 4 )
0
1
2
3
4
5
6
WRIT
PRE
7
8
D1-2
D1-3
CLK
tRCD
Command
ACT (R)
RST
tRAS
tRAD
Channel
Channel 1
Address
Segment
Row 0
A13
BankA
BankA
A10
without
Auto
Precharge
DQM
L
Col. 0
BankA
L
Hi-Z
DQ
Remark
Channel 1
D1-0
D1-1
ACT(R) command is ACT command after RST command.
Restore to Write Operation without Auto Precharge (Other Channel Write)
( Burst length = 4 )
0
1
RST
ACT (R)
2
3
4
5
6
7
8
CLK
Command
WRIT
tRAS
tRAD
Channel
Channel 1
Address
Segment
Row 0
A13
BankA
BankA
A10
without
Auto
Precharge
DQM
L
DQ
Remark
Hi-Z
PRE
Channel 3
Col. 0
BankA
L
D3-0
D3-1
D3-2
D3-3
ACT(R) command is ACT command after RST command.
Preliminary Data Sheet M14412EJ3V0DS00
65
µPD45125421, 45125821, 45125161
Read to Restore to Read Operation without Auto Precharge (Same Channel Restore)
( Read latency = 2, Burst length = 4 )
0
1
2
3
4
5
6
7
8
READ
PRE
CLK
tRCD
Command
ACT (R)
RST
READ
tRAD
tRAS
Channel
Channel 1
Channel 1
Address
Col. 0
Segment
Row 0
A13
BankA
BankA
A10
without
Auto
Precharge
DQM
Col. 4
BankA
L
L
Restore Termination
Hi-Z
DQ
Remark
Channel 1
Q1-0
Q1-1
Q1-4
ACT(R) command is ACT command after RST command.
Read to Restore to Write Operation without Auto Precharge (Same Channel Restore)
( Read latency = 2, Burst length = 8 )
0
1
2
3
4
5
6
7
8
WRIT
PRE
CLK
tRCD
Command
READ
ACT (R)
RST
tRAS
tRAD
Channel
Channel 1
Channel 1
Address
Col. 0
Segment
Row 0
A13
BankA
BankA
A10
without
Auto
Precharge
Channel 1
Col. 5
BankA
L
DQM
DQ
Remark
66
Hi-Z
Restore Termination
Q1-0
Q1-1
ACT(R) command is ACT command after RST command.
Preliminary Data Sheet M14412EJ3V0DS00
D1-5
D1-6
D1-7
µPD45125421, 45125821, 45125161
Write to Restore to Write Operation without Auto Precharge (Same Channel Restore)
( Burst length = 8 )
0
1
2
3
4
5
6
7
8
WRIT
PRE
CLK
tRCD
Command
ACT (R)
RST
WRIT
tRAS
tRAD
Channel
Channel 1
Channel 1
Address
Col. 0
Segment
Row 0
A13
BankA
BankA
A10
without
Auto
Precharge
Channel 1
Col. 1
BankA
L
DQM
Restore Termination
MASK
DQ
Remark
D1-0
D1-1
Hi-Z
D1-2
D1-1
D1-2
D1-3
ACT(R) command is ACT command after RST command.
Write to Restore to Read Operation without Auto Precharge (Same Channel Restore)
( Read latency = 2, Burst length = 8 )
0
1
2
3
4
5
6
7
8
READ
PRE
CLK
tRCD
Command
ACT (R)
RST
WRIT
tRAS
tRAD
Channel
Channel 1
Channel 1
Address
Col. 0
Segment
Row 0
A13
BankA
BankA
A10
without
Auto
Precharge
Channel 1
Col. 1
BankA
L
DQM
MASK
DQ
Remark
D1-0
D1-1
D1-2
Restore Termination
Hi-Z
Q1-1
ACT(R) command is ACT command after RST command.
Preliminary Data Sheet M14412EJ3V0DS00
67
µPD45125421, 45125821, 45125161
Prefetch to Prefetch Operation without Auto Precharge
0
1
2
3
4
5
6
7
9
8
10
CLK
tRRD
Command
ACT
tAPD
ACT
Channel
tPPD
tPPD
PFC
PFC
PFC
Channel 1
Channel 8
Channel 2
Address
Row 0
Row 1
Segment 1
Segment 2
Segment 3
A13
BankA
BankB
BankB
BankB
BankA
without
Auto
Precharge
without
Auto
Precharge
without
Auto
Precharge
A10
DQM
DQ
L
Hi-Z
Prefetch to Restore Operation without Auto Precharge (Other Bank Restore)
0
1
2
3
4
5
6
7
RST
ACT (R)
CLK
tAPD
Command
ACT
tPRD
PFC
tRAD
Channel
Channel 2
Address
Row 0
Segment 1
Segment 1
Row 0
A13
BankA
BankA
BankB
BankB
without
Auto
Precharge
without
Auto
Precharge
A10
DQM
DQ
Remark
68
Channel 1
L
Hi-Z
ACT(R) command is ACT command after RST command.
Preliminary Data Sheet M14412EJ3V0DS00
8
µPD45125421, 45125821, 45125161
Prefetch Operation with Auto Precharge
0
1
2
3
4
5
6
7
8
9
CLK
tPAL
tAPD
Command
ACT
PFC A
ACT
tRC
Channel
Channel 1
Address
Row 0
Segment 1
Row 0
A13
BankA
BankA
BankA
Auto
Precharge
A10
DQM
DQ
L
Hi-Z
Preliminary Data Sheet M14412EJ3V0DS00
69
µPD45125421, 45125821, 45125161
Restore to Prefetch Operation without Auto precharge
0
1
2
3
4
5
6
7
8
CLK
tRAD
ACT (R)
RST
Command
tRAS
ACT (R)
RST
PRE
PFC
tRPD
tRAD
tRRDR
Channel
Channel 1
Channel 2
Address Segment 1
A13
BankA
A10
without
Auto
Precharge
DQM
L
Row 0
Channel 1
Row 1
Segment 3
BankA
Segment 2
BankB
BankB
BankA
BankB
L
without
Auto
Precharge
without
Auto
Precharge
Hi-Z
DQ
Remark
ACT(R) command is ACT command after RST command.
Restore Operation with Auto Precharge
0
1
2
3
4
5
6
7
8
9
CLK
tRAD
Command
RSTA
tRC
ACT (R)
ACT (R)
RST
ACT
tRAD
tRRDR
Channel
Address Segment 1
A13
BankA
A10
Auto
Precharge
DQM
L
DQ
Remark
70
Channel 1
Channel 2
Row 0
BankA
Segment 3
BankB
Row 1
Row 0
BankB
BankA
without
Auto
Precharge
Hi-Z
ACT(R) command is ACT command after RST command.
Preliminary Data Sheet M14412EJ3V0DS00
µPD45125421, 45125821, 45125161
Read to Prefetch Read with Auto Precharge Operation
(Read latency = 1, Prefetch Read latency = 2, Burst length = 8)
0
1
2
3
4
5
6
7
9
8
10
11
12
13
CLK
tPAL
tAPRD
Command
READ
ACT
PFR
ACT
tRC
Channel Channel 1
Channel 1
Illegal to input any other
background operation.
Address
Row 0
Col. 8
Col. 0
A13
BankA Segment
A10
Segment
Row 1
BankA
PRL=2
(Prefetch Read Latency)
DQM
L
READ will be interrupted by PFR.
DQ
Hi-Z
Q1-8
Q1-0
Q1-9
Q1-2
Q1-1
Q1-3
Q1-6
Q1-5
Q1-4
Q1-7
Write to Prefetch Read with Auto Precharge Operation
(Read latency = 1, Prefetch Read latency = 2, Burst length = 8)
0
1
2
3
4
5
6
7
8
9
10
11
12
CLK
tAPRD
Command
WRIT
ACT
tPAL
PFR
ACT
tRC
Channel Channel 1
Channel 1
Illegal to input any other
background operation.
Address
A13
Col. 8
Row 0
Col. 0
Row 1
L
BankA
Segment
BankA
A10
Segment
PRL=2
(Prefetch Read Latency)
DQM
L
WRIT will be interrupted by PFR.
★
DQ
D1-8
D1-9
D1-10
Hi-Z
Q1-0
Q1-1
Q1-2
Preliminary Data Sheet M14412EJ3V0DS00
Q1-3
Q1-4
Q1-5
Q1-6
Q1-7
71
µPD45125421, 45125821, 45125161
Read to Prefetch Read with Auto Precharge Operation
(Read latency = 2, Prefetch Read latency = 4, Burst length = 8)
0
1
2
3
4
5
6
7
9
8
10
11
12
13
CLK
tPAL
tAPRD
Command
READ
ACT
PFR
ACT
tRC
Channel Channel 1
Channel 1
Illegal to input any other
background operation.
Address
Col. 8
A13
Row 0
Col. 0
Row 1
BankA
Segment
BankA
A10
Segment
PRL=4
(Prefetch Read Latency)
DQM
L
READ will be interrupted by PFR.
DQ
★
Hi-Z
Q1-8
Q1-9
Q1-10
Q1-0
Q1-11
Q1-2
Q1-1
Q1-3
Q1-4
Q1-5
Write to Prefetch Read with Auto Precharge Operation
(Read latency = 2, Prefetch Read latency = 4, Burst length = 8)
0
1
2
3
4
5
6
7
8
9
10
11
12
CLK
tPAL
tAPRD
Command
WRIT
ACT
PFR
ACT
tRC
Channel Channel 1
Channel 1
Illegal to input any other
background operation.
Address
A13
Col. 8
Row 0
Col. 0
Row 1
L
BankA
Segment
BankA
A10
DQM
Segment
PRL=4
(Prefetch Read Latency)
L
WRIT will be interrupted by PFR.
DQ
★
72
D1-8
D1-9
D1-10
D1-11
Hi-Z
Preliminary Data Sheet M14412EJ3V0DS00
Q1-0
Q1-1
Q1-2
Q1-3
Q1-4
µPD45125421, 45125821, 45125161
Auto Refresh Operation
0
1
2
3
4
9
10
11
12
CLK
tRP
Command
tRCF
PALL
Address
A10
REF
ACT
H
DQM
L
Hi-Z
DQ
Self Refresh Operation (Entry and Exit)
0
1
2
3
4
5
6
96
97
98
99
100
101
108
109
CLK
CKE
tRCF
tRP
Command
PALL
REF
ACT
Address
A10
DQM
H
L
DQ
Self refresh entry
Self refresh exit
Preliminary Data Sheet M14412EJ3V0DS00
73
µPD45125421, 45125821, 45125161
★
13. Package Drawing
54-PIN PLASTIC TSOP (II) (10.16 mm (400))
54
28
detail of lead end
F
P
E
1
27
A
H
I
G
J
S
L
N
C
D
M
S
B
K
M
NOTES
1. Each lead centerline is located within 0.13 mm of
its true position (T.P.) at maximum material condition.
2. Dimension "A" does not include mold fiash, protrusions or gate
burrs. Mold flash, protrusions or gate burrs shall not exceed
0.15 mm per side.
ITEM
A
MILLIMETERS
22.22±0.05
B
0.91 MAX.
C
0.80 (T.P.)
D
0.32 +0.08
−0.07
E
0.10±0.05
F
1.1±0.1
G
1.00
H
11.76±0.20
I
10.16±0.10
J
0.80±0.20
K
0.145+0.025
−0.015
L
0.50±0.10
M
0.13
N
0.10
P
3°+7°
−3°
S54G5-80-9JF-2
74
Preliminary Data Sheet M14412EJ3V0DS00
µPD45125421, 45125821, 45125161
14. Recommended Soldering Condition
Please consult with our sales offices for soldering conditions of the µPD45125×××.
Type of Surface Mount Device
µPD45125421G5 : 54-pin Plastic TSOP (II) (10.16mm (400))
µPD45125821G5 : 54-pin Plastic TSOP (II) (10.16mm (400))
µPD45125161G5 : 54-pin Plastic TSOP (II) (10.16mm (400))
Preliminary Data Sheet M14412EJ3V0DS00
75
µPD45125421, 45125821, 45125161
15. Revision History
Edition /
Date
Page
Description
This
edition
Previous
edition
−
−
−
2nd edition /
p.2
p.2
Modification
Organization
July ‘99
p.2
p.2
Modification
Prefetch read latency for x4 bits organization
p.5, 6, 7
p.5, 6, 7
Modification
Organization
p.17
p.17
Addition
Note for Prefetch read with auto precharge
p.28
p.28
Modification
Text regarding x4 bits organization
p.36
p.36
Modification
Text regarding x4 bits organization
3rd edition /
p.1
p.1
Addition
Features (Prefetch read latency for x4 bits organization)
Nov. ‘99
p.2
p.2
Deletion
Low power Operation
p.3
p.3
Deletion
Low power Operation
p.4
p.4
Deletion
Low power Operation
p.44
p.44
Modification
Capacitance
p.45
p.45
Modification
DC Characteristics 1
p.47
p.47
Modification
tCK1, tCK2, tAC1, tAC2, tHZ1, tHZ2
p.58
p.58
Modification
D3-3
p.71
p.71
Addition
D1-10
p.72
p.72
Addition
Q1-11 (Read to Prefetch Read with Auto Precharge Operation)
1st edition /
Type of
revision
Location
−
July ‘99
D1-11 (Write to Prefetch Read with Auto Precharge Operation)
p.74
76
p.74
Modification
Package Drawing
Preliminary Data Sheet M14412EJ3V0DS00
µPD45125421, 45125821, 45125161
[MEMO]
Preliminary Data Sheet M14412EJ3V0DS00
77
µPD45125421, 45125821, 45125161
[MEMO]
78
Preliminary Data Sheet M14412EJ3V0DS00
µPD45125421, 45125821, 45125161
NOTES FOR CMOS DEVICES
1
PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note:
Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity
as much as possible, and quickly dissipate it once, when it has occurred. Environmental control
must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using
insulators that easily build static electricity. Semiconductor devices must be stored and transported
in an anti-static container, static shielding bag or conductive material. All test and measurement
tools including work bench and floor should be grounded. The operator should be grounded using
wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need
to be taken for PW boards with semiconductor devices on it.
2
HANDLING OF UNUSED INPUT PINS FOR CMOS
Note:
No connection for CMOS device inputs can be cause of malfunction. If no connection is provided
to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence
causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels
of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused
pin should be connected to V DD or GND with a resistor, if it is considered to have a possibility of
being an output pin. All handling related to the unused pins must be judged device by device and
related specifications governing the devices.
3
STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note:
Power-on does not necessarily define initial status of MOS device. Production process of MOS
does not define the initial operation status of the device. Immediately after the power source is
turned ON, the devices with reset function have not yet been initialized. Hence, power-on does
not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the
reset signal is received. Reset operation must be executed immediately after power-on for devices
having reset function.
Preliminary Data Sheet M14412EJ3V0DS00
79
µPD45125421, 45125821, 45125161
[MEMO]
VirtualChannel and VCMemory are trademarks of NEC Corporation.
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confirm that this is the latest version.
• No part of this document may be copied or reproduced in any form or by any means without the prior written
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• Descriptions of circuits, software, and other related information in this document are provided for illustrative
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software, and information in the design of the customer's equipment shall be done under the full responsibility
of the customer. NEC Corporation assumes no responsibility for any losses incurred by the customer or third
parties arising from the use of these circuits, software, and information.
• While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices,
the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or
property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety
measures in its design, such as redundancy, fire-containment, and anti-failure features.
• NEC devices are classified into the following three quality grades:
"Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a
customer designated "quality assurance program" for a specific application. The recommended applications of
a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device
before using it in a particular application.
Standard: Computers, office equipment, communications equipment, test and measurement equipment,
audio and visual equipment, home electronic appliances, machine tools, personal electronic
equipment and industrial robots
Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support)
Specific: Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems or medical equipment for life support, etc.
The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books.
If customers intend to use NEC devices for applications other than those specified for Standard quality grade,
they should contact an NEC sales representative in advance.
M7 98. 8