ETC UPD65893

Design Manual
CMOS-N5 Family
CMOS Gate Array
Ver. 6.0
Document No. A13826EJ6V0DM00 (6th edition)
Date Published February 2002 N CP(K)
©
Printed in Japan
1998
[MEMO]
2
Design Manual A13826EJ6V0DM
NOTES FOR CMOS DEVICES
1
PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note:
Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity
as much as possible, and quickly dissipate it once, when it has occurred. Environmental control
must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using
insulators that easily build static electricity. Semiconductor devices must be stored and transported
in an anti-static container, static shielding bag or conductive material. All test and measurement
tools including work bench and floor should be grounded. The operator should be grounded using
wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need
to be taken for PW boards with semiconductor devices on it.
2
HANDLING OF UNUSED INPUT PINS FOR CMOS
Note:
No connection for CMOS device inputs can be cause of malfunction. If no connection is provided
to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence
causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels
of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused
pin should be connected to V DD or GND with a resistor, if it is considered to have a possibility of
being an output pin. All handling related to the unused pins must be judged device by device and
related specifications governing the devices.
3
STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note:
Power-on does not necessarily define initial status of MOS device. Production process of MOS
does not define the initial operation status of the device. Immediately after the power source is
turned ON, the devices with reset function have not yet been initialized. Hence, power-on does
not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the
reset signal is received. Reset operation must be executed immediately after power-on for devices
having reset function.
OPENCAD, Vdraw, V.sim, and C.FGRADE are trademarks of NEC Corporation.
Design Compiler is a registered trademark of Synopsys, Inc. in Japan.
Verilog, NC-Verilog, Verilog-XL, Gate Ensemble, and Silicon Ensemble are trademarks of Cadence
Design Systems, Inc.
PrimeTime and Formality are registered trademarks of Synopsys, Inc. in the USA.
SUN and Solaris are trademarks of SUN Microsystems, Inc.
VCS, TetraMAX, TestCompiler, and Testgen are trademarks of Synopsys, Inc.
HP and HP-UX are trademarks of Hewlett-Packard Company.
Motif is a trademark of Open Software Foundation, Inc.
ModelSim is a trademark of Model Technology, Inc.
FastScan is a trademark of Mentor Graphics, Inc.
Design Manual A13826EJ6V0DM
3
The export of this product from Japan is regulated by the Japanese government. To export this product may be prohibited
without governmental license, the need for which must be judged by the customer. The export or re-export of this product
from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales
representative.
• The information in this document is current as of November, 2001. The information is subject to
change without notice. For actual design-in, refer to the latest publications of NEC’s data sheets or
data books, etc., for the most up-to-date specifications of NEC semiconductor products. Not all
products and/or types are available in every country. Please check with an NEC sales representative
for availability and additional information.
• No part of this document may be copied or reproduced in any form or by any means without prior
written consent of NEC. NEC assumes no responsibility for any errors that may appear in this document.
• NEC does not assume any liability for infringement of patents, copyrights or other intellectual property rights of
third parties by or arising from the use of NEC semiconductor products listed in this document or any other
liability arising from the use of such products. No license, express, implied or otherwise, is granted under any
patents, copyrights or other intellectual property rights of NEC or others.
• Descriptions of circuits, software and other related information in this document are provided for illustrative
purposes in semiconductor product operation and application examples. The incorporation of these
circuits, software and information in the design of customer’s equipment shall be done under the full
responsibility of customer. NEC assumes no responsibility for any losses incurred by customers or third
parties arising from the use of these circuits, software and information.
• While NEC endeavours to enhance the quality, reliability and safety of NEC semiconductor products, customers
agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize
risks of damage to property or injury (including death) to persons arising from defects in NEC
semiconductor products, customers must incorporate sufficient safety measures in their design, such as
redundancy, fire-containment, and anti-failure features.
• NEC semiconductor products are classified into the following three quality grades:
"Standard", "Special" and "Specific". The "Specific" quality grade applies only to semiconductor products
developed based on a customer-designated "quality assurance program" for a specific application. The
recommended applications of a semiconductor product depend on its quality grade, as indicated below.
Customers must check the quality grade of each semiconductor product before using it in a particular
application.
"Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio
and visual equipment, home electronic appliances, machine tools, personal electronic equipment
and industrial robots
"Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support)
"Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems and medical equipment for life support, etc.
The quality grade of NEC semiconductor products is "Standard" unless otherwise expressly specified in NEC’s
data sheets or data books, etc. If customers wish to use NEC semiconductor products in applications not
intended by NEC, they must contact an NEC sales representative in advance to determine NEC’s willingness
to support a given application.
(Note)
(1) "NEC" as used in this statement means NEC Corporation and also includes its majority-owned subsidiaries.
(2) "NEC semiconductor products" means any semiconductor product developed or manufactured by or for
NEC (as defined above).
M8E 00. 4
4
Design Manual A13826EJ6V0DM
Regional Information
Some information contained in this document may vary from country to country. Before using any NEC
product in your application, pIease contact the NEC office in your country to obtain a list of authorized
representatives and distributors. They will verify:
•
Device availability
•
Ordering information
•
Product release schedule
•
Availability of related technical literature
•
Development environment specifications (for example, specifications for third-party tools and
components, host computers, power plugs, AC supply voltages, and so forth)
•
Network requirements
In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary
from country to country.
NEC Electronics Inc. (U.S.)
NEC Electronics (France) S.A.
NEC Electronics Hong Kong Ltd.
Santa Clara, California
Tel: 408-588-6000
800-366-9782
Fax: 408-588-6130
800-729-9288
Vélizy-Villacoublay, France
Tel: 01-3067-58-00
Fax: 01-3067-58-99
Hong Kong
Tel: 2886-9318
Fax: 2886-9022/9044
NEC Electronics (Europe) GmbH
Duesseldorf, Germany
Tel: 0211-65 03 01
Fax: 0211-65 03 327
• Branch The Netherlands
Eindhoven, The Netherlands
Tel: 040-244 58 45
Fax: 040-244 45 80
NEC Electronics (France) S.A.
Representación en España
Madrid, Spain
Tel: 091-504-27-87
Fax: 091-504-28-60
NEC Electronics Italiana S.R.L.
Milano, Italy
Tel: 02-66 75 41
Fax: 02-66 75 42 99
NEC Electronics Hong Kong Ltd.
Seoul Branch
Seoul, Korea
Tel: 02-528-0303
Fax: 02-528-4411
NEC Electronics Singapore Pte. Ltd.
Novena Square, Singapore
Tel: 253-8311
Fax: 250-3583
NEC Electronics Taiwan Ltd.
• Branch Sweden
Taeby, Sweden
Tel: 08-63 80 820
Fax: 08-63 80 388
NEC Electronics (UK) Ltd.
Milton Keynes, UK
Tel: 01908-691-133
Fax: 01908-670-290
Taipei, Taiwan
Tel: 02-2719-2377
Fax: 02-2719-5951
NEC do Brasil S.A.
Electron Devices Division
Guarulhos-SP, Brasil
Tel: 11-6462-6810
Fax: 11-6462-6829
J01.12
Design Manual A13826EJ6V0DM
5
Major Revisions in This Edition (1/2)
Page
Throughout
6
Description
Deletion of description on the clock driver
p.22
Modification of 1.1 (1) VDD = 5.0 V ±10%
p.27
2.1.1 Cell utilization rate, usable cell and pin-pair count limits
• Addition of cell utilization rate for each package
• Change of a coefficient in the calculation expression
p.28
Change of Table 2-2 Usable Gates and Pin-Pair Count
p.31
Deletion of indication of “under study” in 2.1.3 Large-scale macro mounting
p.34
Addition of (c) Megamacro in Table 2-3 List of Mountability
p.49
Change of Table 2-6 List of Packages
p.54
Addition of 2.6 Development Flow
p.57
Addition of 2.7 OPENCAD Configuration Tools
p.59
Addition of 2.8 List of Interface Data
p.61
Addition of 2.9 ASIC Product Development Information
p.100
Modification of Table 3-4 Absolute Maximum Ratings
p.101
Modification of Table 3-5 Recommended Operating Range (VDD = 5.0 V ±10%, TA = –40 to +85°C)
pp.113, 114
4.3.2 Estimating power consumption
• Modification of description
• Addition of (5) ∑PDCTS … Clock tree synthesis power consumption
p.119
Modification of description in 4.3.5 Determining power consumption
p.127
Modification of description in 4.5.3 Maximum operating frequency of output buffers
p.134
Addition of BGA package determination in 4.6.6 Three-GND-pin determination
p.143
Modification of Table 5-1 F617 (D-F/F with RB, SB)
p.151
Modification of description in 5.4.3 (1) Benefits of CTS
p.111 in the 5th edition
Deletion of 5.4.4 Using clock input drivers
p.181
Change of CHAPTER 6 TEST PATTERN GENERATION
p.162 in the 5th edition
Deletion of 7.3 Clock Input Drivers (Under Development)
p.203
Addition of description in 7.3.1 Configuration of oscillator
p.206
Addition of description in 7.3.2 Description of oscillator
p.208
Modification of description in 7.3.4 Constants of external circuit
pp.220, 221
Addition of description in APPENDIX A POWER CONSUMPTION (PRELIMINARY)
p.234
Replacement by the latest block information in APPENDIX E BLOCK LIST
p.261
Addition of description in APPENDIX F PIN DESCRIPTIONS
pp.271, 272
APPENDIX G PIN ASSIGNABLE TO OSCILLATOR
• Addition of description
• Separation of the table of µPD65882
pp.275, 279 to 281
APPENDIX H PACKAGE DRAWINGS
• Addition of Caution
• Addition of Remark 2 in the 48-pin plastic TQFP (fine pitch) (S48GA-50-9EU-2)
• Addition of the 48-pin plastic TQFP (fine pitch) (P48GA-50-9EU)
• Addition of Remark in the 60-pin plastic TQFP (fine pitch)
p.287
Addition of marking example of 64-pin TQFP MP in APPENDIX I PACKAGE MARKINGS
pp.289, 290
APPENDIX J RECOMMENDED SOLDERING CONDITIONS
• Modification of description
• Change of recommended condition symbols
Design Manual A13826EJ6V0DM
Major Revisions in This Edition (2/2)
Page
Description
p.293
Modification of condition description in Figure K-4 Input Through Current (VDD = 5.0 V CMOS Level)
p.293
Modification of condition description in Figure K-5 Input Through Current (VDD = 5.0 V TTL Level)
p.293
Addition of description in Figure K-6 Input Through Current (VDD = 5.5 V CMOS Level Schmitt)
p.294
Addition of description in Figure K-7 Input Through Current (VDD = 5.5 V TTL Level Schmitt)
p.294
Modification of condition description in Figure K-8 Input Through Current (VDD = 3.6 V CMOS Level)
p.294
Modification of condition description in Figure K-9 Input Through Current (VDD = 3.3 V TTL Level)
p.294
Addition of description in Figure K-10 Input Through Current (VDD = 3.6 V CMOS Level Schmitt)
p.294
Addition of description in Figure K-11 Input Through Current (VDD = 3.3 V TTL Level Schmitt)
p.296
Figure K-13 fMAX. vs. CL Limit (CMOS Level Output)
• Change of configuration
• Addition of condition of 3.3 V
p.298
Figure K-14 fMAX. vs. CL Limit (CMOS Level Low-Noise Output)
• Change of configuration
• Addition of condition of 3.3 V
p.303
Addition of Figure K-18 IO vs. VO (@3.3 V)
p.305
Addition of Circuit configuration <3> in Figure K-19 Oscillator Configuration Diagram
p.306
Table K-1 CMOS-N5 Family Products
• Change of number of usable gates
• Change of cell utilization rate
p.307
Addition of Remark in Table K-4 Power Consumption by Input Buffer
p.308
Addition of values of 44-pin LQFP in Table K-8 Maximum Allowable Power Consumption (TA =
85°C, TJ = 125°C)
pp.309, 310
Addition of values of 44-pin LQFP in Table K-9 Thermal Resistance
p.312
Addition of Table K-12 tr and tf Calculation Coefficients of Output Buffer (VDD = 3.3 V, TA =
25°C)
p.313
Addition of Table K-14 Recommended Load Capacitance Ranges of Output Buffers (@3.3 V)
p.314
Table K-16 Permissible Number of Simultaneous Operation Pins Between 3 GND Pins (IOL = 12
mA)
Addition of output load capacitance when valid number of GND is 1 in (b) 5.0 V (TTL level and TTL/
CMOS levels coexisting)
p.316
Addition of description in Table K-19 List of Resonator Evaluations
The mark
shows major revised points.
Design Manual A13826EJ6V0DM
7
INTRODUCTION
This manual explains the restrictions and points to be noted when designing LSIs using NEC’s CMOS-N5 Family
of high-speed, high-density CMOS gate arrays.
In order to ensure smooth design of an LSI, read this manual carefully.
Be sure to follow the specifications described in this manual (including general information, cautions, and restrictions).
Failure to do so may result in poor quality, poor performance, or operational faults in LSI products.
8
Design Manual A13826EJ6V0DM
Related Documents
The related documents indicated in this publication may include preliminary versions. However, preliminary versions
are not marked as such.
• CMOS-N5 Family Design Manual
(This manual)
• CMOS-N5 Family Block Library
(A13872E)
• CMOS-N5 Family Memory Block Library
(A14683E)
• CMOS-N5 Family Mega Macro Design Manual
(A14759E)
• Design For Test User’s Manual
(A14357E)
• SEMICONDUCTORS SELECTION GUIDE Products & Packages (CD-ROM)
(X13769E)
To obtain the latest documents when designing, contact an NEC sales office or distributor.
Design Manual A13826EJ6V0DM
9
CONTENTS
CHAPTER 1 OVERVIEW ......................................................................................................................... 21
1.1
1.2
1.3
1.4
Features ........................................................................................................................................21
Internal Structure of CMOS-N5 Family ....................................................................................... 23
Internal Cell Structure .................................................................................................................24
QFP Package ................................................................................................................................ 25
CHAPTER 2 SELECTING THE GATE ARRAY ........................................................................................26
2.1 Estimating Circuit Scale .............................................................................................................. 27
2.1.1
Cell utilization rate, usable cell and pin-pair count limits .................................................................. 27
2.1.2
Notes on estimating number of cells used ........................................................................................ 30
2.1.3
Large-scale macro mounting ............................................................................................................ 31
2.1.4
Notes on mounting large-scale macros (memory) ............................................................................ 47
2.2 Package Selection .......................................................................................................................48
2.3 Verifying Power Consumption ....................................................................................................50
2.4 Pin Placement ..............................................................................................................................51
2.4.1
Notes on pin layout ........................................................................................................................... 51
2.5 I/O Interface ..................................................................................................................................52
2.6
2.7
2.8
2.9
2.5.1
Input blocks ....................................................................................................................................... 52
2.5.2
Output blocks .................................................................................................................................... 53
Development Flow .......................................................................................................................54
OPENCAD Configuration Tools .................................................................................................. 57
List of Interface Data ...................................................................................................................59
ASIC Product Development Information ................................................................................... 61
2.9.1
ASIC product development information (checksheet) ...................................................................... 62
2.9.2
RAM block ........................................................................................................................................ 74
2.9.3
ROM ................................................................................................................................................. 78
2.9.4
High-speed function test (up to OPENCAD V5.3g) .......................................................................... 80
2.9.5
High-speed function test (OPENCAD V5.4 or later) ......................................................................... 82
2.9.6
GTL, PECL, HSTL, PCI, LVDS ......................................................................................................... 84
2.9.7
DPLL block ........................................................................................................................................ 86
2.9.8
Megamacro ....................................................................................................................................... 88
2.9.9
Scan path .......................................................................................................................................... 90
2.9.10
Boundary scan .................................................................................................................................. 94
2.9.11
Automatic layout checklist ................................................................................................................ 96
CHAPTER 3 PRODUCT SPECIFICATIONS ............................................................................................ 98
3.1 Terminology ..................................................................................................................................98
3.2 Absolute Maximum Ratings ...................................................................................................... 100
3.3 Standard Specification of CMOS Interface Conditions (VDD = 5.0 V ±10%,
TA = –40 to +85°C) ......................................................................................................................101
10
3.3.1
Recommended operating range ..................................................................................................... 101
3.3.2
DC characteristics ........................................................................................................................... 102
Design Manual A13826EJ6V0DM
3.3.3
AC characteristics ........................................................................................................................... 103
3.4 Specification 1 (VDD = 3.0 ±0.3 V, TA = –40 to +85°C) ............................................................... 104
3.4.1
Recommended operating range ..................................................................................................... 104
3.4.2
DC characteristics ........................................................................................................................... 105
3.4.3
AC characteristics ........................................................................................................................... 106
3.5 Specification 2 (VDD = 3.3 ±0.3 V, TA = –40 to +85°C) ............................................................... 107
3.5.1
Recommended operating range ..................................................................................................... 107
3.5.2
DC characteristics ........................................................................................................................... 108
3.5.3
AC characteristics ........................................................................................................................... 109
3.6 Pin Capacitance ......................................................................................................................... 109
CHAPTER 4 ESTIMATING ELECTRICAL CHARACTERISTICS .......................................................... 110
4.1 Estimating Static Current Consumption.................................................................................. 110
4.1.1
Estimating static current consumption .............................................................................................110
4.2 Input Through Current ............................................................................................................... 111
4.3 Power Consumption .................................................................................................................. 112
4.3.1
Causes of power consumption ........................................................................................................112
4.3.2
Estimating power consumption ........................................................................................................113
4.3.3
Unit power consumption of memory ................................................................................................117
4.3.4
Compensation method .....................................................................................................................119
4.3.5
Determining power consumption .....................................................................................................119
4.4 Propagation Delay Time ............................................................................................................ 120
4.4.1
Accuracy of propagation delay time ................................................................................................ 120
4.4.2
Calculation in propagation delay time ............................................................................................. 121
4.4.3
Estimating wiring capacitance ........................................................................................................ 123
4.4.4
Fluctuation in propagation delay time ............................................................................................. 124
4.5 Output Buffer Characteristics ................................................................................................... 127
4.5.1
Output buffer rise and fall times ...................................................................................................... 127
4.5.2
Recommended load capacitance range of output buffers .............................................................. 127
4.5.3
Maximum operating frequency of output buffers ............................................................................. 127
4.5.4
Output buffer output current (IOL, IOH) .............................................................................................. 128
4.6 Restrictions to Simultaneous Operation of Output Buffers .................................................. 129
4.6.1
Malfunction due to simultaneous operation of outputs ................................................................... 129
4.6.2
Definitions ....................................................................................................................................... 131
4.6.3
Factors for the determination of simultaneous operation ................................................................ 131
4.6.4
Simultaneous operation pins to be checked ................................................................................... 132
4.6.5
Pin placement and simultaneous operation .................................................................................... 133
4.6.6
Three-GND-pin determination ........................................................................................................ 134
4.6.7
Assumptions for the determination method .................................................................................... 135
4.6.8
Other determination methods ......................................................................................................... 136
CHAPTER 5 CIRCUIT DESIGN GUIDELINES ...................................................................................... 137
5.1 Basic Circuit Configuration ...................................................................................................... 137
5.1.1
Using I/O buffers ............................................................................................................................. 137
5.1.2
Unused pins .................................................................................................................................... 138
5.1.3
Fan-out limitations .......................................................................................................................... 138
Design Manual A13826EJ6V0DM
11
5.1.4
Wired logic circuit prohibitions ........................................................................................................ 138
5.1.5
Notes on using bidirectional buffers ................................................................................................ 139
5.2 Differential Circuit Prohibition .................................................................................................. 140
5.3 RS Latch and Loop Circuits ...................................................................................................... 141
5.3.1
RS latch .......................................................................................................................................... 141
5.3.2
Loop circuit ..................................................................................................................................... 142
5.3.3
Prohibited state of flip-flops ............................................................................................................ 143
5.4 Clocked Signal Design .............................................................................................................. 144
5.4.1
Synchronous circuit design ............................................................................................................. 144
5.4.2
Clock skew ...................................................................................................................................... 149
5.4.3
Clock tree synthesis ........................................................................................................................ 151
5.5 Notes on Configuring High-Speed Circuits ............................................................................. 155
5.6 Delay Time Margin ..................................................................................................................... 156
5.6.1
Timing definitions ............................................................................................................................ 157
5.6.2
Delay time margin calculation (asynchronous circuits) ................................................................... 158
5.6.3
Delay time margin calculation (high-speed circuits) ....................................................................... 159
5.6.4
Minimum pulse width ...................................................................................................................... 162
5.6.5
Metastable state (preliminary) ........................................................................................................ 163
5.6.6
Critical paths ................................................................................................................................... 167
5.6.7
Ensuring operating margin .............................................................................................................. 170
5.7 Internal Bus Configuration ........................................................................................................ 171
5.7.1
Configuring internal bus .................................................................................................................. 171
5.7.2
Preventing internal bus floating ...................................................................................................... 171
5.7.3
Precautions when using internal bus .............................................................................................. 172
5.8 Preventing Contention with External Bus ............................................................................... 173
5.9 Testability ...................................................................................................................................174
5.9.1
Flip-flop initial setting ...................................................................................................................... 174
5.9.2
Counter division .............................................................................................................................. 174
5.9.3
Adding test pins and dividing circuits .............................................................................................. 175
5.10 Racing and Spike Noise ............................................................................................................ 176
5.10.1
Racing (contention) ......................................................................................................................... 176
5.10.2
Spike noise ..................................................................................................................................... 178
CHAPTER 6 TEST PATTERN GENERATION ....................................................................................... 181
6.1 Test Pattern Types ..................................................................................................................... 181
6.2 Notes from Viewpoint of Product Test (LSI Tester) ................................................................ 182
6.2.1
I/O pin naming conventions ............................................................................................................ 182
6.2.2
Limitations on test pattern length .................................................................................................... 182
6.2.3
Number of test patterns .................................................................................................................. 183
6.3 Notes on Creating Test Pattern for Function Test .................................................................. 183
12
6.3.1
Initializing circuit .............................................................................................................................. 183
6.3.2
Test cycle (test rate) ........................................................................................................................ 183
6.3.3
Output determination time (strobe time) ......................................................................................... 183
6.3.4
Specification of timing phase .......................................................................................................... 184
6.3.5
Skew ............................................................................................................................................... 186
6.3.6
Notes on switching I/O mode of bidirectional pin ............................................................................ 186
6.3.7
I/O modulation function ................................................................................................................... 188
Design Manual A13826EJ6V0DM
6.3.8
I/O conflict ....................................................................................................................................... 190
6.3.9
Testing multifunction I/O circuits ..................................................................................................... 190
6.4 Notes on Creating DC Test Patterns ........................................................................................ 191
6.5 Test Pattern for On-Chip RAM .................................................................................................. 192
6.6 High-Speed Function Test (Real-Time Test) ............................................................................ 193
6.6.1
Limitation of the test pattern length ................................................................................................. 193
6.6.2
Test cycle (test rate) ........................................................................................................................ 193
6.6.3
Output determination time (strobe time) ......................................................................................... 193
6.6.4
Notes on high-speed function testing ............................................................................................. 194
6.7 Testability (Fault Coverage) ...................................................................................................... 196
6.7.1
Consideration of testability (fault coverage) .................................................................................... 196
6.7.2
Principle of fault simulation ............................................................................................................. 196
6.8 Consideration of System Simulation ....................................................................................... 199
CHAPTER 7 MULTIFUNCTION BLOCKS ............................................................................................. 200
7.1 Buffer with Fail-Safe Function .................................................................................................. 201
7.2 Input/Output/Bidirectional Buffers with On-Chip Pull-Up/Pull-Down Resistors .................. 202
7.3 Oscillator ....................................................................................................................................203
7.3.1
Configuration of oscillator ............................................................................................................... 203
7.3.2
Description of oscillator ................................................................................................................... 204
7.3.3
Notes on configuring an oscillator ................................................................................................... 207
7.3.4
Constants of external circuit ........................................................................................................... 208
7.4 Memory ....................................................................................................................................... 209
7.4.1
Types of memory blocks ................................................................................................................. 209
7.4.2
RAM blocks ..................................................................................................................................... 210
7.5 Writing Memory Blocks ............................................................................................................. 212
7.5.1
Selecting memory blocks ................................................................................................................ 212
7.5.2
Using memory blocks ..................................................................................................................... 212
7.6 Memory Test ............................................................................................................................... 213
7.6.1
RAM test ......................................................................................................................................... 213
7.6.2
Assigning test I/O pins (TIN, TEB, and TOUT) ............................................................................... 216
7.6.3
Checking connection of RAM test circuit ........................................................................................ 218
7.7 Scan Path Test Block .................................................................................................................219
APPENDIX A POWER CONSUMPTION (PRELIMINARY) .................................................................... 220
APPENDIX B PROPAGATION DELAY TIME ........................................................................................ 222
APPENDIX C ALBATROSS AND DIF FILE FORMATS ........................................................................ 223
C.1 ALBATROSS File Format (Circuit Name.alb) ........................................................................... 223
C.2 DIF File Format (Circuit Name.dif) ............................................................................................ 225
APPENDIX D DRAWING CIRCUIT DIAGRAMS AND TIMING CHARTS ............................................. 226
D.1 Drawing Circuit Diagrams ......................................................................................................... 226
D.1.1
Logic symbols ................................................................................................................................. 226
Design Manual A13826EJ6V0DM
13
D.1.2
Block names (function names) ....................................................................................................... 226
D.1.3
Pin names (I/O pin name of block) ................................................................................................. 226
D.1.4
Gate names (specific name of each block) ..................................................................................... 226
D.1.5
I/O pin names ................................................................................................................................. 227
D.2 Handling Macros ........................................................................................................................230
D.3 Preparing Timing Charts ........................................................................................................... 232
APPENDIX E LIST OF BLOCKS ........................................................................................................... 234
E.1 Interface Block ........................................................................................................................... 234
E.1.1
CMOS Level ................................................................................................................................... 234
E.1.2
TTL Level ........................................................................................................................................ 241
E.1.3
Oscillator ......................................................................................................................................... 246
E.2 Function Block ........................................................................................................................... 247
E.2.1
Level Generator .............................................................................................................................. 247
E.2.2
Inverter, Buffer, CTS Driver, Delay Gate ......................................................................................... 247
E.2.3
OR(NOR) ........................................................................................................................................ 248
E.2.4
AND(NAND) .................................................................................................................................... 249
E.2.5
AND-NOR ....................................................................................................................................... 250
E.2.6
OR-NAND ....................................................................................................................................... 251
E.2.7
Exclusive OR, Exclusive NOR ........................................................................................................ 252
E.2.8
Adder, 3-State Buffer, Decoder, Multiplexer, Generator .................................................................. 253
E.2.9
RS-Latch, RS-F/F ........................................................................................................................... 254
E.2.10 D-Latch ........................................................................................................................................... 254
E.2.11 D-F/F ............................................................................................................................................... 255
E.2.12 T-F/F, JK-F/F ................................................................................................................................... 257
E.3 Scan Path Block ......................................................................................................................... 258
E.3.1
Standard Type ................................................................................................................................. 258
E.3.2
NEC Scan ....................................................................................................................................... 258
E.3.3
Scan Controller ............................................................................................................................... 259
E.4 Boundary Scan Block ................................................................................................................260
E.4.1
TAP Macro ...................................................................................................................................... 260
E.4.2
Level Generator .............................................................................................................................. 260
E.4.3
Data Register .................................................................................................................................. 260
E.4.4
D-latch, Selector, Shift Register ...................................................................................................... 260
E.4.5
Soft Macro ...................................................................................................................................... 260
APPENDIX F PIN DESCRIPTIONS ........................................................................................................ 261
F.1 QFP (Fine Pitch) ......................................................................................................................... 261
F.1.1
160-pin plastic QFP (fine pitch) ....................................................................................................... 261
F.1.2
208-pin plastic QFP (fine pitch) ....................................................................................................... 262
F.1.3
240-pin plastic QFP (fine pitch) ....................................................................................................... 263
F.1.4
304-pin plastic QFP (fine pitch) ....................................................................................................... 264
F.2 TQFP ...........................................................................................................................................265
14
F.2.1
48-pin TQFP ................................................................................................................................... 265
F.2.2
64-pin TQFP ................................................................................................................................... 266
F.2.3
80-pin TQFP ................................................................................................................................... 267
Design Manual A13826EJ6V0DM
F.3 LQFP ...........................................................................................................................................268
F.3.1
44-pin LQFP ................................................................................................................................... 268
F.3.2
100-pin LQFP (fine pitch) ................................................................................................................ 269
F.3.3
160-pin LQFP (fine pitch) ................................................................................................................ 270
APPENDIX G PINS ASSIGNABLE TO OSCILLATOR .......................................................................... 271
APPENDIX H PACKAGE DRAWINGS ................................................................................................... 275
APPENDIX I PACKAGE MARKINGS .................................................................................................... 286
APPENDIX J RECOMMENDED SOLDERING CONDITIONS ............................................................... 289
APPENDIX K DATA ................................................................................................................................ 291
K.1 Figures ........................................................................................................................................291
K.2 Tables ..........................................................................................................................................306
Design Manual A13826EJ6V0DM
15
LIST OF FIGURES (1/3)
Figure No.
Title
Page
1-1
Gate Array Configuration ................................................................................................................................ 23
1-2
Internal Cell Equivalent Circuit ....................................................................................................................... 24
1-3
Equivalent Circuits .......................................................................................................................................... 25
1-4
Cross-Section of QFP Package ...................................................................................................................... 25
2-1
Pin-Pair Count ................................................................................................................................................ 27
2-2
Shape of Cell Range Occupied by Macros (with 4 Basic Macros) ................................................................. 35
2-3
Cell Range Occupied by Macro ...................................................................................................................... 36
2-4
Area Where Macros Cannot Be Implemented ................................................................................................ 37
2-5
Allowable Power Consumption vs. QFP Type ................................................................................................ 50
4-1
Propagation Delay Time (Under Study) ........................................................................................................ 125
4-2
tPD Variation .................................................................................................................................................. 126
4-3
Malfunction Caused by Simultaneous Operation ......................................................................................... 130
5-1
Basic Circuit Configuration ........................................................................................................................... 137
5-2
Wired Logic Circuit Prohibitions ................................................................................................................... 138
5-3
Ringing ......................................................................................................................................................... 139
5-4
Example of Preventive Circuit ...................................................................................................................... 139
5-5
Differential Circuit Prohibition ....................................................................................................................... 140
5-6
Asynchronous RS Latches ........................................................................................................................... 141
5-7
Loop Circuit .................................................................................................................................................. 142
5-8
Clock Skew ................................................................................................................................................... 145
5-9
Clock Skew Countermeasure 1 .................................................................................................................... 146
5-10
Clock Skew Countermeasure 2 .................................................................................................................... 147
5-11
Double-Phase Synchronous Circuit ............................................................................................................. 148
5-12
Countermeasures for Clock Lines Between Macros .................................................................................... 150
5-13
Concept of CTS ............................................................................................................................................ 151
5-14
Image of CTS Use (Example of FC44) ......................................................................................................... 152
5-15
Clock Skew Optimization .............................................................................................................................. 153
5-16
Example of CTS Block Description .............................................................................................................. 154
5-17
Configuring High-Speed Operational (Stable) Circuits ................................................................................. 155
5-18
Setup Time ................................................................................................................................................... 157
5-19
Hold Time ..................................................................................................................................................... 157
5-20
Release Time ............................................................................................................................................... 157
5-21
Removal Time ............................................................................................................................................... 157
5-22
Minimum Pulse Width ................................................................................................................................... 157
5-23
Example of Delay Time Margin Calculation Circuit ...................................................................................... 158
5-24
Timing Estimate ............................................................................................................................................ 158
5-25
Example of In-Phase Clock Circuit ............................................................................................................... 159
5-26
In-Phase Clock Timing ................................................................................................................................. 159
5-27
Example of Inverse-Phase Clock Circuit ...................................................................................................... 161
5-28
Inverse-Phase Clock Timing ......................................................................................................................... 161
16
Design Manual A13826EJ6V0DM
LIST OF FIGURES (2/3)
Figure No.
Title
Page
5-29
Minimum Pulse Width Estimate .................................................................................................................... 162
5-30
Pulse Narrowing ........................................................................................................................................... 162
5-31
System with Critical Paths ............................................................................................................................ 167
5-32
Example of Input-Input Critical Path ............................................................................................................. 169
5-33
Verification of Setup Time ............................................................................................................................. 169
5-34
Bus Configuration ........................................................................................................................................ 171
5-35
Examples of Internal Bus Floating Prevention Circuit .................................................................................. 171
5-36
External Bus Floating Prevention Countermeasure ..................................................................................... 173
5-37
Flip-Flop Initial Setting .................................................................................................................................. 174
5-38
Counter Division .......................................................................................................................................... 174
5-39
Racing .......................................................................................................................................................... 177
5-40
Example of Data Selector Circuit ................................................................................................................. 178
5-41
Example of Test Patterns (Before Improvement) .......................................................................................... 179
5-42
Example of Test Patterns (After Improvement) ............................................................................................. 180
6-1
Timing Phase ................................................................................................................................................ 185
6-2
Example of Incorrect Bidirectional Pin Switch Timing .................................................................................. 186
6-3
Contention During Input/Output Switching ................................................................................................... 187
6-4
Test Pattern Example ................................................................................................................................... 192
6-5
Strobe Time .................................................................................................................................................. 193
6-6
Real-Time Simulation Results ...................................................................................................................... 195
6-7
Concept of Fault Simulation ......................................................................................................................... 197
6-8
Creating Test Patterns by System Simulation .............................................................................................. 199
7-1
Equivalent Circuit Diagram for Buffer with Fail-Safe Function ...................................................................... 201
7-2
Example of Oscillator Configuration ............................................................................................................. 203
7-3
Oscillator Configuration ................................................................................................................................ 204
7-4
Example of GND Pattern on Board .............................................................................................................. 207
7-5
Single-Port RAM Circuit Configuration ......................................................................................................... 210
7-6
Dual-Port RAM Circuit Configuration .............................................................................................................211
7-7
Test Circuit (BIST) Block Diagram ................................................................................................................ 213
7-8
RAM Test Circuits ......................................................................................................................................... 214
7-9
Making TIN Pin Alternate Function ............................................................................................................... 217
7-10
Making TOUT Pin Alternate Function ........................................................................................................... 217
7-11
Example of Test Patterns .............................................................................................................................. 218
7-12
Theory of Scan Path Test Method ................................................................................................................ 219
A-1
Load Dependency of Power Consumption ................................................................................................... 221
B-1
Delay Time Increase Due to Input Waveform ............................................................................................... 222
D-1
Circuit Diagram Example .............................................................................................................................. 227
D-2
Bidirectional Pin Names ............................................................................................................................... 228
Design Manual A13826EJ6V0DM
17
LIST OF FIGURES (3/3)
Figure No.
Title
Page
D-3
Bidirectional Pin Test Pattern Generation ..................................................................................................... 228
D-4
3-State Output Pin Names ........................................................................................................................... 229
D-5
3-State Output Pin Test Pattern Generation ................................................................................................. 229
D-6
Handling Macros .......................................................................................................................................... 231
D-7
Timing Chart Entry ........................................................................................................................................ 232
D-8
Timing Chart Example .................................................................................................................................. 232
K-1
Leakage Current ........................................................................................................................................... 291
K-2
Current Consumption of On-Chip 50 kΩ Resistor (IPD) ................................................................................ 292
K-3
Current Consumption of On-Chip 5 kΩ Resistor (IPU) .................................................................................. 292
K-4
Input Through Current (VDD = 5.0 V CMOS Level) ....................................................................................... 293
K-5
Input Through Current (VDD = 5.0 V TTL Level) ............................................................................................ 293
K-6
Input Through Current (VDD = 5.5 V CMOS Level Schmitt) .......................................................................... 293
K-7
Input Through Current (VDD = 5.5 V TTL Level Schmitt) ............................................................................... 293
K-8
Input Through Current (VDD = 3.6 V CMOS Level) ....................................................................................... 294
K-9
Input Through Current (VDD = 3.3 V TTL Level) ............................................................................................ 294
K-10
Input Through Current (VDD = 3.6 V CMOS Level Schmitt) .......................................................................... 294
K-11
Input Through Current (VDD = 3.3 V TTL Level Schmitt) ............................................................................... 294
K-12
Oscillator Configuration Diagram ................................................................................................................. 295
K-13
fMAX. vs. CL Limit (CMOS Level Output) ........................................................................................................ 296
K-14
fMAX. vs. CL Limit (CMOS Level Low-Noise Output) ...................................................................................... 298
K-15
VDD Dependency of IOL / IOH ......................................................................................................................... 300
K-16
TA Dependency of IOL / IOH ........................................................................................................................... 300
K-17
IO vs. VO (@5.0 V) ........................................................................................................................................ 301
K-18
IO vs. VO (@3.3 V) ........................................................................................................................................ 303
K-19
Oscillator Configuration Diagram ................................................................................................................. 305
18
Design Manual A13826EJ6V0DM
LIST OF TABLES (1/2)
Table No.
Title
Page
2-1
Number of Cells Placed .................................................................................................................................. 28
2-2
Usable Gates and Pin-Pair Count .................................................................................................................. 28
2-3
List of Mountability .......................................................................................................................................... 32
2-4
Minimum Number of Cells Occupied by Basic Macro .................................................................................... 38
2-5
Occupied Cell Ranges .................................................................................................................................... 39
2-6
List of Packages ............................................................................................................................................. 49
3-1
Terminology for Absolute Maximum Ratings .................................................................................................. 98
3-2
Terminology for Recommended Operating Conditions ................................................................................... 98
3-3
Terminology for DC Characteristics ................................................................................................................ 99
3-4
Absolute Maximum Ratings .......................................................................................................................... 100
3-5
Recommended Operating Range (VDD = 5.0 V ±10%, TA = –40 to +85°C) .................................................. 101
3-6
DC Characteristics (VDD = 5.0 V ±10%, TA = –40 to +85°C) ......................................................................... 102
3-7
AC Characteristics (VDD = 5.0 V ±10%, TA = –40 to +85°C) ......................................................................... 103
3-8
Recommended Operating Range (VDD = 3.0 ±0.3 V, TA = –40 to +85°C) ..................................................... 104
3-9
DC Characteristics (VDD = 3.0 ±0.3 V, TA = –40 to +85°C) ........................................................................... 105
3-10
AC Characteristics (VDD = 3.0 ±0.3 V, TA = –40 to +85°C) ............................................................................ 106
3-11
Recommended Operating Range (VDD = 3.3 ±0.3 V, TA = –40 to +85°C) ..................................................... 107
3-12
DC Characteristics (VDD = 3.3 ±0.3 V, TA = –40 to +85°C) ........................................................................... 108
3-13
AC Characteristics (VDD = 3.3 ±0.3 V, TA = –40 to +85°C) ............................................................................ 109
5-1
F617 (D-F/F with RB, SB) ............................................................................................................................. 143
5-2
Features of Single-Phase and Multi-Phase Synchronous Circuit Design .................................................... 144
6-1
Test Pattern Types ........................................................................................................................................ 181
6-2
Restrictions on Pin Names ........................................................................................................................... 182
6-3
Limitations on Number of Test Patterns ........................................................................................................ 182
6-4
Timing Phase Number .................................................................................................................................. 184
6-5
Timing Constraints ........................................................................................................................................ 184
6-6
Clock Mode ................................................................................................................................................... 185
7-1
Recommended Oscillation Frequency Range and Configuration ................................................................ 203
7-2
Example of Criteria ....................................................................................................................................... 208
K-1
CMOS-N5 Family Products .......................................................................................................................... 306
K-2
Capacitance of Interface Block (CB) ............................................................................................................. 306
K-3
Capacitance of Packages (CP) (Preliminary Values) .................................................................................... 307
K-4
Power Consumption by Input Buffer ............................................................................................................. 307
K-5
Output Buffer Power Consumption ............................................................................................................... 308
K-6
Oscillator Power Consumption (Reference Values) (VDD = 5.0 V ±10%, TA = –40 to +85°C) ....................... 308
K-7
Compensation Coefficient (K1, K2) (VDD = 5.0 V ±10%, TA = –40 to +85°C) ................................................. 308
K-8
Maximum Allowable Power Consumption (TA = 85°C, TJ = 125°C) .............................................................. 309
K-9
Thermal Resistance ..................................................................................................................................... 309
Design Manual A13826EJ6V0DM
19
LIST OF TABLES (2/2)
Table No.
Title
Page
K-10
Wiring Capacitance Estimate (Wiring Length Converted to F/I Value) .......................................................... 311
K-11
tr and tf Calculation Coefficients of Output Buffer (VDD = 5.0 V, TA = 25°C) .................................................. 312
K-12
tr and tf Calculation Coefficients of Output Buffer (VDD = 3.3 V, TA = 25°C) .................................................. 312
K-13
Recommended Load Capacitance Ranges of Output Buffers (@5.0 V) ...................................................... 313
K-14
Recommended Load Capacitance Ranges of Output Buffers (@3.3 V) ...................................................... 313
K-15
Reference Time Ranges for Simultaneous Operation (TYP.) ....................................................................... 314
K-16
Permissible Number of Simultaneous Operation Pins Between 3 GND Pins (IOL = 12 mA) ........................ 314
K-17
Coefficient of Number of Simultaneous Operation Pins ............................................................................... 315
K-18
CTS Blocks (Reference) ............................................................................................................................... 316
K-19
List of Resonator Evaluations ....................................................................................................................... 316
K-20
Memory Blocks ............................................................................................................................................. 317
20
Design Manual A13826EJ6V0DM
CHAPTER 1 OVERVIEW
1.1 Features
The following table lists the CMOS-N5 Family features.
Very large-scale integration (VLSI) .......... 3 K to 120 K gates
Process ..................................................... 0.5 µ m rule Si gates, 2-layer metal routing
Input interface ........................................... CMOS TTL compatible
Internal blocks ........................................... More than 190 types of function blocks
Two types are available: high-speed and low-power
Scan path block
Driver for clock tree synthesis
Memory blocks .......................................... Single-port RAM
Dual-port RAM
Variety of peripheral blocks ...................... CMOS TTL level input buffer
Input buffer with fail-safe function
CMOS level output buffer
High drive capability buffer (IOL = 24.0 mA)
Low-noise output buffer
Buffer with internal pull-up resistor (5 kΩ/50 kΩ)
Buffer with internal pull-down resistor (50 kΩ)
Other ......................................................... High latch-up immunity
Design Manual A13826EJ6V0DM
21
CHAPTER 1 OVERVIEW
The features for each power supply voltage are as follows.
(1) V DD = 5.0 V ±10%
High-speed operation ............ tPD = 0.14 ns (2-input NAND (low power gate), fan-outs: 1, wiring length: 0 mm)
tPD = 0.21 ns (2-input NAND (low power gate), fan-outs: 1, standard wiring
length)
tPD = 0.46 ns (2-input NAND (low power gate), fan-outs: 2, wiring length: 2 mm)
tPD = 0.16 ns (2-input NAND, fan-outs: 1, standard wiring length)
tPD = 0.30 ns (2-input NAND, fan-outs: 2, wiring length: 2 mm)
tPD = 0.18 ns (2-input NAND, fan-outs: 2, standard wiring length)
tPD = 0.33 ns (input buffer, fan-outs: 2, wiring length: 2 mm)
tPD = 0.23 ns (input buffer, fan-outs: 1, standard wiring length)
tPD = 1.30 ns (output buffer, CL = 15 pF, IOL = 9 mA)
Power consumption ............... 1.35 µW/MHz/cell (internal gate, operating factor: 0.3)
Maximum clock frequency…..fMAX = 200 MHz (internal toggle F/F, fan-outs: 2, wiring length: 0 mm)
(2) V DD = 3.0 ±0.3 V
High-speed operation ............ tPD = 0.20 ns (2-input NAND (low power gate), fan-outs: 1, wiring length: 0 mm)
tPD = 0.30 ns (2-input NAND (low power gate), fan-outs: 1, standard wiring
length)
tPD = 0.23 ns (2-input NAND, fan-outs: 1, standard wiring length)
tPD = 0.42 ns (2-input NAND, fan-outs: 2, wiring length: 2 mm)
tPD = 0.26 ns (2-input NAND, fan-outs: 2, standard wiring length)
tPD = 0.47 ns (input buffer, fan-outs: 2, wiring length: 2 mm)
tPD = 0.34 ns (input buffer, fan-outs: 1, standard wiring length)
tPD = 2.16 ns (output buffer, CL = 15 pF, IOL = 9 mA)
Power consumption ............... 0.49 µW/MHz/cell (internal gate, operating factor: 0.3)
Maximum clock frequency….. fMAX = 120 MHz (internal toggle F/F, fan-outs: 2, wiring length: 0 mm)
(3) V DD = 3.3 ±0.3 V
High-speed operation ............ tPD = 0.18 ns (2-input NAND (low power gate), fan-outs: 1, wiring length: 0 mm)
tPD = 0.28 ns (2-input NAND (low power gate), fan-outs: 1, standard wiring
length)
tPD = 0.22 ns (2-input NAND, fan-outs: 1, standard wiring length)
tPD = 0.39 ns (2-input NAND, fan-outs: 2, wiring length: 2 mm)
tPD = 0.24 ns (2-input NAND, fan-outs: 2, standard wiring length)
tPD = 0.44 ns (input buffer, fan-outs: 2, wiring length: 2 mm)
tPD = 0.31 ns (input buffer, fan-outs: 1, standard wiring length)
tPD = 2.02 ns (output buffer, CL = 15 pF, IOL = 9 mA)
Power consumption…........... 0.59 µW/MHz/cell (internal gate, operating factor: 0.3)
Maximum clock frequency….. fMAX = 130 MHz (internal toggle F/F, fan-outs: 2, wiring length: 0 mm)
22
Design Manual A13826EJ6V0DM
CHAPTER 1 OVERVIEW
1.2 Internal Structure of CMOS-N5 Family
Figure 1-1 shows the CMOS gate array internal structure, which is comprised of an internal cell region and an I/O
cell region.
Figure 1-1. Gate Array Configuration
Internal cell
Internal cell region
I/O cell region
I/O cell
As shown in this figure, the CMOS-N5 Family does not have fixed routing regions in the internal cell region, and
the entire surface of the internal cell region is filled with basic cells.
The internal cell region consists of various function blocks (such as NAND gates and D-F/F) and memory that are
connected via routing layers to implement the desired circuit functions.
Input and output buffers are placed in the I/O cell region to adjust the input-level conversion and output drive
capability. Some internal cells are also part of the I/O buffer implementation.
Design Manual A13826EJ6V0DM
23
CHAPTER 1 OVERVIEW
1.3 Internal Cell Structure
The circuit diagram in Figure 1-2 represents a CMOS-N5 Family internal cell.
Each cell of the CMOS-N5 Family can be configured as a device such as a two-input NAND/NOR gate, an inverter,
or a buffer.
A CMOS circuit consists of a P-channel MOS transistor (P-ch. Tr) and an N-channel MOS transistor (N-ch. Tr).
Normally, either the P-ch. Tr or the N-ch. Tr is in the OFF state.
Figure 1-2. Internal Cell Equivalent Circuit
Because virtually no power flows in the steady state,
the power consumption for a CMOS circuit is extremely
low.
A CMOS circuit consumes current mostly during
switching. Because a high transient current flows during
switching, either a high-speed capacitor with a high
capacitance must be inserted between the power supply
and ground, or the impedance of the power supply lowered.
In addition, if a waveform with a slow rise/fall time is
applied to a CMOS circuit, both the P-ch. Tr and N-ch. Tr
will remain in the ON state for a period of time, causing
a through current to flow between the P-ch. Tr and N-ch.
Tr, resulting not only in increased current consumption
but also possible malfunction.
Figure 1-3 (a) and (b) show the equivalent circuits of a 2-input NOR gate and a 2-input NAND gate. Because the
ON resistance of the N-ch. Tr is about fifty percent less than that of the P-ch. Tr, a large current can be sent through
the N-ch. Tr. Therefore, as shown in Figure 1-3 (a), the ON resistance of the output rise side at the NOR gate, which
is serially connected to the P-ch. Tr, becomes larger, and the drive capability of the load drops.
In CMOS gate arrays, the NOR fan-out drive is slower than the NAND fan-out drive. Because of this, the NAND
blocks should be used as much as possible to increase the speed and stability of the circuit.
For the same reason, complex gates that serially connect many transistors tend to be slow, and therefore should
not be used in high-speed circuits. Use complex gates to improve cell utilization when speed is not as important.
24
Design Manual A13826EJ6V0DM
CHAPTER 1 OVERVIEW
Figure 1-3. Equivalent Circuits
(a) 2-Input NOR Equivalent Circuit
(b) 2-Input NAND Equivalent Circuit
VDD
VDD
A
Y
B
A
Y
B
1.4 QFP Package
Figure 1-4 shows a cross-section of a normal QFP package. In a normal QFP package, the chip is placed on a
metal plate called an island. The leads and chip are connected by fine bonding wires measuring only several 10 µ m
in diameter.
In a low thermal resistance type QFP package, the lead and island materials have increased thermal dissipation
properties. The construction itself is the same as a normal QFP package.
Figure 1-4. Cross-Section of QFP Package
Bonding wire
Lead
Chip
Island
Design Manual A13826EJ6V0DM
25
CHAPTER 2 SELECTING THE GATE ARRAY
When using gate arrays to develop an LSI to implement some or all of a system designed by the user, the
specifications must be determined so that the circuit scale and the number of I/O pins of the gate arrays are optimum.
As the circuit scale increases, designing the circuit becomes more difficult and the cost of the LSI increases.
However, because the number of I/O pins can be reduced, so can the mounting area on a printed wiring board.
In addition, because the number of LSIs used decreases, the propagation delay time is shortened.
However, as the circuit scale decreases, many separate gate arrays are required to configure the system. This
is disadvantageous in terms of printed circuit board mounting. Moreover, because signals are transferred between
many LSIs, it is difficult to shorten the propagation delay time.
Therefore, when selecting a gate array, take into consideration the propagation delay time and circuit scale.
Select a gate array in the following steps.
[Circuit selection steps]
(1) Estimate circuit scale and master size
↓
(2) Select package
↓
(3) Verify power consumption
↓
(4) Verify pin placement
↓
(5) Verify I/O interface level
↓
(6) Design circuit
↓
(7) Interface
↓
(8) Check using the check items
26
Design Manual A13826EJ6V0DM
CHAPTER 2 SELECTING THE GATE ARRAY
2.1 Estimating Circuit Scale
2.1.1 Cell utilization rate, usable cell and pin-pair count limits
In a channel architecture gate array, the internal cell region is divided into two regions.
• Region where transistors that implement the function block are placed
• Routing dedicated region
In a channelless architecture gate array, the region for implementing the function blocks cannot be clearly distinguished
from the routing region because the transistors that implement the function blocks are laid out over the entire internal
cell region. Consequently, there is a stronger correlation between the number of cells utilized and the number of nets.
The CMOS-N5 Family uses a channelless architecture (sea-of-gates). This means that not all cells in the internal
cell region can be used for function blocks such as gates, flip-flops, and memory. The number of cells actually used
is the difference between the total number of cells and the routing cell region used by the number of wires between
blocks (number of pin pairs).
The maximum cell utilization rate for the CMOS-N5 Family is as follows.
µPD65880, 65881, 65882, 65883, 65884 : 80%
µPD65885, 65887, 65889, 65890, 65893 : 70%
However, if a large-scale block, such as memory, is placed, it may be that the total cell utilization rate is further
limited, depending on the type of macro (see 2.1.3 Large-scale macro mounting for details).
The pin-pair count is limited by the cell utilization rate and can be calculated by the following formula:
Pin-pair count = 150 × number of raw cells × {(100 – cell utilization rate)/100}2/74.69
[Pin-pair count] is the number of wires connecting the output pins and input pins between blocks (see Figure
2-1).
Figure 2-1. Pin-Pair Count
H01
A
N01
H02
B
Block A N01-Block B H01
Block A N01-Block C H02
C
Total of 2 pairs (pin pair count = 2)
If many small-scale blocks such as inverters are used, routing between blocks increases compared with the number
of cells used, which increases the number of routing channels.
Conversely, if many large-scale blocks such as memory are used, routing between blocks decreases compared
with the number of cells used, which decreases the number of channels required.
Consequently, when placing large-scale blocks, such as memory, the cell utilization rate is further limited. Circuits
that do not include memory are limited by the pin-pair count.
Design Manual A13826EJ6V0DM
27
CHAPTER 2 SELECTING THE GATE ARRAY
Table 2-1. Number of Cells Placed
Master
X
Y
Cells Placed
µPD65880
108
32
3456
µPD65881
140
42
5880
µPD65882
218
64
13952
µPD65883
288
88
25344
µPD65884
332
102
33864
µPD65885
364
112
40768
µPD65887
428
130
55640
µPD65889
500
152
76000
µPD65890
572
174
99528
µPD65893
636
194
123384
Remark X × Y under the heading “Cells Placed” indicates that the master
has a cell space of X in the horizontal direction and a cell
space of Y in the vertical direction.
If the actual cell utilization rate and pin-pair count can be satisfied, placement and routing can be guaranteed in
the standard schedule in most cases. On the other hand, in cases where the limits are exceeded, placement and
routing requires a longer time and, in the worst case, becomes impossible.
Table 2-2 shows the number of usable gates and the corresponding pin-pair count with respect to the cell utilization
rate.
Table 2-2. Usable Gates and Pin-Pair Count (1/2)
Master
40% Cell Utilization
Usable
50% Cell Utilization
Pin Pairs
Usable
60% Cell Utilization
Pin Pairs
Usable
Pin Pairs
µPD65880
1382
2498
1728
1735
2073
1110
µPD65881
2352
4251
2940
2952
3528
1889
µPD65882
5580
10087
6976
7004
8371
4483
µPD65883
10137
18323
12672
12724
15206
8143
µPD65884
13545
24483
16932
17002
20318
10881
µPD65885
16307
29474
20384
20468
24460
13099
µPD65887
22256
40227
27820
27935
33384
17878
µPD65889
30400
54947
38000
38157
45600
24420
µPD65890
39811
71957
49764
49970
59716
31981
µPD65893
49353
89205
61692
61948
74030
39646
28
Design Manual A13826EJ6V0DM
CHAPTER 2 SELECTING THE GATE ARRAY
Table 2-2. Usable Gates and Pin-Pair Count (2/2)
Master
70% Cell Utilization
Usable
80% Cell Utilization
Pin Pairs
Usable
Pin Pairs
µPD65880
2419
624
2764
277
µPD65881
4116
1062
4704
472
µPD65882
9766
2521
11161
1120
µPD65883
17740
4580
20275
2035
µPD65884
23704
6120
27091
2720
µPD65885
28537
7368
32614
3274
µPD65887
38948
10056
44512
4469
µPD65889
53200
13736
60800
6105
µPD65890
69669
17989
79622
7995
µPD65893
86368
22301
98707
9911
Design Manual A13826EJ6V0DM
29
CHAPTER 2 SELECTING THE GATE ARRAY
2.1.2 Notes on estimating number of cells used
(1) Input/output/bidirectional buffer blocks
Not only I/O cells but also internal cells are used to configure external interface blocks such as input, output,
and bidirectional blocks. Therefore, add the number of internal cells used for input, output, and bidirectional
buffer blocks described in the CMOS-N5 Family Block Library (A13872E) when calculating the total number
of cells used.
(2) Critical paths
If there is a path in which speed is a problem, measures can be taken in some cases to shorten the propagation
delay of that path. However, routability drops dramatically when such measures are taken. In such a case,
the cell utilization rate and maximum pin-pair count should be reduced by about 10 to 20%.
(3) Macro configuration
Placement and routing are performed for each hierarchical macro (first hierarchy) in the circuit. Therefore,
the hierarchical configuration calls for adequate consideration when a macro is created. Keep in mind the
following points when performing hierarchical designing.
(a) Because the routing between macros of the first hierarchy is long, avoid hierarchical design that implements
one function between macros.
(b) Avoid placing a small-scale macro used to facilitate circuit designing in the first hierarchy.
30
Design Manual A13826EJ6V0DM
CHAPTER 2 SELECTING THE GATE ARRAY
2.1.3 Large-scale macro mounting
Large-scale macro mountability is determined by whether or not it is possible to achieve the range (X × Y) of cells
needed to implement the macros on the physical space of the internal cells indicated by (X × Y). For soft macros
configured by small and medium-scale blocks, virtually no problems of mounting arise as long as the cell utilization
rate is satisfied. However, there are cases in which large-scale hard macros such as RAM blocks (basic macro) and
megamacros cannot be physically mounted due to the size of the master.
(1) Where only one large-scale macro is mounted
Table 2-3 shows the mountability of each large-scale macro on each master.
Design Manual A13826EJ6V0DM
31
CHAPTER 2 SELECTING THE GATE ARRAY
Table 2-3. List of Mountability (1/3)
(a) Single-Port RAM
Master
RB47
RB49
RB4B
RB4D
RB87
RB89
RB8B
RB8D
µPD65880
√
√
√
√
×
×
×
×
√
√
√
×
×
×
µPD65881
√
√
√
√
×
×
×
×
√
√
√
×
×
×
µPD65882
√
√
√
√
√
√
×
×
√
√
√
√
√
×
µPD65883
√
√
√
√
√
√
√
×
√
√
√
√
√
√
µPD65884
√
√
√
√
√
√
√
√
√
√
√
√
√
√
µPD65885
√
√
√
√
√
√
√
√
√
√
√
√
√
√
µPD65887
√
√
√
√
√
√
√
√
√
√
√
√
√
√
µPD65889
√
√
√
√
√
√
√
√
√
√
√
√
√
√
µPD65890
√
√
√
√
√
√
√
√
√
√
√
√
√
√
µPD65893
√
√
√
√
√
√
√
√
√
√
√
√
√
√
Master
RB8M RBAB RBAD
RBAF
RB4F RB4H
RBAH RBC7
RB4M RB4S
RB8F RB8H
RBC9 RBCB RBCD RBCF RBCH RBCM RBEB RBED
µPD65880
×
√
×
×
×
√
√
×
×
×
×
×
×
×
µPD65881
×
√
×
×
×
√
√
√
×
×
×
×
×
×
µPD65882
×
√
√
√
×
√
√
√
√
×
×
×
√
√
µPD65883
×
√
√
√
×
√
√
√
√
√
×
×
√
√
µPD65884
√
√
√
√
√
√
√
√
√
√
√
×
√
√
µPD65885
√
√
√
√
√
√
√
√
√
√
√
×
√
√
µPD65887
√
√
√
√
√
√
√
√
√
√
√
×
√
√
µPD65889
√
√
√
√
√
√
√
√
√
√
√
√
√
√
µPD65890
√
√
√
√
√
√
√
√
√
√
√
√
√
√
µPD65893
√
√
√
√
√
√
√
√
√
√
√
√
√
√
Master
RBEF RBEH RBH7
RBH9
RBHB RBHD RBHF RBHH RBKB
RBKD RBKF RBKH
µPD65880
×
×
×
×
×
×
×
×
×
×
×
×
µPD65881
×
×
√
×
×
×
×
×
×
×
×
×
µPD65882
×
×
√
√
√
×
×
×
√
×
×
×
µPD65883
×
×
√
√
√
√
×
×
√
×
×
×
µPD65884
√
×
√
√
√
√
√
×
√
√
×
×
µPD65885
√
√
√
√
√
√
√
×
√
√
×
×
µPD65887
√
√
√
√
√
√
√
×
√
√
√
×
µPD65889
√
√
√
√
√
√
√
√
√
√
√
√
µPD65890
√
√
√
√
√
√
√
√
√
√
√
√
µPD65893
√
√
√
√
√
√
√
√
√
√
√
√
Remark √: Mountable, ×: Not mountable
32
Design Manual A13826EJ6V0DM
CHAPTER 2 SELECTING THE GATE ARRAY
Table 2-3. List of Mountability (2/3)
(b) Dual-Port RAM
Master
R947
R949
R94B
R94D
R987
R989
R98B
R98D
R98F
R9AB
µPD65880
√
√
√
√
×
×
√
√
√
×
×
√
×
√
µPD65881
√
√
√
√
×
×
√
√
√
×
×
√
×
√
µPD65882
√
√
√
√
√
×
√
√
√
√
×
√
√
√
µPD65883
√
√
√
√
√
√
√
√
√
√
√
√
√
√
µPD65884
√
√
√
√
√
√
√
√
√
√
√
√
√
√
µPD65885
√
√
√
√
√
√
√
√
√
√
√
√
√
√
µPD65887
√
√
√
√
√
√
√
√
√
√
√
√
√
√
µPD65889
√
√
√
√
√
√
√
√
√
√
√
√
√
√
µPD65890
√
√
√
√
√
√
√
√
√
√
√
√
√
√
µPD65893
√
√
√
√
√
√
√
√
√
√
√
√
√
√
Master
R9C9
R9CF
R9EB
R9ED
R9H7
R9H9
R9HB
R9KB
µPD65880
×
×
×
×
×
×
×
×
×
×
µPD65881
√
×
×
×
×
×
×
×
×
×
µPD65882
√
√
×
×
√
×
√
√
×
×
µPD65883
√
√
√
√
√
√
√
√
√
√
µPD65884
√
√
√
√
√
√
√
√
√
√
µPD65885
√
√
√
√
√
√
√
√
√
√
µPD65887
√
√
√
√
√
√
√
√
√
√
µPD65889
√
√
√
√
√
√
√
√
√
√
µPD65890
√
√
√
√
√
√
√
√
√
√
µPD65893
√
√
√
√
√
√
√
√
√
√
R9CB R9CD
R94F R94H
R9AD R9C7
Remark √: Mountable, ×: Not mountable
Design Manual A13826EJ6V0DM
33
CHAPTER 2 SELECTING THE GATE ARRAY
Table 2-3. List of Mountability (3/3)
(c) Megamacro
Master
NA37A
NA51A
NA54A
NA55A
NA59A
NA16550A
µPD65880
×
×
×
√
×
×
µPD65881
×
√
×
√
√
×
µPD65882
√
√
√
√
√
√
µPD65883
√
√
√
√
√
√
µPD65884
√
√
√
√
√
√
µPD65885
√
√
√
√
√
√
µPD65887
√
√
√
√
√
√
µPD65889
√
√
√
√
√
√
µPD65890
√
√
√
√
√
√
µPD65893
√
√
√
√
√
√
Remark √: Mountable, ×: Not mountable
34
Design Manual A13826EJ6V0DM
;
CHAPTER 2 SELECTING THE GATE ARRAY
(2) Where two or more large-scale macros are mounted
Whether two or more macros can be mounted is determined by the range of the cells necessary for implementing
each macro on the chip, and the range of cells that can be implemented on the master.
(a) Range of cells occupied by each macro on chip (soft macro RAM)
An NEC RAM is implemented by soft macros that consist of a basic macro and a logic area. The shape
of the cell area occupied to implement a macro depends on how the basic macro is placed. The cell area
occupied is limited by the master selected.
Figure 2-2. Shape of Cell Range Occupied by Macros (with 4 Basic Macros)
Basic macros
<2>
<1>
<3>
<4>
<1> Limited by the number of vertical cells of the master.
<2> Limited by the number of horizontal cells of the master.
<3> Effective if the number of basic blocks used becomes large.
<4> Physically possible but ineffective (because the placement range that can be set up during
placement and routing is square or rectangular, the diagonally shaded area is wasted).
Table 2-5 lists examples of the cell ranges occupied by macros. However, it is possible to redefine cell
ranges for a RAM outside those in Table 2-4.
To define cell ranges for soft macro RAM, first find the basic macro name and the number of cells required
to configure the soft macro RAM in Table 2-5. Next, find the minimum number of cells occupied by the
macro (X and Y values) in order to place one basic macro in Table 2-4. Then calculate the cell range by
substituting in the variables in the following equation with the values from Tables 2-4 and 2-5.
Design Manual A13826EJ6V0DM
35
CHAPTER 2 SELECTING THE GATE ARRAY
Figure 2-3. Cell Range Occupied by Macro
Y
Hy
y
Hx
x
y = 2n × Hy + Y
x = soft/uty/y
In the above equation, x ≥ N/2 n × Hx must be satisfied.
soft:
Number of cells in the soft macro RAM
uty:
0.60
Hx:
Minimum number of cells occupied in the horizontal direction needed for placing basic macros.
Hy:
Minimum number of cells occupied in the vertical direction needed for placing basic macros.
N:
Number of basic macros used
n
When the number of basic macros is 1, n = 0
When the number of basic macros is 2, n = 0, 1
When the number of basic macros is 4, n = 0, 1, 2
When the number of basic macros is 8, n = 0, 1, 2, 3
When the number of basic macros is 16, n = 0, 1, 2, 3, 4
When the number of basic macros is 32, n = 0, 1, 2, 3, 4, 5
Y:
36
Arbitrary integer (Y = 0, 1, 2, ...)
Design Manual A13826EJ6V0DM
CHAPTER 2 SELECTING THE GATE ARRAY
(b) Array of internal cells of master selected (see Table 2-1)
Internal cells are also used for interface blocks and are limited as closely as possible to the I/O cell range
in the CMOS-N5 Family. The area of internal cells used by the interface block is 17 internal cells from
the left edge to the right edge and 2 cells from the top edge to the bottom edge. Therefore the cell area
in which the macro can be placed must be within the 17 × 2 range (blank part).
Figure 2-4. Area Where Macros Cannot Be Implemented
Internal cells
1
5
10
17
I/O cells
(c) Determining mountability
Macros are mountable if they can all be placed without overlapping, within the allowable area for implementing
macros on the chip. If they are unmountable, modification of the shape of the macro-occupied area must
be considered. If only a few cells overlap, contact NEC to determine mountability taking the pin configuration
and macro placement position into consideration.
Design Manual A13826EJ6V0DM
37
CHAPTER 2 SELECTING THE GATE ARRAY
Table 2-4. Minimum Number of Cells Occupied by Basic Macro
(a) Single-Port RAM
Basic Macro Name
Words
Bits
X
Y
K147
16
4
29
12
K149
32
4
47
13
K14D
128
4
79
22
K18B
64
8
81
21
K18F
256
8
158
38
K1AB
64
10
81
25
(b) Dual-Port RAM
38
Basic Macro Name
Words
Bits
X
Y
K247
16
4
37
13
K249
32
4
63
15
K24D
128
4
112
24
K28B
64
8
113
24
K28F
256
8
224
41
K2AB
64
10
113
28
Design Manual A13826EJ6V0DM
CHAPTER 2 SELECTING THE GATE ARRAY
Table 2-5 shows the block names and cell ranges occupied by each RAM macro on the chip.
Table 2-5. Occupied Cell Ranges (1/8)
(a) Single-Port RAM (75% Cell Utilization)
Cell Ranges Occupied by RAM
Words × Bits
16 × 4
Soft Macro
RAM
RB47
Basic Macro × Q’ty
Type A
Type B
X
Y
K147 × 1
54
12
13
X
Y
122
13
Type C
X
Y
32 × 4
RB49
K149 × 1
71
64 × 4
RB4B
K149 × 2
61
26
128 × 4
RB4D
K14D × 1
96
22
256 × 4
RB4F
K14D × 2
89
44
177
22
512 × 4
RB4H
K14D × 4
81
91
168
44
335
22
1K × 4
RB4M
K14D × 8
78
185
159
91
328
44
2K × 4
RB4S
K14D × 16
155
185
155
91
16 × 8
RB87
K147 × 2
44
24
87
12
122
13
177
22
346
25
32 × 8
RB89
K149 × 2
61
26
64 × 8
RB8B
K18B × 1
100
21
128 × 8
RB8D
K14D × 2
89
44
256 × 8
RB8F
K18F × 1
170
38
512 × 8
RB8H
K18F × 2
165
76
329
38
323
76
181
25
1K × 8
RB8M
K18F × 4
159
155
64 × 10
RBAB
K1AB × 1
98
25
128 × 10
RBAD
K1AB × 2
91
50
256 × 10
RBAF
K1AB × 4
84
103
173
50
512 × 10
RBAH
K1AB × 8
164
103
338
50
16 × 16
RBC7
K147 × 4
36
51
77
24
153
12
224
13
340
22
350
25
32 × 16
RBC9
K149 × 4
53
55
112
26
64 × 16
RBCB
K18B × 2
93
42
186
21
128 × 16
RBCD
K14D × 4
82
91
170
44
256 × 16
RBCF
K18F × 2
165
76
330
38
512 × 16
RBCH
K18F × 4
159
155
324
76
1K × 16
RBCM
K18F × 8
315
155
64 × 20
RBEB
K1AB × 2
93
50
185
25
128 × 20
RBED
K1AB × 4
85
103
175
50
339
50
Type D
X
Y
256 × 20
RBEF
K1AB × 8
165
103
512 × 20
RBEH
K1AB × 16
324
103
16 × 32
RBH7
K147 × 8
33
105
68
51
143
24
286
12
32 × 32
RBH9
K149 × 8
50
113
101
55
214
26
427
13
64 × 32
RBHB
K18B × 4
87
87
179
42
357
21
128 × 32
RBHD
K14D × 8
79
185
161
91
333
44
256 × 32
RBHF
K18F × 4
160
155
325
76
512 × 32
RBHH
K18F × 8
315
155
357
25
64 × 40
RBKB
K1AB × 4
87
103
179
50
128 × 40
RBKD
K1AB × 8
167
103
343
50
256 × 40
RBKF
K18F × 5
315
117
485
76
512 × 40
RBKH
K18F × 10
474
155
624
117
Design Manual A13826EJ6V0DM
39
CHAPTER 2 SELECTING THE GATE ARRAY
Table 2-5. Occupied Cell Ranges (2/8)
(b) Single-Port RAM (70% Cell Utilization)
Cell Ranges Occupied by RAM
Words × Bits
40
Soft Macro
RAM
Basic Macro × Q’ty
Type A
Type B
X
Y
K147 × 1
56
12
RB49
K149 × 1
73
13
RB4B
K149 × 2
62
26
RB4D
K14D × 1
97
22
256 × 4
RB4F
K14D × 2
89
512 × 4
RB4H
K14D × 4
82
1K × 4
RB4M
K14D × 8
79
2K × 4
RB4S
K14D × 16
155
16 × 8
RB87
K147 × 2
45
32 × 8
RB89
K149 × 2
64 × 8
RB8B
K18B × 1
128 × 8
RB8D
K14D × 2
89
44
256 × 8
RB8F
K18F × 1
171
38
512 × 8
RB8H
K18F × 2
165
16 × 4
RB47
32 × 4
64 × 4
128 × 4
X
Y
124
13
44
178
22
91
168
185
185
24
89
12
62
26
124
13
101
21
178
22
76
330
38
324
76
183
25
1K × 8
RB8M
K18F × 4
159
155
64 × 10
RBAB
K1AB × 1
99
25
128 × 10
RBAD
K1AB × 2
92
50
Type C
X
Y
44
336
22
159
91
329
44
314
91
347
25
256 × 10
RBAF
K1AB × 4
85
103
174
50
512 × 10
RBAH
K1AB × 8
165
103
338
50
16 × 16
RBC7
K147 × 4
37
51
78
24
156
12
227
13
341
22
352
25
32 × 16
RBC9
K149 × 4
54
55
114
26
64 × 16
RBCB
K18B × 2
94
42
187
21
128 × 16
RBCD
K14D × 4
83
91
171
44
256 × 16
RBCF
K18F × 2
166
76
331
38
512 × 16
RBCH
K18F × 4
159
155
325
76
1K × 16
RBCM
K18F × 8
315
155
64 × 20
RBEB
K1AB × 2
93
50
186
25
128 × 20
RBED
K1AB × 4
86
103
176
50
340
50
Type D
X
Y
256 × 20
RBEF
K1AB × 8
165
103
512 × 20
RBEH
K1AB × 16
324
103
16 × 32
RBH7
K147 × 8
34
105
68
51
145
24
289
12
32 × 32
RBH9
K149 × 8
50
113
102
55
216
26
431
13
64 × 32
RBHB
K18B × 4
87
87
180
42
359
21
128 × 32
RBHD
K14D × 8
80
185
162
91
334
44
256 × 32
RBHF
K18F × 4
160
155
326
76
512 × 32
RBHH
K18F × 8
316
155
359
25
64 × 40
RBKB
K1AB × 4
88
103
180
50
128 × 40
RBKD
K1AB × 8
168
103
345
50
256 × 40
RBKF
K18F × 5
315
117
485
76
512 × 40
RBKH
K18F × 10
474
155
624
117
Design Manual A13826EJ6V0DM
CHAPTER 2 SELECTING THE GATE ARRAY
Table 2-5. Occupied Cell Ranges (3/8)
(c) Single-Port RAM (60% Cell Utilization)
Cell Ranges Occupied by RAM
Words × Bits
Soft Macro
RAM
Basic Macro × Q’ty
Type A
Type B
X
Y
K147 × 1
61
12
RB49
K149 × 1
77
13
RB4B
K149 × 2
65
26
RB4D
K14D × 1
100
22
256 × 4
RB4F
K14D × 2
91
512 × 4
RB4H
K14D × 4
82
1K × 4
RB4M
K14D × 8
79
2K × 4
RB4S
K14D × 16
155
16 × 8
RB87
K147 × 2
47
32 × 8
RB89
K149 × 2
64 × 8
RB8B
K18B × 1
128 × 8
RB8D
K14D × 2
91
44
256 × 8
RB8F
K18F × 1
173
38
512 × 8
RB8H
K18F × 2
166
16 × 4
RB47
32 × 4
64 × 4
128 × 4
X
Y
129
13
44
181
22
91
170
185
185
24
94
12
65
26
129
13
105
21
182
22
76
332
38
325
76
186
25
1K × 8
RB8M
K18F × 4
159
155
64 × 10
RBAB
K1AB × 1
102
25
128 × 10
RBAD
K1AB × 2
93
50
Type C
X
Y
44
339
22
160
91
331
44
316
91
351
25
256 × 10
RBAF
K1AB × 4
86
103
176
50
512 × 10
RBAH
K1AB × 8
166
103
341
50
16 × 16
RBC7
K147 × 4
39
51
81
24
162
12
233
13
345
22
356
25
32 × 16
RBC9
K149 × 4
55
55
117
26
64 × 16
RBCB
K18B × 2
96
42
191
21
128 × 16
RBCD
K14D × 4
84
91
173
44
256 × 16
RBCF
K18F × 2
167
76
334
38
512 × 16
RBCH
K18F × 4
160
155
326
76
1K × 16
RBCM
K18F × 8
316
155
64 × 20
RBEB
K1AB × 2
95
50
190
25
128 × 20
RBED
K1AB × 4
87
103
178
50
343
50
Type D
X
Y
256 × 20
RBEF
K1AB × 8
167
103
512 × 20
RBEH
K1AB × 16
326
103
16 × 32
RBH7
K147 × 8
35
105
71
51
150
24
299
12
32 × 32
RBH9
K149 × 8
51
113
104
55
220
26
440
13
64 × 32
RBHB
K18B × 4
89
87
183
42
365
21
128 × 32
RBHD
K14D × 8
80
185
163
91
337
44
256 × 32
RBHF
K18F × 4
161
155
328
76
512 × 32
RBHH
K18F × 8
317
155
365
25
64 × 40
RBKB
K1AB × 4
89
103
183
50
128 × 40
RBKD
K1AB × 8
169
103
348
50
256 × 40
RBKF
K18F × 5
317
117
487
76
512 × 40
RBKH
K18F × 10
474
155
626
117
Design Manual A13826EJ6V0DM
41
CHAPTER 2 SELECTING THE GATE ARRAY
Table 2-5. Occupied Cell Ranges (4/8)
(d) Single-Port RAM (50% Cell Utilization)
Cell Ranges Occupied by RAM
Words × Bits
42
Soft Macro
RAM
Basic Macro × Q’ty
Type A
Type B
X
Y
K147 × 1
67
12
RB49
K149 × 1
83
13
RB4B
K149 × 2
68
26
RB4D
K14D × 1
104
22
256 × 4
RB4F
K14D × 2
93
512 × 4
RB4H
K14D × 4
83
1K × 4
RB4M
K14D × 8
80
2K × 4
RB4S
K14D × 16
156
16 × 8
RB87
K147 × 2
51
32 × 8
RB89
K149 × 2
64 × 8
RB8B
K18B × 1
128 × 8
RB8D
K14D × 2
93
44
256 × 8
RB8F
K18F × 1
175
38
512 × 8
RB8H
K18F × 2
168
16 × 4
RB47
32 × 4
64 × 4
128 × 4
X
Y
135
13
44
186
22
91
172
185
185
24
101
12
68
26
136
13
109
21
186
22
76
336
38
326
76
191
25
1K × 8
RB8M
K18F × 4
160
155
64 × 10
RBAB
K1AB × 1
107
25
128 × 10
RBAD
K1AB × 2
96
50
Type C
X
Y
44
344
22
162
91
334
44
156
91
356
25
256 × 10
RBAF
K1AB × 4
87
103
178
50
512 × 10
RBAH
K1AB × 8
167
103
344
50
16 × 16
RBC7
K147 × 4
41
51
86
24
171
12
242
13
351
22
362
25
32 × 16
RBC9
K149 × 4
58
55
121
26
64 × 16
RBCB
K18B × 2
99
42
197
21
128 × 16
RBCD
K14D × 4
85
91
176
44
256 × 16
RBCF
K18F × 2
169
76
337
38
512 × 16
RBCH
K18F × 4
161
155
328
76
1K × 16
RBCM
K18F × 8
317
155
64 × 20
RBEB
K1AB × 2
98
50
196
25
128 × 20
RBED
K1AB × 4
88
103
181
50
347
50
Type D
X
Y
256 × 20
RBEF
K1AB × 8
168
103
512 × 20
RBEH
K1AB × 16
328
103
16 × 32
RBH7
K147 × 8
36
105
74
51
156
24
312
12
32 × 32
RBH9
K149 × 8
52
113
107
55
226
26
452
13
64 × 32
RBHB
K18B × 4
91
87
187
42
373
21
128 × 32
RBHD
K14D × 8
81
185
165
91
341
44
256 × 32
RBHF
K18F × 4
162
155
330
76
512 × 32
RBHH
K18F × 8
318
155
373
25
64 × 40
RBKB
K1AB × 4
91
103
187
50
128 × 40
RBKD
K1AB × 8
171
103
353
50
256 × 40
RBKF
K18F × 5
318
117
490
76
512 × 40
RBKH
K18F × 10
474
155
628
117
Design Manual A13826EJ6V0DM
CHAPTER 2 SELECTING THE GATE ARRAY
Table 2-5. Occupied Cell Ranges (5/8)
(e) Dual-Port RAM (75% Cell Utilization)
Cell Ranges Occupied by RAM
Words × Bits
16 × 4
Soft Macro
RAM
R947
Basic Macro × Q’ty
Type A
Type B
X
Y
K247 × 1
63
13
15
32 × 4
R949
K249 × 1
85
64 × 4
R94B
K249 × 2
76
30
128 × 4
R94D
K24D × 1
129
24
X
Y
151
15
Type C
X
Y
465
24
256 × 4
R94F
K24D × 2
121
48
242
24
512 × 4
R94H
K24D × 4
113
99
233
48
16 × 8
R987
K247 × 2
56
26
111
13
32 × 8
R989
K249 × 2
75
30
150
15
64 × 8
R98B
K28B × 1
131
24
128 × 8
R98D
K24D × 2
121
48
242
24
256 × 8
R98F
K28F × 1
235
41
64 × 10
R9AB
K2AB × 1
129
28
128 × 10
R9AD
K2AB × 2
122
56
244
28
16 × 16
R9C7
K247 × 4
44
55
93
26
186
13
281
15
469
24
Type D
X
Y
32 × 16
R9C9
K249 × 4
67
63
141
30
64 × 16
R9CB
K28B × 2
124
48
247
24
128 × 16
R9CD
K24D × 4
114
99
235
48
256 × 16
R9CF
K28F × 2
230
82
460
41
64 × 20
R9EB
K2AB × 2
123
56
246
28
128 × 20
R9ED
K2AB × 4
116
115
237
56
474
28
16 × 32
R9H7
K247 × 8
41
113
83
55
175
26
349
13
32 × 32
R9H9
K249 × 8
63
129
129
63
271
30
541
15
64 × 32
R9HB
K28B × 4
117
99
240
48
480
24
64 × 40
R9KB
K2AB × 4
117
115
240
56
480
28
Design Manual A13826EJ6V0DM
43
CHAPTER 2 SELECTING THE GATE ARRAY
Table 2-5. Occupied Cell Ranges (6/8)
(f) Dual-Port RAM (70% Cell Utilization)
Cell Ranges Occupied by RAM
Words × Bits
16 × 4
44
Soft Macro
RAM
R947
Basic Macro × Q’ty
Type A
Type B
X
Y
K247 × 1
65
13
15
32 × 4
R949
K249 × 1
87
64 × 4
R94B
K249 × 2
77
30
128 × 4
R94D
K24D × 1
130
24
X
Y
153
15
Type C
X
Y
467
24
256 × 4
R94F
K24D × 2
122
48
243
24
512 × 4
R94H
K24D × 4
113
99
234
48
16 × 8
R987
K247 × 2
53
26
105
13
32 × 8
R989
K249 × 2
76
30
152
15
64 × 8
R98B
K28B × 1
132
24
128 × 8
R98D
K24D × 2
122
48
244
24
256 × 8
R98F
K28F × 1
236
41
64 × 10
R9AB
K2AB × 1
130
28
128 × 10
R9AD
K2AB × 2
123
56
246
28
16 × 16
R9C7
K247 × 4
45
55
95
26
189
13
283
15
470
24
Type D
X
Y
32 × 16
R9C9
K249 × 4
68
63
142
30
64 × 16
R9CB
K28B × 2
125
48
249
24
128 × 16
R9CD
K24D × 4
114
99
235
48
256 × 16
R9CF
K28F × 2
230
82
460
41
64 × 20
R9EB
K2AB × 2
124
56
248
28
128 × 20
R9ED
K2AB × 4
116
115
238
56
476
28
16 × 32
R9H7
K247 × 8
41
113
84
55
177
26
353
13
32 × 32
R9H9
K249 × 8
64
129
130
63
272
30
543
15
64 × 32
R9HB
K28B × 4
117
99
241
48
482
24
64 × 40
R9KB
K2AB × 4
118
115
241
56
482
28
Design Manual A13826EJ6V0DM
CHAPTER 2 SELECTING THE GATE ARRAY
Table 2-5. Occupied Cell Ranges (7/8)
(g) Dual-Port RAM (60% Cell Utilization)
Cell Ranges Occupied by RAM
Words × Bits
16 × 4
Soft Macro
RAM
R947
Basic Macro × Q’ty
Type A
Type B
X
Y
K247 × 1
69
13
15
32 × 4
R949
K249 × 1
91
64 × 4
R94B
K249 × 2
79
30
128 × 4
R94D
K24D × 1
133
24
X
Y
157
15
Type C
X
Y
470
24
256 × 4
R94F
K24D × 2
123
48
246
24
512 × 4
R94H
K24D × 4
114
99
235
48
16 × 8
R987
K247 × 2
56
26
111
13
32 × 8
R989
K249 × 2
78
30
156
15
64 × 8
R98B
K28B × 1
135
24
128 × 8
R98D
K24D × 2
124
48
247
24
256 × 8
R98F
K28F × 1
238
41
64 × 10
R9AB
K2AB × 1
133
28
128 × 10
R9AD
K2AB × 2
125
56
249
28
16 × 16
R9C7
K247 × 4
47
55
98
26
196
13
288
15
474
24
Type D
X
Y
32 × 16
R9C9
K249 × 4
69
63
144
30
64 × 16
R9CB
K28B × 2
127
48
253
24
128 × 16
R9CD
K24D × 4
115
99
237
48
256 × 16
R9CF
K28F × 2
231
82
462
41
64 × 20
R9EB
K2AB × 2
126
56
251
28
128 × 20
R9ED
K2AB × 4
117
115
240
56
480
28
16 × 32
R9H7
K247 × 8
42
113
86
55
182
26
363
13
32 × 32
R9H9
K249 × 8
64
129
131
63
275
30
550
15
64 × 32
R9HB
K28B × 4
118
99
244
48
487
24
64 × 40
R9KB
K2AB × 4
119
115
244
56
487
28
Design Manual A13826EJ6V0DM
45
CHAPTER 2 SELECTING THE GATE ARRAY
Table 2-5. Occupied Cell Ranges (8/8)
(h) Dual-Port RAM (50% Cell Utilization)
Cell Ranges Occupied by RAM
Words × Bits
16 × 4
46
Soft Macro
RAM
R947
Basic Macro × Q’ty
Type A
Type B
X
Y
K247 × 1
75
13
15
32 × 4
R949
K249 × 1
96
64 × 4
R94B
K249 × 2
82
30
128 × 4
R94D
K24D × 1
137
24
X
Y
163
15
Type C
X
Y
474
24
256 × 4
R94F
K24D × 2
126
48
251
24
512 × 4
R94H
K24D × 4
115
99
237
48
16 × 8
R987
K247 × 2
59
26
118
13
32 × 8
R989
K249 × 2
81
30
162
15
64 × 8
R98B
K28B × 1
139
24
128 × 8
R98D
K24D × 2
126
48
251
24
256 × 8
R98F
K28F × 1
240
41
64 × 10
R9AB
K2AB × 1
137
28
128 × 10
R9AD
K2AB × 2
127
56
253
28
16 × 16
R9C7
K247 × 4
49
55
103
26
205
13
296
15
479
24
Type D
X
Y
32 × 16
R9C9
K249 × 4
71
63
148
30
64 × 16
R9CB
K28B × 2
129
48
258
24
128 × 16
R9CD
K24D × 4
117
99
240
48
256 × 16
R9CF
K28F × 2
233
82
465
41
64 × 20
R9EB
K2AB × 2
128
56
256
28
128 × 20
R9ED
K2AB × 4
119
115
243
56
485
28
16 × 32
R9H7
K247 × 8
44
113
89
55
188
26
376
13
32 × 32
R9H9
K249 × 8
65
129
133
63
280
30
559
15
64 × 32
R9HB
K28B × 4
120
99
247
48
494
24
64 × 40
R9KB
K2AB × 4
121
115
247
56
494
28
Design Manual A13826EJ6V0DM
CHAPTER 2 SELECTING THE GATE ARRAY
2.1.4 Notes on mounting large-scale macros (memory)
The following points must be noted when mounting large-scale macros.
• External pin placement
• Block type used for circuits other than macros
(1) External pin placement
Place related external pins close to macros if two or more large-scale macros are mounted. If no consideration
is given to pin placement, the routing of external pins may be long and routing channels wasted.
As a result, routing may not be completed. When mounting two or more large-scale macros, contact NEC for
the macro placement method.
(2) Block type used for circuits other than macros
When the number of cells that can be used for logic is reduced because of large-scale macros, medium-scale
macros, such as 8-bit latches, may not fit in the available space.
Design Manual A13826EJ6V0DM
47
CHAPTER 2 SELECTING THE GATE ARRAY
2.2 Package Selection
The CMOS-N5 Family offers a variety of packages for each master. Base package selection first on the number
of I/O pins in the circuit specification.
There are no input-only or output-only pins in the CMOS-N5 family. Also, the number of I/O pins and the number
of power supply pins may differ depending on the master used. For details, see APPENDIX F PIN DESCRIPTIONS.
48
Design Manual A13826EJ6V0DM
Design Manual A13826EJ6V0DM
0.5
0.5
1.27
0.8
0.8
0.8
0.8
144 pins Note
160 pins
Plastic BGA 256 pins
80 pins
108 pins
144 pins
160 pins
Plastic
FBGA
1.0
1.0
1.4
1.4
1.4
1.4
2.13
1.31
1.51
1.51
1.51
14 × 14
14 × 14
10 × 10
14 × 14
20 × 20
24 × 24
27 × 27
9×9
11 × 11
13 × 13
13 × 13
—
—
—
—
—
—
—
—
√
—
—
—
—
—
√
—
—
—
—
—
—
—
—
—
—
—
—
√
—
—
—
√
√
—
—
—
—
—
—
—
—
—
—
√
—
√
√
√
—
—
—
—
—
—
—
√
√
√
—
—
—
—
—
—
√
√
—
—
—
—
—
—
—
—
—
√
—
—
—
—
—
√
√
—
—
√
—
—
—
—
√
√
√
—
√
—
—
—
—
—
—
—
—
√
√
—
—
—
√
—
—
—
—
—
—
—
—
√
√
√
—
—
—
—
—
—
—
—
—
—
—
√
√
√
—
µPD65880 µPD65881 µPD65882 µPD65883 µPD65884 µPD65885 µPD65887 µPD65889 µPD65890 µPD65893
Remark √: Released, —: Cannot be used, Blank: Under study
Low thermal resistance type
0.5
100 pins Note
Note
0.8
0.4
120 pins
44 pins
LQFP
0.5
1.0
10 × 10
0.5
64 pins Note
100 pins Note
1.0
12 × 12
0.65
64 pins
1.0
1.0
7×7
0.5
48 pins Note
12 × 12
3.7
40 × 40
0.5
304 pins Note
0.5
3.2
32 × 32
0.5
240 pins Note
80 pins
3.2
28 × 28
0.5
TQFP
2.7
24 × 24
Body
0.5
Body Size
QFP
160 pins Note
(fine pitch)
208 pins Note
(mm)
Lead Pitch
(mm)
Pins
Number of
Thickness
(mm)
Package
Table 2-6. List of Packages
CHAPTER 2 SELECTING THE GATE ARRAY
49
CHAPTER 2 SELECTING THE GATE ARRAY
2.3 Verifying Power Consumption
Although CMOS gate arrays are of a low power consumption type, a considerable amount of power is consumed
when they are operated at speeds greater than 30 MHz. The temperature of the LSI increases with the amount of
power used. The reliability of the product is not guaranteed if the temperature increases beyond the maximum values
specified here, therefore it is necessary to hold the power consumption of the LSI below these maximum values.
The maximum power consumption limit varies depending on the package type. To improve the allowable power
consumption, special QFP packages with low thermal resistance heat spreaders are provided. Figure 2-5 shows the
relationship between the QFP type and the allowable power consumption. For detailed data, see 4.3 Power Consumption.
Figure 2-5. Allowable Power Consumption vs. QFP Type
Allowable power consumption
Low
Standard product
50
High
Low thermal resistance type
Design Manual A13826EJ6V0DM
Heat spreader
CHAPTER 2 SELECTING THE GATE ARRAY
2.4 Pin Placement
The positions of the package power supply pins and NC pins are predetermined. The points noted below must
be considered in determining the pin layout (pin placement).
There are cases where the power requirement will increase, depending on the results of investigating items such
as the number of simultaneously operating output pins.
For details, see 4.6 Restrictions to Simultaneous Operation of Output Buffers.
2.4.1 Notes on pin layout
(1) Clock pins, control (set, reset) pins
Because these pins are subject to noise, they must be placed close to ground (GND) pins.
(2) Output pins
Because output pins are subject to clock pin noise, they should be isolated as much as possible. If a large
group of output pins has many simultaneously operating pins, the group should be surrounded by V DD and GND
pins.
(3) No connection (NC) pins
When a gate array is mounted on a printed circuit board, do not use an NC pin as a signal relay pin.
Some NC pins are actually connected to the pads of the chip. Connect the NC pins to ground (GND) or V DD
when mounting on a printed circuit board.
(4) Scan path I/O pins
The placement of test pins for each package is predetermined. If scan path is used, be sure to specify scan
path I/O pins for the specified pin number.
For details, see Design For Test User’s Manual (A14357E).
(5) Placing oscillator
For details of the positions at which an oscillator can be placed, see APPENDIX G PINS ASSIGNABLE TO
OSCILLATORNote.
Do not place pins that may malfunction when noise is superimposed on them (such as a reset pin) in the vicinity
of the oscillator.
Note
If there is no information for the package to be used, contact NEC.
Design Manual A13826EJ6V0DM
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CHAPTER 2 SELECTING THE GATE ARRAY
2.5 I/O Interface
2.5.1 Input blocks
Signal Level
Function
Input Format
CMOS
Buffer
Normal
TTL
Fail safe
Schmitt trigger
Pull-Up/Pull-Down Resistor
No resistor
With 50 kΩ pull-up resistor
With 5 kΩ pull-up resistor
With 50 kΩ pull-down resistor
Signal Level
Function
Input Format
LVTTL
Oscillator
Special
There are two types of input interface blocks:
<1> CMOS level interface block
This block connects to the current CMOS LSI. Blocks with fail-safe functions are also available. A block with
a fail-safe function has a protection function against over voltage. There is no continuity to the gate array
power supply when the gate array power supply voltage is in the OFF state, even if a signal is applied.
<2> TTL level interface block
This block connects to the current TTL LSI. Blocks with fail-safe functions are available in this type as well.
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2.5.2 Output blocks
Signal Level
Function
Output Format
CMOS
Buffer
Normal
3-state
Low noise
Open-drain
Pull-Up/Pull-Down Resistor
No resistor
With 50 kΩ pull-up resistor
With 5 kΩ pull-up resistor
With 50 kΩ pull-down resistor
Signal Level
Function
Output Format
CMOS
Oscillator
Special
Load Drive Capability IOL
3.0 mA
6.0 mA
9.0 mA
12.0 mA
18.0 mA
24.0 mA
A CMOS-level interface block is available as an output interface-level block. This block connects to the current
CMOS LSI, and outputs voltages of the same level as the power supply voltage. In addition, an N-ch open-drain block
with a fail-safe function is also available. This block is provided with a function that protects against over voltage,
ensuring there is no conduction to the power supply of the gate array even if signals are input when the power supply
voltage of gate array is OFF. However, as with the current N-ch open-drain block, this block cannot be clamped with
a voltage higher than that of the power supply voltage.
An oscillator and a low noise buffer for reducing noise generation are also available.
In a CMOS circuit, if an input signal is in a state whereby the level of input is unstable (floating level), excessive
through current will flow, and a noise signal will be input into the circuit, resulting in malfunction. A buffer with a pullup or pull-down resistor must be used for pins that may be open on the substrate. In the CMOS-N5 Family, 5 kΩ pullup resistors are also available for TTL-type bus line.
Design Manual A13826EJ6V0DM
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CHAPTER 2 SELECTING THE GATE ARRAY
2.6 Development Flow
The following figure shows the development flow of a CMOS gate array.
Flow 1: Development procedure and interfacing
NEC
User
Tools, Materials
Pamphlets/
data sheets
System planning
1
Circuit creation
Test pattern creation
Logic design
Circuit design
Circuit creation
Test pattern creation
Design manuals
Block libraries
Macro libraries
Simulation
Sign-off simulation
2
TEGNote 1
Sign-off simulation
Placement and routing
Placement and routing
Actual wiring simulation/
Simulation result check
Actual wiring simulation
Personal OPENCADNote 2
OPENCADNote 2
General-purpose EWS interface tools
Interface manuals
3
ES creation
ES evaluation
CS creation
CS evaluation
Mass production
1
Delivery
Circuit diagram level interface
Simulation level interface
When using NEC's sign-off simulator, placement and routing is
performed immediately after user confirmation.
If another simulator is used, simulation will be executed again by
NEC.
Artwork level interface
Only for users who have ample experience in development using
ASICs from NEC.
2
3
Notes 1. Only when necessary.
2. Extra cost.
54
Design Manual A13826EJ6V0DM
CHAPTER 2 SELECTING THE GATE ARRAY
Flow 2: Development flow
NEC
User
Product planning
Functional specification
Logical design
(Circuit design)
(Test pattern design)
Data input
Simulation results
NG
OK
Mask creation for routing
LSI prototype inspection
Evaluation sample (ES)
Evaluation
Specifications finalized
NG
OK
LSI prototype
inspection for shipment
Mass production evaluation sample (CS)
Evaluation
NG
OK
Mass production
Design Manual A13826EJ6V0DM
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CHAPTER 2 SELECTING THE GATE ARRAY
Flow 3: Front-end detailed flow
Test pattern creation
Circuit creation
Design rule check
GateDRC
STA circuit configuration check
STADRCNote
Pattern rule check
Delay simulation
STA
Function verification
Test pattern verification
Timing verification
Interface
Placement and routing
Note
56
IC test
STADRC is only required when sign-off performed by STA.
Design Manual A13826EJ6V0DM
CHAPTER 2 SELECTING THE GATE ARRAY
2.7 OPENCAD Configuration Tools
The following tools can be selected in accordance with the user environment.
Cautions 1. Refer to the user’s manuals in the OPENCAD Series for the latest versions of the OPENCAD
configuration tools.
2. Some functions may not be supported, so check before using OPENCAD.
Function
NEC Tools
Function simulator
—
Schematic editor
Gate-level
• Netlist
PWC/
Verilog™ HDL
—
simulatorNote 1
V.sim™
Formal verifier
• Test pattern
ALBA
—
STANote 1
Tiara
Fault simulatorNote 2
C.FGRADE™
Design for test
Commercial Tools
ModelSim™/Verilog-XL™/
NC-Verilog™/VCS™
EDIF (2.0.0)/
Vdraw™
Logic synthesis
I/F Data
• Delay data file
—
Design
Compiler®
ModelSim/Verilog-XL/NC-Verilog/VCS
Formality®/Tuxedo-LEC
PrimeTime®
—
TESTACT/NEC_SCAN/
NEC_BSCAN/NEC_BIST/
• Constraint file
TestCompiler™/Testgen™
FastScan™/TetraMAX™
TESTBUS
FloorplannerNote 3
ace_floorplan
galet_floorplan
Placement and routingNote 3
Galet
—
Gate Ensemble™/Silicon Ensemble™
Notes 1. Sign-off tool
2. Tool not supported in HP™ version
3. Tool supported individually
Remark Platform: Sun™ (Solaris™)/HP (HP-UX™)
GUI:
X11R5/Motif™1, 2
Design Manual A13826EJ6V0DM
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CHAPTER 2 SELECTING THE GATE ARRAY
Gate array development is a cooperative effort by the user and NEC. The user is responsible for the steps from
system and circuit design through simulation. NEC is responsible for providing design information, supporting the
user in designing the circuit, and the steps after simulation.
The transfer of development work from the user to NEC is called interfacing. The interface level is divided into the
following two depending on what data is to be provided from the user to NEC.
(1) Circuit diagram level interface
A circuit diagram designed with 74LS or NEC’s gate array blocks is submitted to NEC and NEC performs the
steps after circuit simulation.
NEC will provide the user with the results of design rule checking and circuit simulation, which must be
confirmed and approved by the user.
(2) Simulation level interface
The user performs circuit design and simulation work using various EWS (engineering work stations) and CAD
system simulators, and NEC takes over the rest of the development work (such as automatic placement and
routing and final simulation).
At either interface level, the user may consult NEC about items NEC has provided, as well as which tools are
presently available.
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2.8 List of Interface Data
Embedded array and cell-based IC descriptions should be disregarded when referencing this list.
Caution There may be changes to the data depending on the edition of OPENCAD, so be sure to contact
NEC before commencing design.
File Type and Name
SIMULATOR
V.sim
NETLIST
Note 3
PWC (.pwc)
Note 3
(t1)
—
Note 3
(t1)
Note 3
Note 3
(t1)
Verilog HDL (.v)
EDIF (.edif)
PIN
ASSIGN
Verilog
DIF (.dif)
(t1)
(t1)
(t1)
(t1)
EMC
Check
CB10, EA10 or
later
EMC check file (.emc)
CROSS
Talk
CB10 or later
(except EA10)
pcs file (.pcs)
TEST
Pattern
Without I/O
ALBATROSS (.alb)
modulation
specificationNote 1
Note 4
(t3)
Note 6
(t3)
With I/O
ALBATROSS (.alb)Note 2
modulation
specificationNote 1
Note 5
(t3)
Note 7
(t3)
MACRO
RAM
BIST
RAMPIN file (.rpi)
BIST separation file (.bist.scn)
(when used with SCAN)
(t1)
(t1)
NINCF (.nin)
(t3)
(t3)
ROM.cmd
(t3)
(t3)
(t1)
(t1)
TESTBUS PINF file (.testbus.pinf)
(CB only) Test bus connection check pattern
(testbus.alb)
ROM
Mega- GA
macro
CB
Megamacro unit test specifications
Initial Pattern
PINF file (.testbus.pinf)
Test bus connection check pattern
(testbus.alb)
EPF file (.epf) (when used with SCAN)
Analog Macro
(CB only)
PINF file (.testbus.pinf)
Test bus connection check pattern
(testbus.alb)
EPF file (.epf) (when used with SCAN)
Digital PLL
Initial Pattern
Pin file (.pin) (CB only)
CPU core
(CB only)
PINF file (.testbus.pinf)
Test bus connection check pattern
(testbus.alb)
EPF file (.epf) (when used with SCAN)
Intel-Hex (for CPU core including ROM)
Rev.1.8 12 Dec 2000
Design Manual A13826EJ6V0DM
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CHAPTER 2 SELECTING THE GATE ARRAY
File Type and Name
DFT
BSCAN
SIMULATOR
V.sim
Verilog
(t1)
(t1)
SCAN+BSCAN Initial Pattern
(scan.init.alb)
SET file (.set)
Circuit verification pattern
(.bspat.alb)
Excluding pin file (.exc) (CB only)
(t1)
(t1)
Order file (.bsorder)
(t1)
(t1)
BSDL file (.bsdl)
(t1)
(t1)
SCAN
User macro separation file
(t1)
(t1)
CRITICAL
PATH
tiara command file
(t2)
(t2)
Pin location file
Other
Floorplan
Check
result file
Critical path guidelines (paper)
Floorplan specification document
(paper)
Def file (.floorplan.def)
Note 8
(t2)
(t1)
Note 9
(t1)
(t1)
Note 9
(t1)
CTS
CTS Check report (.rpt)
(t1)
(t1)
Netlist rule
check
(.gatedrc)
(t1)
(t1)
alb check
(.ALBchk)
PIN check
“NO ERR” screen copy
(t1)
(t1)
SCAN check
(.scanchk)
(t1)
(t1)
BSCAN check
(.bscanchk)
Note 10
DFT database
file
(dft_db)
DFT pin
location file
(dft-set)
Test bus
connection
check pattern
testbus.cpt
BSCAN circuit
verification
pattern
bspat.cpt
Note 11
(t3)
(t1)
Sim result
MIN. & MAX.
DC test pattern (up to 32 K patterns)
(fraction of
Function test pattern
pattern number)
High-speed function test pattern
TESTACT
(t2)
Note 8
.slg
.tpe
(t3)
(t1)
.iomoduchk .log
.bus .ovprd .iochk .trcpr
Note 12
Note 12
Note 12
Note 15
Note 15
Note 15
Note 15
Note 15
Note 13
Note 13
Note 13
Note 16
Note 16
Note 16
Note 16
Note 16
Note 14
Note 14
Note 14
Note 17
Note 17
Note 17
Note 17
Note 17
Rev.1.8 12 Dec 2000
Notes 1. There must be a description of I/O modulation in the timing of ALBATROSS.
2. Refers to input modulation and high-speed function test.
3 to 11. Select one for each.
12 and 14 or 15 and 17. Required if high-speed function test is requested.
12 and 13 or 15 and 16. Required if test patterns exceed 32 K.
Remarks 1.
2.
: Required,
: When necessary
(t1): When test run is requested (P&R → SDF)
(t2): When test run is requested ((t1) → Critical path confirmation)
(t3): When test run is requested ((t1) → Simulation)
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Design Manual A13826EJ6V0DM
CHAPTER 2 SELECTING THE GATE ARRAY
2.9 ASIC Product Development Information
An example and the method for describing information related to ASIC product development is included here (as
a checksheet).
Cautions 1. Be sure to check with NEC that the ASIC product development information (checksheet) you
are planning to use is the latest version. Do not use this description example for actual
interfacing.
2. Since this ASIC product development information (checksheet) is an example for description,
it also describes other families. However, refer to the parts related to the CMOS-N5 Family
and parts common to each family only when completing the checksheet.
Design Manual A13826EJ6V0DM
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CHAPTER 2 SELECTING THE GATE ARRAY
2.9.1 ASIC product development information (checksheet)
1. Part number µPD6
2. Company
5841GM
NEC Corporation
–
Department Gate Array Development Department
Name of contact
N.E.C.Smith
3. Specific information
<1> Requested delivery date
ES:
2000
Year
XXX
4
Month
Personal Computer
Customer to distributor: C2
<4> Design tool to be used
<5> Hardware to be used
Customer: OPENCAD Ver 5.0
Customer:
SPARCstation
,
No
<2> Netlist data
Pin layout diagram
VerilogHDL
<3> Test pattern data
LOGPAT
ALB
<4> Timing file
YES
NO
Medium:
A
S
<5> Design rule check results (GateDRC)
Number
E
L
,
C2
Distributor: OPENCAD Ver 5.0
Distributor:
SPARCstation
)
M
EDIF
10
C2 Distributor to D.C: C2
)
P
dif (file name:
Netlist file name:
PWC
Day
Yes
The materials required when interfacing are listed below.
<1> Pin layout diagram
or dif
10
160
pin
QFP
No
Yes (Requirement details:
<8> Special signature
4. Interface materials
JED
Contact details TEL +81-3-XXXX-XXXX
FAX +81-3-XXXX-XXXX
<2> Application
<3> Interface level
<6> Package
<7> Any special requirements?
–
Date: 2000 Year
4
Month 10 Day
Date: 2000 Year
4
Month 10 Day
FD
DAT
Format:
EWS
PC
CGMT
8 mm tape
Network
Other (
)
Date: 2000 Year 4 Month 10 Day
<6> Delay simulation results, including timing check results
V.sim
For V.sim, be sure to provide both MIN. and MAX. of the pattern number fraction slg (/.tpe (trcprint) (OPC V5.4
or later)).
Verilog
For Verilog, be sure to provide both MIN. and MAX. of the pattern number fraction .log/.bus/.ovprd/.iochk/
.trcprint.
Model-S
For Model-S, be sure to provide both MIN. and MAX. of the pattern number fraction .*_rpt/.bus*/.dop/.trcprint.
VCS
For VCS, be sure to provide both MIN. and MAX. of the pattern number fraction .log/.bus/.ovprd/.iochk/.trcprint.
<7> Simulation result check document
Date: 2000 Year 4 Month 10 Day
<8> Critical path guidelines (only when there is a critical path specification)
Date: 2000 Year 4 Month 10 Day
and command file
NEC distributorNote
Distributor:
Distributor, Ltd.
Medium:
CGMT
NEC sales departmentNote
Sales department:
1st Sales Dept.
Name of contact:
TEL:
D.Smith
+81-3-XXXX-XXXX
Name of contact:
TEL:
S.D.Smith
+81-3-XXXX-XXXX
FAX:
+81-3-XXXX-XXXX
FAX:
+81-3-XXXX-XXXX
Note
62
Tool used:
File name:
The names of the NEC distributor and sales department must be included.
Design Manual A13826EJ6V0DM
CHAPTER 2 SELECTING THE GATE ARRAY
1. Enter the product name.
2. Enter the company, department, name of contact, and contact details.
3. Enter the following information.
<1> Requested ES delivery date and number of samples
E
L
<2> Name of product to be mounted
<3> Interface level. For C3, confirm the necessary files later.
<4> Design tool to be used and its version
<5> Hardware to be used
<6> Package pin count and type, and mounting conditions
<7> Whether there is a special requirement and requirement details if YES.
<8> Whether there is a special signature
4. Enter the file name and date for the following materials which are to be submitted when interfacing.
P
Resubmit these materials whenever data is modified.
<1> Mark either pin layout diagram or dif and enter the file name (in the case of dif) and the creation date.
<2> Enter the netlist data file name, data type, medium, format, and the creation date.
<3> Indicate the test pattern data type.
<4> Indicate whether there is a timing file.
<5> Enter the date that GateDRC was executed with the final netlist data.
M
<6> Indicate the simulator type.
<7> Enter the date the simulation result check document was created.
<8> Enter the date the critical path guidelines were created (if there is a critical path specification), and the name
of the Tiara script file.
A
S
Remark Describe the file name for <4> and <5> in (22) Test pattern.
Enter the name of the NEC distributor and NEC sales department.
Design Manual A13826EJ6V0DM
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CHAPTER 2 SELECTING THE GATE ARRAY
5. Product details (C2-level form)
Please fill out the following. This data will be used for designing LSIs and creating delivery specifications.
Note
If this item is satisfied, check the box. For any boxes left unchecked, please write proposed countermeasures.
(1) Are there any additional power supplies? ..............................................................................
YES
NO
1
Additional GND
2
Additional VDD
(2) Is there an oscillator block? ....................................................................................................
YES
NO
Block name:
OS11, OS07, F093
Oscillation input pin
Oscillation output pin
(
(
Oscillation enable input pin (
E
L
Frequency:
CIN
CEN
)
)
Pin No. (
Pin No. (
110
112
COUT
)
Pin No. (
111
20
MHz
)
)
)
• If there is an oscillator block, an oscillation stop function is included ....................................
(3) Conditions
(a) Simulation
cmos_3 V
cmos_3.3 V
(b) Electrical specifications
TA
–40 to 85°C
3.3 V ±0.3 V
VDD
(4) Operating frequency
Input fmax.
Pin name
Output fmax.
CLKIN
Pin name
DAT (15:0)
Output minimum pulse width
Pin name
0 to 70°C
ttl_3.3 V
Other (
3.3 V ±0.165 V
5 V ±10%
M
ttl_5 V
)
5 V ±5%
50
±
Other (
10
)
fmax.
66
MHz
Duty
fmax.
33
MHz
Output load capacitance
50
pF
Pulse width 15.2 ns
Direction
POS
Output load capacitance
NEG
50
pF
A
S
DAT (15:0)
P
cmos_5 V
%
• Output buffer external load capacitance is within the recommended range ..........................
(5) Simultaneous operation
3 GND pin determination method
Total chip level determination method
Simple determination method
Detailed determination method
(a) According to the determination results, simultaneous operation was satisfiedNote ............
(6) Power consumption
Calculation result Total power:
523
mW
Maximum allowable power consumption:
680
mW
• The power consumption is within the allowable rangeNote .....................................................
• When executing a detailed calculation (PWL), calculation is made with TJ = 125 for
TA = –40°C to 85°C or TJ = 100 for TA = 0°C to 75°C ((125 – TA(MAX) ÷ θJA) or
(100 – TA(MAX) ÷ θJA), TA(MAX) ≥ 40°C) ........................................................................................
(7) X-propagation simulation was performedNote .............................................................................
(8) There were no CTS Check result errors (for CTS-mounted products only)Note .......................
(9) There were no timing errors .........................................................................................................
Make checks based on the simulation result check document. If the X-propagation simulation item checkbox was
unchecked, simulation will be performed with no effect on the output pins even if a timing error occurs, so be sure
to execute simulation. If there is a timing error, it will be necessary to modify the circuits and the test pattern to
avoid the output of such an error.
Note that although it is possible to accept only pseudo-errors, whose contents do not affect the output, it is
anticipated that test bugs may be caused by check omissions. Bear in mind that in such cases, NEC may require
users to investigate the origin of these bugs.
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Design Manual A13826EJ6V0DM
CHAPTER 2 SELECTING THE GATE ARRAY
5. Enter the following information.
(1) Indicate whether there are any additional power supplies, and if YES, the number of additional VDD or GND
pins.
(2) Indicate whether there is an oscillator block, and if YES, the name, frequency, and input/output/enable pin
E
L
names and numbers. In the case of YES, also indicate whether an oscillation stop function is included.
For all user patterns, do not make the oscillation input signal the RZ signal and do not set the expected value
“X” (undefined) for the oscillation output signal.
(3) Indicate the type of simulation, TA (temperature range), and VDD (supply voltage range).
P
M
(4) Enter the operating frequency.
Input fmax.
Enter the name of the pin at which the maximum operating frequency is input, the frequency, and the duty
ratio.
Output fmax.
Enter the name of the pin at which the maximum operating frequency is output, the frequency, and the
A
S
load capacitance.
Output minimum pulse width
Enter the name of the pin at which the maximum operating frequency is output, the minimum pulse width,
and the load capacitance, and indicate whether the minimum pulse width is POS or NEG.
• Check and indicate whether the output buffer external load capacitance is within the recommended range.
The following restrictions apply for the maximum operating frequency.
CMOS-9HD, EA-9HD:
CMOS-N5:
100 MHz
60 MHz
Other families:
fmax. of output buffer
(5) Check and indicate which determination method: 3 GND pin determination or total chip level simple
determination/detailed determination was used for simultaneous operation.
Check and indicate whether simultaneous operation is satisfied according to the determination results. If it
is not satisfied, list countermeasures.
(6) Calculate the power consumption using the design manual and enter the result. Also enter the maximum
allowable power consumption of the package, based on the design manual, and indicate whether it is within
the allowable range. If it is out of range, list countermeasures.
For a detailed calculation, execute the calculation with the TJ value corresponding to TA.
(7) Indicate whether X-propagation simulation was performed when executing simulation. Note that X-propagation
simulation must be performed. If it was not performed, give reasons.
(8) Check and enter the results of CTS Check execution.
(9) Based on the simulation result check document, indicate whether there were any timing errors.
Design Manual A13826EJ6V0DM
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CHAPTER 2 SELECTING THE GATE ARRAY
(10) When bidirectional pins are used, there is no circuit designed in such a way that these signals enter the clock
directly after the signals are re-input internally via a bidirectional pin input buffer in output mode
.............................................................................................................................................................
• If the box was left unchecked, countermeasures were taken .......................................................
If this kind of circuit configuration exists, depending on the ringing, the internal circuit that receives these input
signals may malfunction, causing testing problems. This is especially the case if these input signals directly enter
the clock, so users are advised to take countermeasures in line with the specifications in the design manual.
E
L
(11) For CMOS-6, 6A, 6S, 6V, 6X, 8:
Is a TTL18 mA type output buffer used?
For CMOS-8L, 5 V interface:
Is an 18 mA, 24 mA type output buffer used [2-cell configuration]? .....................................
NO
YES
(12) Is there a RAM block? .............................................................................................................
• In the case of YES, please fill out 2.9.2 RAM block.
NO
YES
(13) Is there a ROM block? ............................................................................................................
• In the case of YES, please fill out 2.9.3 ROM.
NO
YES
NO
YES
V5.3g) or 2.9.5 High-speed function test (OPENCAD V5.4 or later).
(15) Is there a GTL, PECL, HSTL, PCI, or LVDS block? ..............................................................
NO
YES
• In the case of YES, please fill out 2.9.6 GTL, PECL, HSTL, PCI, LVDS.
(16) Is there a digital PLL? .............................................................................................................
NO
YES
NO
YES
(18) Is a scan path used? ...............................................................................................................
• In the case of YES, please fill out 2.9.9 Scan path.
NO
YES
(19) For CMOS-8, 8L, 9, 9HD, EA, is there a boundary scan? ....................................................
• In the case of YES, please fill out 2.9.10 Boundary scan.
NO
YES
(20) For EA-9HD, is a bus folder (F098) used for all internal 3-state output pins? .....................
• In the case of NO, it has been confirmed and approved in advance by the
YES
NO
NO
YES
P
(14) Is there a high-speed function test? .......................................................................................
• In the case of YES, please fill out 2.9.4 High-speed function test (up to OPENCAD
M
• In the case of YES, please fill out 2.9.7 DPLL block.
(17) Is there a megamacro? ...........................................................................................................
• In the case of YES, please fill out 2.9.8 Megamacro.
A
S
distributor or engineering department that the bus floating prevention circuit has the
correct configuration ............................................................................................................
(21) Is an internal 3-state output block used (except EA-9HD)? ..................................................
• In the case of YES, it has been confirmed that the bus floating prevention
circuit has the correct configuration ....................................................................................
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(10) Based on the design manual, confirm either that there is no such circuit configuration, or if there is, that
countermeasures are being taken in line with those recommended in the design manual.
(11) Indicate whether there is an output buffer with a 2-cell configuration.
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(12) Indicate whether there is a RAM block.
(13) Indicate whether there is a ROM block.
(14) Indicate whether there is a high-speed function test.
P
(15) Indicate whether there is a GTL, PECL, HSTL, PCI, or LVDS block.
(16) Indicate whether there is a digital PLL.
M
(17) Indicate whether there is a megamacro.
(18) Indicate whether a scan path is used.
(19) In the case of the CMOS-8, 8L, 9, 9HD, EA-9, and EA-9HD Families, indicate whether there is a boundary
scan.
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(20) Indicate whether a bus folder (F098) is used.
In the case of YES, confirm that a bus folder (F098) is used for all internal 3-state output pins.
In the case of NO, confirm that it has been confirmed and approved in advance by the distributor or engineering
department that the bus floating prevention circuit has the correct configuration.
(21) Indicate whether there is an internal 3-state output block.
In the case of YES, confirm that the bus floating prevention circuit has the correct configuration.
If the prevention circuit does not have the correct configuration, through current IDD becomes abnormal when
selecting the tester.
Be careful because this problem cannot be detected by the tool.
Note that because (11) to (19) in the page indicated on the left are examples, YES has been marked for all entries.
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(22) Test pattern:
(a) The following restrictions have been satisfiedNote 1 .......................................................
<1> Up to OPENCAD V5.3g
[CMOS-6, 6A, 6S, 6V, 6X]
Number of Pins
Minimum Number of
Test Patterns Per Pin
Less than 80 pins
150 patterns
Total Number of Test Patterns
32 K patterns
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64 K patternsNote 2
80 pins or more, but less than 160 pins
128 K patternsNote 2
160 pins or more
[CMOS-8, 8L, 9, 9HD, EA]
Number of Pins
Minimum Number of
Test Patterns Per Pin
Less than 80 pins
P
150 patterns
80 pins or more, but less than 144 pins
144 pins or more, but less than 364 pins
364 pins or more
M
<2> OPENCAD V5.4 or later
[CMOS-6, 6A, 6S, 6V, 6X, N5, 8, 8L, 9, 9HD, EA]
Number of Pins
A
S
Less than 145 pins
145 pins or more
Minimum Number of
Test Patterns Per Pin
150 patterns
Total Number of Test Patterns
32 K patterns
64 K patternsNote 2
128 K patternsNote 2
256 K patternsNote 2
Total Number of Test Patterns
128 K patterns (with SCAN)Note 2
256 K patterns (without SCAN) Note 2
512 K patternsNote 2
Caution When dividing the patterns, because there is only one DC pattern, the maximum number
of patterns will be 32 K. It is not necessary to divide LFT patterns.
For high-speed function test patterns, perform simulation with patterns that have been
divided into units of 32 K or less and interface with NEC after confirming that there are
no bugs.
Notes 1. If this item is satisfied, check the box. For any boxes left unchecked, please write proposed
countermeasures.
2. The maximum pattern number for a DC pattern is 32 K. The maximum pattern number per
high-speed function test pattern is also 32 K, except when there are 364 pins or more, in which
case the maximum is 64 K.
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(22) Enter the following information about the test patterns.
(a) Indicate that the restrictions regarding the number of test patterns have been satisfied. If they are not,
check with NEC as the tester restrictions may be unsupportable.
Remark 32 K or fewer DC patterns are counted as one pattern. The number of patterns per high-speed
function test pattern is also 32 K or fewer, except when there are 364 pins or more, in which
case the number is 64 K or fewer.
If a DC pattern is larger than 32 K, check whether cptchk and albchk are 32 K or fewer. It is
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acceptable to submit a pattern larger than 32 K to NEC.
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(b) Please enter test pattern data in the following table.
Test Pattern
Timing Data Number of
Pattern Period (T)/
Check One
Data File Name
File Name
Patterns
Strobe Position (ST)
DC.nlp
DC.alb
20,000
(T = 200 ns /ST = 199.99 ns ) √Note 1
LFT1.nlp
LFT.alb
10,000
(T = 200 ns /ST = 199.99 ns )
√
LFT2.nlp
LFT.alb
10,000
(T = 200 ns /ST = 199.99 ns )
√
FCT.nlp
FCT.alb
20,000
(T = 50 ns /ST =
40 ns
DC
LFT
High- BSCAN DPLL MegaNote 3 macro Note 3
SpeedNote 2
√
)
(T =
/ST =
)
(T =
/ST =
)
(T =
/ST =
)
(T =
/ST =
)
(T =
/ST =
)
(T =
/ST =
)
(T =
/ST =
)
(T =
/ST =
)
(T =
/ST =
)
(T =
/ST =
)
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P
M
(T =
(T =
(T =
(T =
A
S
(T =
(T =
/ST =
)
/ST =
)
/ST =
)
/ST =
)
/ST =
)
/ST =
)
Notes 1. Input the DC pattern in this column. If the pattern period is not 200 ns, enter the pattern period
and reason for change below:
Pattern period:
300
ns
Reason for change: Because the MAX delay is 280 ns
2. Check the High-Speed column for high-speed function test patterns.
3. Check these columns for the setting pattern and initialization pattern.
Remarks 1.
2.
The number of patterns is DC + LFT + High-Speed, totaling no more than 10.
For the ALBATROSS interface, enter the ALBATROSS file name under File Name in the
Test Pattern Data column, and place a dash under File Name in the Timing Data column.
3.
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The pattern period for QB-8 Family is 200 ns or more.
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(b) If there is a test pattern data file and input timing specification for all the test pattern data, enter the timing
data file name, pattern number, pattern period/strobe position, and type of pattern data. If there is a
pattern for the high-speed function test, put check in the High-Speed column.
Be sure to enter the DC pattern in the first row, and if its pattern period is not 200 ns, enter the
pattern period and the reason for the change in the column indicated by Note 1.
For the ALBATROSS interface, enter the ALBATROSS file name for the test pattern data file name, and
enter “-” in the Timing Data File Name column because the timing data is not necessary when I/O
modulation is not specified. Note that the number of patterns is DC + LFT + High-Speed Function Test,
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and totals no more than 20.
Enter “-” in the Timing Data File Name column since the timing specification is disabled because the DPLL
and megamacro patterns are initialization patterns.
The rate for the QB-8 Family is 200 ns or more.
P
Resubmit this information whenever data is modified.
M
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(c) When there is a timing specification
<1> The specified number of timing phases is 6 or less, including the basic timingNote .......
<2> The timing variation (time difference at the change point) of each phase is 10 ns
or moreNote .........................................................................................................................
<3> The I/O switching of the bidirectional buffer is performed at the basic timingNote ..........
<4> There is no contention when the time change is identical for each timing phaseNote ....
<5> When there is an RZ signal specification, the clock is not output directly to
external pinsNote .................................................................................................................
<6> When there is an RZ signal specification, there are no parts in which I/O switching of
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the bidirectional buffer is performed by this signalNote .....................................................
(23) There are no errors in CPTchkNote ....................................................................................................
Bear in mind that because the tester cannot measure the level of pins at which an “HL” or “input change” error occurs
in the DC pattern, defective products may be mixed in the samples at shipment.
For the Verilog products of OPENCAD V5.3g or earlier versions, however, be sure to correct the “Hi-Z input” error
to either “1” or “0”.
P
(24) For the ALBATROSS interface,
(a) ALBA was created using the create interface ALBA function of pattern utility
(target: OPENCAD V5.4 or later)Note .........................................................................................
(b) albchk was executedNote ............................................................................................................
M
If the above is checked, there were no errors in the albchk executionNote ..............................
Bear in mind that because the tester cannot measure the level of pins at which an “Output pin never change error”
or “Input pin never change all pattern” occurs in the DC pattern, defective products may be mixed in the samples
at shipment.
A
S
However, the above messages do not apply for the test pins of NEC that are not used alternately as user pins.
(25) When I/O modulation is specified
(a) I/O modulation is specified for 2 phases or moreNote ...............................................................
(b) There were no errors in the I/O modulation checkNote ..............................................................
(c) The IO_MODULATION ALBA file was input when creating “create I/O modulation ALBA”
(OPENCAD V5.4 only)Note .........................................................................................................................................................
(d) “*ALBATROSS TOP cell name ver4.0 ;” was described in the start line of the strobe ALBA
file (OPENCAD V5.3 only)Note ....................................................................................................
(e) When clock or modulation is specified, it is reflected in the strobe ALBANote .........................
(26) When DPLL is incorporated
There were no errors in the DPLL mode checkNote .........................................................................
Note
If this item is satisfied, check the box. For any boxes left unchecked, please write proposed
countermeasures.
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(c) If there is a timing specification, indicate whether the number of timing phases is 6 or fewer, including
the basic timing, whether the timing variation of each phase is at least 10 ns, whether the bidirectional
buffer I/O switching is carried out at the basic timing, and whether there is conflict when the time change
is identical for each timing phase.
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(23) Indicate whether there are any errors in CPTchk, referring to the CPTchk execution results. If there are errors,
correct them in line with the contents of the box at the bottom of the page.
(24) Because interfacing via the ALBATROSS file is possible from OPENCAD V5.4, for the ALBATROSS interface,
indicate whether albchk was executed, and if it is executed, whether any errors occurred. If it is not executed,
list the reasons why it is not necessary to execute.
(25) When an I/O modulation is specified, check items (a), (b), (d), and (e) for OPENCAD V5.3. For OPENCAD
P
V5.4 or later, check items (a), (b), and (c).
(26) When a DPLL is incorporated, check that there are no errors in the DPLL mode check of Simulation.
If the box is left unchecked, list the reasons why the error(s) will cause no problem.
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CHAPTER 2 SELECTING THE GATE ARRAY
2.9.2 RAM block
(1) About the RAM block
(a) Blocks used
Block Type
(Function)
Number of Bits
Number of Words
Number of Blocks Used
RJ8F
8
256
1
RJ8H
8
512
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1
(b) Compiled RAM is used ................................................................................................................
(c) If compiled RAM is used, there are an even number of wordsNote ..........................................
(d) All RAMs used are RAM with BIST (use of basic RAM only is prohibited) ..............................
(e) The TE pin is directly accessed without inverting the logic from an external pin in the case
P
of G/A and connected to TEB via an inverter in the case of EANote ........................................
(f) In test mode (TE = L), the TIN and TOUT pins are directly accessed without inverting
the logic from external pinsNote ..................................................................................................
(g) If multiple RAMs are used, there is a test output pin (TOUT) provided for each of the
RAMs usedNote ............................................................................................................................
(h) If multiple RAMs are used, the TE and TIN pins are common to all the RAMsNote ................
M
(i) There are no patterns that access non-existent addressesNote ................................................
(j) When BIST RAM is used, the RAM’s TE/TEB pins are not in test modeNote ..........................
(k) A high impedance prevention circuit for normal mode is included ............................................
A
S
If it is not included, be sure to include a prevention circuit, otherwise the tester may
malfunction due to current flow, which may adversely affect shipping (embedded array only).
(l) The instance names of the metalization wafer and base wafer are the same .........................
If they are not the same, submit the instance correspondence of the upper and base wafers
(embedded array only).
(m) Enter the names of the RAM test pins.
TE/TEB (1 pin)
TIN (1 pin)
TENB
TESTI
TOUT (number of RAMs used)
TOUT0, TOUT1
(n) There were no mismatches in the RAM check resultsNote ........................................................
All the boxes from (c) to (k) should be checked. Be aware that if one or more of these items are not checked, you
may be requested to modify the circuitry at the test program creation stage (final development stage).
Note
74
If this item is satisfied, check the box. For any boxes left unchecked, please write proposed
countermeasures.
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(1) Enter the following information about the RAM block.
(a) Enter the RAM block type name, as well as the number of bits, number of words, and number of RAM
blocks used.
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(b) Indicate whether compiled RAM is used.
(c) Odd words are prohibited, so indicate that there is an even number of words.
(d) Check and indicate that all RAMs used are RAM with BIST.
Change to RAM with BIST because the use of basic RAM only is prohibited.
P
(e) Because the TE (TEB) pin must be directly accessed without inverting the logic from an external pin and
connected via an inverter in the case of the EA-9, 9HD Families, indicate that this is the case.
(f) In test mode (TE = L), because the TIN and TOUT pins must be directly accessed without inverting the
logic from external pins, indicate that this is the case.
(g) If multiple RAMs are used, because a test output pin (TOUT) must be provided for each of the RAMs used,
indicate that this is the case.
M
(h) If multiple RAMs are used, because the TE and TIN pins must be common to all the RAMs, indicate that
this is the case.
(i) In the EA-9, 9HD Families, because there can be no patterns that access non-existent addresses, indicate
that this kind of pattern does not exist.
(j) If BIST RAM is used, check and indicate that the TE/TEB pin is not in test mode for all patterns.
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(k) Check and indicate whether a high-impedance prevention circuit for normal mode is included. If it is not
included, be sure to include a prevention circuit, otherwise the tester may malfunction due to current flow,
which may adversely affect shipping (embedded array only).
(l) Check and indicate that instance names of metalization wafer and base wafer are the same.
If they are not the same, submit the instance correspondence of the upper and base wafers (embedded
array only).
(m) Enter the names of the RAM test pins (TE, TIN, TOUT). (Enter one pin for TE and TIN. Because the TOUT
pin cannot be shared in a gate array, enter one pin per RAM used.)
(n) Execute the RAM check and check and indicate that there were no mismatches in the result.
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(2) RAM initialization pattern (pattern for RAM single-unit test)
If there were no mismatches in the RAM check results, you do not need to fill out (a) to (e).
(a) If signals pass between the test pins and RAM block via an internal gate, the logic of this internal gate
is set to the RAM’s test mode in the final pattern of the user-generated test pattern (Note that signals
cannot pass through a sequential circuit.)Note ...........................................................................
(b) If there are bidirectional or 3-state pins (this includes all bidirectional and 3-state pins), enable is secured
for these pins in the final pattern of the user-generated test patternNote .................................
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• If any bidirectional or 3-state pins are being used as test pins, set the TE and TIN pins to input mode
(EN = L) and the TOUT pin to output mode (EN = H) in the initialization pattern.
(c) If there is an internal bus in the LSI (this includes all in-circuit internal buses), that bus is neither shorted
nor in a floating state in the final pattern of the user-generated test patternNote ....................
(d) If there is a sequential circuit in the LSI (this includes all in-circuit sequential circuits), the output of that
sequential circuit is stable in the final pattern of the user-generated test patternNote .............
P
Remark Regarding (d), the output should be stable so as to stabilize the LSI’s internal status and improve
the accuracy of the RAM test.
If any of (a) to (d) above were not checked, an initialization pattern will be required for that item.
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(e) Is an initialization pattern required for any of the above items? ....................................
YES
NO
• In the case of YES, please enter the following information.
<1> Neither “X” nor “Z” has been entered for the inputNote ....................................................
<2> The expected output value is “don’t care”Note ..................................................................
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<3> Initialization pattern range
Note
76
19,990
Pattern to
20,000
Pattern
If this item is satisfied, check the box. For any boxes left unchecked, please write proposed
countermeasures.
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(2) Enter the following information about the RAM initialization pattern (pattern for RAM single-unit test)
(a) The tester automatically inserts the RAM test pattern behind the DC pattern. Therefore, if signals pass
between the RAM test pins and RAM block via an internal gate, because the logic of this internal gate
must be set to the RAM’s test mode, indicate that this is the case (for the RAM test mode pattern, refer
to the design manual).
(b) If there are bidirectional or 3-state pins, because these pins’ enable must be secured in the final test
pattern of the DC pattern, indicate that this is the case.
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(c) If there is an internal bus in the LSI, because bus short or floating states must be suppressed, indicate
that the bus is neither shorted nor floating.
(d) If there is a sequential circuit in the LSI, because the RAM test may not be performed normally, indicate
that the output of that sequential circuit is stable in the final pattern of the DC pattern.
P
M
(e) Indicate whether an initialization pattern is required for any of items (a) to (d). If YES, enter the following
information (<1> to <3> below).
(If any of items (a) to (d) were not satisfied, then an initialization pattern is required.)
<1> If either X or Z is input for the RAM initialization pattern input, because a stable test may not be able
to be performed, indicate that X or Z has not been input.
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<2> Indicate that the status in the RAM initialization pattern is “don’t care” (mask status). This must be
satisfied, because if the initialization pattern is not masked, the test may be defective.
<3> Because the RAM initialization pattern must be added to the end of the DC pattern, check that this
is the case, and enter the pattern range of the RAM initialization pattern.
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2.9.3 ROM
• Blocks used
Block Name
(Instance Name)
Block Type
(Function)
NINCF File
C$0010020
J14F
NINCF0
C$0020030
J14H
NINCF1
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Enter the following information about the ROM block.
• The name (instance name) and type (function name) of the ROM block being used, and the name of the NINCF
file corresponding to that block.
Remark Note that in cases when there are multiple ROM blocks of the same type, if the name (instance name)
and type (function name) of the ROM block is erroneous, the ROM code merge will be reversed.
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2.9.4 High-speed function test (up to OPENCAD V5.3g)
(1) Pattern for high-speed function test
(a) The following conditions are all satisfiedNote 1 ...........................................................................
<1> The initialization pattern has been enteredNote 1 ..............................................................
<2> The test rate (T) is as follows: T ≥ 50 nsNote 1 ..................................................................
<3> There is a strobe at one point onlyNote 1 ...........................................................................
<4> The following equation is true: 10 ns ≤ Strobe time ≤ T – 15 nsNote 1 ............................
<5> The specified number of timing phases is 6 or less, including the basic timingNote 1 ....
<6> The timing variation (time difference at the change point) of each phase is 10 ns
or moreNote 1 .......................................................................................................................
<7> The I/O switching of the bidirectional buffer is performed at the basic timingNote 1 .......
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<8> Each pattern is initialized within 32 KNote 1 .......................................................................
<9> The following restrictions are satisfiedNote 1 .....................................................................
Timing Limit
Signal Type
Input Delay (∆tD)
MIN.
Input Pulse Width (∆tW)
MAX.
Basic timing
MIN.
0 ns
MAX.
—
P
NRZ signal
10 ns
T – 10 ns
RZ signal (clock mode)
10 ns
T – ∆tW – 10 ns
—
10 ns
T – ∆tD – 15 ns
(b) How many test patterns are there? .................................................................................
M
1
(2) Details of simulation using pattern for high-speed function test
(a) Simulation was performed under the following conditionsNote 1 ...............................................
Test period (T)
Load capacitance value
Strobe time
MIN.
MAX.
User-specified value
User-specified value
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Simulation
Condition
50
pFNote 2
User-specified value + 5 ns
125 pF (bidirectional pins)
90 pF (output pins)
User-specified value – 5 ns
(b) There were no mismatches in either MIN. or MAX. simulationNote 1 ........................................
Notes 1. If this item is satisfied, check the box. For any boxes left unchecked, please write proposed
countermeasures.
2. The load capacitance value may change in order to improve the accuracy of the actual wiring
length.
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(1) Enter the following information about the high-speed function test pattern. All these items must be satisfied.
(a) Indicate whether conditions <1> to <9> below are all satisfied.
<1> Indicate that the initialization pattern has been entered in the high-speed function test pattern.
<2> Indicate that the test rate (T) is 50 ns or more.
<3> Indicate that there is a strobe at one point only.
<4> Indicate that the strobe time is 10 ns or more and T – 15 ns or less.
<5> Indicate that the specified number of timing phases is 6 or less, including the basic timing.
<6> Indicate that the timing variation (time difference at the change point) of each phase is 10 ns or
more.
<7> Indicate that the I/O switching of the bidirectional buffer is performed at the basic timing.
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<8> Indicate that each pattern is initialized within 32 K.
<9> Indicate that the restrictions in the table on the left are satisfied.
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(b) Enter the number of high-speed function test patterns.
(2) Enter details of simulation using the pattern for high-speed function test.
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(a) Simulation must be performed under the conditions in the table on the left, so indicate that this was the
case.
(b) Indicate that there were no mismatches in either MIN. or MAX. simulation. The occurrence of a mismatch
changes the timing conditions, so ensure that no mismatch occurs.
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2.9.5 High-speed function test (OPENCAD V5.4 or later)
(1) Pattern for high-speed function test
(a) The following conditions are all satisfiedNote 1 ...........................................................................
<1> The initialization pattern has been enteredNote 1 ..............................................................
<2> The test rate (T) is as follows: T ≥ 50 nsNote 1 ..................................................................
<3> There is a strobe at one point onlyNote 1 ...........................................................................
<4> The following equation is true: 15 ns ≤ Strobe time ≤ T – 10 nsNote 1 ............................
<5> The specified number of timing phases is 6 or less, including the basic timingNote 1 ....
<6> The timing variation (time difference at the change point) of each phase is 10 ns
or moreNote 1 .......................................................................................................................
<7> The I/O switching of the bidirectional buffer is performed at the basic timingNote 1 .......
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<8> Each pattern is initialized within 32 KNote 1 .......................................................................
<9> The following restrictions are satisfiedNote 1 .....................................................................
Timing Limit
Signal Type
Input Delay (∆tD)
MIN.
Basic timing
Input Pulse Width (∆tW)
MAX.
MIN.
0 ns
MAX.
—
P
NRZ signal
10 ns
T – 10 ns
RZ signal (clock mode)
10 ns
T – ∆tW – 10 ns
M
—
145 pins or more:
10 ns
Less than 144 pins:
15 ns
T – ∆tD – 15 ns
(b) How many test patterns are there? .................................................................................
1
(2) Details of simulation using pattern for high-speed function test
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(a) Simulation was performed under the following conditionsNote 1 ...............................................
Simulation
Condition
Test cycle (T)
Load capacitance value
Strobe time
MIN.
MAX.
User-specified value
User-specified value
50 pFNote 2
125 pF (bidirectional pins)
90 pF (output pins)
User-specified value + 5 ns
User-specified value – 5 ns
(b) There were no mismatches in either MIN. or MAX. simulationNote 1 ........................................
Notes 1. If this item is satisfied, check the box. For any boxes left unchecked, please write proposed
countermeasures.
2. The load capacitance value may change in order to improve the accuracy of the actual wiring
length.
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(1) Enter the following information about the high-speed function test pattern. All these items must be satisfied.
(a) Indicate whether conditions <1> to <9> below are all satisfied.
<1> Indicate that the initialization pattern has been entered in the high-speed function test pattern.
<2> Indicate that the test rate (T) is 50 ns or more.
<3> Indicate that there is a strobe at one point only.
<4> Indicate that the strobe time is 15 ns or more and T – 10 ns or less.
<5> Indicate that the specified number of timing phases is 6 or less, including the basic timing.
<6> Indicate that the timing variation (time difference at the change point) of each phase is 10 ns or
more.
<7> Indicate that the I/O switching of the bidirectional buffer is performed at the basic timing.
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<8> Indicate that each pattern is initialized within 32 K.
<9> Indicate that the restrictions in the table on the left are satisfied.
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(b) Enter the number of high-speed function test patterns.
(2) Enter details of simulation using the pattern for high-speed function test.
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(a) Simulation must be performed under the conditions in the table on the left, so indicate that this was the
case.
(b) Indicate that there were no mismatches in either MIN. or MAX. simulation. The occurrence of a mismatch
changes the timing conditions, so ensure that no mismatch occurs.
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CHAPTER 2 SELECTING THE GATE ARRAY
2.9.6 GTL, PECL, HSTL, PCI, LVDS
(1) Blocks used
Block Name
I/O
Number of Blocks Used
FIR1
I
1
EGTL
O
1
BGOW
I/O
2
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If there are IEN pins, please enter (2) to (8).
(2) All the IEN pins are connected directly to an input bufferNote .........................................................
Connect IEN directly to an external buffer (PCI is not a target).
(3) The IEN pins are connected via input buffers FIXA, FUXA, and FIZANote .....................................
Use the dedicated buffers above for the IEN pins (PCI is not a target).
(4) Enter the name of the external pin that controls the IEN pins (PCI is not a target). Pin name
P
GTLIEN
(5) There is at least one pattern in which all the IEN pins are L after pattern 51 of
the DC patternNote ..............................................................................................................................
This pattern is required for IDD measurement, so be sure to make at least one pattern L (PCI is not a target).
(6) If 5 V PCI is being used, a 5 V additional power supply specification (VD5-CMOS9HD,
M
VDD5-EA9HD) was made when the dif file was createdNote ...........................................................
Be aware that this name differs from the usual additional power supply name.
Additional 5VDD
3
(For 9HD, a 5 V additional power supply is required for each edge used)
Pin No.
50, 55, 60
(7) For QB-8, when a high-speed I/F was used, the corresponding reference power supply from those listed
below was specified when the dif file was createdNote ....................................................................
Be aware that this name differs from the usual additional power supply name.
PECL
A
S
VPLR
GTL
HSTL (class1, 2)
VGLR
VHR1
HSTL (class3, 4)
VHR2
(8) If it is necessary to insert modulation to the PCI pin when the PCI pin is usedNote:
Enter the pin name and delay value in the table below.
Pin Name
A01
Delay Value
Delay Value
30
A03
30
A04
30
A05
30
Delay Value
If this item is satisfied, check the box. For any boxes left unchecked, please write proposed
countermeasures.
84
Pin Name
30
A02
Note
Pin Name
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CHAPTER 2 SELECTING THE GATE ARRAY
Enter the following information about the GTL, PECL, HSTL, PCI, and LVDS blocks.
(1) Enter the block name, buffer type (input = I, output = O, bidirectional = I/O), and number of GTL, PECL, HSTL,
PCI, and LVDS blocks used.
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(2) All the GTL IEN pins must be connected directly from outside to GTL input buffers, so indicate that this is the
case (PCI is not a target).
(3) A dedicated control buffer must be used for the IEN pins, so indicate that this is the case (PCI is not a target).
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(4) Enter the name of the external pin that controls the IEN pins (PCI is not a target).
(5) For IDD measurement, there must be at least one pattern 51 patterns or more after the DC pattern in which
all the GTL IEN pins are L. Indicate that there is a pattern in which all the IEN pins are L (PCI is not a target).
(6) When a 5 V PCI is included, a 5 V additional power supply (VDD5) must be specified in the dif file, so indicate
that this specification was made when the file was created.
Note that the specification method differs depending on the series. Specify VD5 for the CMOS-9HD Family,
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and VDD5 for the EA-9HD Family.
For the CMOS-9HD and EA-9HD Families, at least one 5 V additional power supply is necessary for each
row used.
(7) For the QB-8 Family, when a high-speed I/F buffer (PECL, GTL, HSTL) is included, a dedicated additional
A
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power supply must be specified in the dif file, so indicate that this specification was made when the file was
created (PCI is not a target).
(8) When PCI pins are being used, enter the pin name and delay value for those PCI pins at which it is necessary
to insert modulation.
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CHAPTER 2 SELECTING THE GATE ARRAY
2.9.7 DPLL block
(1) Blocks used
Block Name
Number of Blocks Used
F9E6
1
(2) An initialization pattern has been createdNote ..................................................................................
(Execute simulation using the initialization pattern and check that there were no mismatches.)
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(3) In the initialization pattern, all the I/O buffer modes have been securedNote .................................
(4) If the DPLL’s external pins have I/O buffers, the input pins are fixed to input and the output
pins are fixed to output when TMD0, TMD1, (TMD2) are in NEC test modeNote ...........................
(Ensure the 3-state buffer is ON.)
(5) Neither the clock pin (RZ) nor modulation (NRZ) is being used in the initialization patternNote ....
(Do not make a timing specification.)
(6) Except TOUT from the initialization pattern, all the output buffers are “don’t care”
(except oscillation output signal)Note .................................................................................................
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(7) The DPLL’s input and output pins can be accessed directlyNote .....................................................
(8) The RCLK, TMD0, TMD1, TMD2, and TOUT pins do not share signal lines with other
signalsNote ..........................................................................................................................................
(9) The test pattern (DC, LFT) was generated in through path mode and reset mode onlyNote .........
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(10) A dedicated buffer (FI0P/FI0Q) is used for RCLK (H01)Note ...........................................................
(11) Enter the pin correspondence in the following table.
Pin Name
(H01)
(H02)
(H03)
(H04)
(H05)
(H06)
(H07)
(H08)
(H09)
(H10)
(H11)
(H12)
External Pin Name
Pin No.
A
S
PLLRCLK
3
—
—
PLLTCK0
5
Pin Name
External Pin Name
Pin No.
(H15)
(H16)
(H17)
PLLTCK1
6
PLLTMD0
7
(H18)
(H19)
PLLTMD1
8
(H20)
PLLTMD2
9
(N01)
—
—
PLLTSMI
10
(N02)
PLLTOUT
12
(N03)
(N04)
(N05)
(N06)
(H13)
(N07)
(H14)
(N08)
(12) A function error does not occur as a result of creating and simulating the pattern
for checking DPLL connectionNote ....................................................................................................
Note
If this item is satisfied, check the box. For any boxes left unchecked, please write proposed
countermeasures.
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Enter the following information about the DPLL block.
(1) Enter the block names and number of DPLL blocks used.
(2) Indicate whether an initialization pattern has been created. An initialization pattern must be prepared.
Indicate that no mismatches occurred when simulation was executed using the initialization pattern.
(3) In the initialization pattern, in order to perform a stable the DPLL test, it is necessary to fix the mode of the
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I/O buffers not related to the DPLL, so indicate that these buffers have been mode-fixed.
(4) When testing the DPLL, the mode of the external pins must be fixed to input mode when connected to input
pins and output mode when connected to output pins, so indicate that these pins are fixed to either input or
output.
(5) Neither a clock pin nor modulation can be used in the DPLL test initialization pattern.
Indicate that a clock pin (RZ) or modulation (NRZ) is not being used.
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(6) To test the DPLL, all the output buffers except TOUT from the initialization pattern must be “don’t care”.
Indicate that this is the case.
However, the oscillation output signal when the oscillator is included must not be “don’t care”.
(7) To test the DPLL, the input control pin and TOUT must be accessed directly, so indicate whether the input
and output pins can be accessed directly.
(8) Indicate that the RCLK, TMD0, TMD1, TMD2, and TOUT pins do not share signal lines with other signals
(RCLK, TMD0, TMD1, TMD2, and TOUT cannot be shared).
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(9) Indicate that the PLL or NEC test mode is not being used in the test pattern (in the user pattern, do not specify
TMD0 = 0 and TMD1 = 0, or TMD0 = 1 and TMD1 = 1).
(10) A dedicated buffer must be used for the external pin connecting RCLK. Indicate that this is the case.
(11) Enter the names and numbers of the external pins corresponding to the pins in the table on the left.
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(12) Indicate that function errors do not occur when executing simulation after creating the pattern for checking
DPLL connection. Use ALBATROSS or LOGPAT of I/F data as the pattern format at this time.
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CHAPTER 2 SELECTING THE GATE ARRAY
2.9.8 Megamacro
(1) Blocks used
Block Name
Number of Blocks Used
NA54
1
Remark Always initialize the megamacro after
inserting the initialization pattern in each
megamacro into the start of test patterns
such as DC and LFT.
(2) Direct signals have been added from input pins for all the inputs of the megamacroNote .............
(Do not invert signals or pass them through a sequential circuit)
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(3) Direct monitoring is possible at output pins for all the outputs of the megamacroNote ..................
(Do not invert signals or pass them through a sequential circuit)
(4) Which level the CSE pin is fixed? ..........................................................................................
(In the case of H, a BUS configuration for the megamacro outputs is not possible)
H
L
• In the case of CSE = L, what is the circuit configuration of the megamacro outputs?
(a) The megamacro outputs have a BUS configuration ..................................................................
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(b) Megamacro outputs are received via a gate and Hi-Z disappears. ..........................................
(5) A megamacro single-unit test setting pattern has been generatedNote ...........................................
Ensure that the megamacro single-unit test pattern conforms to next (a) to (f) interface conditions.
(a) All the final patterns of output pins other than those of megamacros are “don’t care”Note .....
(b) Neither clock (RZ) nor modulation (NRZ) is usedNote ...............................................................
(c) The I/O buffer mode has been securedNote ...............................................................................
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(d) The internal circuits other than those of the megamacro have been initializedNote ................
(e) There is no Hi-Z or unknown inputNote .......................................................................................
(f) There ware no mismatches as a result of the simulation before placement and routing ........
(6) Is a test pattern required for setting (2) and (3) above? ....................................................... YES
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NO
In the case of YES, incorporate it in the single unit test setting pattern.
(7) The “Megamacro Single Unit Test Specification Document” from the megamacro design
submittedNote
........................................................................................................
manual has been
(If not, include it with this manual)
• The required items for the megamacro to be used should be included in the above document.
Note
If this item is satisfied, check the box. For any boxes left unchecked, please write proposed
countermeasures.
Remark If there are any details regarding the megamacro test circuit configuration that require special
attention, please enter them here.
A bidirectional buffer is used and ID0 to ID7 and OD0 to OD7 are used in common.
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Enter the following information about megamacros.
(1) Enter the name and number of the megamacro blocks used
(2) For the megamacro single-unit test using the tester, direct signals must be added from input pins for all the
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inputs. Check the circuit and indicate that this is the case.
(3) For the megamacro single-unit test using the NEC tester, direct monitoring must be possible at output pins
for all the outputs. Check the circuit and indicate that this is the case.
(4) The configuration of the megamacro output block differs depending on the level of the CSE pin, so indicate
that the level of the CSE pin is fixed to either H or L.
In the case of CSE = L, indicate whether the megamacro outputs are configured as a BUS or as a gate (refer
to the relevant design manual for details of the circuit configuration).
P
(5) When performing the megamacro single unit test, circuits other than the megamacro must be stabilized.
Indicate that a pattern has been generated.
Indicate that all items (a) to (f) were satisfied.
M
(6) When performing the megamacro single-unit test, in order to transfer external signals to megamacro inputs
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without inverting them when gates, etc., have been inserted into the signal lines of the test pins, a setting
pattern is required. Indicate whether a test pattern for setting (2) and (3) is required. If YES, incorporate it
into the single-unit setting pattern.
(7) Indicate whether the required sections of the “Megamacro Single Unit Test Specification Document” in the
megamacro version of each design manual have been copied and submitted with the required items entered
(items such as the instance names and pin reference table are required specifications and therefore must
be prepared).
For example, if a specific method such as sharing the megamacro data input and output is being used, enter this
information.
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CHAPTER 2 SELECTING THE GATE ARRAY
2.9.9 Scan path
(1) Scan
(a) Is scan path used in combination with boundary scan? .................................................
YES
NO
• In the case of YES, please answer (b) and (c) below.
• In the case of NO, please answer the following <1> to <3> before answering (b) and (c).
<1> SMC, SIN, and SOT are located in the positions reserved for dedicated scan path pins in each
package (This is only a restriction when using a package with 313 pins or less)Note ....
<2> Dedicated scan path pins were added to dif .....................................................................
• Please enter the relevant pin numbers in the following table for confirmation.
Pin Name
Pin No.
Pin Name
Pin No.
SMC
45
AMC
8
SIN
44
SCK
38
SOT
46
<3> Do the following 3 pins function alternately as general pins?
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• SIN .......
• SOT ......
Has alternate function
Has alternate function
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Pin name:
Pin name:
AAA
Does not have alternate function
Does not have alternate function
BBB
Does not have alternate function
• SCK ...... Has alternate function Pin name:
• If these pins have alternate functions, the circuits have been configured in accordance
with the design manual ...................................................................................................
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(b) The scan rule check has been executedNote .............................................................................
There were no errorsNote ............................................................................................................
The scan rule check execution results have been submittedNote .............................................
(If not, please submit them)
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• If there is a separate file (non scan target specification file) or a scan bist file, please submit it at the
same time.
File name
separate
(c) The following restrictions apply when designing the scan path.
<1> Use of an internal bus configuration (using F531, F532) is not possible.
<2> Be sure to configure the external I/O pins in the top layer.
<3> When using scan path in combination with boundary scan, do not connect scan output control
buffers (SOEH, SOEL) to the TDO pin (dedicated boundary scan pin) or pins at which a dedicated
boundary scan buffer is used.
All the above restrictions have been complied withNote ...................................................
The standard fault coverage is 95%. If a fault coverage greater than 95% is required, please contact
NEC prior to interfacing.
Note
If this item is satisfied, check the box. For any boxes left unchecked, please write proposed
countermeasures.
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(1) Enter the following information about the scan path.
(a) Indicate whether the scan path is being used in combination with a boundary scan.
In the case of YES (both are used), please answer (b) and (c) below.
In the case of NO (only scan path used), please answer <1> to <3> below before answering (b) and (c).
<1> SMC, SIN, and SOT must be located in the positions reserved for dedicated scan path pins in each
package, so indicate that this is the case. For confirmation, also enter the pin numbers of SMC,
SIN, SOT, AMC, and SCK.
<2> Indicate that dedicated scan path pins were added to dif file.
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<3> SIN, SOT, and SCK can function alternately as general pins, so indicate whether these pins have
P
general-pin alternate functions.
If these pins have alternate functions, enter the pin names and indicate whether the circuits have
been configured in accordance with the design manual.
M
(b) The scan rule check checks the adequacy of the scan circuits and therefore must be executed. Check
the execution results and indicate that there were no errors. The execution results must be submitted
(if an error occurred, fix it, re-execute the scan rule check, and confirm that the error did not reoccur).
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(c) There are blocks that cannot be used when designing the scan path, so refer to the restrictions in <1>
to <3> and indicate that these restrictions have been observed.
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CHAPTER 2 SELECTING THE GATE ARRAY
(2) Multiscan
(a) Enter a check mark in the following table for the number of scan chains.
Number of F/Fs
31999 or Less
Number of scan
1
32000 to 63999 64000 to 127999 128000 to 255999 256000 to 511999 512000 or More
2
4
8
16
32
chains
√
(b) The scan rule check has been executedNote .............................................................................
<1> There were no errorsNote ...................................................................................................
<2> The scan rule check execution results have been submittedNote ....................................
(If not, please submit them)
• If there is a separate file (non scan target specification file) or a scan bist file, please submit it
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at the same time.
File name
separate
(c) Enter the pin names corresponding to the following pins when multiscan pins are used alternately as user
pins.
When SIN, SOT, and SCK pins are not used alternately, it is not necessary to enter this item.
Dedicated
Pin Name
External Pin
Name
Dedicated
Pin Name
External Pin
Name
SIN1
aa
SOT1
SIN17
SIN2
bb
SOT2
SIN18
P
Dedicated
Pin Name
SIN3
cc
SOT3
SIN19
SIN4
dd
SOT4
M
SIN5
SOT5
SIN6
SOT6
SIN7
SOT7
SIN8
SOT8
SIN9
SIN10
SIN11
SIN12
SIN13
SIN14
SIN15
SIN16
SCK
SIN20
SIN21
SIN22
A
S
SOT9
SOT10
External Pin
Name
Dedicated
Pin Name
SOT17
SOT18
SOT19
SOT20
SOT21
SOT22
SIN23
SOT23
SIN24
SOT24
SIN25
SOT25
SIN26
SOT26
SIN27
SOT27
SOT12
SIN28
SOT28
SOT13
SIN29
SOT29
SOT14
SIN30
SOT30
SOT15
SIN31
SOT31
SOT16
SIN32
SOT32
SOT11
External Pin
Name
• If these pins have alternate functions, the circuits have been configured in accordance
with the design manualNote ...................................................................................................................................................
(d) The following restrictions apply when designing the scan path.
<1> Use of an internal bus configuration (using F531, F532) is not possible.
<2> Be sure to configure the external I/O pins in the top layer.
All the above restrictions have been complied withNote ...................................................
The standard fault coverage is 95%. If a fault coverage greater than 95% is required, please contact
NEC prior to interfacing.
Note
92
If this item is satisfied, check the box. For any boxes left unchecked, please write proposed
countermeasures.
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(2) Enter the following information about the multiscan.
(a) Enter the check mark in the following table for the number of scan chains.
Calculate the number of F/Fs from the result of GateDRC.
The number of scan chains is 1, 2, 4, 8, 16, and 32 only as shown in the table. The other numbers are
not supported.
(b) The scan rule check checks the adequacy of the scan circuits and therefore must be executed. Check
the execution results and indicate that there were no errors. The execution results must be submitted
(if an error occurred, fix it, re-execute the scan rule check, and confirm that the error did not reoccur).
If there is a separate file, please submit it.
Confirm that BUNRI and ATGNAME exist together in the separate file.
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(c) SIN, SOT, and SCK can function alternately as general pins, so indicate whether these pins have generalpin alternate functions.
If these pins have alternate functions, enter the pin names and indicate whether the circuits have been
configured in accordance with the design manual.
P
M
A
S
(d) There are blocks that cannot be used when designing the scan path, so refer to the restrictions in <1>
and <2> and indicate that these restrictions have been observed.
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2.9.10 Boundary scan
(1) Dedicated boundary scan pins (including when used in combination with scan)
Please enter the equivalent pin name for the next pins in the table below for confirmation.
Pin Name
External Pin
Name
Dedicated Pin
Name
External Pin
Name
Dedicated Pin
Name
External Pin
Name
TCK
TCK
TMS
TMS
TDO
TDO
TDI
TDI
TRST
TRST
(2) BSCHK was performedNote ...............................................................................................................
There were no errorsNote ...................................................................................................................
The BSCHK execution results have been submittedNote .................................................................
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(If not, please submit them)
(3) Initialization pattern (BSCAN pattern)
(a) The dedicated boundary scan pins are fixed to the following valuesNote .................................
(These pins must be fixed; otherwise they will be in boundary scan mode)
TCK = 0, TMS = 1, TDI = 1, TRST = 0, TDO = Hi-Z
* The same applies for user patterns such as DC and LFT.
P
(b) Patterns in which the final value is fixed to 1, 0, or Hi-Z at each output pin have been
preparedNote ................................................................................................................................
(c) All the final values of the output patterns have been secured at 1, 0, or Hi-Z
(3-state, N-ch open drain)Note ....................................................................................................
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(This is necessary because undefined is prohibited.)
(4) Please enter below the DC measurement pattern of the TAP macro section in the DC test pattern.
(Refer to the design manual for details of the TAP macro DC pattern.)
From
10
pattern to
25
pattern
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Be aware that if the DC pattern is not described, the tester cannot measure the level, possibly causing defective
products to be mixed in the samples at shipment.
• Use SBC4 when using boundary scan only, and SBCG when using boundary scan in combination with scan.
(5) Interface data:
The following data has been prepared in addition to the usual interface dataNote .........................
[SET file], [BSCAN.bs.logpat.alb, Circuit name.bsdl, Circuit name.bsorder] (Initialization pattern),
[NON-SCAN MACRO], [NON-SCAN Bist], [NON-TEST-Ext-Pin]
The item within the parentheses is necessary only for OPENCAD Ver. 5.1 or earlier.
• When SCAN and BSCAN are used in combination, the BSCAN pattern when creating
[Circuit name.scan.init.alb] has been interfaced ............................................................................
Note
94
If this item is satisfied, check the box. For any boxes left unchecked, please write proposed
countermeasures.
Design Manual A13826EJ6V0DM
CHAPTER 2 SELECTING THE GATE ARRAY
Enter the following information about the boundary scan.
(1) For confirmation, enter the names of the external pins corresponding to the dedicated boundary scan pins
(ensure that the names of the dedicated boundary scan pins match those of the external pins).
(2) BSCHK checks the adequacy of the boundary scan circuits, so indicate whether it has been executed (it must
be executed).
Also check the execution results and indicate that no errors occurred.
Indicate that the execution results have been submitted (if not, please submit them. If an error occurred, fix
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it, re-execute BSCHK, and confirm that the error did not reoccur).
(3) Enter the following information about the initialization pattern (BSCAN pattern).
(a) The dedicated boundary scan pins in the initialization pattern (BSCAN pattern) will be in boundary scan
mode if they are not fixed, so indicate that these pins have been fixed to the values shown on the left.
P
(b) Indicate that patterns in which the final value is fixed to 1 and patterns in which the final value is fixed
to 0 at each output pin have been prepared.
(c) The output buffer status in the initialization pattern (BSCAN pattern) is fixed because the data will become
undeterminable if a Hi-Z state exists. The Hi-Z status is prohibited (except for 3-state and N-ch open drain)
in the initialization pattern (BSCAN pattern), so indicate that all the final values of the output patterns have
been secured at either 1 or 0.
M
Also ensure that the status of 3-state buffers is not undefined.
(4) If DC patterns for TAP macro are not described in the DC pattern, the level of the TAP macro I/O pins cannot
be set. It is therefore necessary to describe DC patterns for TAP macro in the DC pattern. Enter pattern range
in which DC patterns for TAP macro will be described.
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(5) Indicate that a SET file and initialization pattern (BSCAN pattern) have been prepared as the I/F data (in the
case of boundary scan, the SET file and initialization pattern (BSCAN pattern) are added to the usual I/F data).
When SCAN and BSCAN are used in combination, circuit-name.SCAN.init.alb is necessary. An initialization
pattern (BSCAN pattern) is also necessary when creating circuit-name.SCAN.init.alb.
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CHAPTER 2 SELECTING THE GATE ARRAY
2.9.11 Automatic layout checklist
(1) SCAN incorporation (Check the following (a) to (e) only for products that incorporate SCAN)
(a) SMC, SIN, and SOT pins are located in the positions reserved for dedicated scan path pins
in each package ...........................................................................................................................
(b) There were no errors in circuit.scanchk (scan check result) .....................................................
(c) When SCAN was incorporated, placement and routing were performed using dif,
in which scan pins had been added ...........................................................................................
(d) SCAN reordering has not been performed .................................................................................
Please contact NEC before using this function.
(e) Placement and routing were performed by circuit.nesp.pwc (a SCAN-incorporated product) ...
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(2) Placement and routing
(a) The pin layout has been checked for problems .........................................................................
(b) The additional power supply locations have been checked for problems ................................
(c) The output load capacitance has been checked for errors .......................................................
(d) Cell locations have been specified (for other than external pins) .............................................
• If so, specify [forced location : group location].
(e) If a 2-cell configuration I/O buffer is being used, the assignable pins have been assigned
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positions (9HD is not a target) ....................................................................................................
(f) An oscillation block with a feedback resistor is being used ......................................................
• If so, please contact NEC before starting placement and routing.
(3) GALET execution result check
(a) There were no verify result errors ...............................................................................................
(b) If the manual was modified after placement and routing, the progress file was checked
M
for errors after outdef (and merge.def for products that incorporate CTS and a high-driving
buffer) was re-output ...................................................................................................................
(c) If ECO was performed, there were no verify result errors .........................................................
(d) When CTS was incorporated, the skew between the clocks was checked for problems ........
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(e) When a digital PLL was incorporated, the wiring was checked for problems ..........................
(Ensure that the routing between H01 and the external pins is as short as possible)
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Enter the following information about the automatic layout check results. (Only C3I/F is required.)
(1) Enter the following when SCAN is incorporated.
<1> There are location restrictions for SMC, SIN, and SOT. Check these restrictions.
<2> Check whether there are 30 separate pins for simultaneous operation (30 is the default setting). If the
response is NO, enter the number of pins input.
<3> Confirm that there were no errors in Srchk.log.
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(2) Enter the following information about placement and routing.
<1> Use pwcz for placement and routing.
<2> When placement and routing is executed, scan pins must be added to dif.
<3> Confirm that the pin layout specified in dif has no errors.
<4> Confirm that the additional power supply data specified in dif has no errors.
<5> Confirm that the output load capacitance specified in dif has no errors.
<6> Use a name that is changed into the product name for the top cell of the netlist used in the placement
P
and routing.
<7> Check the box and indicate the specifying method if the internal cell layout has been specified, and if
not, do not check the box.
<8> If a 2-cell configuration I/O buffer is being used, confirm that the layout positions specified in dif are
positions in which pins can be assigned (the CMOS-9HD and EA-9HD Families are not targets).
<9> When an oscillation block with a feedback resistor is incorporated, a special power supply must be
specified. Indicate that it has been specified.
M
(3) Enter the following information about the execution result check.
<1> Confirm that there were no verify result errors.
<2> If the manual was modified after placement and routing, confirm that the progress file was checked for
errors after def was re-output.
A
S
<3> If ECO was performed, confirm that there were no verify result errors.
<4> Confirm that the skew between the clocks was checked for problems when CTS was incorporated.
<5> The digital PLL must be forcibly placed in order to maximize its performance.
Design Manual A13826EJ6V0DM
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CHAPTER 3 PRODUCT SPECIFICATIONS
To enable connection to both CMOS and TTL products, the CMOS-N5 Family is provided with two types of input/
output interface blocks, each with a specified VIL and VIH: CMOS level and TTL level. In general, usable operating
conditions differ between the CMOS products and TTL products. This chapter describes the recommended operating
conditions and the DC and AC characteristics corresponding to the usable power supply voltage range and
temperature range.
3.1 Terminology
Table 3-1. Terminology for Absolute Maximum Ratings
Parameter
Symbol
Definition
VDD
Range of voltages which will not damage or reduce reliability when applied to the VDD
pin.
Input voltage
VI
Range of voltages which will not damage or reduce reliability when applied to the input
pin.
Output voltage
VO
Range of voltages which will not damage or reduce reliability when applied to the
output pin.
Input current
II
Maximum allowable current which will not cause latchup when applied to the input
pin.
Output current
IO
Maximum allowable DC current which will not cause damage or reduce reliability
when flowing to or from the output pin.
Operating temperature
TA
Range of ambient temperatures for normal logical operation.
Storage temperature
Tstg
Range of element temperatures which will not damage or reduce reliability in the state
where neither voltage nor current is applied.
Power supply voltage
Table 3-2. Terminology for Recommended Operating Conditions
Parameter
Symbol
Definition
Power supply voltage
VDD
Range of voltages for normal logical operation when VSS = 0 V.
Input voltage, high
VIH
For voltage applied to the input of the gate array, this value indicates the voltage of
the high-level state in which the input buffer operates normally.
• If voltage greater than the MIN. value is applied, the input voltage is assured to be
high-level.
Input voltage, low
VIL
For voltage applied to the input of the gate array, this value indicates the voltage of
the low-level state in which the input buffer operates normally.
• If a voltage less than the MAX. value is applied, the input voltage is assured to be
low-level.
Positive trigger voltage
VP
Input level that inverts the output level when the input of the gate array is changed
from the low-level side to the high-level side.
Negative trigger voltage
VN
Input level that inverts the output level when the input of the gate array is changed
from the high-level side to the low-level side.
Hysteresis voltage
VH
Difference between the positive- and negative-trigger voltage.
Input rise time
tri
Limit value for the rise time from 10% to 90% of the input voltage applied to the input
of the gate array.
Input fall time
tfi
Limit value for the fall time from 90% to 10% of the input voltage applied to the input
of the gate array.
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Table 3-3. Terminology for DC Characteristics
Parameter
Symbol
Definition
Static current consumption
I DDS
In the state where there is no voltage change in the input and output pins, indicates
the current that flows in from the power supply pin at the specified power supply
voltage.
Off-state output current
IOZ
For a 3-state output, this value indicates the current that flows through the output pin
at the specified voltage when the output is at high impedance.
Output short-circuit current
Input leakage current
I OS
II
Current that flows out if the output pin is short-circuited to GND when output is at the
high level.
Current that flows through the input pin when voltage is applied to the input pin.
Output current, low
IOL
Current that flows to the output pin at the specified low-level output voltage.
Output current, high
I OH
Current that flows from the output pin at the specified high-level output voltage.
Output voltage, low
VOL
Output voltage when output is open in the low-level state.
Output voltage, high
VOH
Output voltage when output is open in the high-level state.
Design Manual A13826EJ6V0DM
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3.2 Absolute Maximum Ratings
Table 3-4. Absolute Maximum Ratings
Parameter
Ratings
Unit
VDD
–0.5 to +6.0
V
VI/V O
–0.5 to +6.0
V
Input current
II
20
mA
Output current
IO
I OL = 3.0 mA type
10
mA
I OL = 6.0 mA type
15
mA
I OL = 9.0 mA type
20
mA
I OL = 12.0 mA type
30
mA
I OL = 18.0 mA type
40
mA
I OL = 24.0 mA type
60
mA
Power supply voltage
Input voltage/output voltage
Symbol
Conditions
Operating ambient temperature
TA
–40 to +85
°C
Storage temperature
Tstg
–65 to +150
°C
Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any
parameter. That is, the absolute maximum ratings are rated values at which the product is on the
verge of suffering physical damage, and therefore the product must be used under conditions that
ensure that the absolute maximum ratings are not exceeded.
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3.3 Standard Specification of CMOS Interface Conditions (VDD = 5.0 V ±10%, TA = –40 to +85°C)
3.3.1 Recommended operating range
Table 3-5. Recommended Operating Range (VDD = 5.0 V ±10%, TA = –40 to +85°C)
Parameter
Power supply voltage
Symbol
Conditions
VDD
Note 1
TYP.
MAX.
Unit
4.5
5.0
5.5
V
0.7VDD
VDD
V
0.00
0.3VDD
V
Input voltage, high
VIH
Input voltage, low
VIL
Positive trigger voltage
VP
Old-type
0.60
4.00
V
VN
Schmitt input
0.60
3.10
V
0.20
0.80
V
Negative trigger voltage
CMOS interface
MIN.
Note2
Hysteresis voltage
VH
Positive trigger voltage
VP
New-type
2.85
3.75
V
VN
Schmitt input
1.15
1.75
V
1.30
2.07
V
2.29
VDD
V
0.00
0.77
V
Negative trigger voltage
Note 3
Hysteresis voltage
VH
Input voltage, high
VIH
Input voltage, low
VIL
Positive trigger voltage
VP
Old-type
1.15
2.54
V
VN
Schmitt input
0.59
2.10
V
0.15
0.60
V
Negative trigger voltage
TTL interface
Note2
Hysteresis voltage
VH
Positive trigger voltage
VP
New-type
1.68
2.55
V
VN
Schmitt input
0.64
1.33
V
0.83
1.44
V
0
200
ns
0
200
ns
0
10
ms
0
10
ms
Negative trigger voltage
Note 3
Hysteresis voltage
VH
Input rise time
tri
Input fall time
t fi
Input rise time
tri
Input fall time
t fi
Normal input
Schmitt input
Notes 1. Use a new-type CMOS interface, which has W suffixed to the block name.
2. Schmitt buffer without W suffixed to the block name.
3. Schmitt buffer with W suffixed to the block name.
Remark When inputting a slow signal with a long rise/fall time, noise on the signal line may affect the operation,
so be sure to use a Schmitt trigger input buffer.
Because fluctuation on the power supply line due to simultaneous operation of output buffers reduces
the capability of the Schmitt trigger input buffer, carefully determine pin placement.
Design Manual A13826EJ6V0DM
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3.3.2 DC characteristics
Table 3-6. DC Characteristics (VDD = 5.0 V ±10%, TA = –40 to +85°C)
Parameter
Static current
Symbol
consumptionNote 1
Conditions
I DDS
VI = VDD or GND
Off-state output current
IOZ
VO = VDD or GND
Output short-circuit currentNote 2
I OS
VO = GND
MIN.
TYP.
MAX.
Unit
0.1
100
µA
±10
µA
–250
mA
±10–5
±10
µA
131.0
319.7
µA
Input leakage current
Normal input
II
VI = VDD or GND
With pull-up resistor (50 kΩ)
II
VI = GND
45
With pull-up resistor (5 kΩ)
II
VI = GND
0.3489
1.00
2.2
mA
With pull-down resistor (50 kΩ)
II
VI = VDD
45
131.0
319.7
µA
Pull-up resistor (50 kΩ) Note 3
RPU
VI = GND
17.2
38.2
100
kΩ
RPU
VI = GND
2.5
5.0
12.9
kΩ
RPD
VI = VDD
17.2
38.2
100
kΩ
VOL
I OL = 0 mA
0.1
V
VOH
I OH = 0 mA
VDD – 0.1
3.0 mA type
IOL
VOL = 0.4 V
3.00Note 4
mA
6.0 mA type
IOL
VOL = 0.4 V
6.00
mA
9.0 mA type
IOL
VOL = 0.4 V
9.00
mA
12.0 mA type
IOL
VOL = 0.4 V
12.00
mA
18.0 mA type
IOL
VOL = 0.4 V
18.00
mA
24.0 mA type
IOL
VOL = 0.4 V
24.00
mA
3.0 mA type
I OH
VOH = V DD – 0.4 V
–3.00
mA
6.0 mA type
I OH
VOH = V DD – 0.4 V
–6.00
mA
9.0 mA type
I OH
VOH = V DD – 0.4 V
–9.00
mA
12.0 mA type
I OH
VOH = V DD – 0.4 V
–12.00
mA
18.0 mA type
I OH
VOH = V DD – 0.4 V
–18.00
mA
24.0 mA type
I OH
VOH = V DD – 0.4 V
–24.00
mA
Pull-up resistor (5
kΩ) Note 3
Pull-down resistor (50
Output voltage, low
kΩ) Note 3
(CMOS-level output)
Output voltage, high
V
(CMOS-level output)
Output current, low
(CMOS-level output)
Output current, high
(CMOS-level output)
Notes 1. Static current consumption increases when an I/O block with an on-chip pull-up/pull-down resistor and
an oscillator are used. See CHAPTER 4 ESTIMATING ELECTRICAL CHARACTERISTICS for details.
2. The output short-circuit time is less than one second and for only one LSI pin.
3. The pull-up resistor and pull-down resistor values vary depending on the input and output voltages.
4. This value is 2.0 mA if a pull-up resistor of 5 kΩ is connected.
Remark The + and – signs of the current values in the table indicate the direction of the current. Current flowing
into a device is indicated by +; current flowing out is indicated by –.
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3.3.3 AC characteristics
Table 3-7 shows the AC characteristics.
The maximum operating clock frequency (fMAX) of the internal cell toggle flip-flop is the value of the toggle frequency
(ftog ) in the table. Note that the fMAX varies in the actual circuit according to the circuit configuration.
Table 3-7. AC Characteristics (V DD = 5.0 V ±10%, TA = –40 to +85°C)
Parameter
Maximum toggle frequency
Symbol
ftog
Conditions
tPD
TYP.
MAX.
Unit
Internal toggle F/F
Fan-outs = 2, wiring length = 0 mm
Propagation delay time
MIN.
200
Internal gate
Fan-outs = 2, wiring length = 2 mm
0.30
ns
Fan-outs = 1, standard wiring length
0.16
ns
Fan-outs = 2, standard wiring length
0.18
ns
Fan-outs = 1, standard wiring length
0.21
ns
Fan-outs = 1, wiring length = 0 mm
0.14
ns
Fan-outs = 1, standard wiring length
0.23
ns
Fan-outs = 2, wiring length = 2 mm
0.33
ns
1.30
ns
1.23
ns
1.62
ns
Internal gate (low power gate)
Input buffer
Output buffer (FO01)
CL = 15 pF
Output rise time
tr
Output buffer (FO01)
CL = 15 pF
Output fall time
tf
Output buffer (FO01)
CL = 15 pF
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3.4 Specification 1 (VDD = 3.0 ±0.3 V, TA = –40 to +85 °C)
3.4.1 Recommended operating range
Table 3-8. Recommended Operating Range (VDD = 3.0 ±0.3 V, TA = –40 to +85°C)
Parameter
Symbol
Power supply voltage
VDD
Input voltage, high
VIH
Input voltage, low
VIL
Positive trigger voltage
VP
Negative trigger voltage
VN
Hysteresis voltage
VH
Input rise time
tri
Input fall time
t fi
Input rise time
tri
Input fall time
t fi
Conditions
CMOS interface
Schmitt input
Normal input
Schmitt input
MIN.
TYP.
MAX.
Unit
2.7
3.0
3.3
V
0.8VDD
VDD
V
0.0
0.2VDD
V
1.75
2.40
V
0.70
1.10
V
0.81
1.46
V
0
200
ns
0
200
ns
0
10
ms
0
10
ms
Remark When inputting a slow signal with a long rise/fall time, noise on the signal line may affect the operation,
so be sure to use a Schmitt trigger input buffer.
Because fluctuation on the power supply line due to simultaneous operation of output buffers reduces
the capability of the Schmitt trigger input buffer, carefully determine pin placement.
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3.4.2 DC characteristics
Table 3-9. DC Characteristics (VDD = 3.0 ±0.3 V, T A = –40 to +85°C)
Parameter
Symbol
Note 1
Conditions
Static current consumption
IDDS
V I = VDD or GND
Off-state output current
I OZ
VO = V DD or GND
Output short-circuit currentNote 2
IOS
VO = GND
MIN.
TYP.
MAX.
Unit
54.7
µA
±8
µA
–200
mA
±6×10–5
±8
µA
Input leakage current
Normal input
II
VI = V DD or GND
With pull-up resistor (50 kΩ)
II
VI = GND
10.5
40.8
110.0
µA
With pull-up resistor (5 kΩ)
II
VI = GND
0.08
0.41
0.80
mA
II
VI = V DD
10.5
40.8
110.0
µA
RPU
VI = GND
24.5
73.5
314.0
kΩ
RPU
VI = GND
3.4
7.4
41.3
kΩ
RPD
VI = V DD
24.5
73.5
314.0
kΩ
VOL
I OL = 0 mA
0.1
V
VOH
I OH = 0 mA
VDD – 0.1
1.0 mA type
I OL
VOL = 0.4 V
1.00Note 4
mA
3.0 mA type
I OL
VOL = 0.4 V
3.00
mA
6.0 mA type
I OL
VOL = 0.4 V
6.00
mA
9.0 mA type
I OL
VOL = 0.4 V
9.00
mA
12.0 mA type
I OL
VOL = 0.4 V
12.00
mA
18.0 mA type
I OL
VOL = 0.4 V
18.00
mA
1.0 mA type
IOH
VOH = VDD – 0.4 V
–1.00
mA
3.0 mA type
IOH
VOH = VDD – 0.4 V
–3.00
mA
6.0 mA type
IOH
VOH = VDD – 0.4 V
–6.00
mA
9.0 mA type
IOH
VOH = VDD – 0.4 V
–9.00
mA
12.0 mA type
IOH
VOH = VDD – 0.4 V
–12.00
mA
18.0 mA type
IOH
VOH = VDD – 0.4 V
–18.00
mA
With pull-down resistor (50 kΩ)
Pull-up resistor (50 kΩ) Note 3
Pull-up resistor (5
kΩ) Note 3
Note 3
Pull-down resistor (50 kΩ)
Output voltage, low
(CMOS-level output)
Output voltage, high
V
(CMOS-level output)
Output current, low
(CMOS-level output)
Output current, high
(CMOS-level output)
Notes 1. Static current consumption increases when an I/O block with an on-chip pull-up/pull-down resistor and
an oscillator are used. See CHAPTER 4 ESTIMATING ELECTRICAL CHARACTERISTICS for details.
2. The output short-circuit time is less than one second and for only one LSI pin.
3. The pull-up resistor and pull-down resistor values vary depending on the input and output voltages.
4. This value is 0.8 mA if a pull-up resistor of 5 kΩ is connected.
Remark The + and – signs of the current values in the table indicate the direction of the current. Current flowing
into a device is indicated by +; current flowing out is indicated by –.
Design Manual A13826EJ6V0DM
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CHAPTER 3 PRODUCT SPECIFICATIONS
3.4.3 AC characteristics
Table 3-10 shows the AC characteristics.
The maximum operating clock frequency (fMAX) of the internal cell toggle flip-flop is the value of the toggle frequency
(ftog ) in the table. Note that the fMAX varies in the actual circuit according to the circuit configuration.
Table 3-10. AC Characteristics (VDD = 3.0 ±0.3 V, TA = –40 to +85°C)
Parameter
Maximum toggle frequency
Symbol
f tog
Conditions
t PD
TYP.
MAX.
Unit
Internal toggle F/F
Fan-outs = 2, wiring length = 0 mm
Propagation delay time
MIN.
120
Internal gate
Fan-outs = 2, wiring length = 2 mm
0.42
ns
Fan-outs = 1, standard wiring length
0.23
ns
Fan-outs = 2, standard wiring length
0.26
ns
Fan-outs = 1, standard wiring length
0.30
ns
Fan-outs = 1, wiring length = 0 mm
0.20
ns
Fan-outs = 1, standard wiring length
0.34
ns
Fan-outs = 2, wiring length = 2 mm
0.47
ns
1.92
ns
1.76
ns
2.16
ns
Internal gate (low power gate)
Input buffer
Output buffer (FO01)
CL = 15 pF
Output rise time
tr
Output buffer (FO01)
CL = 15 pF
Output fall time
tf
Output buffer (FO01)
CL = 15 pF
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3.5 Specification 2 (VDD = 3.3 ±0.3 V, TA = –40 to +85 °C)
3.5.1 Recommended operating range
Table 3-11. Recommended Operating Range (VDD = 3.3 ±0.3 V, T A = –40 to +85°C)
Parameter
Symbol
Power supply voltage
VDD
Input voltage, high
VIH
Input voltage, low
VIL
Positive trigger voltage
VP
Negative trigger voltage
VN
Hysteresis voltage
VH
Input rise time
tri
Input fall time
t fi
Input rise time
tri
Input fall time
t fi
Conditions
CMOS interface
Schmitt input
Normal input
Schmitt input
MIN.
TYP.
MAX.
Unit
3.0
3.3
3.6
V
0.8VDD
VDD
V
0.0
0.2VDD
V
1.95
2.60
V
0.75
1.20
V
0.90
1.57
V
0
200
ns
0
200
ns
0
10
ms
0
10
ms
Remark When inputting a slow signal with a long rise/fall time, noise on the signal line may affect the operation,
so be sure to use a Schmitt trigger input buffer.
Because fluctuation on the power supply line due to simultaneous operation of output buffers reduces
the capability of the Schmitt trigger input buffer, carefully determine pin placement.
Design Manual A13826EJ6V0DM
107
CHAPTER 3 PRODUCT SPECIFICATIONS
3.5.2 DC characteristics
Table 3-12. DC Characteristics (VDD = 3.3 ±0.3 V, TA = –40 to +85°C)
Parameter
Symbol
Note 1
Conditions
Static current consumption
IDDS
V I = VDD or GND
Off-state output current
I OZ
VO = V DD or GND
IOS
VO = GND
Output short-circuit
currentNote 2
MIN.
TYP.
MAX.
Unit
54.7
µA
±8
µA
–200
mA
±6×10–5
±8
µA
Input leakage current
Normal input
II
VI = V DD or GND
With pull-up resistor (50 kΩ)
II
VI = GND
14.5
59.7
135.0
µA
With pull-up resistor (5 kΩ)
II
VI = GND
0.10
0.49
0.95
mA
II
VI = V DD
14.5
59.7
135.0
µA
Pull-up resistor (50 kΩ) Note 3
RPU
VI = GND
22.2
55.3
248.3
kΩ
Pull-up resistor (5 kΩ) Note 3
RPU
VI = GND
3.2
6.7
36.0
kΩ
RPD
VI = V DD
22.2
55.3
248.3
kΩ
VOL
I OL = 0 mA
0.1
V
VOH
I OH = 0 mA
VDD – 0.1
1.0 mA type
I OL
VOL = 0.4 V
1.00Note 4
mA
3.0 mA type
I OL
VOL = 0.4 V
3.00
mA
6.0 mA type
I OL
VOL = 0.4 V
6.00
mA
9.0 mA type
I OL
VOL = 0.4 V
9.00
mA
12.0 mA type
I OL
VOL = 0.4 V
12.00
mA
18.0 mA type
I OL
VOL = 0.4 V
18.00
mA
1.0 mA type
IOH
VOH = VDD – 0.4 V
–1.00
mA
3.0 mA type
IOH
VOH = VDD – 0.4 V
–3.00
mA
6.0 mA type
IOH
VOH = VDD – 0.4 V
–6.00
mA
9.0 mA type
IOH
VOH = VDD – 0.4 V
–9.00
mA
12.0 mA type
IOH
VOH = VDD – 0.4 V
–12.00
mA
18.0 mA type
IOH
VOH = VDD – 0.4 V
–18.00
mA
With pull-down resistor (50 kΩ)
Note 3
Pull-down resistor (50 kΩ)
Output voltage, low
(CMOS-level output)
Output voltage, high
V
(CMOS-level output)
Output current, low
(CMOS-level output)
Output current, high
(CMOS-level output)
Notes 1. Static current consumption increases when an I/O block with an on-chip pull-up/pull-down resistor and
an oscillator are used. See CHAPTER 4 ESTIMATING ELECTRICAL CHARACTERISTICS for details.
2. The output short-circuit time is less than one second and for only one LSI pin.
3. The pull-up resistor and pull-down resistor values vary depending on the input and output voltages.
4. This value is 0.8 mA if a pull-up resistor of 5 kΩ is connected.
Remark The + and – signs of the current values in the table indicate the direction of the current. Current flowing
into a device is indicated by +; current flowing out is indicated by –.
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3.5.3 AC characteristics
Table 3-13 shows the AC characteristics.
The maximum operating clock frequency (fMAX) of the internal cell toggle flip-flop is the value of the toggle frequency
(ftog ) in the table. Note that the fMAX varies in the actual circuit according to the circuit configuration.
Table 3-13. AC Characteristics (VDD = 3.3 ±0.3 V, TA = –40 to +85°C)
Parameter
Maximum toggle frequency
Symbol
f tog
Conditions
t PD
TYP.
MAX.
Unit
Internal toggle F/F
Fan-outs = 2, wiring length = 0 mm
Propagation delay time
MIN.
130
Internal gate
Fan-outs = 2, wiring length = 2 mm
0.39
ns
Fan-outs = 1, standard wiring length
0.22
ns
Fan-outs = 2, standard wiring length
0.24
ns
Fan-outs = 1, standard wiring length
0.28
ns
Fan-outs = 1, wiring length = 0 mm
0.18
ns
Fan-outs = 1, standard wiring length
0.31
ns
Fan-outs = 2, wiring length = 2 mm
0.44
ns
1.76
ns
1.62
ns
2.02
ns
Internal gate (low power gate)
Input buffer
Output buffer (FO01)
CL = 15 pF
Output rise time
tr
Output buffer (FO01)
CL = 15 pF
Output fall time
tf
Output buffer (FO01)
CL = 15 pF
3.6 Pin Capacitance
The pin capacitance is the sum of the interface block capacitance and the package characteristic capacitance.
Table K-2 shows the capacitance (CB) of the interface blocks. Table K-3 shows the capacitance (CP) of each package.
The pin capacitance is calculated by the following formula:
Pin capacitance (C T) = interface block capacitance (C B) + capacitance of each package (C P)
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This chapter explains the methodology for calculating the power consumption and propagation delay time.
4.1 Estimating Static Current Consumption
4.1.1 Estimating static current consumption
In the CMOS gate array, only a minute leakage current flows from the power supply to GND in the standby state.
If a dedicated oscillation block or an I/O buffer with an on-chip pull-up/pull-down resistor is not used, the static current
consumption is equal to the leakage current. On the other hand, if an I/O buffer with an on-chip pull-up/pull-down
resistor is used, the static current consumption increases due to direct current flowing through that resistor according
to the signal level.
In addition, when an on-chip feedback resistor-type oscillator is used and the oscillation is stopped by clamping
the input pin, direct current flows into the feedback resistor, and as a result the static current consumption increases.
To calculate static current consumption, use the following equation:
IDDS(MAX.) = I L + IPD × m + IPU × n + IRF × k (µA)
IL:
Leakage current (see Figure K-1)
IPD: Current consumption of 50 kΩ on-chip resistor (see Figure K-2)
IPU: Current consumption of 5 kΩ on-chip resistor (see Figure K-3)
IRF:
Current consumption of the on-chip feedback resistor of the oscillator (under study)
m:
Total of number of signal low levels in an I/O buffer with a 50 kΩ on-chip pull-up resistor and number of signal
n:
Number of signal low levels in an I/O buffer with a 5 kΩ on-chip pull-up resistor
k:
Number of oscillators
high levels in an I/O buffer with a 50 kΩ on-chip pull-down resistor
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Calculation example
When VDD = 5 V ±5%, T A = 40°C, calculate the static current consumption under the following conditions.
External Pin
Signal Level
High
Low
Input with 5 kΩ pull-up resistor
2
0
Input with 50 kΩ pull-down resistor
2
8
Normal input
5
5
Normal output
8
2
From Figure K-1, the leakage current is IL = 20.3 µA.
From Figure K-2, the current consumption in the 50 kΩ pull-down resistor is IPD = 193.1 µA.
From the signal level, the current consumption in the 5 kΩ pull-up resistor is I PU = 0.0 µA.
Therefore,
I DDS = I L + I PD + IPU
= 20.3 + 193.1 + 0.0 µA
= 213.4 µA
4.2 Input Through Current
If the input voltage (VIN ) is the same as the power supply voltage (VDD), the input leakage current will be the same
as the value listed in CHAPTER 3 PRODUCT SPECIFICATIONS. However, if the input voltage is lower than the
power supply voltage, or if the input voltage is higher than the GND level, then a current will flow from the VDD line
via the P-ch transistor and N-ch transistor into the GND. This current is called the input through current. Figures K4 to K-11 show the input through current (reference values) for each interface level.
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4.3 Power Consumption
Although CMOS device transistors consume less power than bipolar devices, they still consume a considerable
amount of power if the circuit scale is large and the operating frequency is high. Because the temperature of an LSI
(chip), which has a significant influence on the reliability (life) of the LSI, rises with the power consumption, it is
necessary to hold the power consumption of the LSI below a maximum.
4.3.1 Causes of power consumption
As with standard CMOS devices, the current consumption is the sum of the following values:
• Charge current of load capacitance connected to each transistor:
ic
• Discharge current of load capacitance connected to each transistor: i d
• Through current when each transistor is switching:
io
• Leakage current of the device:
IL
VDD
ic + io
ic
id
id + io
CL
Because there is no charge, discharge, or through current when the LSI is not operating, the power consumption
of the chip is determined by the leakage current of the entire device. In as much as the charge, discharge, and through
currents become extremely large compared with the leakage current when the LSI is operating, the effect of leakage
current can be ignored in the chip power consumption. When the output rise (fall) time of each transistor is extremely
fast compared with the input rise (fall) time, the through current increases greatly. However, the through current is
normally proportional to the charge and discharge currents.
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4.3.2 Estimating power consumption
Power consumption is determined by the charge, discharge, and through currents of each transistor.
However, as it is problematic to define each transistor state, a rough calculation of power consumption is made
for each type of block.
The calculated results of the formulas shown below are values at VDD = 5 V and TA = 85°C; thus, adjustments must
be made if the power supply or the temperature is different.
Total power consumption (PD)
PD = ΣPDCELL + ΣPDM + ΣPDI + ΣPDO + ΣPDCTS + ΣPOSC
(1) ΣPDCELL ............. Internal cell power consumption (excluding the cells used by memory and interface
block)
Σ PDCELL = Σ (4.52Note 1 × f × Cell × A) (µW)
f: Operating frequency (MHz)
Cell: Number of cells operating at frequency f
A: Gate operating factorNote 2
(2) ΣPDM ................. Memory block power consumption
RAM block power consumption
Σ PDRAM = Σ (PRM × fRM × RRM + PWM × fWM × RWM) (mW)
PRM: Unit power consumption during read (mW/MHz)Note 3
fRM: Operating frequency during read
RRM: Operating factor during readNote 4
PWM: Unit power consumption during write (mW/MHz)Note 3
fWM: Operating frequency during write
RWM: Operating factor during writeNote 4
(3) ΣPDI .................. Input buffer and bidirectional buffer input power consumption
Σ PDI = Σ (PI × f + PCONST) × Buffer (µW)
PI: Power consumption for each input buffer (µW/Buffer/MHz)
f: Operating frequency (MHz)
PCONST: Constant power consumptionNote 6
Buffer: Number of input buffers and bidirectional buffer inputs operating at frequency f
If input buffer operation is intermittent, use the average operating frequency (fA)Note 5
Remark Refer to Table K-4.
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(4) ΣPDO ................. Output buffer and bidirectional buffer output power consumption
Σ PDO = Σ {(PO + PCO × CL) × f + PCONST} × Buffer (mW)
PO: Power consumption for each output buffer (without load) (mW/MHz)
PCO: Power consumption for each output buffer (load dependent) (mW/MHz/pF)
CL: Load capacitance
f: Operating frequency (MHz)
If output buffer operation is intermittent, use the average operating frequency (fA)Note 5
PCONST: Constant power consumptionNote 6
Buffer: Number of output buffers and bidirectional buffer outputs operating at frequency f
Remark Refer to Table K-5.
(5) ΣPDCTS …….. Clock tree synthesis power consumption
Σ PDCTS = Σ PCTS (µW)
f: Operating frequency (MHz)
FF: Number of flip-flops
FC42: PCTS = 6.73 × (FF × 0.057) × f
FC82: PCTS = 6.73 × (FF × 0.114) × f
FC44: PCTS = 6.73 × (FF × 0.077) × f
FC84: PCTS = 6.73 × (FF × 0.154) × f
(6) ΣPOSC …….. Oscillator power consumption
Σ POSC = POSC1 × number of oscillators (1 or 2) (mW)
POSC1: Power consumption per one oscillator (mW/MHz)
The power consumption of the oscillator is shown in Table K-6. The values in Table K-6 are reference values
because the power consumption of the oscillator varies greatly depending on the resonator and constant.
Evaluation using an evaluation sample is required to determine the power consumption.
The oscillator configuration diagram is shown in Figure K-12.
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Notes 1. The power consumption per cell (µW/Cell/MHz) is specified under the following conditions:
<1> Assume that the ratio of combination circuits, flip-flops, and latches in the circuit is as follows:
Gates : Flip-flops : Latches = 0.5 : 0.4 : 0.1.
<2> Assume that the data frequency of latches is 1 MHz and that they operate 40% of the total
time that the gates are active.
<3> Assume that the clock frequency of flip-flops is 1 MHz and the data frequency is 0.25 MHz.
<4> Assume that the load of each output is Σ F/I = 2,
= 1.64 (F/I equivalent).
See APPENDIX A POWER CONSUMPTION (PRELIMINARY) if conditions have been modified
to review the power consumption.
2. Gate operating factor
This is the percentage of the cells of the entire circuit that are operating in the same general time
period.
For example, if 30% of the gates of a circuit are operating in the same period, the operating factor
is 0.3.
3. Unit power consumption (under study)
The numerical values are listed in 4.3.3 Unit power consumption of memory.
4. Write and read operating factors
0
30
Read
70
Write
100%
Standby
For example, if the RAM operating percentage is as shown in the figure above, then,
RRM = 0.3 and RWM = 0.4
5. Average operating frequency (fA)
If operation is intermittent, the average operating frequency (fA) can be investigated.
f A = f M × TM ÷ T T
TM: Actual operating interval
TM
TT: Intermittent operating cycle
fM: Operating frequency of actual
operating interval
TT
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Notes 6. Constant power consumption
If direct current is flowing through the input, output, and bidirectional buffers, a constant power
consumption is added.
Example 1. Direct current via the pull-up/pull-down resistor
PCONST = (VDD2/R) × A
VDD: Power supply voltage
R
Outside LSI
R: Pull-up/pull-down resistance
Use a typical value if the resistor
IOL
is incorporated in the LSI
A: Operating factor
Low-level percentage when using a pull-up resistor, or high-level percentage
when using a pull-down resistor
The user should specify the operating factor based on the circuit specifications
Example 2. To drive items that require a large current, such as LEDs
PCONST = VO × IO × A
VPU
VO: Output voltage
I O:
Output current
A:
Percentage of LED ON time
VO
IOL
VPU: Pull-up voltage
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4.3.3 Unit power consumption of memory
In the calculation formula for memory block power consumption in 4.3.2 Estimating power consumption, use the
following values.
(1) Single-port RAM
Unit: mW/MHz
Unit: mW/MHz
RAM Name
PWM
PRM
RAM Name
PWM
PRM
RB47
0.261
0.188
RBHH
5.880
3.04
RB49
0.285
0.198
RBKB
2.756
1.680
RB4B
0.570
0.396
RBKD
5.512
3.360
RB4D
0.336
0.191
RBKF
2.895
1.795
RB4F
0.672
0.382
RBKH
5.790
3.590
RB4H
1.344
0.764
RB4M
2.688
1.528
RB4S
5.376
3.056
RB87
0.522
0.376
RB89
0.570
0.396
RB8B
0.579
0.359
RB8D
0.672
0.382
RB8F
0.735
0.380
RB8H
1.470
0.760
RB8M
2.940
1.520
RBAB
0.689
0.420
RBAD
1.378
0.840
RBAF
2.756
1.680
RBAH
5.512
3.360
RBC7
1.044
0.752
RBC9
1.140
0.792
RBCB
1.158
0.718
RBCD
1.344
0.764
RBCF
1.470
0.760
RBCH
2.940
1.520
RBCM
5.880
3.04
RBEB
1.378
0.840
RBED
2.756
1.680
RBEF
5.512
3.360
RBEH
11.024
6.720
RBH7
2.088
1.504
RBH9
2.280
1.584
RBHB
2.316
1.436
RBHD
2.688
1.528
RBHF
2.940
1.520
Remark
PWM: Power consumption during write operation
PRM:
Power consumption during read operation
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(2) Dual-port RAM
Unit: mW/MHz
RAM Name
PWM
PRM
R947
0.256
0.079
R949
0.280
0.085
R94B
0.560
0.170
R94D
0.314
0.075
R94F
0.628
0.150
R94H
1.256
0.300
R987
0.512
0.158
R989
0.560
0.170
R98B
0.561
0.176
R98D
0.628
0.150
R98F
0.630
0.182
R9AB
0.654
0.211
R9AD
1.308
0.422
R9C7
1.024
0.316
R9C9
1.120
0.340
R9CB
1.122
0.352
R9CD
1.256
0.300
R9CF
1.260
0.364
R9EB
1.308
0.422
R9ED
2.616
0.844
R9H7
2.048
0.632
R9H9
2.240
0.680
R9HB
2.244
0.704
R9KB
2.616
0.844
Remark PWM: Power consumption during write operation
PRM:
118
Power consumption during read operation
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4.3.4 Compensation method
The results calculated by the formulas in 4.3.2 Estimating power consumption are values for VDD = 5.0 V and
TA = 85°C. If different power supply or operating ambient temperature specifications are used, adjustments must
be calculated using the following equation.
PW = PD × K1 + ΣPCONST × K2
PD: Calculated result of total power consumption (including constant power consumption)
ΣPCONST: Sum of constant power consumption only
K1: Compensation coefficient (refer to Table K-7)
K2: Compensation coefficient (refer to Table K-7)
The TYP. value is usually used to determine the power consumption.
However, the MAX. value is used when high reliability is demanded.
The MAX. value can also be used to calculate the maximum power consumption value in each power supply and
temperature specification range.
4.3.5 Determining power consumption
The power consumption is determined on the basis of whether or not the calculated power consumption (PD) is
within the maximum allowable power consumption (PWL) specified for each package and master.
The maximum allowable power consumption (PWL) specified for each package and master is listed in Table K-8
Maximum Allowable Power Consumption.
PD ≤ PWL
The values in Table K-9 are for TA = –40 to +85°C with natural convection. If a different maximum operating ambient
temperature is used, the maximum allowable power consumption for the environment used must be calculated by
means of the maximum junction temperature (TJ (MAX.)), the maximum ambient temperature (TA (MAX.)), and the thermal
resistance (θja) specified for each package and master. The thermal resistance (θja) for each package and master is
listed in Table K-9 Thermal Resistance. Thermal resistance was measured under the conditions of a 90 × 90 mm
by 1.6 mm thick sample mounted on a glass-epoxy circuit board.
PWL =
(TJ (MAX.) – TA (MAX.))
θja
(W)
Condition: TA (MAX.) ≥ 40°C
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4.4 Propagation Delay Time
4.4.1 Accuracy of propagation delay time
The propagation delay time (tPD) of a CMOS gate array fluctuates due to I/O buffers, internal function blocks, and
the following factors:
Factors fluctuating propagation delay time
• Load capacitance (number of fan-outs, wiring capacitance)
• Power supply voltage
• Operating ambient temperature
• Manufacturing variation
• Other circuit-based factors
Circuit-based causes other than those related to power supply voltage, operating ambient temperature, and load
capacitance include: fluctuation due to the input signal waveform, fluctuation in the equivalent input capacitance of
the transfer gate, the Miller effect, and fluctuation in the input threshold voltage. NEC has introduced delay simulators
and static delay calculators, taking these fluctuation factors into consideration as much as possible, so that a more
precise propagation delay can be calculated. Thus, rough calculations of propagation delay time made by the user
may not match the numerical values listed in the CMOS-N5 Family Block Library (A13872E).
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4.4.2 Calculation in propagation delay time
The calculation formula shown below is rough and simplified. The calculation results are comparatively accurate
for a load range that satisfies the following conditions. The larger the load capacitance, the larger the error becomes
and the smaller the calculated numerical result of the simulator becomes. With this prior understanding, this formula
can be used as a guide.
Conditions
The sum of the prestage F/I of the block, which is the object of the delay calculation, is within
15% of the F/O limit of the prestage drive block.
Example
Block A
Block B
Let Block B be the object of the propagation calculation. The accuracy of the simplified
calculation formula is high when the sum of the F/I connected to the output of block A is within
15% of the block A F/O limit.
If these details or the above conditions are not applicable, see APPENDIX B PROPAGATION DELAY TIME for
methods to improve the calculation accuracy. The delay data for each block that is needed for the calculation is listed
in the CMOS-N5 Family Block Library (A13872E).
(1) Input buffer and internal function block delay time
The delay time of the internal function block and memory blocks can be calculated roughly from the load
(number of fan-outs) connected to that output pin and the wiring length (wiring capacitance).
tPD = tLD0 + (Σ F/O +
) × t1 (ns)
tLD0: Delay time of the block itself with F/O = 0 and
=0
ΣF/O: Number of fan-outs of the relevant output pins
: Wiring capacitance connected to the relevant output pins
(see 4.4.3 Estimating wiring capacitance)
t1: Delay coefficient of the relevant output pins
(2) Internal bus delay time
tPD = tLD0 + {Σ F/O +
+ (N – 1) × 1.38} × t1 (ns)
tLD0: Delay time of the block itself with F/O = 0 and
=0
ΣF/O: Number of fan-outs connected to the bus
N: Sum of 3-state output buffers (F531, F532) connected to the bus
: Wiring capacitance connected to the relevant output pins
(see 4.4.3 Estimating wiring capacitance)
t1: Delay coefficient of the relevant output pins
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(3) Output buffer delay time
Using the following equation, the output buffer delay time can be roughly calculated from the load capacitance
connected to the output pin.
tPD = tLD0 + T × CL (ns)
tLD0: Delay time of the block itself with CL = 0 pF
CL: Load capacitance connected to the relevant output pin
T: Delay coefficient of the relevant output pin
The I/O buffer delay time is calculated under the following condition.
CMOS level interface: Threshold voltage = 1/2VDD
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4.4.3 Estimating wiring capacitance
Since placement and routing is performed on the master based on the circuit connection information, the physical
wiring length that is connected as a function block load is unknown before placement and routing of the gate array.
Therefore, an estimation of the wiring lengths is made in order to calculate the propagation delay time before placement
and routing. The wiring length estimation is calculated statistically based on the results of actual layouts, and most
of the wiring length (70% of all routing) becomes shorter than the value specified as an assumed wiring length.
Table K-10 shows estimated values of assumed wiring capacitances for the CMOS-N5 Family.
Placement and routing are executed for each hierarchical macro (top hierarchy). Consequently, wiring lengths
within macros are shorter than wiring lengths between macros. The assumed wiring length is treated by the delay
simulator in two categories: intramacro and intermacro. Table K-10 shows top hierarchy intermacro estimates.
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4.4.4 Fluctuation in propagation delay time
The propagation delay time (tPD) fluctuates due to I/O buffers and internal function blocks, and a variety of other
reasons, as described in 4.4.1 Accuracy of propagation delay time. The CMOS-N5 Family Block Library (A13872E)
indicates the minimum and maximum values under the conditions: VDD = 5.0 V ±10% and TA = –40 to +85°C (TJ =
–40 to +125°C)
The difference between the typical value and these values is called the degrading factor. The propagation delay
coefficient is listed for the minimum, typical, and maximum specifications in the CMOS-N5 Family.
With the CMOS-N5 Family, the degrading factor of each block is studied to improve the accuracy of calculation
of the propagation delay time. Therefore, a uniform degrading factor cannot be used, unlike with conventional
products. However, Figure 4-1 (a) through (c) shows, for reference, the dependency of the delay coefficient on the
power supply voltage and operating junction temperature. The coefficient of the degrading factor can be recalculated
by limiting the operating ambient temperature and power consumption (for example, by limiting the temperature rise
due to power consumption to about 10°C). The operating junction temperature when the operating ambient temperature
or power consumption is limited can be calculated by the formula below. The lower the operating junction temperature,
the closer to 1 the coefficient of the degrading factor (if the operating junction temperature is limited to 100°C, the
delay time is 5% shorter than when the operating junction temperature is limited to 125°C).
TJ = TA(MAX.) + PD × θja (°C)
TJ: Operating junction temperature
TA(MAX.): Maximum value of operating ambient temperature
PD: Power consumption estimated by the calculation formula in 4.3.2 Estimating power consumption
θja: Thermal resistance listed in Table K-10
Please note that since Figure 4-1 (a) through (c) shows the average values of the delay distribution (variations in
the process are already included in the value of the power supply voltage), the guaranteed values are the result
of simulation.
Reference data
RMAX = RV(MAX.) × RT(MAX.)
RMIN = RV(MIN.) × RT(MIN.)
tPD(MAX) = tPD(TYP.) × RMAX.
tPD(MIN) = tPD(TYP.) × RMIN.
Standard specification: CMOS interface condition (VDD = 5.0 V ±10%, TA = –40 to +85°C (TJ = –40 to +125°C))
RMAX. =
RMIN. =
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Figure 4-1. Propagation Delay Time (Under Study)
(a) VDD dependency (MAX.)
Under study
(b) VDD dependency (MIN.)
Under study
(c) TJ dependency
Under study
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In addition to the degrading factor applicable from the device specification, there is also the relative variation
generated by the chips internal paths and by the manufacture of the P-ch and N-ch transistors. This relative variation
is an important factor in verifying the timing of the circuit. The CMOS-N5 Family’s relative variation is as follows.
Relative variation α = 10%
Figure 4-2 shows the variation with tPD(TYP.) as the typical value.
126
TYP. (TYP.)
TYP. (MAX.)
MAX. (MIN.)
MAX. (MAX.)
tPD (TYP.)
tPD (TYP.) × (1 + α)
1–α
1+α
tPD (MAX.)
Design Manual A13826EJ6V0DM
tPD (MAX.) ×
TYP. (MIN.)
tPD (TYP.) × (1 – α)
MIN. (MAX.)
1+α
1–α
tPD (MIN.) ×
MIN. (MIN.)
tPD (MIN.)
Figure 4-2. tPD Variation
CHAPTER 4 ESTIMATING ELECTRICAL CHARACTERISTICS
4.5 Output Buffer Characteristics
4.5.1 Output buffer rise and fall times
The rise and fall times of the output buffer vary greatly according to differences in the drive capability due to the
output level and to the connected load capacitance. The output buffer rise and fall times (tr, tf) can be calculated as
follows:
tr = tr0 + Ftr × CL (ns)
tf = tf0 + Ftf × CL (ns)
tr0:
Reference rise time (load capacitance, CL = 0 pF)
tf0:
Reference fall time (load capacitance, CL = 0 pF)
Ftr, Ftf: Load capacitance coefficient
C L:
Load capacitance (pF) (0 < CL ≤ 300 pF)
Refer to Tables K-11 and K-12 for output buffer coefficients.
4.5.2 Recommended load capacitance range of output buffers
The maximum allowable load capacitance CL(MAX.) of the output buffer should be CL(MAX.) ≤ 300 pF. In addition, Tables
K-13 and K-14 show the recommended load capacitance range for each drive capability of the output buffer. The
optimal output buffer based on Tables K-13 and K-14 should be selected. In particular, if a load capacitance outside
the recommended range is used, it must be noted that the overshoot and undershoot generated in the output signal
increases if a lower load capacitance is used.
4.5.3 Maximum operating frequency of output buffers
The maximum operating frequency of the output buffer is determined by the drive capability and the load capacitance.
As explained in 4.5.2 Recommended load capacitance range of output buffers, there are recommended ranges
for load capacitance. The shaded parts of the graphs in Figures K-13 and K-14 correspond to these ranges.
The parts to the right of the shaded part can be used if there are no problems with the propagation delay time, rise
time, and fall time. On the other hand, be aware that the overshoot and undershoot in the parts to the left of the shaded
part are large.
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4.5.4 Output buffer output current (IOL, IOH)
NEC defines the output current of a CMOS gate array at VOL = 0.4 V and VOH = VDD – 0.4 V. However, there are
cases in which the VOL and VOH that are used differ for actual applications. In such cases, the coefficients shown in
(1) to (3) below should be used in estimating the IOL and IOH characteristics in accordance with the actual conditions.
Output current calculation
IOL’ = IOL × KV × KT (mA)
IOH’ = IOH × KV × KT (mA)
IOL: IOL specification when VOL = 0.4 V
KV: Voltage coefficient
KT: Temperature coefficient
(1) Dependency on power supply voltage
The dependency on the power supply voltage is shown in Figure K-15.
(2) Dependency on operating ambient temperature
The dependency on the operating ambient temperature is shown in Figure K-16.
(3) Dependency on output voltage
VOL = 0.4 to 0.6 V, VOH = (VDD – 0.4 V) to (VDD – 0.6 V)
....... Because IOL and IOH vary almost proportionately to the output voltage, a direct approximation
is possible. However, this excludes the IOH of the TTL level output buffer.
Equations for estimating the output buffer current
IOL’ = IOL × VOL/0.4
(mA)
IOH’ = IOH × (VDD – VOH)/0.6 (mA)
IOL: IOL specification when VOL = 0.4 V
VOL: VOL value used
IOH: IOH specification when VOH = (VDD – 0.4 V)
VOH: VOH value used
The IO vs. VO curves are shown in Figures K-17 and K-18. The MIN. curve is shown for the conditions VDD
= 4.5 V and TJ = 125°C. The TYP. curve is shown for the conditions VDD = 5.0 V and TJ = 25°C. The MAX.
curve is shown for the conditions VDD = 5.5 V and TJ = –40°C. The direct currents IOH and IOL that can actually
be used should be within the absolute maximum ratings.
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4.6 Restrictions to Simultaneous Operation of Output Buffers
4.6.1 Malfunction due to simultaneous operation of outputs
When the output buffer operates, a current that charges/discharges the output load capacitance flows between the
load and LSI. If the current is too large, noise is generated in the power supply line, resulting in the malfunction of
the system.
There are two types of malfunctions:
<1> The LSI malfunctions due to fluctuation in the LSI input threshold level
<2> The next stage circuit malfunctions due to noise appearing at the LSI output pin
The cause of malfunction due to simultaneous operation of output buffers is described as follows.
The circuit in Figure 4-3 (a) can be considered when LSI B’s output buffer is switched from “H” to “L”. When this
happens, the current discharged from the load flows to GND via the power supply line of LSI B. As a result of this
discharge current and the impedance of the GND line, the power supply to the GND line decreases and the GND level
(VG) inside LSI B increases. If the output buffer switches from “L” to “H”, the current that charges the load capacitance
flows, and noise is generated in the power supply line. As a result, VDD temporarily decreases.
When many output buffers simultaneously operate, if the capacity of the load to be driven becomes large, the
voltage level inside the LSI chip fluctuates due to the charge/discharge current, which may result in malfunction, as
shown in Figure 4-3 (b) and (c).
To prevent such malfunctions, the number of simultaneously operating output buffers must be limited. The number
of output buffers that can simultaneously operate differs depending on the following five factors:
<1> Numbers of VDD and GND
<2> Load capacity (CL)
<3> Load drive capability of the output buffer to be used (IOL)
<4> Type of input interface level
<5> Type of output interface level
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Figure 4-3. Malfunction Caused by Simultaneous Operation
(a) Circuit diagram
LSI
VOA
VthB
A
VOB
LSI
VthC
B
VG
LSI
VDD
C
i
CL
VOA: Output level of LSI A
VOB: Output level of LSI B
VthB: Input threshold level of LSI B
VthC: Input threshold level of LSI C
V G:
GND level of LSI B
(b) Fluctuation in input threshold level of LSI B
V
signal is input to LSI B
VDD
VOA
VthB
VG
t
(c) Generated noise moving to the output pin of LSI B
V
signal is input to LSI C
VDD
VthC
VOB
VG
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4.6.2 Definitions
Output simultaneous operation is the switching of multiple output buffers in the same direction (H → L, HZ → L
or L → H, HZ → H) within a fixed time (see Table K-15) as a result of conditions such as the buffer type and load
capacitance. Output simultaneous operation is counted for each operation, and the respective simultaneous operation
limits apply independently.
The following switching of signals is considered one output simultaneous operation group.
(1) Output signal switching from H → L, HZ → L, X → L, H → X
(2) Output signal switching from L → H, HZ → H, X → H, L → X
Remark HZ: High impedance, X: Undefined
Output signal switching from L → HZ and H → HZ is not counted as simultaneous operation. For bidirectional pins,
operating that occurs during switching from input to output must also be considered.
4.6.3 Factors for the determination of simultaneous operation
Because noise generated by charge/discharge currents is the cause of malfunction, the number of simultaneously
operating output pins is limited by the following factors:
(1) Drive capability of the output buffers
(2) Load capacitance
(3) Number of output simultaneous operation pins
(4) Number of LSI power supply pins
(5) Routing pattern of GND and power supply on the circuit board
(6) Placement of the output simultaneous operation pins
(7) Input buffer types
Items (1), (2), and (3) specify the charge/discharge current, and item (7) specifies the LSI’s noise margin using
the input buffer interface. Items (4) and (5) restrict the inductance of the closed loop through which the charge/
discharge current flows. Therefore, these items cannot be specified quantitatively. The simultaneous operation limit
specified by NEC has a default value for the impedance of this loop. It is therefore possible that noise will be
generated, depending on the particular user’s circuit board layout. Adequate noise countermeasures must
be incorporated into the design of the circuit board.
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4.6.4 Simultaneous operation pins to be checked
Simultaneous operation of outputs should be checked for output buffer groups that meet the conditions explained
below.
Conditions
(1) When buffers are driven in parallel by a shared internal block, or one signal output from a shared internal block
is split into multiple buffers due to the fan-out limit, and the buffers are driven in parallel.
Internal block
Internal block
(2) When the output buffers are driven by sequential circuits operated by a shared control signal and when, due
to the delay time of the combination circuits, the operation timing differential of the distributed output buffers
is less than the simultaneous operation reference time for each buffer and load capacitance shown in Table
K-15 Reference Time Ranges for Simultaneous Operation (TYP.) .
132
D
Q
Combination
circuit
D
Q
Combination
circuit
D
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Combination
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(3) When, due to identical timing of the external input, the timing differential of output buffer operation is less than
the simultaneous operation reference time for each buffer and load capacitance shown in Table K-15 Reference
Time Ranges for Simultaneous Operation (TYP.).
LSI
Internal circuit
Identical timing of
input signals
Internal circuit
Identical timing of
output signals
Internal circuit
Determination of the simultaneous operation reference time (described in Table K-15 Reference Time Ranges
for Simultaneous Operation (TYP.)) is performed by the simple total of the tLD0 (TYP.) values listed in the
CMOS-N5 Family Block Library (A13872E).
However, checking for simultaneous operation of outputs is not performed in those cases in which the following
conditions apply:
(1) There are no sequential circuits in the specified circuit, and the gate array is not connected to the control input
of a sequential circuit of an external device.
(2) The operation timing differential of the output buffer is greater than the simultaneous operation reference time
for each buffer and load capacitance shown in Table K-15 Reference Time Ranges for Simultaneous
Operation (TYP.).
(3) Operation does not occur other than during initialization (set and reset).
(Because malfunctions due to simultaneous operation are absorbed by initialization.)
4.6.5 Pin placement and simultaneous operation
The size of closed loop inductance, through which the charge/discharge currents of the output buffers flow,
determines the size of the generated noise. The inductance of this closed loop depends on the LSI pin placement
and the circuit board on which the LSI is mounted. Care must be taken in placing pins in order to control noise caused
by simultaneous operation.
• As far as possible, avoid placing input pins in the output buffers that operate simultaneously.
• Locate input pins (especially clock input pins) susceptible to noise as close to the GND pin as possible. Separate
these pins as far as possible from output buffers that operate simultaneously.
• Separate output buffers that operate simultaneously as far as possible from the input pins, and enclose them
by GND pins.
• If it is difficult to enclose output buffers that operate simultaneously by GND pins, disperse the buffers as much
as possible. In any case, separate the output buffers that operate simultaneously as far as possible from the
input pins.
• Increase the number of GND/VDD pins at a rate of one VDD to two GND.
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4.6.6 Three-GND-pin determination
By this method, a determination is made not for the number of GND and VDD pins of the LSI, but for three GND
pins. Therefore, locations at which simultaneous operation is concentrated can be taken into consideration.
Simultaneous operation is assessed by the output buffer type, output load capacitance, and the number of valid
GND pins. Table K-16 shows the number of pins that can operate simultaneously between three valid GND pins.
Because the permissible number of simultaneous operation pins when a 12 mA output buffer is used is shown in this
table, calculate the permissible number of pins by using the coefficient shown in Table K-17 if a buffer with a different
driving capability and output level is used.
If the driving capability is the same when IOL is a value other than 12 mA, divide the values in Table K-16 by the
coefficient in Table K-17.
IOL = Permissible number of simultaneous operation pins between 3GND pins with 12 mA/Coefficient
Criteria if drive capability or load capacitance is different
In the case of buffers with different driving capabilities, the following expression must be used to calculate the
permissible number of simultaneous operation pins (Mi) in Table K-16, taking the number of simultaneous
operation pins (mi) and coefficient (β i) of each driving capability into consideration.
Σ (mi × β i/Mi) ≤ 1
Calculation example
IOL = 18 mA
CMOS level
30 pF
5 pcs.
IOL = 24 mA
CMOS level
50 pF
2 pcs.
5 × 1.264 ÷ 12.5 + 2 × 1.352 ÷ 10 ≤ 1
BGA package determination
Determination is performed for the internal chip in the BGA package. For internal chip pin layout, refer to
APPENDIX F PIN DESCRIPTIONS.
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4.6.7 Assumptions for the determination method
The determination of simultaneous operation is also affected significantly by the power supply and GND pins of
the circuit board.
It is assumed by the determination method that simultaneous operation is considered for comparative circuit board
and LSI pin placements. The reference values are determined based on this assumption. Consequently, if the routing
pattern of a circuit board is narrow (especially the power supply and GND routing), or if the closed loop from the power
supply wiring on the circuit board through the LSI and GND wiring on the circuit board and back to the power supply
wiring is long, and the impedance is large, then the noise generated by simultaneous operation will become greater
than the noise level specified by the determination method. This must be kept in mind in order to avoid problems.
In such a case, it is effective to shorten the above closed loop by means of a bypass capacitor.
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4.6.8 Other determination methods
The methods explained below must be used if the determination reference cannot be satisfied by the standard
power supply and number of GND pins.
(1) Increasing V DD and GND pins
Increase the V DD and GND pins so that the condition of the number of simultaneous operation pins is satisfied.
Increase the number of pins at a ratio of one VDD pin to two GND pins.
(2) Re-examine the applicable environment
<1> Reduction of output load capacitance
The size of the noise generated by charge/discharge currents that flow when the output changes depends
on the size of the output load capacitance. Consequently, the size of the generated noise can be reduced
by reducing the load capacitance, thereby increasing the allowable number of simultaneous operation
pins.
<2> Modification of buffer type
The peak values of the output charge/discharge currents depend on the buffer drive capability and the
buffer function. By changing to a buffer type with a lower drive capability or to a low-noise buffer, the
generated noise can be controlled and the allowable number of simultaneous operation pins can be
increased.
<3> Reduce simultaneous operation pins by adding delay time
Output simultaneous operation is the switching of multiple output buffers in the same direction (H → L,
HZ → L or L → H, HZ → H) within a fixed time (see Tables K-13 and K-14), as determined by conditions
such as the buffer type and load capacitance. Consequently, if delay time is added to the simultaneously
operating output pins and the operating time does not fall within the time specified in Table K-15 Reference
Time Ranges for Simultaneous Operation (TYP.), then it becomes unnecessary to consider these pins
as operating simultaneously, and the number of simultaneous operation pins is thereby reduced.
Remark HZ: High impedance
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This chapter explains the points to be noted and limits to be applied in designing a circuit.
When designing an LSI using CMOS gate arrays, once a circuit has been designed it cannot be easily modified,
unlike when designing a circuit using standard TTL or CMOS ICs.
It is therefore important to observe the limits and follow the design rules described in CHAPTER 2 SELECTING
THE GATE ARRAY, CHAPTER 4 ESTIMATING ELECTRICAL CHARACTERISTICS, and this chapter to design an
LSI without errors.
If an LSI is designed without observing the design rules, not only is the development period after interfacing with
NEC extended, but also the product may need to be re-developed.
5.1 Basic Circuit Configuration
5.1.1 Using I/O buffers
When designing an LSI with gate arrays, place input/output buffers between the LSI and the input/output pins (see
Figure 5-1).
Reasons:
<1> To protect the LSI from destruction due to static electricity
<2> To obtain sufficient output drive capability
Figure 5-1. Basic Circuit Configuration
Input pin
Output pin
Input buffer
Output buffer
Input pin
Output pin
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5.1.2 Unused pins
With gate arrays, unused input pins cannot be left open (the state where they are not connected to anything) in
any block. The pins must be input at either a high or low level by using F091 (H- and L-level generator). If a block’s
input pins are left open, it cannot function correctly since the input level is undetermined. This condition also becomes
a source of increased IL (leakage current). In addition, large fan-outs should be avoided when F091 is used. If several
blocks are clamped to a single block, the routing becomes concentrated, making placement and routing difficult. In
such a case, divide the circuit by a certain unit to avoid routing concentration.
A warning error will be posted by the tester during a design rule check if the block’s output pins have been left open.
Discard unnecessary blocks.
5.1.3 Fan-out limitations
There are limitations on the number of charged gates that can be connected to a block’s output pins (the fan-out
number). The recommended fan-outs for each block (including the fan-in number) are given in the CMOS-N5 Family
Block Library (A13872E).
Because signal rise and fall times increase when the number of charged gates increases, the estimation accuracy
of the propagation delay time becomes lower. Moreover, if rise and fall times become very long, data-through develops
in the flip-flops causing abnormal logic operation. Therefore, do not exceed the fan-out restrictions when designing.
Be sure also to design with fan-out numbers that are 1/3 of the limit in circuits that have strict speed specifications.
5.1.4 Wired logic circuit prohibitions
Other than for the bus, do not configure wired logic as mutually connected block outputs.
The P-ch transistors and the N-ch transistors become conductive at the same time as a function of the logic state
if the outputs of the block are connected to each other. Pay attention to this since the steady low-power characteristics
that are a feature of CMOS circuits can be lost when the output is at an intermediate level because current can flow
from VDD to GND.
Figure 5-2. Wired Logic Circuit Prohibitions
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5.1.5 Notes on using bidirectional buffers
If an output signal is input as is to an internal circuit with a bidirectional buffer, the internal circuit that receives this
input signal may malfunction due to distortion of the output waveform and ringing as shown in Figure 5-3. Take special
care to avoid inputting input signals to the clock of the flip-flop. In the output mode, make sure that the signal
immediately before the output buffer is input to the internal circuit as shown in Figure 5-4.
Figure 5-3. Ringing
Figure 5-4. Example of Preventive Circuit
Selector
0
1
SEL
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5.2 Differential Circuit Prohibition
As a rule, differential circuits should not be configured from gate arrays. Since gate-array placement and routing
design is done automatically, the range of waveforms that are internally generated cannot be guaranteed with gate
arrays, and the desired functions will not materialize. Therefore, avoid structuring the circuit shown in Figure 5-5 (a);
instead structure the circuit as shown in Figure 5-5 (b).
Figure 5-5. Differential Circuit Prohibition
(a) Example of incorrect circuit
Input
Output
(b) Example of correct circuit
Input
Output
D
Q
C
D
C
QB
Clock
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5.3 RS Latch and Loop Circuits
5.3.1 RS latch
Gate-configured asynchronous RS latches should not be used with gate arrays. This is not only because initialization
may not be able to take place via simulation or high variation in circuit path speed due to routing location effects.
Figure 5-6. Asynchronous RS Latches
R
Q
R
INIT
QB
QB
S
Q
S
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5.3.2 Loop circuit
The following points must be noted when loop circuits, such as feedback loops, are used.
(1) As shown in Figure 5-7, if gates lie between feedback loops, such as divider circuits, the frequency characteristics
will drop due to the delay time caused by these gates. The delay times of these loops must be determined
beforehand and the frequency characteristics must be verified. See 5.6 Delay Time Margin for the margin
verification method.
Figure 5-7. Loop Circuit
tPD
D
Q
D
Q
b
C
C QB
a
CLK
Period T
CLK
Point
a
Point
b
tPD of gate
tPD of F/F
Setup time
of F/F
fMAX = 1/T
(2) A loop circuit cannot be formed in a scan path configuration. In this case, employ a countermeasure such as
isolating the loop circuit by using gates.
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5.3.3 Prohibited state of flip-flops
The state in which both the set and reset inputs of an RS latch or flip-flop are enabled at the same time is prohibited.
This is because the retained data becomes unstable if both the set and reset inputs are disabled simultaneously. What
value the retained data will take is influenced by delicate timing such as the timing of the set and reset signal input
and delay of the internal signal of the flip-flop and cannot be guaranteed.
Consequently, be aware of the following when using flip-flops with set/reset inputs.
<1> Do not enable set and reset inputs at the same time.
<2> When it is necessary to enable set and reset inputs simultaneously, disable one side first and then disable
the other side. By doing this, the state that the flip-flop was in when it was disabled will be maintained.
Table 5-1. F617 (D-F/F with RB, SB)
D
SB
D
C
RB
H04
H01
H02
H03
N01
N02
C
RB
SB
Q
QB
0
1
1
0
1
1
1
1
1
0
X
1
1
Hold
Hold
Q
QB
X
X
0
1
0
1
X
X
1
0
1
0
X
X
0
0
0
0
←Use prohibited
X: Undefined
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5.4 Clocked Signal Design
Gate arrays should basically be designed as synchronous circuits.
5.4.1 Synchronous circuit design
There are two techniques used for designing synchronous circuits: the single-phase synchronous circuit design
technique normally used for circuits designed using general-purpose LSIs, and the multi-phase synchronous circuit
design technique often used in CPU design.
The features of single-phase and multi-phase synchronous circuit design are shown in Table 5-2.
Table 5-2. Features of Single-Phase and Multi-Phase Synchronous Circuit Design
Advantages
Disadvantages
Single-phase synchronous
circuit design
• Circuit is simple.
• Generally suited to high-speed circuits.
• Signal skew on the clock line must be
considered in configuring shift registers
Multi-phase synchronous
circuit design
• Timing tests for shift registers are
unnecessary.
• A multi-phase clock signal must be generated.
• Number of gates increases.
• Generally unsuited to high-speed operation.
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(1) Single-phase synchronous circuit design
Single-phase synchronous circuits should be designed when sequential circuits will operate with a single clock
signal. This relatively simple design method is necessary to adjust timing such as clock skew between
sequential circuits.
Figure 5-8. Clock Skew
F/F - A
D
Buffer - 1
F/F - B
D
F/F - C
D
F/F - A
a
F/F - B
b
Buffer - 1
s
F/F - C
c
The s to a delay time differs from the s to b and s to c delay times due to wiring resistance.
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Clock skew is a shift of the clock signal between sequential circuits.
This shift becomes greater if the wiring resistance becomes large and is also dependent on the wiring length
from the point of divergence of the circuits. Follow the measures below to allow for clock skew when performing
single-phase circuit design.
(a) Try to allocate similar clock lines in the same macro. (see Figure 5-9 (a)).
(b) When allocating a large number of clock lines, allocate the lines as shown in Figure 5-9 (b) so that errors
due to clock skew do not occur.
(c) Accelerate the operation of the final-stage register by structuring the synchronous counters and shift
registers (see Figure 5-10).
(d) Use clock tree synthesis (see 5.4.3 Clock tree synthesis).
Figure 5-9. Clock Skew Countermeasure 1
(a)
Macro
CLK
(b)
Macro
CLK
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Figure 5-10. Clock Skew Countermeasure 2
(a) Circuits with potential for malfunction
DATA
D
Q
D
Q
D
Q
D
Q
OUT
D
Q
OUT
CLK
(b) Circuit with a clock skew countermeasure
DATA
D
Q
D
Q
D
Q
CLK
If buffers are inserted in the clock line due to the fan-out limitation, the countermeasures illustrated in Figure
5-10 (b) must be taken.
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(2) Multi-phase synchronous circuit design
Operation of sequential circuits in multi-phase synchronous circuit design normally involves two or more clock
signals with a constant relationship. This method avoids contention of clock operation between sequential
circuits.
Figure 5-11. Double-Phase Synchronous Circuit
DATA
D
D
D
D
OUT
Φ1
Φ2
DATA
Φ1
Φ2
OUT
Undefined
Figure 5-11 is an example of a double-phase clock circuit. The two clock signals (Φ1 and Φ2) vary in timing
to avoid hold time errors between two sequential circuits. Even if there is interaction between complex
sequential circuits, testing for timing contention can be curtailed by alternately operating sequential circuits.
In addition, since the number of gates is reduced in this circuit example, a latch can be used instead of a flipflop.
In multi-phase synchronous circuit design, configure the several clock signals from the basic clock signal. This
will result in a lower clock frequency than that needed for a normal single-phase circuit (high speed is possible
with a pipeline structure).
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5.4.2 Clock skew
Clock skew is generated by wiring length variations in actual placement and routing. Hold time errors in sequential
circuits can result from this clock skew. Normally, discrepancies due to these kinds of variations cannot be detected
in the simulation that is performed before the placement and routing. The following guidelines are provided to minimize
this problem.
(a) Clock line design in a macro
One clock line should be supplied in single-phase synchronous circuit design.
It is basically not necessary to test for clock skew in multi-phase synchronous circuit design. However, it is
necessary to check the operating frequency.
(b) Clock line design between macros
There are clock skew problems especially between macros in single-phase synchronous design. Some
examples of countermeasures are shown in Figure 5-12.
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Figure 5-12. Countermeasures for Clock Lines Between Macros
(a) Insert delay gates
Macro A
Macro B
D
Q
D
Delay gate
A delay gate must be inserted
within macro B in order to gain flipflop hold time.
Q
(b) Receive signal by inverse-phase clock
Macro A
Macro B
D
Q
D
Q
D
Q
(c) Make circuit multi-phase
Macro A
D
Macro B
Q
D
Q
D
Q
D
Q
Φ1
Φ2
Figure 5-12 (b) uses the inverse phase of the clock to create a hold time margin. With this method, it is necessary
to keep the clock frequency and duty cycle in mind.
Figure 5-12 (c) is a measure using a multi-phase clock. In this case, it is necessary to keep the clock frequency
in mind.
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5.4.3 Clock tree synthesis
Clock tree synthesis (CTS) is a technique that minimizes clock skew between flip-flops that are connected to the
clock line. As shown in Figure 5-13 (a), the distance between the clock driver and each flip-flop is not constant. In
addition, wiring resistance increases due to shrink processing. Because of this, the variations in wiring length are
linked to clock skew. With CTS, a buffer is inserted in the clock line. This uniformly distributes the clock line, as shown
in Figure 5-13 (b). Therefore, NEC recommends the use of the CTS instead of clock drivers.
Figure 5-13. Concept of CTS
(a) Conventional
(b) CTS
First-level driver
Second-level driver
Third-level driver
Flip-flop
(1) Benefits of CTS
In CTS, a CTS block is substituted for the clock drivers (FCKA to E) that are usually used. Figure 5-14 shows
how the clock line buffer is inserted. An inverter is used since the path delay time is shortened with actual
CTS. This is how clock distribution is performed. As a result, the number of blocks that are inserted includes
the number of CTS drivers. The block names and the number of stages of inserted block are shown in Table
K-18. The selection of the blocks to be used is based on the number of clock line branches.
Caution NEC recommends the use of only one CTS per chip. Using more than one CTS is possible,
however, it may cause the cell usage rate to decrease and the clock skew to increase as the
number of times CTS is used increases. In addition, because more time is needed for clock
tree synthesis and placement and routing as the number of CTS operations is increased,
users are advised to check their design schedule.
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Figure 5-14. Image of CTS Use (Example of FC44)
D
F144
D
D
F144
D
F144
D
F144
D
D
F144
F144
F144
D
F144
D
F144
F144
.........
FC44
............
F144
F144
F144
D
F144
D
F144
...........................
D
D
D
F144
F144
D
D
F144
F144
D
D
F144
D
D
Total: 16 blocks
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





F144
Total: 64 blocks
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(2) Clock tree synthesis guidelines
The following precautions apply when using CTS.
(a) The section from the output of the clock tree synthesis block (FCTS) to the block that requires optimized
clock skew must be described by one net.
If a function block is inserted in the path, the clock skew up to the function block is optimized.
Figure 5-15. Clock Skew Optimization
D
D
FCTS
In clock tree synthesis, the clock skew is
optimized as far as the thick wires.
D
D
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CHAPTER 5 CIRCUIT DESIGN GUIDELINES
(b) The FCTS is described in the TOP level hierarchy and is not entered in the macro. This makes skew
optimization difficult.
Figure 5-16. Example of CTS Block Description
Macro A
FCTS
Macro B
FCTS
(c) Routing detours increase with large macros and high use rates, and there are cases where clock skew
cannot be sufficiently optimized.
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5.5 Notes on Configuring High-Speed Circuits
Generally, when comparing the characteristics of P-ch and N-ch transistors, an N-ch transistor can pass a higher
current than a P-ch transistor. Therefore, a NOR gate consisting of P-ch transistors connected in series has a reduced
load drive capability at the rising of the output. For example, a NOR block is slower than a NAND block, and has poor
fan-out characteristics.
Guidelines to be followed when structuring a circuit that will run at high speed are shown below.
(1) Structure the circuit by using logic conversion techniques and standard NAND blocks.
• The circuit’s speed will improve, as will the circuit’s stability (see Figure 5-17 (a)).
(2) Structure the circuit so that the fan-out is as small as possible to lighten the load.
• In general, observe the 1/3 to 1/2 fan-out limit (see Figure 5-17 (b)).
(3) Convert from low-power blocks to standard blocks.
Figure 5-17. Configuring High-Speed Operational (Stable) Circuits
Circuits Not Suitable for High-Speed
(Stable) Operation
(a)
D
C
Q
D
C
Q
Circuits Suitable for High-Speed
(Stable) Operation
D
D
C QB
C QB
(b)
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5.6 Delay Time Margin
Logic circuits consist of combination circuits whose output is determined simply by the state at their inputs and
sequential circuits whose output is determined by the state at their inputs and their previous state. Specifically,
sequential circuits consist of gate circuits with feedback, flip-flops, and latches.
Bearing in mind testability considerations and ease of design estimation for delay time, it is clear that individual
combination and sequential circuits cannot be too large. Also, a majority of the sequential circuits are operated in
synchronization with the system clock, which has an adequate margin with respect to the delay times of the combination
circuits.
In the portion where adequate margin cannot be secured by the clock, timing of the entry of the sequential circuit,
i.e., each input of flip-flops and latches, must be secured.
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5.6.1 Timing definitions
(1) Setup time (t su)
Figure 5-18. Setup Time
In latches or flip-flops, the data setup time needed
tsu
to read data at the active edge of the clock.
D
C
(2) Hold time (th )
Figure 5-19. Hold Time
In latches or flip-flops, the data hold time needed
th
to read data at the active edge of the clock.
D
C
(3) Release time (trel )
Figure 5-20. Release Time
In latches and flip-flops, the time needed from release
of the reset or set until the active edge of the next
trel
clock becomes valid.
R
C
(4) Removal time (trem )
Figure 5-21. Removal Time
In latches and flip-flops, the time needed to make
the active edge of the clock invalid when the reset
trem
or set is cancelled.
R
C
(5) Minimum pulse width (tw )
Figure 5-22. Minimum Pulse Width
In latches or flip-flops, the minimum time of the
clock, reset, or set pulse width needed in order to
tW
read data correctly.
tW
C
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5.6.2 Delay time margin calculation (asynchronous circuits)
The setup time and the hold time for the circuit in Figure 5-23 are described as an example of calculating the delay
time margin. Here, the variation and wiring length are set conditionally as to decrease the margin. If the specifications
that are determined by each block (tsu and th) are satisfied, then decisions about normal operation can be ascertained.
Figure 5-23. Example of Delay Time Margin
Figure 5-24. Timing Estimate
Calculation Circuit
(a) Setup time (t su)
tPDA
s
tPDB
a
b
D Q
F/F
C
s
s
a
a
b
b
tPDA'
tPDB'
Calculation equations:
t su < tPDB’ – tPDA’
= tPDB(MIN.) – tPDA[MIN.(MAX.)]
= tPDB(MIN.) – tPDA(MIN.) ×
1+α
1–α
t h < t PDA” – tPDB”
= tPDA(MIN.) – tPDB[MIN.(MAX.)]
= tPDA(MIN.) – tPDB(MIN.) ×
1+α
1–α
α : Distribution coefficient (0.1)
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5.6.3 Delay time margin calculation (high-speed circuits)
In circuits operating at high frequencies, the operating margin for an internal functional block’s delay time is small
since the single-cycle time is short.
Here, the delay time margin calculation for both in-phase and inverse-phase circuits is described.
(1) In-phase clock
Consider the shift register operation containing delay between flip-flops F1 and F2 in Figure 5-25.
As shown in Figure 5-26, the points at which this circuit is inspected are where the output data (Q in F1) passes
through delay A and is input to F2 (sampling timing <1>) and at sampling timing <2>, where a check is made
to see if the data is read normally.
Therefore, the value resulting from adding the maximum delay at point a to the setup time of F2 must be
obtained within one time period (T).
Figure 5-25. Example of In-Phase Clock Circuit
F1
DATA
D
F2
Delay A
Q
Point a
C
D
Q
C
CLK
Figure 5-26. In-Phase Clock Timing
T
CLK
Q in F1
tPD of F1
Point a
tPD up to
point a
(TYP.)
Distribution from
TYP. to MAX. side Note
Sampling < 1 >
Sampling < 2 >
Note Do not cross into the next sampling timing with respect to the F2 setup time.
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Calculation equation:
T – (t PD(F1)(MAX.) + tPDA(MAX.) ) > tSU(F2)
The following countermeasures are necessary if this relationship is not satisfied:
• Reduce the amount of delay of delay A
• Lower the operating frequency (lengthen period T)
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(2) Inverse-phase clock
Figure 5-27 is an inverse modification of the F2 clock’s active edge shown in Figure 5-25. Since both the rise
and fall edges are used, the operating margin varies with the CLK duty. The circuit normally operates under
the following conditions.
Figure 5-27. Example of Inverse-Phase Clock Circuit
F1
DATA
D
F2
Q
Delay A
Point a
C
D
Q
CB
CLK
Figure 5-28. Inverse-Phase Clock Timing
T
tPOS
CLK
Q in F1
tPD of F1
Point a
tPD up to
point a
(TYP.)
Distribution from
TYP. to MAX. side
Note
Sampling < 1 >
Sampling < 2 >
Note Do not cross into the next sampling timing with respect to the F2 setup time.
Calculation equation:
t POS – (t PD(F1)(MAX) + t PDA(MAX)) > tSU(F2)
The following countermeasures are necessary if this relationship is not satisfied:
• Reduce the amount of delay of delay A
• Lower the operating frequency (lengthen period T)
• Increase the CLK duty
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5.6.4 Minimum pulse width
With circuits operating at high speed, there are cases when the minimum pulse width for a flip-flop input clock is
not satisfied due to the delay difference between the rise and fall of the signal and the relative variation of an identical
path.
For example, in Figure 5-29, the signal input by CLK passes through delay B and is input to the clock of the flipflop. The timing is shown in Figure 5-30. In regard to delay B, when the fall time delay (tPDB(LL)) is greater than the
rise time delay (tPDB(HH)), tNEG becomes greater than tNEG(MIN.), and the pulse becomes narrow. tNEG(MIN.) is estimated
by the conditional setting of tPDB(LL) to the maximum and tPDB(HH) to the minimum relative variation direction.
Figure 5-29. Minimum Pulse Width Estimate
Delay B
CLK
Q
tPDB(HH)
CLK
Figure 5-30. Pulse Narrowing
tNEG
TB
R
Point a
tPDB(LL)
tPDB(LL)
Point a
tPDB(HH)
tNEG(MIN.)
Calculation equations:
tNEG(MIN.) = tNEG + (tPDB(HH)(MAX.) – tPDB(LL)[MAX.(min.)]) > tW
→ tNEG(MIN.) = tNEG + (tPDB(HH)(MAX.) – tPDB(LL)(MAX.) ×
1–β
1+β
) > tW
β: Distribution coefficient (0.1)
The ratio tPDB(HH)/tPDB(LL) is controlled in order to regulate the minimum pulse width of the signal that is input to the
flip-flop clock. This increases the duty cycle. In the example above, if the functional block in delay B is changed to
a type in which the fall delay (tPDB(LL)) is fast and the rise delay (tPDB(HH)) is slow, tNEG(MIN.) increases. In addition, it
is necessary to be aware that the high-level pulse width must satisfy the minimum pulse width standard.
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5.6.5 Metastable state (preliminary)
If the setup and hold time standards are not satisfied and the clock and data or clock and set/reset are changed
simultaneously, the output may be oscillated at the flip-flop and latch and become an intermediate level that is neither
high nor low. This unstable state is called a metastable state. The metastable state ends after a certain time, and
the output settles into a high or low level. However, an unstable state results since the level that is defined has no
relationship to the data input level.
In the cases where the setup, hold, release, and removal times cannot be satisfied, take the countermeasures
shown below to prevent this unstable state from spreading over the entire circuit.
Setup time (tsu) ............ Time that the data signal must secure before the clock changes
Hold time (th) ............... Time that the data signal must hold after the clock changes
CLK
DATA
th
tsu
Caution The specified tsu and th must be satisfied (see the CMOS-N5 Family Block Library (A13872E)).
Release time (trel) ....... Time after the set/reset signal changes until the clock becomes valid
Removal time (trem) ..... Time needed in order to make the clock invalid
CLK
trem
trel
Set/Reset
Caution The set or reset signals must not be cancelled in the vicinity of the active edge of the clock.
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(1) Metastable state generation and recovery time
SET
DATA
D
CLK
C
Q
Setup/hold time not satisfied
Release/removal time not satisfied
CLK
DATA
SET
Expected value
Example of
abnormality
Recovery
Unstable state
(metastable)
Undefined state
(not known whether H or L)
Unstable state
(metastable)
Recovery
Undefined state
(not known whether H or L)
In the CMOS-N5 Family, the time of the metastable state is specified as shown below. After this time, the state
is either H or L, but it is not clear which (shown as “undefined” in the above figure).
Metastable time = tPD (MAX.) × 6
tPD (MAX.) ...... Maximum value of the delay time from the active edge of the clock until the output changes
(when the ratings of the setup/hold time could not be satisfied); or, release/removal time (when
the ratings of the release/removal time could not be satisfied).
There is no problem even if tPD0(MAX.) is used in F×××-type sequential circuits. For the respective
values, see the CMOS-N5 Family Block Library (A13872E).
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(2) Avoiding a metastable state
When the stipulated times cannot be satisfied (asynchronous input signals), configure the circuit so that the
occurrence of metastability will not affect the later stage. Examples of the abnormality and how to avoid it are
shown below.
Example of abnormality
When the output from b in the figure below is input to the counter, an excess number of counts may occur.
DATA
D
Q
a
D
Q
b
Counter
CLK
C
C
R
QB
R
RESET
Setup/hold time not satisfied
CLK
DATA
Expected value a
Unstable Undefined
Abnormality a
Expected value b
Abnormality b
Unstable
Undefined
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Example of avoiding abnormality
Output c is stable due to the insertion of the flip-flop. However, although the initial clock at c can have two
values as a function of the instability of b, there is no effect on the counter in the following example.
DATA
D
Q
a
D
Q
b
D
Q
c
Counter
CLK
CB
C
R
C
R
RESET
Setup/hold time not satisfied
CLK
DATA
Expected value a
Unstable
Undefined
Abnormality a
CLKB
Expected value b
Abnormality b
Undefined
Output c
(When the unstable state of b is H)
Output c
(When the unstable state of b is L)
Remark Clock width > tPD(MAX.) × 6 + (tsu or th)
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R
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5.6.6 Critical paths
A critical path relates to the system timing contained in the gate array. It is the path that establishes the delay time
for the gate array (see Figure 5-31). In this example, a detailed investigation of the paths A, B, and C (the critical
paths) is necessary.
• Path A:
Is the input timing of the device in the next stage satisfied for gate array output sampling by CLK?
• Path B, C: Is the sampling timing satisfied in the gate array by the controlling device’s output timing?
Figure 5-31. System with Critical Paths
Path B
Path C
Gate array
F/F
Control
device
Next stage
device
CLK
Path A
The following three types of critical paths are available:
<1> Input to output
<2> Input to input
<3> Output to output
The inspection and specification methods for these critical paths are explained in the following sections.
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(1) Calculating and designing a critical path
As described in 4.4.3 Estimating wiring capacitance, placement and routing are executed by determining
the placement range for each macro hierarchy (first hierarchy only). Consequently, the intramacro and intermacro
wiring lengths differ significantly. The following points must be noted when the propagation delay time of the
critical path is estimated using the virtual wiring capacitance listed in Table K-10.
<1> The critical path can be terminated in one macro hierarchy (first hierarchy) (excluding the I/O buffer).
<2> The load connected to the path can be reduced by making the critical path as simple as possible (limiting
the fan-out value to 1/3).
<3> Except as given above, the input and output pins should be placed as close together as possible in regard
to critical paths from the input to output pins.
<4> Circuits other than critical paths should not be included in macro hierarchy.
(2) Critical path between input and output
Path A in the circuit example of Figure 5-31 is not influenced by other inputs. The maximum tPD value must
be designed to be smaller than the value required by the system.
In addition, keep in mind the large dependency of the output buffer’s delay time on the external load capacitance
CL .
Calculation equation:
tPD(MAX.) < System specification value
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(3) Critical path between two inputs
The circuit configuration in Figure 5-32 will be calculated as an example to study the input sampling timing.
Calculation will be made assuming that the timing of a signal input from outside is as shown in Figure 5-33,
since the mutual timing specification between the input pins must be well defined in this timing verification.
Figure 5-32. Example of Input-Input Critical Path
Figure 5-33. Verification of Setup Time
(F611)
DATA
tPDD
DATA
D Q
CLK
C
CLK
tPDC
4.7 ns (MIN.)
The following points must be taken into consideration with respect to the conditions used:
• Absolute variation is in the direction of the smallest margin
• Relative variation is in the direction of the largest tPDD and the smallest tPDC
The method for making these decisions is shown below.
Calculation equations:
DATA is assumed to be a time differential of 4.7 ns (MIN) from CLK, as shown in Figure 5-33.
tPDC(MIN.) – tPDD[MIN.(max.)] + 4.7 > tSU
→ tPDC(MIN.) – tPDD(MIN.) ×
1+α
1–α
+ 4.7 > tSU
α: Distribution coefficient (0.1)
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5.6.7 Ensuring operating margin
When a circuit lacks an operating margin as the result of a delay margin check and a critical path check, there are
several things that can be done, depending on the circuit’s configuration.
Generally, the following methods are used.
<1> Reassess input and output specifications
• Decrease the input fMAX. and lower the input fMAX. duty variation
• Ease the input and output timing and decrease the output’s load capacitance
<2> Reassess pin placement
• Shorten the wiring length to decrease the delay between input and output (adjacent placement of pins)
<3> Modify the circuit
• Decrease the delay time by simplifying the circuit
• Decrease the delay time by decreasing the load on the circuit
• Obtain a margin by inserting a delay gate
Delay calculations (or recalculations) are necessary when modifying a circuit, so it is particularly important to
estimate the inserted gate output wiring length as 0 mm in regard to delay gate insertion.
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5.7 Internal Bus Configuration
5.7.1 Configuring internal bus
Typical data selection techniques include the data selector format and the bus format. The circuit configuration
of a data selector (multiplexer) can become very complex. On the other hand, the bus format enables a comparatively
simple circuit configuration that it is easier to understand and the number of cells used does not increase. However,
the propagation delay time may increase. Therefore it is important to select the optimum format according to the circuit
structure.
Figure 5-34. Bus Configuration
5.7.2 Preventing internal bus floating
As a basic rule when using an internal bus, only one block configured on the same bus line should be in the output
enabled state. This is necessary to avoid the input of the next stage block being in a floating state. Examples of a
good internal bus circuit structure are shown in Figure 5-35.
Figure 5-35. Examples of Internal Bus Floating Prevention Circuit
(a) Example 1
(b) Example 2
F091
H
L
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5.7.3 Precautions when using internal bus
Although the internal bus can operate with multiple blocks connected on the same bus line, the signal rise and fall
times may increase due to an increase in wiring length and an increase in the fan-in loading of the previous block.
Since problems in operating stability and reliability may result, the following constraints must be observed. For further
information, see 5.8 Preventing Contention with External Bus.
(1) Observe the bus constraints indicated by the following formula:
F/O + N ≤ 50
(1.4 × F/O +1.1 × N + 1.9) × f < 410
F/O ... Sum of the fan-in loading (F/I) of the gates connected to the bus
N ....... Sum of the 3-state output buffers (F531, F532) connected to the bus
f ......... Operating frequency (MHz) of the bus
Contact NEC if it is required that the design exceeds the above conditions.
(2) Basically, the following states are prohibited on the bus line.
(a) More than two outputs are enabled on the same bus line.
(b) All outputs are disabled on the same bus line.
Consider enable-signal skew in order to converge the above states within no more than 20 ns.
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5.8 Preventing Contention with External Bus
In addition to the explanation in 5.7.3 Precautions when using internal bus, the two items below should be noted
when connecting gate array and other LSIs in a system using a bus configuration.
(1) Bus contention
(2) Bus floating
Take measures via timing design and pull-up/pull-down resistors in order to avoid these problems.
In addition, in order to avoid external bus floating, I/O blocks with pull-up and pull-down resistors can also be used.
For further information, see CHAPTER 7 MULTIFUNCTION BLOCKS.
Figure 5-36. External Bus Floating Prevention Countermeasure
VDD
System bus
Gate array
Other LSI devices
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5.9 Testability
There is more than just logic design when designing a gate array. Testing and test circuits are also necessary.
Consider the points shown below when designing the circuit and generating a test pattern. For more information, see
CHAPTER 6 TEST PATTERN GENERATION.
•
Flip-flop (F/F) initial setting
•
Division of counters
•
Addition of test pins
•
Division (modularization) of internal circuits by test pins
5.9.1 Flip-flop initial setting
When the device is powered up, it is not known whether the output state of a block, such as a flip-flop or counter,
is high level or low level. Consequently, the initial state must be set using the first few patterns during simulation.
In the design stage, the circuit should be configured so that an initial setting pattern is not too long, and blocks with
reset inputs should be used as much as possible so that the initial state of the internal circuit can be reset.
Figure 5-37. Flip-Flop Initial Setting
D
S
D
T
C QB
T
QB
R
C QB
S
QB
R
5.9.2 Counter division
With multi-bit counters, the effective test method is to divide the counters to reduce the number of test patterns.
For example, the number of pulses necessary until the final stage of a 16-bit counter operates is 2 to the 16th pulses.
By dividing the 16-bit counter into two 8-bit counters as shown in Figure 5-38, however, the number of pulses can
be cut by 1/100 to 1/200.
Figure 5-38. Counter Division
16-bit counter
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5.9.3 Adding test pins and dividing circuits
Similar to the case in 5.9.2 Counter division, when testing multibit counters and large-scale macros, the LSI test
can often be simplified and the number of test patterns reduced by setting up “test pins”, which enable the operation
mode to be set externally.
(1) An effective method to test LSIs when the circuit is internally divided into several operation modes is to set
up pins (test pins) to enable the setting of a specific test mode.
(2) Large-scale circuits are often configured by several partitioned macros (modules), when testing such a circuit,
an effective method is to set up specific test pins per partitioned module to enable testing of the circuit in a
divided state.
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5.10 Racing and Spike Noise
5.10.1 Racing (contention)
The state where the timing changes when there are more than two input signals in a logic block is called racing
(contention).
If the test pattern shown in Figure 5-39 (b) is added to a circuit such as that in Figure 5-39 (a), a shift in flip-flop
data and clock timing occurs due to the difference between the two delays in buffer 1 and 2 and the routing delay
difference. The result of this is that the expected operation does not occur. In the case of Figure 5-39 (a), data is first
set in the flip-flop, making it necessary to consider a change in the clock. The test pattern for this is shown in Figure
5-39 (c).
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Figure 5-39. Racing
(a) Circuit with potential for racing
1
DATA
D
Q
OUT
C
2
CLK
(b) Test patterns with potential for racing
1
2
3
4
5
6
7
DATA
CLK
OUT
(Expected output)
OUT
(When the CLK changes
faster than the DATA)
(c) Test patterns that do not cause racing
1
2
3
4
5
6
7
DATA
CLK
OUT
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5.10.2 Spike noise
Spike noise is noise in a circuit that employs two or more gate inputs and is caused by a small input timing shift
when the input signal timing changes. The time interval of this spike noise changes as a function of the size of the
shift in timing. If the spike noise is input to the next-stage flip-flop clock or the set/reset, the affected signal path related
to the flip-flop’s output signal can generate errors in operation.
Consequently, when gates with two or more inputs are used, it must be checked whether an influence is exerted
on the next-stage gates and the external output signals by spikes generated by changes occurring when the multiple
inputs operate simultaneously. It must also be confirmed whether or not operating errors are occurring. If the spike
noise cannot be ignored in the following stage, the test pattern and circuit need to be modified so as to not
influence the following stage.
Following is an example of the generation of spike noise and measures that can be taken against it.
Figure 5-40. Example of Data Selector Circuit
DA
c
OUT
DB
b
SEL
A
a
The AND-NOR data selector circuit shown in Figure 5-40 will generate the test pattern shown in Figure 5-41.
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Figure 5-41. Example of Test Patterns (Before Improvement)
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17
DA
DB
SEL
a
b
c
OUT
In this case, when both the DA and DB input data signals are in a high-level state, spike noise is generated at the
output signal OUT since the SEL (select signal) changes from H to L. The pattern in Figure 5-41 generates spikes
at pattern locations 2, 8, 11, and 15.
As is clear from the circuit diagram, when DA and DB are in the high-level state, the state of b and c are determined
by the state of SEL. In addition, when SEL changes from H to L, b changes from L to H and c changes from H to
L in the same pattern. Moreover, a changes when it goes through inverter A and the delay through A is greater than
that of SEL. Because of this, b is delayed more than c for inverter A. Consequently, the state of b and c are
simultaneously L and L at 2, 8, 11, and 15 of the test pattern, and L-to-H-to-L spike noise is generated for OUT.
Implement the following two measures if this spike noise is input to the flip-flop clock or the set/reset.
<1> Stop the flip-flop output changing due to spike noise by ensuring that the data is not changed, or by some
other method at the spike noise generation timing.
<2> Modify the test pattern.
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In the case shown in Figure 5-41, when SEL changes from H to L, make at least one of DA or DB change to L.
There is no spike noise at the output OUT if the timing is designed as shown in Figure 5-42.
Figure 5-42. Example of Test Patterns (After Improvement)
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17
DA
DB
SEL
a
b
c
OUT
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CHAPTER 6 TEST PATTERN GENERATION
When designing with gate arrays, the circuit’s expected function and performance are verified through simulation
on a computer. To execute the simulation, the user is requested to prepare a circuit diagram and test patterns.
These test patterns are also used for product inspection before shipment. During shipment inspection, the functions
of the LSI are verified (test function) and the DC characteristics (such as power supply leakage current, input leakage
current, and output current) are tested. Unless adequate consideration is given to the shipment inspection, therefore,
the product is not thoroughly tested when shipped. Users are therefore requested to generate test patterns with which
fault detection and DC testing can be performed.
During simulation, the conditions under which the LSI is actually used by the user can be realized relatively easily.
The LSI tester, which tests the actual LSI, however, cannot completely reproduce the conditions under which the user
actually uses the LSI, in many cases. The test patterns should therefore be generated in accordance with the capability
of the LSI tester and by observing specified limits.
This chapter describes the points to be noted when generating test patterns.
6.1 Test Pattern Types
The types of test patterns available are shown in Table 6-1.
One DC test pattern is essential, but other test patterns may also be necessary depending on circuit or user
requirements. When the LSI tester is used to perform DC measurement, the measurement is carried out using up
to the first 32,000 patterns of the DC test pattern.
Table 6-1. Test Pattern Types
Pattern Name
DC test pattern
Function test pattern
High-speed function test pattern
Megamacro initialization pattern
Megamacro single-unit test setting pattern
Megamacro test pattern
Scan test pattern
RAM test pattern
Digital PLL initialization pattern
Purpose
DC measurement, logic verification
Logic verification
Logic verification (real time)
Initialization
Setting megamacro peripheral values
Logic verification (megamacro single unit)
Fault detection
Logic verification (RAM single unit)
Initialization
Pattern Generator
User
User
User
NEC (inserted by user)
User
NEC
User or NEC
NEC
User
Boundary scan test pattern
Logic verification (boundary scan circuit)
User or NEC
Although the pattern length per pattern is not restricted (except for the high-speed function test), the total pattern
length is. For details, refer to 6.2.2 Limitations on test pattern length.
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6.2 Notes from Viewpoint of Product Test (LSI Tester)
6.2.1 I/O pin naming conventions
(1) Maximum number of characters for I/O pins
64 characters MAX.
(2) Characters allowed
Some characters must not be used when specifying a pin name. The characters that can be used are listed
in the table below.
Table 6-2. Restrictions on Pin Names
Usable characters
Alphabetic uppercase letters
Numeric characters
“_” (underscore)
Unusable characters
“ / ” (slash) and all other special characters other than the underscore
Alphabetic lowercase letters
6.2.2 Limitations on test pattern length
The length of a test pattern is limited by the size of the LSI tester’s memory.
The minimum and maximum lengths of test patterns (for DC test and for the function test) are listed in Table 6-3.
Table 6-3. Limitations on Number of Test Patterns
PackageNote 1
Number of Patterns Minimum Number of Test Patterns
(Applicable to DC Test Patterns)
144 pins or less: with SCAN
150 patterns
Maximum Number of Test
Patterns Note 2
128 K patterns
144 pins or less: without SCAN
256 K patterns
145 pins or more
512 K patterns
Notes 1. The number of package pins includes the number of power supply pins (GND, V DD, etc.).
2. The maximum length of test pattern does not need to be considered for the RAM test pattern, scan test
pattern created by NEC, and high-speed function test pattern.
Examine each length of test pattern for the user-created test pattern and megamacro boundary scan,
taking the limited pattern length above into consideration.
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6.2.3 Number of test patterns
There can be more than one test pattern. The maximum number of patterns is 10, including all interface test patterns
such as those for DC test and function test. In this case, the RAM test pattern, scan test pattern created by NEC,
and high-speed function test pattern do not need to be considered.
However, the number of test patterns should be minimized as far as possible in order to increase efficiency. Even
if the test pattern is divided for the sake of convenience of design, in principle, submit one test pattern to NEC (the
test patterns can be easily combined by using the wave editor of the pattern utility or OPENCAD).
To divide the test pattern, initialize each pattern (see 6.3.1 Initializing circuit). If this is not possible, be sure to
inform NEC of the sequence of the test patterns (in writing).
The test pattern must be divided in the following cases.
• If the time conditions (input delay and pulse width) and output judge time (strobe time) of the input signals differ
For details, see 6.3 Notes on Creating Test Pattern for Function Test.
6.3 Notes on Creating Test Pattern for Function Test
6.3.1 Initializing circuit
Whether the output state of blocks, such as flip-flops and counters, is at the high level or low level immediately
after power application is unknown (see 5.9.1 Flip-flop initial setting). Consequently, the initial status of sequential
circuits such as flip-flops and counters is “x” (undefined) during simulation. To verify operation of the circuit, it is
necessary to change the internal function block state from an indeterminate state to a determinate state (circuit
initialization).
When designing a circuit, prepare a pattern that can initialize the circuit at the beginning of the test pattern, and
at the same time, consider use of a reset pin, so that the circuit can be easily initialized.
When preparing divided test patterns, in principle, initialization is necessary for each pattern (see Figure 6-4 Test
Pattern Example).
6.3.2 Test cycle (test rate)
The test rate is referred to as the cycle of one test pattern.
Currently, the test cycle limitation at NEC for a general function test is as follows:
Test cycle: 200 ns
If a higher-speed test cycle than above is desired, perform the high-speed function test. For the high-speed function
test pattern, refer to 6.6 High-Speed Function Test (Real-Time Test).
6.3.3 Output determination time (strobe time)
The output determination time (strobe time) refers to the time during which the output value of the product is
referenced with the expected value on the test pattern. In the current normal function test pattern, this time is always
the final time (199.99 ns) of the period, and anything outside of this becomes a high-speed function.
For details of the high-speed function test pattern, see 6.6 High-Speed Function Test (Real-Time Test).
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6.3.4 Specification of timing phase
For the specification of timing phases currently supported, refer to Table 6-4 (including the basic timing).
The skew among the pins of the LSI tester (specified as ±5 ns) must be considered, and the time differential of
each phase must be set to 10 ns or greater.
The basic timing phase indicates the NRZ signal when (∆tD = 0 ns. NRZ signals with an equal delay time (∆tD)
are considered as in-phase and counted as one phase no matter how many input pins there are with the same timing.
Likewise, RZ signals with an equal delay time (∆tD) and pulse width (∆tW) are also considered as in phase.
Positive clocks and negative clocks with an equal ∆tD and ∆tW are also counted as one phase. However, NRZ
signals and RZ signals with an equal ∆tD are in-phase.
Table 6-4. Timing Phase Number
Timing Phase NumberNote
PKG
All packages
6
Note Including basic timing phases.
Table 6-5. Timing Constraints
Timing Limit
Signal Type
Input Delay (∆tD)
MIN.
Basic timing
MAX.
0 ns
Input Pulse Width (∆tW)
MIN.
MAX.
—
NRZ signal
10 ns
T – 10 ns
RZ signal (clock mode)
10 ns
T – ∆tW – 10 ns
—
145 pins or more:
10 ns
144 pins or less:
15 ns
T – ∆tD – 15 ns
Remarks 1. NRZ (No Return to Zero) signal: Indicates there is only one change within one test pattern (1 test
rate).
2. RZ (Return to Zero) signal: A signal with a change of 0 → 1 → 0 or 1 → 0 → 1 within one test pattern.
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Figure 6-1. Timing Phase
T
T
Basic timing
∆tD
∆tD
NRZ signal
with input delay
∆tD
∆tW
∆tD
∆tW
∆tD
∆tW
∆tD
∆tW
RZ signal (P)
(clock mode)
RZ signal (N)
(clock mode)
Cautions 1. At least 10 ns must remain between changes of each signal.
2. RZ signal input to bidirectional pins is prohibited.
Remark T: Test cycle (test rate)
The clock mode (RZ) signal of the input has two polarities, which determine how it is used.
Table 6-6. Clock Mode
Input Pattern
Definition
Operation
Positive Clock (P)
Negative Clock (N)
1 (H)
Clock generation
0→1→0
(positive clock generation)
1→0→1
(negative clock generation)
0 (L)
Clock stop
0 hold
1 hold
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6.3.5 Skew
When two or more input signals are changed at the same time during simulation, no skew occurs between input
signals. With an LSI tester that is used to check the quality of products, however, the input signals do not change
at exactly the same time because of a skew of several ns that exists between input pins, even if it is specified that
the signals change at the same time. Consequently, even if no problem is found during simulation, the product may
not pass a quality test because of the skew between pins.
Therefore, take the following measures so that the product will operate normally even if there is an input skew when
creating a test pattern.
(1) Do not change a flip-flop’s data input and clock at the same time
→ Instead, alternate by one pattern.
(2) Use a clock signal (RZ signal) and an input delay signal (NRZ signal).
→ Stagger the input.
If it is assumed that the input skew is 10 ns and the setup time between data and clocks is 5 ns, then a 15
ns delay time is needed, as shown below.
LSI tester input skew
+
Setup time
=
Input delay time specified to clock signal
10 ns
+
5 ns
=
15 ns
6.3.6 Notes on switching I/O mode of bidirectional pin
(1) Although the switching of the bidirectional pins’ I/O mode is generally carried out at the basic timing, for the
DC test pattern and function test pattern, it is possible to shift the I/O switch timing of a single set. This is known
as the I/O modulation function (refer to 6.3.7 I/O modulation function for details).
Note, however, that the bidirectional pin I/O mode cannot be switched using the RZ signal (because the mode
will change twice within 1 rate: input → output → input. See Figure 6-2.)
Figure 6-2. Example of Incorrect Bidirectional Pin Switch Timing
Control pin
Bidirectional pin
186
in
out
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(2) In cases when an input delay has been added to the control pin in the bidirectional pin I/O mode, or when
the I/O mode switch timing is different to the basic timing because there is a delay until the internal circuit
is enabled, ensure that the input and output values match when switching the I/O mode. This processing
prevents a current from flowing when the device’s output signal conflicts with the LSI tester’s driver (input),
and is used to avoid power supply modulation or other such causes of malfunction. If it is not possible to
match the input and output values, ensure that the conflict does not exceed 20 ns (see 6.3.8 I/O conflict).
Note that it is prohibited to input the RZ signal (clock waveform) to a bidirectional pin.
Figure 6-3. Contention During Input/Output Switching
Input mode (high impedance)
LSI pin
Contention
High impedance
Output (comparator)
LSI tester
Input (driver)
T
T
Remark T: Pattern period
(3) In cases when due to the circuit specifications of PCI bus circuits, etc. the I/O mode switch timing differs from
the basic timing, and the bidirectional mode is switched after the pre-switching value is fetched inside the
circuit, use the I/O modulation function (refer to 6.3.7 I/O modulation function for details).
External pin
Internal data
Clock input
F/F
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6.3.7 I/O modulation function
Although in the case of the DC test pattern and function test pattern it is possible to shift the I/O switch timing of
a single set, the following restrictions apply.
T
T
∆td
T
∆td
I/O switch signal
I/O switching
Input
Remark T:
Output
Input
Pattern period
∆td: Input delay of I/O switch signal
When shifting the I/O switch timing from the basic timing, the I/O switch time on the tester side is set as the I/O
modulation.
The following expression must be satisfied, assuming ∆t rmax is the slowest time of all the pins and patterns among
the bidirectional pin (simulation result) I/O switch times, and ∆ts is the I/O modulation time.
∆ts ≥ ∆t rmax + 5 ns
The reason for this is that in cases when the bidirectional mode is switched after the pre-switching value is fetched
inside circuits such as a PCI bus circuit, because it is necessary to hold the external (LSI tester) value until the pin’s
I/O mode has been switched, the circuit must be driven longer (I/O mode switching delayed longer) than in the
simulation result: 5 ns of the skew between the LSI tester pins.
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T
T
T
∆td
∆td
I/O switch signal
∆tr1
∆tr2
I/O switching 1
∆tr3
∆tr4
I/O switching 2
∆ts
∆ts
I/O switching by tester
(I/O modulation time)
Input
Remark T:
∆td:
Output
Input
Pattern period
Input delay of I/O switch signal
∆tr1 to ∆t r4: Bidirectional pins’ I/O switch times
(∆t r3 in the above figure corresponds to ∆trmax in the aforementioned equation.)
∆ts:
I/O modulation (I/O switching on the tester side) time
In addition to satisfying the above conditions, the following restrictions must be observed.
Item
Restriction
I/O Modulation (∆t s)
Interval Between I/O Modulation and Other Input Delay (∆t p)
MIN.
MAX.
MIN.
10 ns
T – 10 ns
10 ns
T
∆ts
I/O switch signal
∆tp
Other input
When setting both the input delay (∆t d) and I/O modulation (∆ts) for the same pin, ensure that either of the following
is satisfied: ∆ts = ∆td, or ∆t s + 10 ns ≤ ∆td.
Note that the I/O conflict time must be kept within 20 ns, even when using the I/O modulation function.
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6.3.8 I/O conflict
If it is not possible to match the bidirectional pins’ input and output values, the I/O conflict must not exceed 20 ns.
The reference for judging I/O conflict is shown below.
Simulation Result
Expected Value
Input
Mode Undefined
Output 1
0, X
0, X
Output 0
1, X
1, X
Output X
0, 1, X
0, 1, X, Z
6.3.9 Testing multifunction I/O circuits
(1) Oscillators
Oscillators cannot be actually oscillated and tested with a simulator and LSI tester. Input a dummy signal to
the input pin of the oscillator.
Use the inverted signal of the input signal as the expected value of the output of the oscillator.
The oscillator input signal is equivalent to the clock signal. Because a stable test cannot be performed due
to conflict if this input signal and external data or set/reset input signals are changed at the same timing, be
sure to stagger the timing.
Because the test pattern is not modeled in an oscillating state, the external timing of data or reset signals related
to the clock in an oscillating state (oscillator input signals) is not tested.
(2) Open-drain output
The expected output value in the case of output disable must be high impedance (Z).
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6.4 Notes on Creating DC Test Patterns
Restrictions for DC test patterns are basically same as those for function test patterns. The test pattern is not only
used to test the functions but also used to test DC characteristics during shipment inspection. Therefore, the following
points must be noted in creating a test pattern.
<1>
<2>
If possible, prepare a dedicated test pattern set for the DC test pattern.
The length of the DC test pattern should be more than 150 patterns. If the length of the pattern exceeds
32,000, perform the DC test between 1st and 32000th pattern.
<3>
If possible, make input pins change at least two times (except for oscillation stop control pin).
<4>
Output pins must output a high level and a low level at least once each.
<5>
The output pin of a three-state output buffer must output a high-impedance state (off state).
<6>
When a bidirectional buffer is used, make sure that the input state and output state are switched at least
once.
<7>
The test cycle must be sufficiently longer than the delay time (operating time) of the circuit. The basic cycle
is 200 ns. Be sure to set the output determination time (strobe time) towards the end of the cycle (this is
so the output is determined after the circuit has entered the stable state).
<8>
If an RZ (Return to Zero) signal is input to an input pin, make sure that the RZ signal is not output as is.
The output value of the output pin that outputs the RZ signal is always either one of two values at output
determination time, and the other value cannot be tested.
<9>
Bus fighting and bus floating for the internal bus is prohibited.
<10> Initialize the circuit until 50th pattern.
<11> The IDDq test is performed in the DC measurement pattern. The measurement pattern is selected automatically.
If possible, operate the internal circuit to improve coverage.
<12> Be sure to set to oscillation mode when an oscillator block is mounted.
<13> In the test pattern in oscillation mode, input the same pattern as normal clock pattern for the input pin (XT1)
and expected value of output pin (XT2) should be its inverse.
The RZ signal has changes of “0 → 1 → 0” and “1 → 0 → 1” in one test pattern (1 test rate). By contrast, the NRZ
(No Return to Zero) signal has only one change in one test pattern (1 test rate).
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6.5 Test Pattern for On-Chip RAM
NEC supplies a test pattern for RAM, and the user does not have to consider RAM tests. However, the following
limitations are applied if NEC supplies the test pattern for RAM. (For details, see 7.4 Memory).
(1) Additional RAM pins (TIN, TEB, and TOUT) are needed in order to test the RAM.
(2) If there are multiple RAMs or connections between RAM and logic circuits, the connection to each RAM must
be tested by the user test patterns.
(3) Be sure to make the user mode of the TEB pin high at the first pattern of each test pattern.
Figure 6-4. Test Pattern Example
DC test pattern
Initialization pattern
Function test pattern
Initialization pattern
RAM test circuit connection verification pattern
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;;
;
High-speed function
test pattern
Initialization pattern
CHAPTER 6 TEST PATTERN GENERATION
6.6 High-Speed Function Test (Real-Time Test)
Checking the designed circuit through simulation at the actual operating frequency is a very effective technique
for checking the actual operation of the LSI. In this way, problems concerning the timing of the circuit during actual
operation that may have been overlooked by the designer can be found.
During the shipment inspection of the product, the actual operating conditions cannot be always simulated because
the performance of the LSI tester may be limited. The high-speed function test, however, can simulate conditions
very close to the actual operating conditions.
This section describes the following limits of the high-speed function test. Create a test pattern observing these
limits.
6.6.1 Limitation of the test pattern length
The length per test pattern must consist of 32,000 patterns MAX.
6.6.2 Test cycle (test rate)
The test rate is referred to as the cycle of one test pattern.
Currently, the test cycle limitation at NEC for a general high-speed function test is as follows:
Test cycle: 50 ns MIN.
6.6.3 Output determination time (strobe time)
The output determination time (strobe time) indicates the time required to verify the output value of the product
against the expected value on the test pattern. Currently, up to two strobe times can be assigned per test pattern.
However, only one strobe time can be assigned per pin. If three or more strobe times or several strobe times per pin
must be established, each one must have its own test pattern.
Setting strobe time within 15 ns the beginning of the basic timing or with 10 ns before the end of the timing is
prohibited.
Figure 6-5. Strobe Time
Test cycle T [ns]
<b>
<a>
<c>
<a>
<b>
<c>
15 ns ≤ strobe time ≤ T − 10 ns
Caution Open-drain, GTL, and HSTL buffers are not real-time test targets.
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6.6.4 Notes on high-speed function testing
To conduct the high-speed function test, execute MIN/MAX simulations under the following conditions. The
results of both the simulations must match.
Confirm these simulations before and after placement and routing.
Note that I/O modulation cannot be used.
Ask NEC for the delay data (path delay file) after placement and routing.
At this time, the load capacitance data file (DIF FILE) for the output pins used for simulation is necessary.
Submit this file to NEC.
For the format of the DIF file, see APPENDIX C ALBATROSS AND DIF FILE FORMATS.
The purpose of these simulations is to detect the possibility of occurrence of problems when inspection is performed
with an LSI tester. Therefore, conditions different from the actual operating conditions must sometimes be set.
Specify settings of the time condition for input signals, the output determination time (strobe time), and the test
cycle (test rate) for each phase in “High-speed function test guidelines”.
<1>
MAX. simulation conditions
Test cycle (T):
User-specified value
Load capacitance (CL):
Bidirectional pin: 125 pF, MAX. value of load capacitance with LSI tester
Strobe time:
Set to specified value –5 ns with skew of strobe time assumed to be –5 ns
Output pin: 90 pF
<2>
MIN. simulation conditions
Test cycle (T):
User-specified value
Load capacitance (CL):
50 pF, MIN. value of load capacitance with LSI tester
Strobe time:
Set to specified value +5 ns with skew of strobe time assumed to be +5 ns
During real-time simulation, the simulation result may not converge in one pattern and the output may change at
the next pattern, as shown in Figure 6-6.
If the simulation result is different between the MAX simulation and MIN simulation, take the following measures:
• Change the expected output value of the test pattern, which differs between the two test patterns, to “X” (Don’t
care).
Synthesize the test patterns (see Figure 6-6).
• Alternatively, include only the timing actually requiring inspection as the system, as the expected values.
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Figure 6-6. Real-Time Simulation Results
Minimum simulation result
Output value
“1”
“1”
“0”
“0”
“0”
“1”
“1”
“0”
“X”
“1”
“X”
“0”
Maximum simulation result
Output value
Expected value after
output synthesis
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6.7 Testability (Fault Coverage)
6.7.1 Consideration of testability (fault coverage)
Fault simulation is a way to verify the testability (fault coverage) when an ASIC is developed. In other words, it
diagnoses the validity of a test pattern created to test the functions of logic circuits and detects the faults that are not
detected by that test pattern.
During the ASIC manufacturing process, various faults may arise. These faults are broadly classified into dynamic
faults and static faults.
Dynamic faults create long delay paths, spikes, and timing violations. Such faults are caused by the operating
environment or design errors.
Static faults are represented by physical damage to the chip such as routing shorts and opens. In most of the cases,
the production process is responsible for these faults. Logic simulation verifies the functions and timing of a created
circuit. However, it does not verify the test efficiency of a test pattern for detecting static faults in the chip actually
produced. Fault simulation defines static faults in the circuit and verifies whether faults have been accurately detected
by the input test pattern from the output pins of the ASIC developed.
The purpose of fault simulation is to inspect how efficiently test patterns can detect a fault at the boundary of the
function blocks of the created circuit. The test efficiency of these test patterns is called testability (fault coverage)
and is expressed as a percentage to indicate how well the test patterns can detect the faults in the circuit.
Testability (fault coverage) =
Number of faults detectable by given test input pattern
Total number of faults in circuit tested
× 100 (%)
If the testability (fault coverage) is low, the LSI may not be tested well and defective products may be shipped.
NEC recommends that the fault coverage, as far as possible, be made at least 90% in order to raise the quality
of the product.
To improve testability (fault coverage), it is recommended to provide a test circuit at the circuit design stage and
to employ the scan path test method.
6.7.2 Principle of fault simulation
Fault simulation generally operates by the same algorithm as the logic simulation that tests the logical functions.
In the execution of fault simulation, however, the faults can be set in the circuit. Figure 6-7 shows examples of fault
simulation.
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Figure 6-7. Concept of Fault Simulation (1/2)
(a) Circuit example
a
(b) Test patterns
e
a
H
b
b
J
c
g
f
c
I
d
d
g
It is assumed that this circuit has a fault and that the output of the 2-input AND gate H is always at the low level.
If an input signal the same as Figure 6-7 (c) is input in this case, it can be seen that the result of output “g” will be
different (see Figure 6-7 (c) and (d)). Accordingly, this fault can be detected by these test patterns.
(c) Observation of point e and point f
(d) Fault result of AND H
a
a
b
b
c
c
d
d
<e>
<e>
<f>
<f>
g
g
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There may also be cases of a fault in which the output of the 2-input AND gate I is always at the low level.
As shown in Figure 6-7 (e), this input signal (test pattern) becomes the same as the test pattern in Figure 6-7 (c),
which shows that they are ineffective in detecting this fault.
Figure 6-7. Concept of Fault Simulation (2/2)
(e) Fault result of AND I
a
b
c
d
<e>
<f>
g
Fault simulation defines these types of faults one by one with respect to the internal circuit and checks whether
the defined faults can be detected at the output pin by performing simulation.
The types of faults that can generally be defined by fault simulation are called single degenerate faults.
The following two types of single degenerate faults are defined in circuits:
<1>
Stuck-at-1: Fault where a given part is fixed at the high level (“1”)
<2>
Stuck-at-0: Fault where a given part is fixed at the low level (“0”)
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6.8 Consideration of System Simulation
System simulation is a method for checking the functions of a gate array under development by simulating the
operations of the gate array in an environment close to the actual operating environment, such as on a board or in
equipment.
After checking the functions of the gate array in equipment, the test pattern of the gate array alone is extracted
by monitoring the signals at the input/output pins of the gate array.
This test pattern can be used as a test pattern for LSI testing. However, be sure to confirm that there is no
problem (that the points to be noted in creating the test pattern are satisfied) by executing a simulation of only
the gate array.
Figure 6-8. Creating Test Patterns by System Simulation
Specification design
Design of test patterns
for system simulation
Circuit design
System simulation
NG
OK
Extraction of test patterns
for chip as an independent unit
Revision of I/O attribute
input of bidirectional Z
revision of X input
Revision of input skew
Simulation chip as an
independent unit
NG
OK
Interface with NEC test patterns
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CHAPTER 7 MULTIFUNCTION BLOCKS
The CMOS-N5 Family offers the following multifunction blocks, in addition to the normal function blocks. This
chapter explains the functions and usage of each multifunction block.
• Buffer with fail-safe function
• Buffer with on-chip pull-up/pull-down resistors
• Oscillator
• Memory block
• Megamacros (under development)
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7.1 Buffer with Fail-Safe Function
Because input voltage higher than VDD cannot be applied to a conventional gate array, no I/O voltage can be applied
when the supply voltage of the gate array is turned off. A buffer with a fail-safe function can accept voltage even if
the supply voltage to the gate array is off.
If a high-level signal is input to the normal input buffer while the power supply to the gate array is off, voltage is
applied to the power line via a protection diode (see Figure 7-1). Also, if a high-level signal is input to N-ch open drain
pins while the power supply to the gate array is off, voltage is applied to the power line via a protection diode. The
buffer with a fail-safe function prevents voltage being applied to the power line when the supply voltage to the gate
array is off, even if a high-level signal is input. It can therefore be used for hot insertion and removal as long as the
specified static voltage condition is satisfied.
Figure 7-1. Equivalent Circuit Diagram for Buffer with Fail-Safe Function
(a) Conventional input buffer
(b) Input buffer with fail-safe function
IDD
VDD
VDD
VF
VI–VF
VI
VI
(c) Conventional N-ch open-drain buffer
(d) N-ch open drain with fail-safe function
IDD
VDD
VF
VO–VF
VO
VO
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7.2 Input/Output/Bidirectional Buffers with On-Chip Pull-Up/Pull-Down Resistors
The CMOS-N5 Family has input buffers, Schmitt input buffers, 3-state output buffers, N-ch open-drain output
buffers, bidirectional buffers, Schmitt input bidirectional buffers, and I/O blocks with on-chip pull-up/pull-down
resistors. By using these, a more compact system can be created.
For the name of each block, contact NEC.
Pull-up resistor
VDD
Pad
VDD
Pad
VDD
Pad
Pull-down resistor
Pad
Pad
Pad
During simulation, undefined (X) or high-impedance (Z) values cannot be input to the input pins of the input buffers
with on-chip pull-up/pull-down resistors and bidirectional buffers.
The expected output value must be set to high impedance (Z) or don’t care (X) when the output pins of 3-state output
buffers and bidirectional buffers with on-chip pull-up/pull-down resistors are not active.
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7.3 Oscillator
7.3.1 Configuration of oscillator
Three types of dedicated oscillator blocks are provided for configuring an oscillator: one using external feedback
resistors, one using internal feedback resistors, and one that includes an oscillation stop function. An oscillator can
be configured using any of these blocks simply by connecting a resonator, capacitor, and limiting resistor to the external
pins. Note that the maximum number of dedicated oscillator blocks that can be used is two (three or more blocks
are not supportable). When two blocks are used, be sure to place the blocks at opposite polarity to prevent mutual
interference, and design so that each circuit operates on a separate clock. If it is necessary to use more than one
block, contact NEC.
In addition, do not use the clock generated by the oscillator on the both rising and falling edges.
The recommended oscillation frequency range and the combination of blocks for oscillator configuration are shown
in Table 7-1.
For the configuration of an oscillator block whose placement is restricted, refer to APPENDIX G PINS ASSIGNABLE
TO OSCILLATOR at the back of the manual. When using an oscillator block that includes a stop function, be sure
to control stopping the oscillator from an external source. Note that although there is no restriction on the placement
of the stop control pin, it should be placed as close as possible to the oscillator block.
Table 7-1. Recommended Oscillation Frequency Range and Configuration
Feedback Resistor
Stop Function
Configuration
External
No
OSI4
OSO9
MHz band
No
No
OSI1
OSO1
MHz band
Yes
Yes
OSI2
OSO7
Input
1 MΩ
Internal
Frequency
Placement Restrictions
Output
Figure 7-2. Example of Oscillator Configuration
VDD
Input A
(VI)
Resonator
Rd Output B
(VO)
CIN
Inside
LSI
chip
COUT
Output C
Remark Evaluation using an evaluation sample (ES or CS) is required to determine capacitors CIN and COUT,
limiting resistor Rd, and power consumption.
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7.3.2 Description of oscillator
Describe as follows when using an oscillator.
Figure 7-3. Oscillator Configuration (1/2)
(a) OSI1 + OSO1
CIN
XT1
Input pin
Rf
O
OSI1
COUT
I1
XT2
Output pin
O2
To internal circuit
OSO1
(b) OSI4 + OSO9
CIN
XT1
Input pin
Rf
O
OSI4
COUT
XT2
Output pin
I1
O2
To internal circuit
OSO9
Remark When using OSO9, an external feedback resistor with a value of 1 MΩ, Rf , is required.
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Figure 7-3. Oscillator Configuration (2/2)
(c) OSI2 + OSO7
Stop control pin
Input buffer
CIN
XT1 EN
Input pin
Rf
O
OSI2
COUT
XT2
Output pin
I1
EN
O2
To internal circuit
OSO7
Caution The input pin (XT1) must be set to high level when oscillation is stopped.
Remark The output of O2 is low level when oscillation is stopped. The equivalent circuits and truth tables of OSI2
and OSO7 are shown below.
OSI2 Equivalent Circuit
OSI2 Truth Table
VDD
S1
XT1
EN
N01
H01
O
XT1
EN
O
0
0
0
1
0
1
1
1
1
0
1
X
EN = H
EN = L
S1: close
S1: open
OSO7 Equivalent Circuit
EN
I1
O2
Use prohibited
H02
OSO7 Truth Table
H02
H01
N02
N01
XT2
I1
EN
XT2
O2
0
0
1
1
1
0
0
0
1
1
0
0
0
1
X
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Describe the test pattern of an oscillator as follows.
• Use the inverse of the pattern transmitted to the internal circuit as the input pattern of the input pin (XT1) of OSI1,
OSI2, and OSI4.
• Use the same pattern that was transmitted to the internal circuit as the output pattern of the output pin (XT2)
of OSO1, OSO7, and OSO9.
• Always input 0 to the stop control pin of OSO7 in the DC test pattern.
The pattern transmitted to the internal circuit and the pattern output to the output pin (XT2) of OSO1, OSO7, and
OSO9 is the inverted input pattern.
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7.3.3 Notes on configuring an oscillator
Because the CMOS-N5 gate array has an oscillation dedicated block, it can be used to configure an oscillator by
connecting a resonator and external constants outside the package. Although an oscillator can be easily configured,
certain differences from logic circuits must be noted because an oscillator is an analog circuit that operates at a high
frequency. In order for the oscillator to operate stably, it is necessary to optimize the external constants (input capacitor,
output capacitor, and limiting resistor). In addition, because the oscillator is an analog circuit, the following points must
also be noted.
<1> Place VDD and GND as follows around the oscillator pins (oscillator).
VDD
GND
OSOx
OSIx
block
block
pin
pin
VDD
GND
Remarks 1. Do not include the OSOx (oscillator) block pin as a target of the simultaneous operation review.
2. VDD and GND surrounding the oscillator pins can be used in the simultaneous operation review.
<2> Place the pins that may cause malfunction due to noise such as clock pins and reset pins as far as possible
from the oscillator pins.
<3> Output buffers are a source of noise, and so should be placed as far as possible from the oscillator pins
(oscillator).
<4> The following points must be noted regarding the printed circuit board.
• Place the input and output pins, and the resonator and external constants of the oscillator as close together
as possible, and keep the length of the wiring between them as short as possible.
• Keep the length of the wiring between the GND of the capacitors and of the gate array as short as possible.
Use as thick a wiring line as possible.
• Keep the leads of the resonator and capacitors as short as possible. Secure the resonator and capacitors
onto the printed circuit board to minimize the effects of mechanical vibration.
• Enclose the external constants in a GND pattern as far as possible.
Figure 7-4. Example of GND Pattern on Board
IC
Board
GND pattern
The following points must be noted during evaluation to determine the external constants.
• Use the printed circuit board that is to be actually used (because the oscillation operation range may fluctuate
due to the difference in the dielectric constant of the board).
• Check the external constants using a developed CMOS-N5 gate array (ES or CS) and the resonator to be actually
used.
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7.3.4 Constants of external circuit
An evaluation of the matching with the resonator is required to generate a clock signal. Table 7-2 shows an example
of the criteria for this evaluation. Determine the parameters to be measured through consultation with the resonator
manufacturer.
Table 7-2. Example of Criteria
Items to Be Measured
Determination Criteria
<1> Oscillation frequency
Frequency must be within accuracy of resonator
<2> Oscillation start voltage (V s)
2.0 V or less
<3> Oscillation hold voltage (Vh)
V h ≤ Vs
<4> Operation on power application
Check oscillation by repeatedly turning power on and off
<5> Current consumption
As low as possible
<6> Peak value of oscillated waveform
3.2 V ≤ VIH, V OH ≤ VDD
0 V ≤ VIL , VOL ≤ 1.3 V
<7> Duty factor
50% ±10%
Note that oscillation is evaluated with an ES or CS model. However, because all the gate array, resonator, and
external constants are subject to variations due to production and operating conditions, take these variations into
consideration during evaluation.
When evaluating parameters <4> through <7> above, fluctuations in the power supply and temperature of the gate
array must also be taken into consideration. Measure these parameters under the following MIN., TYP., and MAX.
conditions.
[Example] When fluctuations in power supply and temperature are taken into consideration:
TA = –40 to +85°C
VDD = 5 V ±10%
Measure these parameters under the following MIN., TYP., and MAX. conditions.
MIN.
TYP.
MAX.
TA (°C)
–40
25
+85
VDD (V)
5.5
5.0
4.5
Remark The values in this table indicate the conditions of the MIN., TYP., and MAX. values of the propagation
delay time (tPD) of the gate array, and do not refer to the MIN., TYP., and MAX. values of the oscillation
frequency of the resonator.
Table K-19 shows the resonators externally connected to OSO7 (OSO1) or OSO9, the recommended external
constants, and the circuit configuration. This data was evaluated in cooperation with each resonator manufacturer.
The circuit configuration is shown in Figure K-19. In addition, it is recommended to reduce the capacitance of the
system board (reduce the influence on C1 (CIN ) and C2 (COUT) as much as possible.
Caution If the frequency exceeds 40 MHz when using a resonator, be sure to contact NEC beforehand.
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7.4 Memory
The CMOS-N5 Family can be used to place memory blocks. This section explains the types of memory blocks
and the points to be noted in using the memory blocks.
7.4.1 Types of memory blocks
The types of memory blocks available in the CMOS-N5 Family are listed below.
• Single-port RAM
• Dual-port RAM
Lists of each memory block are provided in Table K-20. These memory blocks can also be mixed together.
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7.4.2 RAM blocks
As shown in Figures 7-5 and 7-6, the high-density RAMs of the CMOS-N5 Family have a bit/word architecture based
on basic macros (hard macros). The BIST (Built-In Self Test) circuit and on-chip selector are configured by soft macros.
This architecture eases restrictions on placement and routing, and reduces complexity when multiple RAMs are
incorporated.
The memory test is a test-dedicated macro, called BIST, that is incorporated in a soft macro. Three test pins
eliminate the trouble of directly testing the I/O of all the pins.
When using an NEC RAM, be sure to use an NEC standard test circuit (BIST).
Figure 7-5. Single-Port RAM Circuit Configuration
Selector circuit
DI
1
DI
0
AD
Basic macro
(Hard macro)
1
DO
DO
AD
0
WEB
1
WEB
0
Sel
REB
REB
CSB
TEB
TIN
CSB
Test circuit (BIST)
TEB
TD
TIN
TA
CD
TWE
TOUT
TOUT
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Figure 7-6. Dual-Port RAM Circuit Configuration
Selector circuit
DI
1
DI
0
WA
Basic macro
(Hard macro)
DO
DO
Selector circuit
1
1
WA
0
Sel
1
WEB
RA
RA
0
WEB
0
Sel
WSB
CSB
RSB
RSB
TEB
Test circuit (BIST)
TEB
TIN
TD
TIN
TA
CD
TWE
TOUT
TOUT
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7.5 Writing Memory Blocks
When writing memory blocks as circuit diagrams or connection data, bear in mind the following points.
7.5.1 Selecting memory blocks
The RAM blocks of the CMOS-N5 Family are configured as soft macros. Therefore, RAM blocks with any bit/word
configuration can be placed by combining the basic memory cells. However, the blocks that are used frequently are
registered in advance as simulation models (see CMOS-N5 Family Memory Block Library (A14683E)). Select the
block with the bit/word size closest to your needs from these models.
If a memory block with the desired size does not exist because the number of bits is exceeded, connect blocks
of the same word size with different bit size in parallel.
Conversely, if the number of words is exceeded, divide the addresses by creating a chip select signal with a decoder,
in the same manner as an ordinary memory circuit.
When using a memory with an unmatched number of bits and words, use soft macros in the way described above.
For the circuit configuration and test circuit (BIST) configuration, consult NEC.
7.5.2 Using memory blocks
Memory blocks, as with other function blocks, have specifications for fan-in (F/I) and fan-out (F/O); see the CMOSN5 Family Memory Block Library (A14683E). The blocks must be connected without exceeding restrictions such
as the limit on the number of fan-outs.
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7.6 Memory Test
7.6.1 RAM test
Because the RAM block of the CMOS-N5 Family employs BIST, the limits on the number of test patterns is relaxed,
so that the user can easily check the memory.
BIST consists of signal generators for test signals including test address, test data, and test enable, as well as an
expected value generator, and a comparator, as shown in Figure 7-7. The user simply needs to connect the three
pins, TIN, TEB, and TOUT, to external pins to test a RAM. When placing two or more RAM blocks, the test inputs (TIN
and TEB) can be shared with the respective pins of the other RAM blocks. The test output (TOUT), however, cannot
be shared. Connect the test output to different external pins. Figure 7-8 shows a connection example.
To test RAM, basically, data is applied from an external input pin to a test input pin (TIN or TEB), and a test output
(TOUT) extracted from an external pin. If the signal is inverted or a clock is necessary because an inverter or flipflop is used, the basic test pattern cannot be used. The final state of the user’s test pattern must be in a state in which
the test can be conducted (a state in which TIN, TOUT, and TEB can transfer the RAM test signal from external pins).
The RAM test pattern is prepared by NEC.
Figure 7-7. Test Circuit (BIST) Block Diagram
TA
TIN
TEB
Address
generator
Timing
generator
TD
Write data
generator
Expected value
exD
generator
Comparator
TOUT
CD
(RAM output)
WEB generator
TWE
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Figure 7-8. RAM Test Circuits (1/2)
(a) Connection example for placing one RAM block
Internal gate
DIn
ADm
DOn
TOUT
WEB
REB
FI01
TEB
CSB
TEB
TIN
FI01
TIN
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FO01
TOUT
CHAPTER 7 MULTIFUNCTION BLOCKS
Figure 7-8. RAM Test Circuits (2/2)
(b) Connection example for placing multiple RAM blocks
FI01
FO01
TEB
TEB
TOUT
TIN
T01
FI01
TIN
FO01
TEB
TOUT
T02
⋅⋅⋅
TIN
FO01
TEB
TIN
TOUT
T0 (n – 1)
FO01
TEB
TIN
TOUT
T0n
(1) Be sure to use one TEB input and TIN input. Connect each input to the respective RAM. Even if the capacitance
of the RAM block differs, be sure to use one TEB input and TIN input commonly as shown in the figure.
(2) The TOUT pins must be made independent and must be output to external pins.
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7.6.2 Assigning test I/O pins (TIN, TEB, and TOUT)
(1) When there are unused pins
If there are unused pins, excluding power supply pins and NC pins, they can be used for testing.
(2) When there are no unused pins
Pins used for logic can also be used as test pins. The points noted below must be considered when making
pins alternate-function. Note that the TEB pin is a dedicated pin, therefore it cannot be used for other functions.
<1> Making the TIN pin alternate-function
The TIN pin can be used as a normal input pin and a normal output pin. To use as a normal output pin,
the TEB signal must be made an enable signal and the pin must be made bidirectional. The pin then
can be used as an output pin during normal usage and as an input pin during testing. Figure 7-9 shows
a connection example.
<2> Making the TOUT pin alternate-function
The TOUT pin can be used as a normal input pin and a normal output pin. To use as a normal input pin,
the TEB signal must be made an enable signal and the pin must be made bidirectional. The pin then
can be used as an input pin during normal usage and as an output pin during testing. To use as a normal
output pin, it can be used in combination with an internal selector circuit, and the pin can be switched
by the TEB signal. Figure 7-10 shows a connection example.
Caution Pins used for the GTL interface buffer, N-ch open-drain buffer, and CMOS 5 V withstand
voltage buffer cannot be made alternate-function pins.
• Handling pins on the board
Handle each pin using one of the following procedures.
<1> TEB pinNote 1: • Use a pull-up buffer
• Pull up externally
• Externally connect to VDD
<2> TIN pinNote 2:
• Use a pull-up buffer
• Use a pull-down buffer
• Externally connect to VDD
• Externally connect to GND
Notes 1. Handle in the direction that is not the test mode.
2. When not alternatively used as a normal pin
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Figure 7-9. Making TIN Pin Alternate Function
(a) Alternate-function use with normal input pin
(b) Alternate-function use with normal output pin
(bidirectional pin)
Internal gate
Internal gate
TIN
TIN
TEB
Figure 7-10. Making TOUT Pin Alternate Function
(a) Alternate-function use with normal input pin
(b) Alternate-function use with normal output pin
(bidirectional pin)
Internal gate
Internal gate
TOUT
TOUT
TEB
TEB
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D0 Y
D1
A
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CHAPTER 7 MULTIFUNCTION BLOCKS
7.6.3 Checking connection of RAM test circuit
Whether the BIST circuit is correctly connected is checked by the RAMCHK flow on OPENCAD. The RAMCHK
flow automatically generates connection checking patterns (8 patterns) as shown in Figure 7-11, and is appended
to the end of the user’s test pattern (test pattern for DC checkNote) to check the connection. Be sure to implement
this RAMCHK flow before interfacing the test pattern to NEC.
Make sure that the pin signals necessary for BIST (TEB, TIN, TOUTx) can be directly input/output from an external
source at the end of the test pattern (test pattern for DC checkNote). A RAM-BIST pattern for a tester is available from
NEC and does not have to be created by the user.
Note If the DC pattern is independent, that DC pattern is indicated.
Figure 7-11. Example of Test Patterns
Valid input value
Input other than RAM test
Store final value
TEB
TIN
TOUT
“X” (don't care)
TOUT2
“X” (don't care)
TOUT3
“X” (don't care)
Several TOUT outputs of
the RAM are output to
the external pin.
(All the expected output
values are the same.)
“X” (don't care)
Other output
1
User test patterns
2
3
4
5
6
7
8
Test patterns for verification of
RAM test circuit connection
Remark Input other than RAM test: Input 8 pattern signals so as to hold the final value of the user’s test pattern.
TEB:
Set low level and input eight patterns.
TIN:
Input eight patterns of repetitive 01 signals.
TOUT:
Set the expected output value to 01000100. When multiple RAMs are
placed, the number of TOUT pins equal to the number of RAMs must be
output to external pins (the RAM tests are executed completely in parallel).
Other outputs:
218
Set the expected output value to X (don’t care).
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CHAPTER 7 MULTIFUNCTION BLOCKS
7.7 Scan Path Test Block
It is extremely difficult to generate a test pattern that checks the operation of an LSI efficiently with a circuit frequently
using flip-flops and with a deep logical depth. Scan path testing can change the connections of all the internal flipflops of an LSI like shift registers. Therefore, the circuit can be tested efficiently by easily initializing all the flip-flops
of a circuit with a deep logical depth and reading all the flip-flop states in a certain state.
For details, see Design For Test User’s Manual (A14357E).
Figure 7-12. Theory of Scan Path Test Method
SIN
SMC
I1
F/F
1
I2
F/F
j+1
O1
I3
Combination
circuit A
F/F
2
Combination
circuit B
F/F
j
In
F/F
j+2
F/F
k
SCK
Remark In:
On:
O2
Combination
circuit C
On
SOT
Input signal when testing a combination circuit, or normal input
Diagnostic output when testing a combination circuit, or normal output
SIN: Input signal when testing a sequential circuit
SMC: Mode switching signal
SCK: Test clock
SOT: Diagnostic output when testing a sequential circuit
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APPENDIX A POWER CONSUMPTION (PRELIMINARY)
An accurate calculation of the power consumption of internal circuits requires a very large amount of data, such
as the capacitance, the number of synchronously operating blocks, and the operating frequency of each block.
Consequently, the calculation becomes too complicated to be performed. On the basis of assumptions concerning
such items as circuit operation and configuration, NEC provides reference values for power consumption. It must
be noted that these values may be larger or smaller than the actual values, depending on factors such as the user’s
actual circuit and its configuration.
This chapter provides a power consumption calculation method that divides the power consumption of the internal
circuit into combination circuits, latches, flip-flops. This calculation should be used to review circuit power
consumption. However, if the results are to be used to calculate the life-span of a battery, an extra margin should
be provided.
Internal cell power consumption
Σ P DCELL = Σ PDGate + Σ PDLatch + Σ PDF/F + Σ P DT
(1) Combination circuits
PDGate = 6.73 × f × Cell (µw)
f:
Data operating frequency
CellNote: Number of cells that operate at f
Note
“Cell” is not the number of blocks.
(2) Latches
PDLatch = (PD(Gate = ON) × N + P D(Gate = OFF) × (1 – N)) × f × Cell (µ W)
PD(Gate = ON): 3.43 (µW/Cell/MHz)
Gate ON rate =
N:
T(Gate = ON)
T(Gate = ON) + T(Gate = OFF)
PD(Gate = OFF) : 0.23 (µW/Cell/MHz)
f:
Data operating frequency
CellNote:
Number of cells that operate at f
Note
220
“Cell” is not the number of blocks.
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APPENDIX A POWER CONSUMPTION (PRELIMINARY)
(3) D-F/F, JK-F/F, shift registers, and counters
2 × PD(OUTPUT) + PD(CLK) × (N – 2)
PDF/F =
N
× f × Cell (µW)
PD(OUTPUT) : 1.19 (µW/Cell/MHz)
0.68 (µW/Cell/MHz)
PD(CLK):
T(DATA)
N:
T (CLK)
T(DATA) :
Data cycle
T(CLK) :
Clock cycle
f:
Clock operating frequency
CellNote:
Number of cells that operate at f
Example The following indicates the case when the clock has a cycle speed double that of 1 data cycle.
N = 1/0.5 = 2
Note
“Cell” is not the number of blocks.
(4) T-F/F
PDT = 3.8 × f × Cell ( µ W)
f:
Clock operating frequency
CellNote: Number of cells that operate at f
Note
“Cell” is not the number of blocks.
(5) Load dependency of power consumption (preliminary)
The power consumption depends to a great extent on the load capacitance, as expressed by
PD = CV2f
Figure A-1. Load Dependency of Power Consumption
Under study
The unit power consumption when F/O = 2 is an extremely small 3 µ W/MHz. Because power consumption has a
significant effect on reliability, a realistic value must be used.
The value covers a distribution of about 70% of load values, based on statistical data accumulated at NEC, such
as wiring length and pin pairs.
Load =
(F/I equivalent)
Example
F/O : +
:
(Under study)
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APPENDIX B PROPAGATION DELAY TIME
The delay time of each block varies significantly with the input signal waveform as shown in Figure B-1. With the
CMOS-N5 Family whose delay time is as short as several 100 ps at each block, the influence of the input waveform
is not negligible.
Figure B-1. Delay Time Increase Due to Input Waveform
tr/t f (MIN) < t r/tf (TYP) < tr/t f (MAX)
tr/tf (MAX)
tr/tf (TYP)
Delay time
tr/tf (MIN)
Output load
Consequently, the simulator considers the input waveform of each block so that a highly accurate delay simulation
is executed. However, discrepancies in results due to the input waveform cannot be listed in the block libraryNote.
For this reason, the accuracy of the propagation delay time calculations listed in the block libraryNote are valid only
under certain limited conditions. The propagation delay times of critical paths, in which the load is likely to be light,
are calculated accurately in the CMOS-N5 Family.
Note that Figure B-1 is indicating a tendency only. Verify the actual value by performing simulation.
Note
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CMOS-N5 Family Block Library (A13872E)
Design Manual A13826EJ6V0DM
APPENDIX C ALBATROSS AND DIF FILE FORMATS
C.1 ALBATROSS File Format (Circuit Name.alb)
(1) File format
The ALBATROSS file format has the following restrictions:
• Free format
• Parameters must be separated by blank space or a colon (:).
• Each statement must be terminated with a semicolon (;).
• Items within quotes (“ ”) can be repeated.
• Maximum of 80 columns per line (when the last character is not a semicolon, the line must continue on the
next line)
• Identifiers, pin names, and units (NS fixed) must be specified in uppercase letters
• Pin names consist of a maximum of 64 characters
• The description of the timing data (MODULATION + CLOCK) is based on the limitations shown in 6.6 HighSpeed Function Test (Real-Time Test).
(2) File configuration
The ALBATROSS file consists of the following seven parameters.
*ALBATROSS
...
File header
*TIMING
...
Header
PERIOD
...
Pattern period
MODULATION
...
Input skew
CLOCK
...
Clock pin
*END_OF_TIMING ...
End record
*END
File end
...
(3) Details of file
The details of each parameter are as follows:
(a) File header
Syntax:
*ALBATROSS circuit;
Function: Pattern header
1: circuit (character string) circuit name
(b) Header
Syntax:
*TIMING
Function: Header
(c) Pattern period
Syntax:
PERIOD period_t time_unit;
Function: Period value of pattern
1: period_t
Pattern cycle
2: time_unit
Cycle unit
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APPENDIX C ALBATROSS AND DIF FILE FORMATS
(d) Input skew
Syntax:
MODULATION modulation_t time_unit: “pin”;
Function: Value of skew added to input pin
1: modulation_t
Value of input skew
2: time_unit
Unit of value of skew
3: pin
Pin name
(e) Clock
Syntax:
CLOCK TYPE = type: “ch_time time_unit”: pin;
Function: Definition of clock pin and clock waveform
• TYPE = type
P: Positive clock
N: Negative clock
(f)
• ch_time
Waveform time
• time_unit
Unit of change time
• pin
Pin name
End
Syntax:
*END_OF_TIMING;
Function: End
(g) File end
Syntax:
*END
Function: File end
(4) Example
*ALBATROSS CF191
*TIMING;
PERIOD 200 NS;
MODULATION 20 NS: IN1 IN2 IN3;
CLOCK TYPE = P: 50NS 150NS: CLK;
*END_OF_TIMING;
*END
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Design Manual A13826EJ6V0DM
APPENDIX C ALBATROSS AND DIF FILE FORMATS
C.2 DIF File Format (Circuit Name.dif)
(1) File format
The DIF file format has the following restrictions:
• Free format
• The delimiter is a blank space.
• Maximum of 512 characters per line
• The first column of a comment line begins with “-”.
(2) File configuration
The DIF file consists of the following three parameters:
DIF
.... Header
/DESIGN .... Design block
/END
.... End
(3) Details of file
The details of each parameter are as follows:
(a) Header
Syntax:
DIF
Function: Header
(b) Design block
Syntax:
/PIA
Function: All external pins (V DD, GND, etc.)
(c) Condition block
Syntax:
/PIN
Function: Overall design (such as value of pin capacitance
added to output pin)
(d) End card
Syntax:
/END
Function: Termination of DIF file
(4) Example
DIF
/DESIGN VIS3
/PIA
IN1 PAD = 3;
IN2 PAD = 4;
/PIN
OUT1 DIR = OUTPUT
CMIN = 18 CTYP = 15 CMAX = 60;
/END
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APPENDIX D DRAWING CIRCUIT DIAGRAMS AND TIMING CHARTS
D.1 Drawing Circuit Diagrams
Today circuits are designed using an engineering workstation (EWS). The circuit diagram drawn by the user is
converted to NEC format on the EWS or through the interface service offered by NEC.
When the user draws a circuit diagram, the following points should be kept in mind to ensure smooth interfacing
with NEC.
D.1.1 Logic symbols
As a general rule, use the logic symbols that are in the block libraryNote. However, when there are differences
between the EWS library and the block libraryNote, follow the format of the EWS library.
Note
CMOS-N5 Family Block Library (A13872E)
D.1.2 Block names (function names)
Input buffers and other blocks have different designations, but may have logic symbols that are virtually the same.
In particular, the various input/output buffer interface levels cannot be determined from simulation results. Because
of this, the block name should be entered so that it is easily understood.
In addition, since block names are displayed in advance in EWS libraries, entries do not have to be made when
using the EWS.
D.1.3 Pin names (I/O pin name of block)
Block I/O pins are named in the order “H01, H02,.../N01, N02,....” If a block has more than one I/O pin, the pin names
must be used whenever possible.
Pin names are usually displayed in EWS libraries. If a pin name is displayed, it does not have to be entered. For
more information on displaying pin names, follow the instructions in the interface manual for the EWS.
D.1.4 Gate names (specific name of each block)
Enter the respective characteristic gate names for block names entered in a circuit diagram. A gate name must
consist of no more than 255 alphanumeric characters. To avoid duplication of gate names and pin names, make the
names unique.
When an EWS is used, there are special cases where the naming rules are a function of the system being employed.
For details, follow the instructions in the interface manual for the EWS.
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Design Manual A13826EJ6V0DM
APPENDIX D DRAWING CIRCUIT DIAGRAMS AND TIMING CHARTS
D.1.5 I/O pin names
A pin name of up to 64 alphanumeric characters must be assigned to each I/O pin of the LSI device. Each pin name
must be unique and must not duplicate a gate name.
When an EWS is used, there are special cases where the naming rules are a function of the system being employed.
For details, follow the instructions in the interface manual for the EWS.
Figure D-1. Circuit Diagram Example
IN1
N01
TST
FI01
NR01
F204
CLMP
H02
FF01
S N01
D
Q
F091
C QB
R
F614
IN2
RST
D
S
FF02
N01
Q
C QB
R
F614
FF03
S
N01
D
Q
C QB
R
F614
OB01
OUT
FO01
FI01
CLK
FI01
IN3
(1) Input pin names
The pin name of an input pin must consist of 1 to 64 alphanumeric characters.
In addition, undefined and high impedance states cannot be input to an input pin because this causes the
measurement conditions to change during testing with the LSI tester, making measurement impossible. Undefined
and high impedance states also cannot be input to the input pins of input buffers and bidirectional buffers with
on-chip pull-up/pull-down resistors.
If undefined or high impedance states are input as a test pattern, an error will result when executing simulation.
Design Manual A13826EJ6V0DM
227
APPENDIX D DRAWING CIRCUIT DIAGRAMS AND TIMING CHARTS
(2) Bidirectional pin names
If the input and output of a bidirectional buffer are implemented from one pin, this must be named by using
a bidirectional pin. The pin name must consist of 1 to 64 alphanumeric characters.
Figure D-2. Bidirectional Pin Names
Input signal
Output signal
Bidirectional pin
Control signal
When a bidirectional pin test pattern is generated, care must be taken with regard to the following points:
<1> For switching from the output mode to the input mode, set the input and output signals to the same level.
<2> Do not set the control signal to the undefined state (if the state of the control signal becomes undefined,
an undefined state is propagated to the input signal, generating an error in simulation).
During switching from the input mode to the output mode, an undefined state is propagated to the input signal
due to the delay time of the control signal, generating an error in simulation. For such switching, it is important
to configure the circuit so that an undefined state is not propagated to the input signal (see 6.3.6 Notes on
switching I/O mode of bidirectional pin).
Figure D-3. Bidirectional Pin Test Pattern Generation
Control signal
Expected value
(Input)
228
(Output)
Design Manual A13826EJ6V0DM
(Input)
APPENDIX D DRAWING CIRCUIT DIAGRAMS AND TIMING CHARTS
(3) 3-state output pin description
A 3-state output pin must be named as shown in the example in Figure D-4. The pin name must consist of
1 to 64 alphanumeric characters.
Figure D-4. 3-State Output Pin Names
Output pin
Output pin
Control signal
Figure D-5. 3-State Output Pin Test Pattern Generation
High impedance
Output pin
(Output)
Design Manual A13826EJ6V0DM
229
APPENDIX D DRAWING CIRCUIT DIAGRAMS AND TIMING CHARTS
D.2 Handling Macros
The logic of a large-scale circuit is often designed using hierarchical techniques to enable block design in a system
and to diversify the man-hours needed for design.
In the hierarchical design technique, functional units used in common are defined as macros (user macros). Each
LSI chip is designed by connecting several macros to enable a specified function. In particular, a large-scale circuit
is usually divided into several blocks, each of which is a hierarchical block and combined to configure the entire circuit.
When designing hierarchical circuits, note the following guidelines (see Figure D-6).
<1> Each hierarchical block should perform a single logical operation.
<2> Make the design in a way that the total structure and the signal flow can be understood at the top level hierarchy
(the top level hierarchy should be drawn on a single page).
<3> Whenever possible, design circuits that comprise a closed loop so that the loop fits within the macro.
<4> Input pins and clamps (if needed) must be on the same page.
<5> Note should be taken of the clock line flow. Ensure that delay differentials between pages do not exceed basic
rules.
<6> Each macro (bottom hierarchy) must have a single function.
<7> A page should not contain signal lines only (pass-through only).
<8> External I/O buffers can be specified only at the top level hierarchy. Avoid connecting I/O pins directly to an
external device from a lower macro other than that at the top level hierarchy.
<9> A macro should not contain input, output, and bidirectional buffers.
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Design Manual A13826EJ6V0DM
APPENDIX D DRAWING CIRCUIT DIAGRAMS AND TIMING CHARTS
Figure D-6. Handling Macros
(a) Good example
(b) Bad example
Top level hierarchy
Top level hierarchy
LSI
LSI
Input pin
Input pin
Macro
Macro
Input
buffer
Output
buffer
Input pin
Input buffer
Output pin
Output pin
Input pin
Input buffer
First level hierarchy
Output buffer
First level hierarchy
Design Manual A13826EJ6V0DM
231
APPENDIX D DRAWING CIRCUIT DIAGRAMS AND TIMING CHARTS
D.3 Preparing Timing Charts
If the user provides NEC with a timing chart for generating the test patterns, or even if the user generates the test
patterns, the timing charts must be drawn using the guidelines explained in this section.
(1) Entry method
The pin names of all I/O pins must be written in the vertical column. For each pattern, apply 1 or 0 level for
inputs and the expected values for outputs. Continuous sequential numbers, starting with 1, must be assigned
to the test patterns.
Figure D-7 shows an example of filling out the timing chart.
Figure D-7. Timing Chart Entry
Pin Name
1
2
3
4
5
6
7
CLK
DATA
OUT
(2) Timing discrepancies
Because the output in actual circuits changes after the input pattern is applied, there is a timing delay between
the input and output, as shown in Figure D-8 (a). However, the delay time between the input and output can
be ignored when test patterns are generated, as shown in Figure D-8 (b). The patterns must be generated
so that the entire circuit operates at the same timing.
Figure D-8. Timing Chart Example
(a) Actual circuit
(b) Timing chart entry
(Test pattern entry)
232
Input
Input
Output
Output
Design Manual A13826EJ6V0DM
APPENDIX D DRAWING CIRCUIT DIAGRAMS AND TIMING CHARTS
(3) Handling of “X” (undefined or don’t care)
Depending on the configuration of the circuit, the value of an output pin may not be determined in the first few
patterns. In that case, specify “X” (undefined) as the expected value of the output pin. When specifying “don’t
care” in cases where, due to the operation of the circuit it cannot be determined whether the value will become
“1” or “0”, only specify “X” as the expected output value during the corresponding period. In this case, the
expected value will not be collated.
However, do not specify “X” for the input pin. If “X” is inadvertently specified for the input pin, an error will occur
during simulation. If the input level of a certain period can be either high level or low level, specify either “1”
or “0”.
(4) Handling of “Z” (high impedance)
The output pins of a 3-state output buffer or a bidirectional buffer may become high impedance “Z” in some
cases. In these cases, specify “Z” as the expected output value.
However, do not specify “Z” for the input pin. If “Z” is inadvertently specified for the input pin, an error will occur
during simulation.
(5) Repeated pattern
When the same waveform is repeatedly input, such as in clock input, it can be efficiently input as a repeated
pattern.
(6) Specifying critical path
In terms of system design, signal paths in which speed (the delay time between input and output) is especially
important and paths in which the propagation delay time between input and output must be within a certain
period, can be specified so that they satisfy the required performance, if clarified at the time of design.
If this is the case, specify the corresponding paths as critical paths. Critical paths include the following three
types:
• Maximum delay time (tPD) as an absolute value (MAX.)
• Minimum delay time (tPD) as an absolute value (MIN.)
• Relative variable range between the paths
Specification of a critical path can be effective only for the delay time between input and output. A maximum
of six paths can be specified as critical paths.
Entry example
Mode No.
Assigned Pin
Output Load
Pattern No.
(pF)
1
1
IN1 → OUT2
15
131
Delay Time (ns) Determination
MIN.
MAX.
13
50
2
3
4
5
6
Design Manual A13826EJ6V0DM
233
APPENDIX E LIST OF BLOCKS
Blocks marked with
cannot be used with 3 V and 3.3 V Master.
E.1 Interface Block
E.1.1 CMOS Level
Function
Input Buffer
Input Buffer with Failsafe
Input Buffer with EN(AND)
Input Buffer with EN(OR)
Output Buffer
Low-noise Output Buffer
234
Block
Description
Cells (I/O)
FI01
—
3 (1)
FID1
50kΩ Pull-down
3 (1)
FIU1
5kΩ Pull-up
3 (1)
FIW1
5kΩ Pull-up
3 (1)
FIS1W
Schmitt
6 (1)
FDS1W
Schmitt 50kΩ Pull-down
6 (1)
FUS1W
Schmitt 50kΩ Pull-up
6 (1)
FWS1W
Schmitt 50kΩ Pull-up
6 (1)
FIA1
—
3 (1)
FDA1
50kΩ Pull-down
3 (1)
FIE1W
Schmitt
6 (1)
FDE1W
Schmitt 50kΩ Pull-down
6 (1)
FN11
—
6 (1)
FN21
50kΩ Pull-down
6 (1)
FN13
—
4 (1)
FN23
50kΩ Pull-down
4 (1)
FO09
3mA
4 (1)
FO04
6mA
4 (1)
FO01
9mA
4 (1)
FO02
12mA
12 (1)
FO03
18mA
12 (1)
FO06
24mA
12 (1)
FE09
3mA
5 (1)
FE04
6mA
5 (1)
FE01
9mA
5 (1)
FE02
12mA
5 (1)
FE03
18mA
5 (1)
FE06
24mA
5 (1)
Design Manual A13826EJ6V0DM
APPENDIX E LIST OF BLOCKS
Function
3-State Buffer
Block
Description
Cells (I/O)
B00T
3mA
7 (1)
B0DT
3mA 50kΩ Pull-down
7 (1)
B0UT
3mA 50kΩ Pull-up
7 (1)
B0WT
3mA 5kΩ Pull-up
7 (1)
B00E
6mA
7 (1)
B0DE
6mA 50kΩ Pull-down
7 (1)
B0UE
6mA 50kΩ Pull-up
7 (1)
B0WE
6mA 5kΩ Pull-up
7 (1)
B008
9mA
7 (1)
B0D8
9mA 50kΩ Pull-down
7 (1)
B0U8
9mA 50kΩ Pull-up
7 (1)
B0W8
9mA 5kΩ Pull-up
7 (1)
B007
12mA
17 (1)
B0D7
12mA 50kΩ Pull-down
17 (1)
B0U7
12mA 50kΩ Pull-up
17 (1)
B0W7
12mA 5kΩ Pull-up
17 (1)
B009
18mA
17 (1)
B0D9
18mA 50kΩ Pull-down
17 (1)
B0U9
18mA 50kΩ Pull-up
17 (1)
B0W9
18mA 5kΩ Pull-up
17 (1)
B00H
24mA
17 (1)
B0DH
24mA 50kΩ Pull-down
17 (1)
B0UH
24mA 50kΩ Pull-up
17 (1)
B0WH
24mA 5kΩ Pull-up
17 (1)
Design Manual A13826EJ6V0DM
235
APPENDIX E LIST OF BLOCKS
Function
Low-noise 3-State Buffer
N-ch Open drain Buffer
N-ch Open drain Buffer with Failsafe
236
Block
Description
Cells (I/O)
BE0T
3mA
7 (1)
BEDT
3mA 50kΩ Pull-down
7 (1)
BEUT
3mA 50kΩ Pull-up
7 (1)
BEWT
3mA 5kΩ Pull-up
7 (1)
BE0E
6mA
7 (1)
BEDE
6mA 50kΩ Pull-down
7 (1)
BEUE
6mA 50kΩ Pull-up
7 (1)
BEWE
6mA 5kΩ Pull-up
7 (1)
BE08
9mA
7 (1)
BED8
9mA 50kΩ Pull-down
7 (1)
BEU8
9mA 50kΩ Pull-up
7 (1)
BEW8
9mA 5kΩ Pull-up
7 (1)
BE07
12mA
7 (1)
BED7
12mA 50kΩ Pull-down
7 (1)
BEU7
12mA 50kΩ Pull-up
7 (1)
BEW7
12mA 5kΩ Pull-up
7 (1)
BE09
18mA
7 (1)
BED9
18mA 50kΩ Pull-down
7 (1)
BEU9
18mA 50kΩ Pull-up
7 (1)
BEW9
18mA 5kΩ Pull-up
7 (1)
BE0H
24mA
7 (1)
BEDH
24mA 50kΩ Pull-down
7 (1)
BEUH
24mA 50kΩ Pull-up
7 (1)
BEWH
24mA 5kΩ Pull-up
7 (1)
EXT1
9mA
4 (1)
EXT3
9mA 50kΩ Pull-up
4 (1)
EXW3
9mA 5kΩ Pull-up
4 (1)
EXT9
12mA
4 (1)
EXTB
12mA 50kΩ Pull-up
4 (1)
EXWB
12mA 5kΩ Pull-up
4 (1)
EXT5
18mA
4 (1)
EXT7
18mA 50kΩ Pull-up
4 (1)
EXW7
18mA 5kΩ Pull-up
4 (1)
EXTD
24mA
4 (1)
EXTF
24mA 50kΩ Pull-up
4 (1)
EXWF
24mA 5kΩ Pull-up
4 (1)
EXO1
9mA
4 (1)
EXO9
12mA
4 (1)
EXO5
18mA
4 (1)
EXOD
24mA
4 (1)
Design Manual A13826EJ6V0DM
APPENDIX E LIST OF BLOCKS
Function
I/O Buffer
Block
Description
Cells (I/O)
B00U
3mA
10 (1)
B0DU
3mA 50kΩ Pull-down
10 (1)
B0UU
3mA 50kΩ Pull-up
10 (1)
B0WU
3mA 5kΩ Pull-up
10 (1)
B00C
6mA
10 (1)
B0DC
6mA 50kΩ Pull-down
10 (1)
B0UC
6mA 50kΩ Pull-up
10 (1)
B0WC
6mA 5kΩ Pull-up
10 (1)
B003
9mA
10 (1)
B0D3
9mA 50kΩ Pull-down
10 (1)
B0U3
9mA 50kΩ Pull-up
10 (1)
B0W3
9mA 5kΩ Pull-up
10 (1)
B001
12mA
20 (1)
B0D1
12mA 50kΩ Pull-down
20 (1)
B0U1
12mA 50kΩ Pull-up
20 (1)
B0W1
12mA 5kΩ Pull-up
20 (1)
B005
18mA
20 (1)
B0D5
18mA 50kΩ Pull-down
20 (1)
B0U5
18mA 50kΩ Pull-up
20 (1)
B0W5
18mA 5kΩ Pull-up
20 (1)
B00F
24mA
20 (1)
B0DF
24mA 50kΩ Pull-down
20 (1)
B0UF
24mA 50kΩ Pull-up
20 (1)
B0WF
24mA 5kΩ Pull-up
20 (1)
Design Manual A13826EJ6V0DM
237
APPENDIX E LIST OF BLOCKS
Function
Low-noise I/O Buffer
238
Block
Description
Cells (I/O)
BE0U
3mA
10 (1)
BEDU
3mA 50kΩ Pull-down
10 (1)
BEUU
3mA 50kΩ Pull-up
10 (1)
BEWU
3mA 5kΩ Pull-up
10 (1)
BE0C
6mA
10 (1)
BEDC
6mA 50kΩ Pull-down
10 (1)
BEUC
6mA 50kΩ Pull-up
10 (1)
BEWC
6mA 5kΩ Pull-up
10 (1)
BE03
9mA
10 (1)
BED3
9mA 50kΩ Pull-down
10 (1)
BEU3
9mA 50kΩ Pull-up
10 (1)
BEW3
9mA 5kΩ Pull-up
10 (1)
BE01
12mA
10 (1)
BED1
12mA 50kΩ Pull-down
10 (1)
BEU1
12mA 50kΩ Pull-up
10 (1)
BEW1
12mA 5kΩ Pull-up
10 (1)
BE05
18mA
10 (1)
BED5
18mA 50kΩ Pull-down
10 (1)
BEU5
18mA 50kΩ Pull-up
10 (1)
BEW5
18mA 5kΩ Pull-up
10 (1)
BE0F
24mA
10 (1)
BEDF
24mA 50kΩ Pull-down
10 (1)
BEUF
24mA 50kΩ Pull-up
10 (1)
BEWF
24mA 5kΩ Pull-up
10 (1)
Design Manual A13826EJ6V0DM
APPENDIX E LIST OF BLOCKS
Function
Schmitt I/O Buffer
Block
Description
Cells (I/O)
BSIUW
3mA
13 (1)
BSDUW
3mA 50kΩ Pull-down
13 (1)
BSUUW
3mA 50kΩ Pull-up
13 (1)
BSWUW
3mA 5kΩ Pull-up
13 (1)
BSICW
6mA
13 (1)
BSDCW
6mA 50kΩ Pull-down
13 (1)
BSUCW
6mA 50kΩ Pull-up
13 (1)
BSWCW
6mA 5kΩ Pull-up
13 (1)
BSI3W
9mA
13 (1)
BSD3W
9mA 50kΩ Pull-down
13 (1)
BSU3W
9mA 50kΩ Pull-up
13 (1)
BSW3W
9mA 5kΩ Pull-up
13 (1)
BSI1W
12mA
23 (1)
BSD1W
12mA 50kΩ Pull-down
23 (1)
BSU1W
12mA 50kΩ Pull-up
23 (1)
BSW1W
12mA 5kΩ Pull-up
23 (1)
BSI5W
18mA
23 (1)
BSD5W
18mA 50kΩ Pull-down
23 (1)
BSU5W
18mA 50kΩ Pull-up
23 (1)
BSW5W
18mA 5kΩ Pull-up
23 (1)
BSIFW
24mA
23 (1)
BSDFW
24mA 50kΩ Pull-down
23 (1)
BSUFW
24mA 50kΩ Pull-up
23 (1)
BSWFW
24mA 5kΩ Pull-up
23 (1)
Design Manual A13826EJ6V0DM
239
APPENDIX E LIST OF BLOCKS
Function
Low-noise Schmitt I/O Buffer
I/O Buffer with EN(AND)
240
Block
Description
Cells (I/O)
BFIUW
3mA
13 (1)
BFDUW
3mA 50kΩ Pull-down
13 (1)
BFUUW
3mA 50kΩ Pull-up
13 (1)
BFWUW
3mA 5kΩ Pull-up
13 (1)
BFICW
6mA
13 (1)
BFDCW
6mA 50kΩ Pull-down
13 (1)
BFUCW
6mA 50kΩ Pull-up
13 (1)
BFWCW
6mA 5kΩ Pull-up
13 (1)
BFI3W
9mA
13 (1)
BFD3W
9mA 50kΩ Pull-down
13 (1)
BFU3W
9mA 50kΩ Pull-up
13 (1)
BFW3W
9mA 5kΩ Pull-up
13 (1)
BFI1W
12mA
13 (1)
BFD1W
12mA 50kΩ Pull-down
13 (1)
BFU1W
12mA 50kΩ Pull-up
13 (1)
BFW1W
12mA 5kΩ Pull-up
13 (1)
BFI5W
18mA
13 (1)
BFD5W
18mA 50kΩ Pull-down
13 (1)
BFU5W
18mA 50kΩ Pull-up
13 (1)
BFW5W
18mA 5kΩ Pull-up
13 (1)
BFIFW
24mA
13 (1)
BFDFW
24mA 50kΩ Pull-down
13 (1)
BFUFW
24mA 50kΩ Pull-up
13 (1)
BFWFW
24mA 5kΩ Pull-up
13 (1)
BN2U
3mA
13 (1)
BN4U
3mA 50kΩ Pull-down
13 (1)
BN2C
6mA
13 (1)
BN4C
6mA 50kΩ Pull-down
13 (1)
BN23
9mA
13 (1)
BN43
9mA 50kΩ Pull-down
13 (1)
BN21
12mA
23 (1)
BN41
12mA 50kΩ Pull-down
23 (1)
BN25
18mA
23 (1)
BN45
18mA 50kΩ Pull-down
23 (1)
BN2F
24mA
23 (1)
BN4F
24mA 50kΩ Pull-down
23 (1)
Design Manual A13826EJ6V0DM
APPENDIX E LIST OF BLOCKS
Function
I/O Buffer with EN(OR)
Block
Description
Cells (I/O)
BN3U
3mA
11 (1)
BN5U
3mA 50kΩ Pull-down
11 (1)
BN3C
6mA
11 (1)
BN5C
6mA 50kΩ Pull-down
11 (1)
BN33
9mA
11 (1)
BN53
9mA 50kΩ Pull-down
11 (1)
BN31
12mA
21 (1)
BN51
12mA 50kΩ Pull-down
21 (1)
BN35
18mA
21 (1)
BN55
18mA 50kΩ Pull-down
21 (1)
BN3F
24mA
21 (1)
BN5F
24mA 50kΩ Pull-down
21 (1)
E.1.2 TTL Level
Function
Input Buffer
Input Buffer with Failsafe
Input Buffer with EN(AND)
Input Buffer with EN(OR)
Block
Description
Cells (I/O)
FI02
—
3 (1)
FID2
50kΩ Pull-down
3 (1)
FIU2
50kΩ Pull-up
3 (1)
FIW2
5kΩ Pull-up
3 (1)
FIS2W
Schmitt
6 (1)
FDS2W
Schmitt 50kΩ Pull-down
6 (1)
FUS2W
Schmitt 50kΩ Pull-up
6 (1)
FWS2W
Schmitt 5kΩ Pull-up
6 (1)
FIA2
—
3 (1)
FDA2
50kΩ Pull-down
3 (1)
FIE2W
Schmitt
6 (1)
FDE2W
Schmitt 50kΩ Pull-down
6 (1)
FN12
—
7 (1)
FN22
50kΩ Pull-down
7 (1)
FN14
—
4 (1)
FN24
50kΩ Pull-down
4 (1)
Design Manual A13826EJ6V0DM
241
APPENDIX E LIST OF BLOCKS
Function
I/O Buffer
242
Block
Description
Cells (I/O)
B00V
3mA
10 (1)
B0DV
3mA 50kΩ Pull-down
10 (1)
B0UV
3mA 50kΩ Pull-up
10 (1)
B0WV
3mA 5kΩ Pull-up
10 (1)
B00D
6mA
10 (1)
B0DD
6mA 50kΩ Pull-down
10 (1)
B0UD
6mA 50kΩ Pull-up
10 (1)
B0WD
6mA 5kΩ Pull-up
10 (1)
B004
9mA
10 (1)
B0D4
9mA 50kΩ Pull-down
10 (1)
B0U4
9mA 50kΩ Pull-up
10 (1)
B0W4
9mA 5kΩ Pull-up
10 (1)
B002
12mA
20 (1)
B0D2
12mA 50kΩ Pull-down
20 (1)
B0U2
12mA 50kΩ Pull-up
20 (1)
B0W2
12mA 5kΩ Pull-up
20 (1)
B006
18mA
20 (1)
B0D6
18mA 50kΩ Pull-down
20 (1)
B0U6
18mA 50kΩ Pull-up
20 (1)
B0W6
18mA 5kΩ Pull-up
20 (1)
B00G
24mA
20 (1)
B0DG
24mA 50kΩ Pull-down
20 (1)
B0UG
24mA 50kΩ Pull-up
20 (1)
B0WG
24mA 5kΩ Pull-up
20 (1)
Design Manual A13826EJ6V0DM
APPENDIX E LIST OF BLOCKS
Function
Low-noise I/O Buffer
Block
Description
Cells (I/O)
BE0V
3mA
10 (1)
BEDV
3mA 50kΩ Pull-down
10 (1)
BEUV
3mA 50kΩ Pull-up
10 (1)
BEWV
3mA 5kΩ Pull-up
10 (1)
BE0D
6mA
10 (1)
BEDD
6mA 50kΩ Pull-down
10 (1)
BEUD
6mA 50kΩ Pull-up
10 (1)
BEWD
6mA 5kΩ Pull-up
10 (1)
BE04
9mA
10 (1)
BED4
9mA 50kΩ Pull-down
10 (1)
BEU4
9mA 50kΩ Pull-up
10 (1)
BEW4
9mA 5kΩ Pull-up
10 (1)
BE02
12mA
10 (1)
BED2
12mA 50kΩ Pull-down
10 (1)
BEU2
12mA 50kΩ Pull-up
10 (1)
BEW2
12mA 5kΩ Pull-up
10 (1)
BE06
18mA
10 (1)
BED6
18mA 50kΩ Pull-down
10 (1)
BEU6
18mA 50kΩ Pull-up
10 (1)
BEW6
18mA 5kΩ Pull-up
10 (1)
BE0G
24mA
10 (1)
BEDG
24mA 50kΩ Pull-down
10 (1)
BEUG
24mA 50kΩ Pull-up
10 (1)
BEWG
24mA 5kΩ Pull-up
10 (1)
Design Manual A13826EJ6V0DM
243
APPENDIX E LIST OF BLOCKS
Function
Schmitt I/O Buffer
244
Block
Description
Cells (I/O)
BSIVW
3mA
13 (1)
BSDVW
3mA 50kΩ Pull-down
13 (1)
BSUVW
3mA 50kΩ Pull-up
13 (1)
BSWVW
3mA 5kΩ Pull-up
13 (1)
BSIDW
6mA
13 (1)
BSDDW
6mA 50kΩ Pull-down
13 (1)
BSUDW
6mA 50kΩ Pull-up
13 (1)
BSWDW
6mA 5kΩ Pull-up
13 (1)
BSI4W
9mA
13 (1)
BSD4W
9mA 50kΩ Pull-down
13 (1)
BSU4W
9mA 50kΩ Pull-up
13 (1)
BSW4W
9mA 5kΩ Pull-up
13 (1)
BSI2W
12mA
23 (1)
BSD2W
12mA 50kΩ Pull-down
23 (1)
BSU2W
12mA 50kΩ Pull-up
23 (1)
BSW2W
12mA 5kΩ Pull-up
23 (1)
BSI6W
18mA
23 (1)
BSD6W
18mA 50kΩ Pull-down
23 (1)
BSU6W
18mA 50kΩ Pull-up
23 (1)
BSW6W
18mA 5kΩ Pull-up
23 (1)
BSIGW
24mA
23 (1)
BSDGW
24mA 50kΩ Pull-down
23 (1)
BSUGW
24mA 50kΩ Pull-up
23 (1)
BSWGW
24mA 5kΩ Pull-up
23 (1)
Design Manual A13826EJ6V0DM
APPENDIX E LIST OF BLOCKS
Function
Low-noise Schmitt I/O Buffer
I/O Buffer with EN(AND)
Block
Description
Cells (I/O)
BFIVW
3mA
13 (1)
BFDVW
3mA 50kΩ Pull-down
13 (1)
BFUVW
3mA 50kΩ Pull-up
13 (1)
BFWVW
3mA 5kΩ Pull-up
13 (1)
BFIDW
6mA
13 (1)
BFDDW
6mA 50kΩ Pull-down
13 (1)
BFUDW
6mA 50kΩ Pull-up
13 (1)
BFWDW
6mA 5kΩ Pull-up
13 (1)
BFI4W
9mA
13 (1)
BFD4W
9mA 50kΩ Pull-down
13 (1)
BFU4W
9mA 50kΩ Pull-up
13 (1)
BFW4W
9mA 5kΩ Pull-up
13 (1)
BFI2W
12mA
13 (1)
BFD2W
12mA 50kΩ Pull-down
13 (1)
BFU2W
12mA 50kΩ Pull-up
13 (1)
BFW2W
12mA 5kΩ Pull-up
13 (1)
BFI6W
18mA
13 (1)
BFD6W
18mA 50kΩ Pull-down
13 (1)
BFU6W
18mA 50kΩ Pull-up
13 (1)
BFW6W
18mA 5kΩ Pull-up
13 (1)
BFIGW
24mA
13 (1)
BFDGW
24mA 50kΩ Pull-down
13 (1)
BFUGW
24mA 50kΩ Pull-up
13 (1)
BFWGW
24mA 5kΩ Pull-up
13 (1)
BN2V
3mA
14 (1)
BN4V
3mA 50kΩ Pull-down
14 (1)
BN2D
6mA
14 (1)
BN4D
6mA 50kΩ Pull-down
14 (1)
BN24
9mA
14 (1)
BN44
9mA 50kΩ Pull-down
14 (1)
BN22
12mA
24 (1)
BN42
12mA 50kΩ Pull-down
24 (1)
BN26
18mA
24 (1)
BN46
18mA 50kΩ Pull-down
24 (1)
BN2G
24mA
24 (1)
BN4G
24mA 50kΩ Pull-down
24 (1)
Design Manual A13826EJ6V0DM
245
APPENDIX E LIST OF BLOCKS
Function
Block
I/O Buffer with EN(OR)
Description
Cells (I/O)
BN3V
3mA
11 (1)
BN5V
3mA 50kΩ Pull-down
11 (1)
BN3D
6mA
11 (1)
BN5D
6mA 50kΩ Pull-down
11 (1)
BN34
9mA
11 (1)
BN54
9mA 50kΩ Pull-down
11 (1)
BN32
12mA
21 (1)
BN52
12mA 50kΩ Pull-down
21 (1)
BN36
18mA
21 (1)
BN56
18mA 50kΩ Pull-down
21 (1)
BN3G
24mA
21 (1)
BN5G
24mA 50kΩ Pull-down
21 (1)
E.1.3 Oscillator
Function
Block
Description
Cells (I/O)
Oscillator Input Buffer
OSI1
—
0 (1)
Oscillator Input Buffer for Enable
OSI2
—
0 (1)
Oscillator Input Buffer for OSO9
OSI4
—
0 (1)
Oscillator Output Buffer (Internal Feedback Resistor)
OSO1
—
0 (1)
Oscillator Output Buffer (for Enable Type)
OSO7
—
0 (1)
Oscillator Output Buffer (External Feedback Resistor)
OSO9
—
0 (1)
246
Design Manual A13826EJ6V0DM
APPENDIX E LIST OF BLOCKS
E.2 Function Block
E.2.1 Level Generator
Function
Block
H,L Level Generator
F091
Description
—
Cells (I/O)
1 (—)
E.2.2 Inverter, Buffer, CTS Driver, Delay Gate
Function
Inverter
Buffer
CTS Driver (Inverter Type)
Delay Gate
Block
Description
Cells (I/O)
L101
Single Out, Low Power
1 (—)
F101
Single Out
1 (—)
F102
Single Out, x2-drive
2 (—)
F143
Single Out, x3-drive
3 (—)
F144
Single Out, x4-drive
4 (—)
F145
Single Out, x5-drive
5 (—)
F146
Single Out, x6-drive
6 (—)
F148
Single Out, x8-drive
12 (—)
L111
Single Out, Low Power
1 (—)
F111
Single Out
2 (—)
F112
Single Out, x2-drive
3 (—)
F153
Single Out, x3-drive
4 (—)
F154
Single Out, x4-drive
5 (—)
F158
Single Out, x8-drive
11 (—)
FC42
Single type
132 (—)
FC82
Single type, x2-drive
396 (—)
FC44
Double type
340 (—)
FC84
Double type, x2-drive
F131
—
6 (—)
F132
—
10 (—)
Design Manual A13826EJ6V0DM
1020 (—)
247
APPENDIX E LIST OF BLOCKS
E.2.3 OR(NOR)
Function
2-Input NOR
3-Input NOR
4-Input NOR
5-Input NOR
6-Input NOR
8-Input NOR
2-Input OR
3-Input OR
4-Input OR
5-Input OR
6-Input OR
8-Input OR
248
Block
Description
Cells (I/O)
L202
Low Power
1 (—)
F202
—
2 (—)
F222
x2-drive
4 (—)
F282
x4-drive
6 (—)
L203
Low Power
2 (—)
F203
—
3 (—)
F223
x2-drive
6 (—)
L204
Low Power
2 (—)
F204
—
4 (—)
L205
Low Power
4 (—)
F205
—
5 (—)
F225
x2-drive
6 (—)
F206
—
5 (—)
F226
x2-drive
6 (—)
L208
Low Power
7 (—)
F208
—
7 (—)
F228
x2-drive
8 (—)
L212
Low Power
2 (—)
F212
—
2 (—)
F232
x2-drive
3 (—)
F252
x4-drive
6 (—)
L213
Low Power
2 (—)
F213
—
3 (—)
F233
x2-drive
4 (—)
L214
Low Power
3 (—)
F214
—
3 (—)
F234
x2-drive
4 (—)
L215
Low Power
4 (—)
F215
—
5 (—)
F235
x2-drive
7 (—)
L216
Low Power
4 (—)
F216
—
5 (—)
F236
x2-drive
7 (—)
L218
Low Power
6 (—)
F218
—
8 (—)
F238
x2-drive
9 (—)
Design Manual A13826EJ6V0DM
APPENDIX E LIST OF BLOCKS
E.2.4 AND(NAND)
Function
2-Input NAND
3-Input NAND
4-Input NAND
5-Input NAND
6-Input NAND
8-Input NAND
2-Input AND
3-Input AND
4-Input AND
5-Input AND
6-Input AND
8-Input AND
Block
Description
Cells (I/O)
L302
Low Power
1 (—)
F302
—
2 (—)
F322
x2-drive
4 (—)
F382
x4-drive
6 (—)
L303
Low Power
2 (—)
F303
—
3 (—)
F323
x2-drive
6 (—)
L304
Low Power
2 (—)
F304
—
4 (—)
F324
x2-drive
8 (—)
F305
—
5 (—)
F325
x2-drive
6 (—)
F306
—
5 (—)
F326
x2-drive
6 (—)
F308
—
6 (—)
F328
x2-drive
7 (—)
L312
Low Power
2 (—)
F312
—
2 (—)
F332
x2-drive
3 (—)
F352
x4-drive
6 (—)
L313
Low Power
2 (—)
F313
—
3 (—)
F333
x2-drive
4 (—)
L314
Low Power
3 (—)
F314
—
3 (—)
F334
x2-drive
4 (—)
L315
Low Power
4 (—)
F315
—
5 (—)
F335
x2-drive
7 (—)
L316
Low Power
4 (—)
F316
—
5 (—)
F336
x2-drive
7 (—)
L318
Low Power
5 (—)
F318
—
6 (—)
F338
x2-drive
8 (—)
Design Manual A13826EJ6V0DM
249
APPENDIX E LIST OF BLOCKS
E.2.5 AND-NOR
Function
1-2-Input AND-NOR
Block
Description
Cells (I/O)
L421
Low Power
2 (—)
F421
—
3 (—)
L422
Low Power
2 (—)
F422
—
4 (—)
L423
Low Power
2 (—)
F423
—
4 (—)
L424
Low Power
2 (—)
F424
—
4 (—)
L425
Low Power
3 (—)
F425
—
6 (—)
L427
Low Power
3 (—)
F427
—
5 (—)
L428
Low Power
3 (—)
F428
—
5 (—)
L429
Low Power
6 (—)
F429
—
6 (—)
L440
Low Power
3 (—)
F440
—
5 (—)
L441
Low Power
5 (—)
F441
—
7 (—)
L444
Low Power
8 (—)
F444
—
8 (—)
L446
Low Power
4 (—)
F446
—
5 (—)
L447
Low Power
5 (—)
F447
—
5 (—)
L448
Low Power
5 (—)
F448
—
5 (—)
3-3-3-3-Input AND-NOR
F449
—
8 (—)
3-3-3-Input AND-NOR
L460
Low Power
6 (—)
F460
—
7 (—)
1-2-3-Input AND-NOR
F462
—
6 (—)
1-1-3-Input AND-NOR
L463
Low Power
3 (—)
F463
—
5 (—)
L464
Low Power
5 (—)
F464
—
5 (—)
1-1-1-1-2-Input AND-NOR
F465
—
5 (—)
4-4-4-4-Input AND-NOR
F466
—
10 (—)
1-1-2-Input AND-NOR
1-3-Input AND-NOR
2-2-Input AND-NOR
2-2-2-Input AND-NOR
2-3-Input AND-NOR
1-2-2-Input AND-NOR
2-2-2-2-Input AND-NOR
1-4-Input AND-NOR
1-5-Input AND-NOR
4-4-4-Input AND-NOR
1-1-1-2-Input AND-NOR
1-1-1-3-Input AND-NOR
1-1-2-2-Input AND-NOR
1-1-4-Input AND-NOR
250
Design Manual A13826EJ6V0DM
APPENDIX E LIST OF BLOCKS
E.2.6 OR-NAND
Function
1-4-Input OR-NAND
Block
Description
Cells (I/O)
L430
Low Power
4 (—)
F430
—
5 (—)
L431
Low Power
2 (—)
F431
—
3 (—)
L432
Low Power
2 (—)
F432
—
4 (—)
L433
Low Power
2 (—)
F433
—
4 (—)
L434
Low Power
2 (—)
F434
—
4 (—)
2-3-Input OR-NAND
F435
—
5 (—)
3-3-Input OR-NAND
L436
Low Power
3 (—)
F436
—
6 (—)
1-2-2-Input OR-NAND
F437
—
5 (—)
2-2-2-Input OR-NAND
F438
—
6 (—)
1-5-Input OR-NAND
L439
Low Power
5 (—)
F439
—
6 (—)
L450
Low Power
5 (—)
F450
—
6 (—)
L451
Low Power
7 (—)
F451
—
8 (—)
L452
Low Power
4 (—)
F452
—
5 (—)
L453
Low Power
5 (—)
F453
—
6 (—)
4-4-4-Input OR-NAND
F457
—
10 (—)
1-1-1-2-Input OR-NAND
L458
Low Power
3 (—)
F458
—
5 (—)
L459
Low Power
5 (—)
F459
—
5 (—)
1-1-1-1-2-Input OR-NAND
F490
—
5 (—)
1-2-3-Input OR-NAND
L491
Low Power
5 (—)
F491
—
5 (—)
L493
Low Power
6 (—)
F493
—
7 (—)
1-1-2-2-Input OR-NAND
F495
—
6 (—)
3-3-3-3-Input OR-NAND
F496
—
8 (—)
4-4-4-4-Input OR-NAND
F498
—
14 (—)
1-2-Input OR-NAND
1-1-2-Input OR-NAND
1-3-Input OR-NAND
2-2-Input OR-NAND
2-4-Input OR-NAND
4-4-Input OR-NAND
1-1-3-Input OR-NAND
1-1-4-Input OR-NAND
1-1-1-3-Input OR-NAND
3-3-3-Input OR-NAND
Design Manual A13826EJ6V0DM
251
APPENDIX E LIST OF BLOCKS
E.2.7 Exclusive OR, Exclusive NOR
Function
2-Input Exclusive OR
3-Input Exclusive OR
2-Input Exclusive NOR
3-Input Exclusive NOR
252
Block
Description
Cells (I/O)
L511
Low Power
3 (—)
F511
—
4 (—)
L516
Low Power
6 (—)
F516
—
7 (—)
L512
Low Power
3 (—)
F512
—
4 (—)
L517
Low Power
7 (—)
F517
—
7 (—)
Design Manual A13826EJ6V0DM
APPENDIX E LIST OF BLOCKS
E.2.8 Adder, 3-State Buffer, Decoder, Multiplexer, Generator
Function
Block
Description
Cells (I/O)
1-Bit Full Adder
F521
—
9 (—)
4-Bit Full Adder
F523
—
32 (—)
4-Bit Look Ahead Carry Generator
F526
—
34 (—)
4-Bit Carry Look Ahead Adder
F527
—
69 (—)
3-State Buffer
L531
with EN, Low Power
4 (—)
F531
with EN
5 (—)
F533
with EN, x2-drive
7 (—)
F53F
with EN, x4-drive
11 (—)
L532
with ENB, Low Power
4 (—)
F532
with ENB
5 (—)
F534
with ENB, x2-drive
7 (—)
F53G
with ENB, x4-drive
11 (—)
F541
Inverter with EN
6 (—)
F543
Inverter with EN, x2-drive
8 (—)
F54F
Inverter with EN, x4-drive
12 (—)
F542
Inverter with ENB
6 (—)
F544
Inverter with ENB, x2-drive
8 (—)
F54G
Inverter with ENB, x4-drive
12 (—)
L560
Positive Out, Low Power
F560
Positive Out
L561
Negative Out, Low Power
F561
Negative Out
L565
Low Power
3 (—)
F565
—
4 (—)
L571
with ENB, Low Power
4 (—)
F571
with ENB
6 (—)
F564
—
8 (—)
F570
with ENB
10 (—)
F563
—
18 (—)
F569
with ENB
18 (—)
L572
with ENB, Low Power
15 (—)
F572
with ENB
17 (—)
8-Bit Odd Parity Generator
F581
—
19 (—)
8-Bit Even Parity Generator
F582
—
19 (—)
2 to 4 Decoder
2 to 1 Multiplexer (Positive Out)
4 to 1 Multiplexer (Positive Out)
8 to 1 Multiplexer (Positive Out)
Quad 2 to 1 Multiplexer (Negative Out)
Design Manual A13826EJ6V0DM
6 (—)
10 (—)
6 (—)
10 (—)
253
APPENDIX E LIST OF BLOCKS
E.2.9 RS-Latch, RS-F/F
Function
Block
Description
Cells (I/O)
RS-Latch
F595
—
5 (—)
RS-F/F with R,S
F596
—
11 (—)
E.2.10 D-Latch
Function
D-Latch
Block
Description
Cells (I/O)
F601
—
6 (—)
L601
Q Out, Low Power
4 (—)
F601NQ
Q Out
5 (—)
F601NB
QB Out
5 (—)
D-Latch, High Speed
F6R1
—
6 (—)
D-Latch with R
F602
—
6 (—)
L602
Q Out, Low Power
5 (—)
F602NQ
Q Out
6 (—)
F602NB
QB Out
5 (—)
D-Latch with R, High Speed
F6R2
—
7 (—)
D-Latch with RB
F603
—
7 (—)
L603
Q Out, Low Power
5 (—)
F603NQ
Q Out
5 (—)
F603NB
QB Out
6 (—)
D-Latch with RB, High Speed
F6R5
—
6 (—)
D-Latch with SB
F60K
—
7 (—)
F60KNQ
Q Out
6 (—)
F60KNB
QB Out
5 (—)
F60J
—
7 (—)
F60JNQ
Q Out
6 (—)
F60JNB
QB Out
6 (—)
F604
—
6 (—)
L604
Q Out, Low Power
4 (—)
F604NQ
Q Out
5 (—)
F604NB
QB Out
5 (—)
D-Latch (GB), High Speed
F6R8
—
6 (—)
D-Latch (GB) with RB
F605
—
7 (—)
L605
Q Out, Low Power
5 (—)
F605NQ
Q Out
5 (—)
F605NB
QB Out
6 (—)
F6R9
—
6 (—)
D-Latch with RB,SB
D-Latch (GB)
D-Latch (GB) with RB, High Speed
254
Design Manual A13826EJ6V0DM
APPENDIX E LIST OF BLOCKS
E.2.11 D-F/F
Function
D-F/F
D-F/F with R
D-F/F with S
D-F/F with R,S
D-F/F with RB
D-F/F with SB
D-F/F with RB,SB
D-F/F (CB)
D-F/F (CB) with RB
D-F/F (CB) with SB
D-F/F (CB) with RB,SB
D-F/F with 2 to 1 Selector
Block
Description
Cells (I/O)
F641
—
8 (—)
L641
Q Out, Low Power
6 (—)
F641NQ
Q Out
7 (—)
F641NB
QB Out
7 (—)
F642
—
9 (—)
F642NQ
Q Out
8 (—)
F642NB
QB Out
8 (—)
F643
—
9 (—)
F643NQ
Q Out
8 (—)
F643NB
QB Out
8 (—)
F644
—
L644
Q Out, Low Power
8 (—)
F644NQ
Q Out
9 (—)
F644NB
QB Out
9 (—)
F615
—
9 (—)
L645
Q Out, Low Power
7 (—)
F615NQ
Q Out
8 (—)
10 (—)
F615NB
QB Out
8 (—)
F616
—
9 (—)
F616NQ
Q Out
8 (—)
F616NB
QB Out
8 (—)
F647
—
L647
Q Out, Low Power
8 (—)
F647NQ
Q Out
9 (—)
F647NB
QB Out
9 (—)
F661
—
8 (—)
L661
Q Out, Low Power
6 (—)
F661NQ
Q Out
7 (—)
F661NB
QB Out
7 (—)
F665
—
9 (—)
F665NQ
Q Out
8 (—)
F665NB
QB Out
8 (—)
F666
—
9 (—)
F666NQ
Q Out
8 (—)
F666NB
QB Out
8 (—)
F667
—
L667
Q Out, Low Power
8 (—)
F667NQ
Q Out
9 (—)
F667NB
QB Out
F641S
—
F641SQ
Q Out
9 (—)
F641SB
QB Out
9 (—)
Design Manual A13826EJ6V0DM
10 (—)
10 (—)
9 (—)
10 (—)
255
APPENDIX E LIST OF BLOCKS
Function
Block
D-F/F with R,2 to 1 Selector
D-F/F with S,2 to 1 Selector
D-F/F with R,S,2 to 1 Selector
D-F/F with RB,2 to 1 Selector
D-F/F with SB,2 to 1 Selector
D-F/F with RB,SB,2 to 1 Selector
D-F/F (CB) with 2 to 1 Selector
D-F/F (CB) with RB,2 to 1 Selector
D-F/F (CB) with SB,2 to 1 Selector
D-F/F (CB) with RB,SB,2 to 1 Selector
D-F/F with Hold
D-F/F with RB,Hold
D-F/F with SB,Hold
Description
Cells (I/O)
F642S
—
11 (—)
F642SQ
Q Out
10 (—)
F642SB
QB Out
10 (—)
F643S
—
11 (—)
F643SQ
Q Out
10 (—)
F643SB
QB Out
10 (—)
F644S
—
12 (—)
F644SQ
Q Out
11 (—)
F644SB
QB Out
11 (—)
F615S
—
11 (—)
F615SQ
Q Out
10 (—)
F615SB
QB Out
10 (—)
F616S
—
11 (—)
F616SQ
Q Out
10 (—)
F616SB
QB Out
10 (—)
F647S
—
12 (—)
F647SQ
Q Out
11 (—)
F647SB
QB Out
11 (—)
F661S
—
10 (—)
F661SQ
Q Out
F661SB
QB Out
9 (—)
F665S
—
11 (—)
F665SQ
Q Out
10 (—)
F665SB
QB Out
10 (—)
9 (—)
F666S
—
11 (—)
F666SQ
Q Out
10 (—)
F666SB
QB Out
10 (—)
F667S
—
12 (—)
F667SQ
Q Out
11 (—)
F667SB
QB Out
11 (—)
F641H
—
10 (—)
F641HQ
Q Out
F641HB
QB Out
9 (—)
F615H
—
11 (—)
F615HQ
Q Out
10 (—)
F615HB
QB Out
10 (—)
9 (—)
F616H
—
11 (—)
F616HQ
Q Out
10 (—)
F616HB
QB Out
10 (—)
F647H
—
12 (—)
F647HQ
Q Out
11 (—)
F647HB
QB Out
11 (—)
D-F/F (CB) with 2 to 1 Selector(2 CTRL),RB
F673
—
11 (—)
D-F/F (CB) with Hold,2 to 1 Selector(2 CTRL),RB
F674
—
12 (—)
D-F/F with RB,SB,Hold
256
Design Manual A13826EJ6V0DM
APPENDIX E LIST OF BLOCKS
E.2.12 T-F/F, JK-F/F
Function
T-F/F with R,S
Block
Description
Cells (I/O)
F744
—
9 (—)
L744
Q Out, Low Power
7 (—)
F744NQ
Q Out
8 (—)
F745
—
8 (—)
F745NQ
Q Out
7 (—)
F747
—
9 (—)
L747
Q Out, Low Power
7 (—)
F747NQ
Q Out
8 (—)
T-F/F with Data-Hold R,S
F791
—
12 (—)
T-F/F (TB) with RB
F765
—
8 (—)
F765NQ
Q Out
7 (—)
F767
—
9 (—)
L767
Q Out, Low Power
7 (—)
F767NQ
Q Out
8 (—)
T-F/F (TB) with Data-Hold RB,SB
F792
—
12 (—)
JK-F/F
F771
—
10 (—)
F771NQ
Q Out
9 (—)
F771NB
QB Out
9 (—)
JK-F/F, High Speed
F7D1
—
10 (—)
JK-F/F with R,S
F774
—
12 (—)
F774NQ
Q Out
11 (—)
F774NB
QB Out
11 (—)
F775
—
11 (—)
F775NQ
Q Out
10 (—)
F775NB
QB Out
10 (—)
F776
—
11 (—)
F776NQ
Q Out
10 (—)
F776NB
QB Out
10 (—)
F777
—
12 (—)
F777NQ
Q Out
11 (—)
F777NB
QB Out
11 (—)
F781
—
10 (—)
F781NQ
Q Out
9 (—)
F781NB
QB Out
9 (—)
JK-F/F (CB), High Speed
F7E1
—
10 (—)
JK-F/F (CB) with RB,SB
F787
—
12 (—)
F787NQ
Q Out
11 (—)
F787NB
QB Out
11 (—)
T-F/F with RB
T-F/F with RB,SB
T-F/F (TB) with RB,SB
JK-F/F with RB
JK-F/F with SB
JK-F/F with RB,SB
JK-F/F (CB)
Design Manual A13826EJ6V0DM
257
APPENDIX E LIST OF BLOCKS
E.3 Scan Path Block
E.3.1 Standard Type
Function
Block
Description
Cells (I/O)
Scan D-F/F with R,S,2 to 1 Selector
S000
—
12 (—)
Scan D-F/F with 2 to 1 Selector
S002
—
10 (—)
Scan D-F/F with 2 to 1 Selector, High Speed
S003
—
11 (—)
Scan D-F/F with R,S,Hold,2 to 1 Selector
S050
—
16 (—)
Scan D-F/F with Hold,2 to 1 Selector
S052
—
14 (—)
Scan JK-F/F with R,S,D-F/F Function
S100
—
14 (—)
Scan JK-F/F with D-F/F Function
S102
—
12 (—)
Scan JK-F/F with R,S,Hold,D-F/F Function
S150
—
18 (—)
Scan JK-F/F with Hold,D-F/F Function
S152
—
16 (—)
Scan D-Latch with R,D-F/F Function
S201
—
13 (—)
Scan D-Latch with D-F/F Function
S202
—
12 (—)
Scan D-Latch with D-F/F Function, High Speed
S204
—
12 (—)
Scan D-Latch with R,Special Function,R
S301
—
8 (—)
Scan D-Latch with Special Function
S302
—
7 (—)
Scan D-Latch with Special Function, High Speed
S303
—
7 (—)
E.3.2 NEC Scan
Function
Block
Description
Cells (I/O)
NEC Scan D-Latch
SE601
—
13 (—)
NEC Scan D-Latch with R
SE602
—
14 (—)
NEC Scan D-Latch with RB
SE603
—
14 (—)
NEC Scan D-Latch(GB)
SE604
—
13 (—)
NEC Scan D-Latch(GB) with RB
SE605
—
14 (—)
NEC Scan D-F/F
SE611
—
11 (—)
NEC Scan D-F/F with R,S
SE614
—
13 (—)
NEC Scan D-F/F with RB
SE615
—
12 (—)
NEC Scan D-F/F with SB
SE616
—
12 (—)
NEC Scan D-F/F with RB,SB
SE617
—
13 (—)
NEC Scan D-F/F (CB)
SE631
—
11 (—)
NEC Scan D-F/F (CB) with RB,SB
SE637
—
13 (—)
258
Design Manual A13826EJ6V0DM
APPENDIX E LIST OF BLOCKS
E.3.3 Scan Controller
Function
Block
Description
Cells (I/O)
Clock Distributor
SCD1
—
8 (—)
Clock Distributor with Test (Positive Clock)
SCDC
—
2 (—)
Clock Distributor with Test (Negative Clock)
SCDD
—
2 (—)
I/F Control (AMC) with EN
SFEH
—
3 (—)
I/F Control (AMC) with ENB
SFEL
—
2 (—)
I/F Control (SMC) with EN
SOEH
—
3 (—)
I/F Control (SMC) with ENB
SOEL
—
2 (—)
Megamacro Skip
SMS1
—
4 (—)
Set/Reset Control
SRH1
—
2 (—)
Set-B/Reset-B Control
SRL1
—
2 (—)
Loop Cut
SRPD
—
12 (—)
Clock Generator
SCKG
—
16 (—)
Common Input
SCI1
—
2 (—)
Common Output
SCO1
—
4 (—)
GND
SGND
—
2 (—)
Design Manual A13826EJ6V0DM
259
APPENDIX E LIST OF BLOCKS
E.4 Boundary Scan Block
E.4.1 TAP Macro
Function
Block
Description
Cells (I/O)
BScan TAP Macro
SBCJ
—
262 (—)
BScan TAP Macro with NEC Scan
SBCL
—
315 (—)
E.4.2 Level Generator
Function
BScan Level Generator (CLANP)
Block
SBZ1
Description
—
Cells (I/O)
1 (—)
E.4.3 Data Register
Function
Block
Description
Cells (I/O)
BScan Data Register for Input
SVRNI2
—
12 (—)
BScan Data Register for Output
SVRN22
—
24 (—)
BScan Data Register for 3-state
SVRN32
—
50 (—)
BScan Data Register for Bid
SVRNB2
—
57 (—)
E.4.4 D-latch, Selector, Shift Register
Function
Block
Description
Cells (I/O)
BScan D-Latch with SB Q Out, Low Power
L606
—
5 (—)
BScan Selector
SBD1
—
4 (—)
BScan Shift Register
SBR1
—
8 (—)
BScan Data Selector for Output
SVSNA2
—
7 (—)
BScan Data Selector for Bid
SVSNB2
—
7 (—)
BScan Data Enable Selector for 3-state
SVSNC2
—
9 (—)
BScan Data Enable Selector for Bid
SVSNE2
—
9 (—)
E.4.5 Soft Macro
Function
Block
Description
Cells (I/O)
BScan TAP Controller
SBCK
—
392 (—)
BScan Instruction Register (Internal Circuit)
SBM4
—
46 (—)
BScan Instruction Register
SBM5
—
140 (—)
BScan Instruction Decoder
SBM6
—
24 (—)
BScan Instruction Decoder with NEC Scan
SBMC
—
37 (—)
BScan Bypass Register
SBS3
—
26 (—)
260
Design Manual A13826EJ6V0DM
APPENDIX F PIN DESCRIPTIONS
Caution Be sure to contact NEC to confirm whether the desired package has been released or not.
Also contact NEC if a package that has been confirmed as usable is not included in this document.
F.1 QFP (Fine Pitch)
Type
VDD
120
GND
VDD
VDD
F.1.1 160-pin plastic QFP (fine pitch)
100
81
80
79
GND
GND
159
160
42
41
GND
20
GND Position
40
VDD
1
VDD
GND
121
VDD
GND
VDD Position
µPD65885
21, 41, 42, 79, 80, 101, 121,
µPD65887
122, 159, 160
1, 20, 40, 81, 100, 120
NC Pin
None
Signal Pin Note
144
Note Total number of usable signal pins.
Design Manual A13826EJ6V0DM
261
APPENDIX F PIN DESCRIPTIONS
155
VDD
208
1
Type
GND
26
GND Position
VDD Position
µPD65885
1, 2, 26, 51, 52, 79, 105, 106,
27, 53, 78, 104, 130, 157,
µPD65887
131, 155, 156, 182
183, 208
µPD65889
µPD65890
µPD65893
Note Total number of usable signal pins.
262
104
Design Manual A13826EJ6V0DM
VDD
78
GND
VDD
51
VDD
GND
182
GND
GND
VDD
130
GND
VDD
VDD
GND
VDD
GND
F.1.2 208-pin plastic QFP (fine pitch)
NC Pin
None
Signal Pin Note
188
APPENDIX F PIN DESCRIPTIONS
GND
VDD
VDD
GND
GND
179
160
139
120
220
VDD
240
1
Type
20
40
GND Position
VDD Position
µPD65887
1, 2, 20, 41, 59, 60, 80, 101,
21, 40, 61, 81, 100, 120, 140,
µPD65889
121, 122, 139, 161, 179, 180,
160, 181, 201, 220, 240
µPD65890
200, 221
VDD
100
GND
VDD
80
VDD
GND
VDD
59
GND
VDD
GND
VDD
GND
200
GND
GND
VDD
GND
VDD
VDD
GND
F.1.3 240-pin plastic QFP (fine pitch)
NC Pin
None
Signal Pin Note
212
µPD65893
Note Total number of usable signal pins.
Design Manual A13826EJ6V0DM
263
APPENDIX F PIN DESCRIPTIONS
Type
265
GND
285
VDD
303
1
19
VDD
GND
37
GND Position
GND
VDD
GND
171
151
VDD
133
GND
113
GND
VDD
95
GND
57
VDD Position
µPD65890
1, 2, 20, 39, 40, 58, 75, 76,
19, 37, 38, 57, 77, 78, 113,
µPD65893
95, 96, 115, 116, 133, 134,
114, 151, 152, 171, 189, 190,
153, 154, 172, 191, 192, 210,
209, 229, 230, 265, 266, 303,
227, 228, 247, 248, 267, 268,
304
285, 286
Note Total number of usable signal pins.
264
Design Manual A13826EJ6V0DM
75
VDD
GND
247
GND
VDD
GND
189
VDD
GND
209
GND
VDD
GND
VDD
227
VDD
GND
GND
VDD
GND
F.1.4 304-pin plastic QFP (fine pitch)
NC Pin
None
Signal Pin Note
256
APPENDIX F PIN DESCRIPTIONS
F.2 TQFP
VDD
F.2.1 48-pin TQFP
36
25
30
37
24
48
13
1
12
GND
6
Type
µPD65880
GND Position
VDD Position
6
30
NC Pin
None
Signal Pin Note
46
µPD65881
µPD65882
Note Total number of usable signal pins.
Design Manual A13826EJ6V0DM
265
APPENDIX F PIN DESCRIPTIONS
GND
F.2.2 64-pin TQFP
48
33
41
49
32
64
17
1
Type
µPD65881
GND Position
VDD Position
9, 41
10
µPD65882
µPD65883
Note Total number of usable signal pins.
266
16
VDD
GND
9 10
Design Manual A13826EJ6V0DM
NC Pin
None
Signal Pin Note
61
APPENDIX F PIN DESCRIPTIONS
GND
GND
F.2.3 80-pin TQFP
60
41
VDD
61
40
VDD
VDD
80
21
VDD
Type
µPD65882
GND
20
GND
1
GND Position
VDD Position
1, 20, 41, 60
21, 40, 61, 80
NC Pin
None
Signal Pin Note
72
µPD65883
Note Total number of usable signal pins.
Design Manual A13826EJ6V0DM
267
APPENDIX F PIN DESCRIPTIONS
F.3 LQFP
F.3.1 44-pin LQFP
33
VDD
23
34
22
39
17
44
12
1
Type
µPD65880
11
GND Position
VDD Position
17
39
µPD65881
Note Total number of usable signal pins.
268
GND
Design Manual A13826EJ6V0DM
NC Pin
None
Signal Pin Note
42
APPENDIX F PIN DESCRIPTIONS
VDD
VDD
F.3.2 100-pin LQFP (fine pitch)
51
50
GND
100
1
26
25
Type
µPD65882
GND
GND
VDD
75
76
VDD
GND
GND Position
VDD Position
26, 50, 76, 100
1, 25, 51, 75
NC Pin
None
Signal Pin Note
92
µPD65883
µPD65884
µPD65885
Note Total number of usable signal pins.
Design Manual A13826EJ6V0DM
269
APPENDIX F PIN DESCRIPTIONS
GND
159
1
Type
101 100
GND Position
GND
20 21
42
40
GND
VDD Position
µPD65884
21, 41, 42, 79, 80, 101, 121,
µPD65889
122, 159, 160
1, 20, 40, 81, 100, 120
µPD65890
Note Total number of usable signal pins.
270
VDD
81
80
79
VDD
120
122
VDD
GND
VDD
GND
VDD
GND
VDD
F.3.3 160-pin LQFP (fine pitch)
Design Manual A13826EJ6V0DM
NC Pin
None
Signal Pin Note
144
APPENDIX G PINS ASSIGNABLE TO OSCILLATOR
Caution Be sure to contact NEC to confirm whether the desired package has been released or not.
Also contact NEC if a package that has been confirmed as usable is not included in this document.
The pins shown in the following tables can be assigned when configuring an oscillator using the oscillation block.
For the combination of OSI4 + OSO9, pins other than the V DD pin and GND pin can be assigned anywhere.
µ PD65880
Package
Type
OSI1 + OSO1, OSI2 + OSO7
Number of Pins
OSI1, OSI2
OSO1, OSO7
TQFP
48Note
3
2
27
26
LQFP
44
14
13
36
35
Note Low thermal resistance type
µ PD65881
Package
Type
TQFP
OSI1 + OSO1, OSI2 + OSO7
Number of Pins
OSI1, OSI2
OSO1, OSO7
48Note
2
1
26
25
3
2
35
34
2
1
24
23
64
LQFP
44
Note Low thermal resistance type
Design Manual A13826EJ6V0DM
271
APPENDIX G PINS ASSIGNABLE TO OSCILLATOR
µPD65882 (1)
Package
Type
TQFP
OSI1 + OSO1, OSI2 + OSO7
Number of Pins
OSI1, OSI2
OSO1, OSO7
48Note 1
2
1
26
25
18
17
50
49
23
22
63
62
3
2
53
52
64Note 2
80
100Note 1
LQFP
Notes 1. Low thermal resistance type
2. This 64-pin TQFP is a package with a 0.65 mm pitch.
µPD65882 (2)
Package
Type
OSI1 + OSO1, OSI2 + OSO7
Number of Pins
OSI1, OSI2
OSO1, OSO7
64Note
2
1
34
33
TQFP
Note This is a package with a 0.5 mm pitch.
µPD65883
Package
Type
OSI1 + OSO1, OSI2 + OSO7
Number of Pins
OSI1, OSI2
OSO1, OSO7
64
18
17
50
49
23
22
63
62
TQFP
80
LQFP
100Note
3
2
53
52
Note Low thermal resistance type
µPD65884
Package
Type
OSI1 + OSO1, OSI2 + OSO7
Number of Pins
OSI1, OSI2
OSO1, OSO7
LQFP
160
83
82
3
2
LQFP
100Note
3
2
53
52
Note Low thermal resistance type
272
Design Manual A13826EJ6V0DM
APPENDIX G PINS ASSIGNABLE TO OSCILLATOR
µ PD65885
Package
Type
QFP
OSI1 + OSO1, OSI2 + OSO7
Number of Pins
OSI1, OSI2
OSO1, OSO7
160 Note
3
2
83
82
208 Note
159
158
55
54
3
2
53
52
(fine pitch)
LQFP
100 Note
Note Low thermal resistance type
µ PD65887
Package
Type
QFP
OSI1 + OSO1, OSI2 + OSO7
Number of Pins
OSI1, OSI2
OSO1, OSO7
160 Note
3
2
83
82
159
158
55
54
183
182
63
62
(fine pitch)
208
Note
240 Note
Note Low thermal resistance type
µ PD65889
Package
Type
QFP
OSI1 + OSO1, OSI2 + OSO7
Number of Pins
208
OSI1, OSI2
OSO1, OSO7
159
158
55
54
183
182
63
62
83
82
3
2
Note
(fine pitch)
240 Note
LQFP
160
Note Low thermal resistance type
Design Manual A13826EJ6V0DM
273
APPENDIX G PINS ASSIGNABLE TO OSCILLATOR
µ PD65890
Package
Type
QFP
OSI1 + OSO1, OSI2 + OSO7
Number of Pins
OSI1, OSI2
OSO1, OSO7
208 Note
159
158
55
54
63
62
(fine pitch)
240 Note
183
182
304 Note
232
231
80
79
160
83
82
3
2
LQFP
Note Low thermal resistance type
µ PD65893
Package
Type
QFP
OSI1 + OSO1, OSI2 + OSO7
Number of Pins
208
OSI1, OSI2
OSO1, OSO7
159
158
55
54
63
62
183
182
232
231
80
79
Note
(fine pitch)
240 Note
304
Note
Note Low thermal resistance type
274
Design Manual A13826EJ6V0DM
APPENDIX H PACKAGE DRAWINGS
Caution Be sure to contact NEC to confirm whether the desired package has been released or not.
Also contact NEC if a package that has been confirmed as usable is not included in this document.
160-PIN PLASTIC QFP (FINE PITCH) (24x24)
A
B
120
121
81
80
detail of lead end
S
C D
R
Q
160
1
41
40
F
G
H
I
J
M
P
K
S
N S
L
M
NOTE
ITEM
Each lead centerline is located within 0.10 mm of
its true position (T.P.) at maximum material condition.
MILLIMETERS
A
26.0±0.2
B
24.0±0.2
C
24.0±0.2
D
26.0±0.2
F
2.25
G
2.25
H
0.22 +0.05
−0.04
I
0.10
J
K
0.5 (T.P.)
1.0±0.2
L
0.5±0.2
0.17 +0.03
−0.07
M
N
0.10
P
Q
2.7±0.1
0.125±0.075
R
5°±5°
S
3.0 MAX.
S160GM-50-3ED,JED,KED,RED-5
Design Manual A13826EJ6V0DM
275
APPENDIX H PACKAGE DRAWINGS
208-PIN PLASTIC QFP (FINE PITCH) (28x28)
A
B
156
157
105
104
detail of lead end
S
C D
Q
208
1
R
53
52
F
G
H
I
J
M
P
K
N S
S
L
NOTE
M
ITEM
Each lead centerline is located within 0.10 mm of
its true position (T.P.) at maximum material condition.
MILLIMETERS
A
30.6±0.2
B
28.0±0.2
C
28.0±0.2
D
30.6±0.2
F
1.25
G
1.25
H
0.22 +0.05
−0.04
I
0.10
J
K
0.5 (T.P.)
1.3±0.2
L
0.5±0.2
0.17 +0.03
−0.07
M
N
0.10
P
Q
3.2±0.1
0.4±0.1
R
5°±5°
S
3.8 MAX.
P208GD-50-LML,MML,SML,WML-7
276
Design Manual A13826EJ6V0DM
APPENDIX H PACKAGE DRAWINGS
240-PIN PLASTIC QFP (FINE PITCH) (32x32)
A
B
180
181
121
120
detail of lead end
S
C
D
R
Q
240
1
F
G
61
60
H
I
J
M
P
K
M
N
S
L
NOTE
S
ITEM
Each lead centerline is located within 0.10 mm of
its true position (T.P.) at maximum material condition.
MILLIMETERS
A
34.6±0.2
B
32.0±0.2
C
32.0±0.2
D
34.6±0.2
F
1.25
G
1.25
H
0.22 +0.05
−0.04
I
0.10
J
0.5 (T.P.)
K
1.3±0.2
L
0.5±0.2
M
0.17 +0.03
−0.07
N
P
3.2±0.1
0.10
Q
0.4±0.1
R
3° +7°
−3°
S
3.8 MAX.
P240GN-50-LMU, MMU, SMU-4
Design Manual A13826EJ6V0DM
277
APPENDIX H PACKAGE DRAWINGS
304 PIN PLASTIC QFP (FINE PITCH) (40x40)
A
B
228
229
153
152
detail of lead end
S
C
D
R
Q
304
1
77
76
F
G
H
I
J
M
P
K
M
N S
L
NOTE
S
ITEM
Each lead centerline is located within 0.10 mm of
its true position (T.P.) at maximum material condition.
MILLIMETERS
A
42.6±0.2
B
40.0±0.2
C
40.0±0.2
D
42.6±0.2
F
1.25
G
1.25
H
0.22 +0.05
−0.04
I
0.10
J
K
0.5 (T.P.)
1.3±0.2
L
0.5±0.2
M
0.145 +0.055
−0.045
N
0.10
P
Q
3.7±0.1
0.4±0.1
R
5°±5°
S
4.3 MAX.
P304GL-50-NMU, PMU, TMU-4
278
Design Manual A13826EJ6V0DM
APPENDIX H PACKAGE DRAWINGS
48-PIN PLASTIC TQFP (FINE PITCH) (7x7)
A
B
36
37
25
24
detail of lead end
S
C
D
Q
48
R
13
12
1
F
G
J
H
I
M
P
K
S
N
S
L
M
NOTE
ITEM
Each lead centerline is located within 0.10 mm of
its true position (T.P.) at maximum material condition.
MILLIMETERS
A
9.0±0.2
B
7.0±0.2
C
7.0±0.2
D
9.0±0.2
F
0.75
G
0.75
H
0.22 +0.05
−0.04
I
J
0.10
0.5 (T.P.)
K
1.0±0.2
L
0.5±0.2
M
0.145 +0.055
−0.045
N
0.10
P
1.0±0.1
Q
0.1±0.05
R
3° +7°
−3°
S
1.27 MAX.
S48GA-50-9EU-2
Remarks 1. The lead thickness is 0.145 mm for Engineering Samples (ES) and Commercial Samples (CS)
however, it is 0.17 mm for Mass Production (MP).
2. This package drawing corresponds to the ES (Engineering Sample) and CS (Commercial Sample).
Design Manual A13826EJ6V0DM
279
APPENDIX H PACKAGE DRAWINGS
48-PIN PLASTIC TQFP (FINE PITCH) (7x7)
A
B
36
37
detail of lead end
25
24
S
P
C
T
D
R
48
13
12
1
L
U
Q
F
G
J
H
I
M
K
S
N
S
M
NOTE
ITEM
Each lead centerline is located within 0.10 mm of
its true position (T.P.) at maximum material condition.
A
MILLIMETERS
9.0±0.2
B
7.0±0.2
C
7.0±0.2
D
F
9.0±0.2
0.75
G
0.75
H
0.22 +0.05
−0.04
I
0.10
J
0.5 (T.P.)
K
L
1.0±0.2
0.5±0.2
0.17 +0.03
−0.07
M
N
0.08
P
1.0±0.1
Q
0.1±0.05
R
3°+4°
−3°
S
1.27 MAX.
P48GA-50-9EU
Remarks 1. The lead thickness is 0.17 mm for Mass Production (MP) however, it is 0.145 mm for Engineering
Samples (ES) and Commercial Samples (CS).
2. This package drawing corresponds to the MP (Mass Production).
280
Design Manual A13826EJ6V0DM
APPENDIX H PACKAGE DRAWINGS
64-PIN PLASTIC TQFP (12x12)
A
B
48
detail of lead end
33
32
49
S
P
T
C
D
R
L
U
64
Q
17
16
1
F
G
J
H
I
M
ITEM
K
S
M
N
S
NOTE
Each lead centerline is located within 0.13 mm of
its true position (T.P.) at maximum material condition.
MILLIMETERS
A
B
14.0±0.2
12.0±0.2
C
12.0±0.2
D
F
14.0±0.2
1.125
G
1.125
H
0.32 +0.06
−0.10
I
0.13
J
0.65 (T.P.)
K
1.0±0.2
L
0.5
M
0.17 +0.03
−0.07
N
0.10
P
1.0
Q
0.1±0.05
R
3° +4°
−3°
S
1.1±0.1
T
0.25
U
0.6±0.15
P64GK-65-9ET-3
Remark This package has a 0.65 mm pitch.
A package with a 0.5 mm pitch is under preparation.
Design Manual A13826EJ6V0DM
281
APPENDIX H PACKAGE DRAWINGS
80-PIN PLASTIC TQFP (FINE PITCH) (12x12)
A
B
60
41
61
40
detail of lead end
S
C
D
P
T
80
R
21
1
20
U
Q
F
G
L
H
I
J
M
K
S
N
S
M
NOTE
ITEM
Each lead centerline is located within 0.08 mm of
its true position (T.P.) at maximum material condition.
MILLIMETERS
A
B
14.0±0.2
12.0±0.2
C
12.0±0.2
D
F
14.0±0.2
1.25
G
1.25
H
0.22±0.05
I
0.08
J
0.5 (T.P.)
K
L
1.0±0.2
0.5
M
0.145±0.05
N
0.08
P
1.0
Q
0.1±0.05
R
3° +4°
−3°
S
1.1±0.1
T
0.25
U
0.6±0.15
P80GK-50-9EU-1
282
Design Manual A13826EJ6V0DM
APPENDIX H PACKAGE DRAWINGS
44 PIN PLASTIC QFP (10x10)
A
B
detail of lead end
23
22
33
34
S
P
C
T
D
R
12
11
44
1
L
U
Q
F
J
G
H
I
M
K
M
N
S
S
NOTE
ITEM
Each lead centerline is located within 0.16 mm of
its true position (T.P.) at maximum material condition.
MILLIMETERS
A
12.0±0.2
B
10.0±0.2
C
10.0±0.2
D
12.0±0.2
F
1.0
G
1.0
H
0.37 +0.08
−0.07
I
0.2
J
0.8 (T.P.)
K
1.0±0.2
L
0.5
M
0.17 +0.03
−0.06
N
0.10
P
Q
1.4±0.05
0.1±0.05
R
3° +4°
−3°
S
U
1.6 MAX.
0.6±0.15
S44GB-80-8ES-1
Remark Use the above package drawing as 44-pin LQFP package drawing.
Design Manual A13826EJ6V0DM
283
APPENDIX H PACKAGE DRAWINGS
100-PIN PLASTIC LQFP (FINE PITCH) (14x14)
A
B
75
76
51
50
detail of lead end
S
C D
Q
R
26
25
100
1
F
G
H
I
J
M
K
P
S
N
S
L
M
NOTE
Each lead centerline is located within 0.08 mm of
its true position (T.P.) at maximum material condition.
ITEM
MILLIMETERS
A
16.00±0.20
B
14.00±0.20
C
14.00±0.20
D
16.00±0.20
F
1.00
G
1.00
H
0.22 +0.05
−0.04
I
J
0.08
0.50 (T.P.)
K
1.00±0.20
L
0.50±0.20
M
0.17 +0.03
−0.07
N
0.08
P
1.40±0.05
Q
0.10±0.05
R
3° +7°
−3°
S
1.60 MAX.
S100GC-50-8EU, 8EA-2
284
Design Manual A13826EJ6V0DM
APPENDIX H PACKAGE DRAWINGS
160-PIN PLASTIC LQFP (FINE PITCH) (24x24)
A
B
81
80
120
121
detail of lead end
S
C
D
R
Q
41
40
160
1
F
G
H
I
J
M
P
K
N
S
S
L
M
NOTE
ITEM
Each lead centerline is located within 0.10 mm of
its true position (T.P.) at maximum material condition.
MILLIMETERS
A
26.0±0.2
B
24.0±0.2
C
24.0±0.2
D
26.0±0.2
F
2.25
G
2.25
H
0.22 +0.05
−0.04
I
J
0.10
0.5 (T.P.)
K
1.0±0.2
L
0.5±0.2
M
0.145+0.055
−0.045
N
0.10
P
1.4±0.1
Q
0.125±0.075
R
3° +7°
−3°
S
1.7 MAX.
S160GM-50-8ED-3
Remark The lead thickness is 0.145 mm for Engineering Samples (ES) and Commercial Samples (CS) however,
it is 0.17 mm for Mass Production (MP).
Design Manual A13826EJ6V0DM
285
APPENDIX I PACKAGE MARKINGS
This appendix shows examples of the markings for various packages. In some cases, the font type, size, and
relative positions of the markings may differ from the examples shown here.
QFP (Fine Pitch) Package Marking Example
160-pin QFP (fine pitch)
208-pin QFP (fine pitch)
240-pin QFP (fine pitch)
JAPAN
Trademark
Master code
Origin
D 6 5 8 8 0 G D 0 0 1
Master sub code
Package code
9 3 1 5 K 1 0 0 0
Lot No.
Pin No. 1 index
286
Design Manual A13826EJ6V0DM
304-pin QFP (fine pitch)
APPENDIX I PACKAGE MARKINGS
TQFP, LQFP Package Marking Examples
C0.3 mm
C0.3 mm
48-pin TQFP ES (Engineering Sample),
CS (Commercial Sample)
Trademark
Master code
6 2 2
Y 0 1
Master sub code
1 1 5 K 1
Lot No.
C0.5 mm
C0.3 mm
Pin No. 1 index
C0.5 mm
C0.5 mm
48-pin TQFP MP
64-pin TQFP MP
(MP: Mass Production)
Trademark
Master code
6 2 2
Y 0 1
Master sub code
1 1 5 K 1
Lot No.
C0.5 mm
C0.5 mm
Pin No. 1 index
64-pin TQFP
80-pin TQFP
Trademark
Master code
JAPAN
Origin
6 5 8 8 0 G K0 0 1
Master sub code
9 3 1 5 K 1 0 0 0
Package code
Lot No.
Pin No.1 index
Design Manual A13826EJ6V0DM
287
APPENDIX I PACKAGE MARKINGS
44-pin LQFP
100-pin LQFP
160-pin LQFP
Trademark
Master code
JAPAN
D 6 5 8 8 0 G C
Origin
0 0 1
Master sub code
Package code
9 3 1 5 K 1 0 0 0
Lot No.
Pin No.1 index
288
Design Manual A13826EJ6V0DM
APPENDIX J RECOMMENDED SOLDERING CONDITIONS
This product should be soldered and mounted under the following recommended conditions.
For soldering methods and conditions other than those recommended below, contact your NEC sales representative.
For the details of the recommended soldering conditions, refer to the Semiconductor Device Mounting
Technology Manual (C10535E).
µ PD65880
µ PD65881
µPD65882
µPD65883
µPD65884
QFP
Note
160
—
—
—
—
—
(fine pitch)
208Note
—
—
—
—
—
240Note
—
—
—
—
—
Note
Package
Number of Pins
304
TQFP
LQFP
—
—
—
—
—
48 Note
<1>
<1>
<1>
—
—
64
—
<1>
<1>
<1>
80
—
—
<1>
<1>
44
<1>
<1>
—
100Note
—
—
<1>
<1>
<1>
160
—
—
—
—
<1>
Number of Pins
µ PD65885
µ PD65887
µPD65889
µPD65890
µPD65893
QFP
160Note
<2>
<2>
—
—
—
(fine pitch)
208Note
<3>
<3>
<3>
<3>
<3>
240Note
—
<4>
<4>
<4>
<4>
Note
304
—
—
—
<4>
<4>
48 Note
—
—
Package
TQFP
LQFP
—
—
—
64
—
—
—
80
—
—
—
—
—
—
—
—
<5>
<5>
44
—
—
100Note
<1>
<1>
160
—
—
Note Low thermal resistance type
Remarks 1. <1>: IR35-107-2 and VP15-107-2, <2>: IR35-203-1 and VP15-203-1, <3>: IR35-207-3 and VP15207-3, <4>: IR35-203-2 and VP15-203-2, <5>: IR35-103-2 and VP15-103-2
2. —: Not supported
Blank: Under development, or the recommended soldering conditions are undetermined.
For details, contact NEC.
Design Manual A13826EJ6V0DM
289
APPENDIX J RECOMMENDED SOLDERING CONDITIONS
The recommended condition symbols for soldering are shown below.
Surface Mounting Type Soldering Conditions
Recommended
Condition Symbol
Soldering Method
IR35-103-2
Infrared reflow
Package peak temperature: 235°C, Time: 30 seconds max. (at 210°C or higher),
Count: Two times or less, Exposure limit: 3 days Note (after that, prebake at 125°C for
10 to 72 hours)
VP15-103-2
VPS
Package peak temperature: 215°C, Time: 25 to 40 seconds (at 200°C or higher),
Count: Two times or less, Exposure limit: 3 days Note (after that, prebake at 125°C for
10 to 72 hours)
IR35-107-2
Infrared reflow
Package peak temperature: 235°C, Time: 30 seconds max. (at 210°C or higher),
Count: Two times or less, Exposure limit: 7 days Note (after that, prebake at 125°C for
10 to 72 hours)
VP15-107-2
VPS
Package peak temperature: 215°C, Time: 25 to 40 seconds (at 200°C or higher),
Count: Two times or less, Exposure limit: 7 days Note (after that, prebake at 125°C for
10 to 72 hours)
IR35-203-1
Infrared reflow
Package peak temperature: 235°C, Time: 30 seconds max. (at 210°C or higher),
Count: Once, Exposure limit: 3 daysNote (after that, prebake at 125°C for 20 to 72
hours)
VP15-203-1
VPS
Package peak temperature: 215°C, Time: 25 to 40 seconds (at 200°C or higher),
Count: Once, Exposure limit: 3 daysNote (after that, prebake at 125°C for 20 to 72
hours)
IR35-203-2
Infrared reflow
Package peak temperature: 235°C, Time: 30 seconds max. (at 210°C or higher),
Count: Two times or less, Exposure limit: 3 days Note (after that, prebake at 125°C for
20 to 72 hours)
VP15-203-2
VPS
Package peak temperature: 215°C, Time: 25 to 40 seconds (at 200°C or higher),
Count: Two times or less, Exposure limit: 3 days Note (after that, prebake at 125°C for
20 to 72 hours)
IR35-207-3
Infrared reflow
Package peak temperature: 235°C, Time: 30 seconds max. (at 210°C or higher),
Count: Three times or less, Exposure limit: 7 daysNote (after that, prebake at 125°C
for 20 to 72 hours)
VP15-207-3
VPS
Package peak temperature: 215°C, Time: 25 to 40 seconds (at 200°C or higher),
Count: Three times or less, Exposure limit: 7 daysNote (after that, prebake at 125°C
for 20 to 72 hours)
Partial heating
Soldering Conditions
Pin temperature: 300°C max., Time: 3 seconds max. (per pin row)
Note After opening the dry pack, store it at 25°C or less and 65% RH or less for the allowable storage period.
Caution Do not use different soldering methods together (except for partial heating).
290
Design Manual A13826EJ6V0DM
APPENDIX K DATA
K.1 Figures
Figure K-1. Leakage Current
IL 1000
(µ A)
100
10
1
0
20
40
60
80
100
120
140 TA (°C)
VDD = 5.0 V±10%
VDD = 3.3 ±0.3 V
Design Manual A13826EJ6V0DM
291
APPENDIX K DATA
Figure K-2. Current Consumption of On-Chip 50 kΩ Resistor (IPD)
350
IPD
(µ A)
5.0 V±10%
3.3 ±0.3 V
300
3.0 ±0.3 V
250
200
150
100
50
−60
−40
−20
0
20
40
60
80
100
TA (°C)
Figure K-3. Current Consumption of On-Chip 5 kΩ Resistor (IPU)
2500
IPU
(µ A)
5.0 V±10%
3.3 ±0.3 V
3.0 ±0.3 V
2000
1500
1000
500
−60
292
−40
−20
0
20
40
Design Manual A13826EJ6V0DM
60
80
100
TA (°C)
APPENDIX K DATA
Figure K-4. Input Through Current
Figure K-5. Input Through Current
(VDD = 5.0 V TTL Level)
II (mA)
II (mA)
(VDD = 5.0 V CMOS Level)
7.0
6.0
7.0
6.0
5.0
5.0
4.0
4.0
3.0
3.0
2.0
2.0
1.0
1.0
0.0
0.0
1.0
2.0
3.0
4.0
0.0
0.0
5.0
1.0
2.0
3.0
4.0
5.0
VIN (V)
Figure K-6. Input Through Current
Figure K-7. Input Through Current
Note
(VDD = 5.5 V TTL Level SchmittNote)
)
7.0
II (mA)
II (mA)
(VDD = 5.5 V CMOS Level Schmitt
6.0
7.0
6.0
5.0
5.0
4.0
4.0
3.0
3.0
2.0
2.0
1.0
1.0
0.0
0.0
1.0
2.0
3.0
4.0
5.0
6.0
0.0
0.0
1.0
2.0
3.0
4.0
VIN (V)
Note This is a graph of the Schmitt buffer with
W in the last of the block name.
6.0
VIN (V)
5.0
6.0
VIN (V)
Note This is a graph of the Schmitt buffer with
W in the last of the block name.
Design Manual A13826EJ6V0DM
293
APPENDIX K DATA
Figure K-8. Input Through Current
Figure K-9. Input Through Current
(VDD = 3.3 V TTL Level)
II (mA)
II (mA)
(VDD = 3.6 V CMOS Level)
7.0
6.0
7.0
6.0
5.0
5.0
4.0
4.0
3.0
3.0
2.0
2.0
1.0
1.0
0.0
0.0
1.0
2.0
3.0
0.0
0.0
4.0
1.0
2.0
3.0
Figure K-10. Input Through Current
Figure K-11. Input Through Current
(VDD = 3.3 V TTL Level SchmittNote)
Note
)
7.0
II (mA)
II (mA)
(VDD = 3.6 V CMOS Level Schmitt
6.0
7.0
6.0
5.0
5.0
4.0
4.0
3.0
3.0
2.0
2.0
1.0
1.0
0.0
0.0
1.0
2.0
3.0
4.0
0.0
0.0
1.0
2.0
W in the last of the block name.
294
3.0
3.5
VIN (V)
VIN (V)
Note This is a graph of the Schmitt buffer with
3.5
VIN (V)
VIN (V)
Note This is a graph of the Schmitt buffer with
W in the last of the block name.
Design Manual A13826EJ6V0DM
APPENDIX K DATA
Figure K-12. Oscillator Configuration Diagram
Rf
LT
Cin
Cout
CT
Design Manual A13826EJ6V0DM
295
APPENDIX K DATA
Figure K-13. fMAX. vs. CL Limit (CMOS Level Output) (1/2)
(a) I OL = 3.0 mA (@3.3 V)
(b) I OL = 3.0 mA (@5.0 V)
I OL = 6.0 mA (@3.3 V)
Output maximum operating
frequency fMAX. (MHz)
100
Under study
10
1
0
50
100
150
200
250
300
Output load capacitance CL (pF)
(c) I OL = 6.0 mA (@5.0 V)
(d) I OL = 9.0 mA (@5.0 V)
I OL = 9.0 mA (@3.3 V)
I OL = 12.0 mA (@3.3 V)
100
Output maximum operating
frequency fMAX. (MHz)
Output maximum operating
frequency fMAX. (MHz)
100
10
1
0
50
100
150
200
250
300
10
1
0
Load capacitance CL (pF)
296
Design Manual A13826EJ6V0DM
50
100
150
200
250
Load capacitance CL (pF)
300
APPENDIX K DATA
Figure K-13. fMAX. vs. CL Limit (CMOS Level Output) (2/2)
(e) I OL = 12.0 mA (@5.0 V)
(f) I OL = 18.0 mA (@5.0 V)
I OL = 18.0 mA (@3.3 V)
I OL = 24.0 mA (@3.3 V)
100
Output maximum operating
frequency fMAX. (MHz)
Output maximum operating
frequency fMAX. (MHz)
100
10
1
0
50
100
150
200
250
300
10
1
0
Load capacitance CL (pF)
50
100
150
200
250
300
Load capacitance CL (pF)
(g) I OL = 24.0 mA (@5.0 V)
Output maximum operating
frequency fMAX. (MHz)
100
10
1
0
50
100
150
200
250
300
Load capacitance CL (pF)
Design Manual A13826EJ6V0DM
297
APPENDIX K DATA
Figure K-14. fMAX. vs. C L Limit (CMOS Level Low-Noise Output) (1/2)
(a) I OL = 3.0 mA (@3.3 V)
(b) I OL = 3.0 mA (@5.0 V)
I OL = 6.0 mA (@3.3 V)
Output maximum operating
frequency fMAX. (MHz)
100
Under study
10
1
0
50
100
150
200
250
300
Load capacitance CL (pF)
(c) I OL = 6.0 mA (@5.0 V)
(d) I OL = 9.0 mA (@5.0 V)
I OL = 9.0 mA (@3.3 V)
I OL = 12.0 mA (@3.3 V)
100
Output maximun operating
frequency fMAX. (MHz)
Output maximum operating
frequency fMAX. (MHz)
100
10
1
0
50
100
150
200
250
300
10
1
0
Load capacitance CL (pF)
298
Design Manual A13826EJ6V0DM
50
100
150
200
250
Load capacitance CL (pF)
300
APPENDIX K DATA
Figure K-14. fMAX. vs. C L Limit (CMOS Level Low-Noise Output) (2/2)
(e) I OL = 12.0 mA (@5.0 V)
(f) I OL = 18.0 mA (@5.0 V)
I OL = 18.0 mA (@3.3 V)
I OL = 24.0 mA (@3.3 V)
100
Output maximum operating
frequency fMAX. (MHz)
Output maximun operating
frequency fMAX. (MHz)
100
10
1
0
50
100
150
200
250
300
10
1
0
Load capacitance CL (pF)
50
100
150
200
250
300
Load capacitance CL (pF)
(g) I OL = 24.0 mA (@5.0 V)
Output maximum operating
frequency fMAX. (MHz)
100
10
1
0
50
100
150
200
250
300
Load capacitance CL (pF)
Design Manual A13826EJ6V0DM
299
APPENDIX K DATA
Voltage coefficient (KV)
Figure K-15. VDD Dependency of I OL / IOH
1.20
1.15
1.10
1.05
1.00
4.0
4.5
5.0
5.5
6.0
VDD (V)
Temperature coefficient (KT)
Figure K-16. T A Dependency of IOL / I OH
1.7
1.6
1.5
1.4
1.3
1.2
1.1
1.0
−40
300
−20
0
20
40
Design Manual A13826EJ6V0DM
60
80
TA (°C)
APPENDIX K DATA
Figure K-17. IO vs. VO (@5.0 V) (1/2)
(1) I OL = 3 mA
(b) IOH vs. VOH
30
MAX.
25
20
VDD – 6.0 VDD – 5.0 VDD – 4.0 VDD – 3.0 VDD – 2.0 VDD – 1.0
0
IOH (mA)
IOL (mA)
(a) IOL vs. VOL
TYP.
–10
15
–20
MIN.
MIN.
10
–30
5
0
0.0
VOH (V)
VDD
TYP.
–40
1.0
2.0
3.0
4.0
5.0
–50
6.0
MAX.
VOL (V)
–60
(2) I OL = 6 mA
(b) IOH vs. VOH
60
MAX.
50
IOH (mA)
IOL (mA)
(a) IOL vs. VOL
40
20
–20
–40
–60
MIN.
10
0
0.0
VOH (V)
VDD
MIN.
TYP.
30
VDD – 6.0 VDD – 5.0 VDD – 4.0 VDD – 3.0 VDD – 2.0 VDD – 1.0
0
TYP.
–80
1.0
2.0
3.0
4.0
5.0
–100
6.0
MAX.
VOL (V)
–120
(3) I OL = 9 mA
(b) IOH vs. VOH
100
90
80
IOH (mA)
IOL (mA)
(a) IOL vs. VOL
MAX.
70
60
50
VDD – 6.0 VDD – 5.0 VDD – 4.0 VDD – 3.0 VDD – 2.0 VDD – 1.0
0
–30
MIN.
–60
TYP.
40
TYP.
–90
30
MIN.
20
–120
10
0
0.0
VOH (V)
VDD
MAX.
1.0
2.0
3.0
4.0
5.0
6.0
VOL (V)
–150
–180
Design Manual A13826EJ6V0DM
301
APPENDIX K DATA
Figure K-17. IO vs. VO (@5.0 V) (2/2)
(4) I OL = 12 mA
(b) IOH vs. VOH
120
MAX.
100
IOH (mA)
IOL (mA)
(a) IOL vs. VOL
80
TYP.
60
VDD – 6.0 VDD – 5.0 VDD – 4.0 VDD – 3.0 VDD – 2.0 VDD – 1.0
0
VOH (V)
VDD
–30
–60
MIN.
40
–90
MIN.
20
0
0.0
TYP.
–120
–150
1.0
2.0
3.0
4.0
5.0
6.0
MAX.
VOL (V)
–180
(5) I OL = 18 mA
(b) IOH vs. VOH
200
MAX.
IOH (mA)
IOL (mA)
(a) IOL vs. VOL
150
VDD – 6.0 VDD – 5.0 VDD – 4.0 VDD – 3.0 VDD – 2.0 VDD – 1.0
0
–50
MIN.
TYP.
100
VOH (V)
VDD
–100
TYP.
MIN.
–150
50
–200
0
0.0
–250
1.0
2.0
3.0
4.0
5.0
MAX.
6.0
–300
VOL (V)
(6) I OL = 24 mA
(b) IOH vs. VOH
250
MAX.
IOH (mA)
IOL (mA)
(a) IOL vs. VOL
200
150
VDD – 6.0 VDD – 5.0 VDD – 4.0 VDD – 3.0 VDD – 2.0 VDD – 1.0
0
–50
–100
TYP.
MIN.
–150
100
–200
MIN.
50
TYP.
–250
–300
0
0.0
302
1.0
2.0
3.0
4.0
5.0
6.0
–350
VOL (V)
–400
MAX.
Design Manual A13826EJ6V0DM
VOH (V)
VDD
APPENDIX K DATA
Figure K-18. IO vs. VO (@3.3 V) (1/2)
(1) I OL = 1 mA
(b) IOH vs. VOH
IOH (mA)
IOL (mA)
(a) IOL vs. VOL
30
25
VDD – 4.0
0
VDD – 3.0
VDD – 2.0
VDD – 1.0
VOH (V)
VDD
VDD – 1.0
VOH (V)
VDD
VDD – 1.0
VOH (V)
VDD
–5
–10
20
MAX.
15
–15
TYP.
TYP.
–25
10
MIN.
–30
5
0
0.0
MIN.
–20
–35
MAX.
–40
1.0
2.0
3.0
4.0
VOL (V)
(2) I OL = 3 mA
(b) IOH vs. VOH
IOH (mA)
IOL (mA)
(a) IOL vs. VOL
50
MAX.
40
VDD – 4.0
0
VDD – 3.0
VDD – 2.0
–10
MIN.
–20
30
–30
TYP.
TYP.
20
–40
MIN.
10
0
0.0
–50
MAX.
–60
1.0
2.0
3.0
4.0
VOL (V)
(3) I OL = 6 mA
(b) IOH vs. VOH
IOH (mA)
IOL (mA)
(a) IOL vs. VOL
80
70
MAX.
60
VDD – 4.0
0
VDD – 2.0
–20
MIN.
–40
50
TYP.
TYP.
40
30
–60
MIN.
–80
20
MAX.
–100
10
0
0.0
VDD – 3.0
–120
1.0
2.0
3.0
4.0
VOL (V)
Design Manual A13826EJ6V0DM
303
APPENDIX K DATA
Figure K-18. IO vs. VO (@3.3 V) (2/2)
(4) I OL = 9 mA
(b) IOH vs. VOH
IOH (mA)
IOL (mA)
(a) IOL vs. VOL
100
90
80
VDD – 3.0
–60
TYP.
VDD – 1.0
VOH (V)
VDD
VDD – 1.0
VOH (V)
VDD
VDD – 1.0
VOH (V)
VDD
MIN.
–40
50
40
VDD – 2.0
–20
MAX.
70
60
TYP.
–80
30
MIN.
20
10
0
0.0
VDD – 4.0
0
–100
MAX.
–120
1.0
2.0
3.0
4.0
VOL (V)
(5) I OL = 12 mA
(b) IOH vs. VOH
150
135
120
IOH (mA)
IOL (mA)
(a) IOL vs. VOL
MAX.
105
VDD – 3.0
MIN.
–80
TYP.
TYP.
–100
75
60
–120
–140
MIN.
45
30
VDD – 2.0
–40
–60
90
MAX.
–160
–180
15
0
0.0
VDD – 4.0
0
–20
–200
1.0
2.0
3.0
4.0
VOL (V)
(6) I OL = 18 mA
(b) IOH vs. VOH
180
IOH (mA)
IOL (mA)
(a) IOL vs. VOL
MAX.
150
VDD – 3.0
–20
–40
–60
–80
120
TYP.
90
60
MIN.
–100
–120
–140
–160
MIN.
30
0
0.0
VDD – 4.0
0
–180
TYP.
MAX.
–200
1.0
2.0
3.0
4.0
VOL (V)
304
Design Manual A13826EJ6V0DM
VDD – 2.0
APPENDIX K DATA
Figure K-19. Oscillator Configuration Diagram
Circuit configuration <1>
(On-chip Rf type)
Circuit configuration <2>
(On-chip Rf type)
Rf
Rf
Rf
Rd
C1
Circuit configuration <3>
C2
Rd
C1
C2
C1
C2
Remark Rf : Feedback resistor
Design Manual A13826EJ6V0DM
305
APPENDIX K DATA
K.2 Tables
Table K-1. CMOS-N5 Family Products
Master
Number of Row Gates
Number of Usable Gates
µPD65880
3456
2764
µPD65881
5880
4704
µPD65882
13952
11161
µPD65883
25344
20275
µPD65884
33864
27091
µPD65885
40768
28537
µPD65887
56496
38948
µPD65889
76000
53200
µPD65890
99528
69669
µPD65893
123384
86368
Remark Total number of gates integrated on the chip in terms of 2-input NAND
(1 cell = 1 gate)
Usable cell rate: µ PD65880, 65881, 65882, 65883, 65884 ... 80%
µ PD65885, 65887, 65889, 65890, 65893 ... 70%
Table K-2. Capacitance of Interface Block (CB)
(a) Input buffer
Interface Level
CB(MIN.) (pF)
CB(MAX.) (pF)
Normal
With Failsafe
Normal
With Failsafe
CMOS
4.0
3.50
7.0
5.0
TTL
4.0
3.50
7.0
5.0
Remark VDD = 0 V; TJ = 25°C; f = 1 MHz
(b) Output buffer/bidirectional buffer
Interface Level
CMOS
CB (pF)
3 mA
6 mA
9 mA
12 mA
18 mA
24 mA
MIN.
4.0
4.0
4.0
4.0
4.0
4.0
MAX.
7.0
7.0
7.0
7.0
7.0
7.0
Remark VDD = 0 V; TJ = 25°C; f = 1 MHz
306
Design Manual A13826EJ6V0DM
APPENDIX K DATA
Table K-3. Capacitance of Packages (C P) (Preliminary Values)
Package
Number of Pins
Lead Pitch
Chip Size
CP (pF)
QFP
160
0.5 mm
24 × 24 mm
1.5
(fine pitch)
208
0.5 mm
28 × 28 mm
1.9
240
0.5 mm
32 × 32 mm
2.0
304
0.5 mm
40 × 40 mm
2.8
48
0.5 mm
7 × 7 mm
0.9
64
0.65 mm
12 × 12 mm
0.9
TQFP
LQFP
80
0.5 mm
12 × 12 mm
0.9
44
0.8 mm
10 × 10 mm
0.7
100
0.5 mm
14 × 14 mm
1.0
160
0.5 mm
24 × 24 mm
1.5
Table K-4. Power Consumption by Input Buffer
Block Type
PI
FI01
16.8470
FI02
17.4223
FIS1
20.8117
FIS2
17.9722
FIA1
5.2705
FIA2
5.3776
FIE1
10.4223
FIE2
7.4192
FIS1W
12.3430
FIS2W
10.6810
Remark The same power consumption value
is applied to the same type buffer.
Design Manual A13826EJ6V0DM
307
APPENDIX K DATA
Table K-5. Output Buffer Power Consumption
Block Type
PO
PCO
FO09
0.2257
0.0264
FO04
0.2374
0.0268
FO01
0.2984
0.0271
FO02
0.3829
0.0272
FO03
0.6270
0.0263
FO06
1.0067
0.0254
FE09
0.1675
0.0271
FE04
0.1621
0.0275
FE01
0.2461
0.0266
FE02
0.2598
0.0265
FE03
0.4336
0.0266
FE06
0.7298
0.0255
Table K-6. Oscillator Power Consumption (Reference Values) (V DD = 5.0 V ±10%, TA = –40 to +85°C)
Frequency
(MHz)
Cin (pF)
External Constant Used
Cout (pF)
LT (µ H)
Duty
(%)
CT (pF)
VSTART
(V)
VHOLD
(V)
POSCS
(mW)
4
100
100
53.0
1.97
1.97
27.50
8
68
68
51.2
1.23
1.23
33.00
16
39
39
50.7
2.23
2.20
63.25
32
15
15
53.6
2.17
2.14
107.25
48
1
15
50.4
2.56
2.47
123.75
50
5
5
48.3
3.77
3.58
154.00
3.3
68
VSTART: Oscillation start voltage
VHOLD: Oscillation hold voltage
Table K-7. Compensation Coefficient (K1, K2)
(VDD = 5.0 V ±10%, TA = –40 to +85 °C)
308
TYP. Value
MAX. Value
Compensation coefficient (K1)
1.00
1.40
Compensation coefficient (K2)
0.00
0.15
Design Manual A13826EJ6V0DM
APPENDIX K DATA
Table K-8. Maximum Allowable Power Consumption (TA = 85 °C, T J = 125°C)
Unit: W
Package
Number of Pins µPD65880 µPD65881 µPD65882 µPD65883 µPD65884 µPD65885 µPD65887 µPD65889 µPD65890 µPD65893
QFP
160
—
—
—
—
—
0.70
0.75
(fine pitch)
208
—
—
—
—
—
0.76
0.83
240
—
—
—
—
—
—
0.81
304
—
—
—
—
—
—
—
48
0.31
0.37
0.40
—
—
—
64
—
0.41
0.43
0.52
0.47
TQFP
LQFP
80
—
—
0.30
0.37
44
0.30
0.34
0.39
0.43
100
—
—
0.35
0.36
0.44
160
—
—
—
—
0.64
—
—
—
0.93
1.00
1.05
0.88
1.02
1.11
—
1.00
1.05
—
—
—
—
0.48
—
—
—
0.76
0.81
Remark Blank: Under evaluation or study, —: Cannot be used
Table K-9. Thermal Resistance (1/2)
(a) Without wind (with no forced air cooling)
Unit: °C/W
Package
Number of Pins µPD65880 µPD65881 µPD65882 µPD65883 µPD65884 µPD65885 µPD65887 µPD65889 µPD65890 µPD65893
QFP
160
—
—
—
—
—
57
53
—
—
—
(fine pitch)
208
—
—
—
—
—
52
48
43
40
38
240
—
—
—
—
—
49
45
39
36
—
—
—
—
40
38
89
84
82
—
—
—
52
49
TQFP
304
—
—
—
48
128
108
98
97
92
76
108
64
LQFP
80
—
—
130
44
130
115
103
93
100
—
—
114
111
160
—
—
—
62
Remark Blank: Under evaluation or study, —: Cannot be used
(b) With 1 m/s forced air cooling
Unit: °C/W
Package
Number of Pins µPD65880 µPD65881 µPD65882 µPD65883 µPD65884 µPD65885 µPD65887 µPD65889 µPD65890 µPD65893
QFP
160
—
—
—
—
—
45
41
—
—
—
(fine pitch)
208
—
—
—
—
—
43
39
35
33
32
240
—
—
—
—
—
43
38
34
31
304
—
—
—
—
—
—
—
34
33
48
107
87
68
80
76
62
79
74
62
—
—
—
40
37
TQFP
64
LQFP
80
—
—
111
88
44
116
103
90
81
100
—
—
104
96
160
—
—
—
56
Remark Blank: Under evaluation or study, —: Cannot be used
Design Manual A13826EJ6V0DM
309
APPENDIX K DATA
Table K-9. Thermal Resistance (2/2)
(c) With 2 m/s forced air cooling
Unit: °C/W
Package
Number of Pins µPD65880 µPD65881 µPD65882 µPD65883 µPD65884 µPD65885 µPD65887 µPD65889 µPD65890 µPD65893
QFP
160
—
—
—
—
—
41
37
—
—
—
(fine pitch)
208
—
—
—
—
—
43
38
34
32
30
240
—
—
—
—
—
40
36
32
29
304
—
—
—
—
—
—
—
32
30
48
96
78
60
76
72
71
66
53
—
—
—
36
33
TQFP
64
LQFP
57
80
—
—
106
81
44
104
91
78
69
100
—
—
94
89
160
—
—
—
51
Remark Blank: Under evaluation or study, —: Cannot be used
310
Design Manual A13826EJ6V0DM
APPENDIX K DATA
Table K-10. Wiring Capacitance Estimate (Wiring Length Converted to F/I Value)
(1/2)
Master
Pin-Pair Count
1
2
3
4
5
6
µPD65880
1.621
3.266
4.911
6.556
8.200
9.845
µPD65881
1.641
3.356
5.070
6.785
8.500
10.214
µPD65882
1.684
3.552
5.421
7.289
9.158
11.027
µPD65883
1.730
3.767
5.803
7.840
9.876
11.913
µPD65884
1.757
3.892
6.026
8.161
10.295
12.430
µPD65885
1.780
3.997
6.213
8.430
10.647
12.863
µPD65887
1.819
4.175
6.532
8.889
11.245
13.602
µPD65889
1.861
4.372
6.883
9.393
11.904
14.414
µPD65890
1.904
4.569
7.233
9.897
12.562
15.226
µPD65893
1.943
4.747
7.552
10.356
13.160
15.965
(2/2)
Master
Pin-Pair Count
7
8
9
10
11 to 15
16 to 20
µPD65880
11.490
13.135
14.779
16.424
24.648
32.871
µPD65881
11.929
13.644
15.358
17.073
25.647
34.220
µPD65882
12.895
14.764
16.632
18.501
27.844
37.187
µPD65883
13.949
15.986
18.022
20.059
30.241
40.424
µPD65884
14.564
16.699
18.833
20.967
31.640
42.312
µPD65885
15.080
17.297
19.513
21.730
32.813
43.897
µPD65887
15.958
18.315
20.672
23.028
34.811
46.594
µPD65889
16.925
19.435
21.946
24.456
37.009
49.561
µPD65890
17.891
20.555
23.220
25.884
39.206
52.528
µPD65893
18.769
21.574
24.378
27.182
41.204
55.226
Design Manual A13826EJ6V0DM
311
APPENDIX K DATA
Table K-11. tr and tf Calculation Coefficients of Output Buffer (VDD = 5.0 V, TA = 25 °C)
Buffer Type
Normal type
Output Level
CMOS
Low-noise type
CMOS
Drive Capability
t r0
Ftr
t f0
Ftf
I OL = 3.0 mA
0.817
0.1562
1.279
0.2654
I OL = 6.0 mA
0.611
0.1035
0.716
0.1319
I OL = 9.0 mA
0.502
0.0611
0.603
0.0867
I OL = 12.0 mA
0.388
0.0510
0.443
0.0651
I OL = 18.0 mA
0. 394
0.0345
0.494
0.0426
I OL = 24.0 mA
0.413
0.0266
0.623
0.0305
I OL = 3.0 mA
1.210
0.1532
1.554
0.2621
I OL = 6.0 mA
1.112
0.1018
1.118
0.1296
I OL = 9.0 mA
1.097
0.0631
0.990
0.0876
I OL = 12.0 mA
1.116
0.0542
0.938
0.0678
I OL = 18.0 mA
1.213
0.0415
0.935
0.0492
I OL = 24.0 mA
1.333
0.0352
1.013
0.0389
Remark The rise and fall times of the output buffer are specified by the following conditions:
CMOS level = VDD × 10% to VDD × 90%, input signal tr, tf = 0.4 ns (VDD = 5.0 V)
Table K-12. t r and t f Calculation Coefficients of Output Buffer (V DD = 3.3 V, T A = 25 °C)
Buffer Type
Normal type
Output Level
CMOS
Low-noise type
CMOS
Drive Capability
t r0
Ftr
t f0
Ftf
I OL = 6.0 mA
0.817
0.1562
1.279
0.2654
I OL = 9.0 mA
0.611
0.1035
0.716
0.1319
I OL = 3.0 mA
I OL = 12.0 mA
0.502
0.0611
0.603
0.0867
I OL = 18.0 mA
0.388
0.0510
0.443
0.0651
I OL = 24.0 mA
0. 394
0.0345
0.494
0.0426
I OL = 3.0 mA
I OL = 6.0 mA
1.210
0.1532
1.554
0.2621
I OL = 9.0 mA
1.112
0.1018
1.118
0.1296
I OL = 12.0 mA
1.097
0.0631
0.990
0.0876
I OL = 18.0 mA
1.116
0.0542
0.938
0.0678
I OL = 24.0 mA
1.213
0.0415
0.935
0.0492
Remarks 1. The rise and fall times of the output buffer are specified by the following conditions:
CMOS level = VDD × 10% to VDD × 90%, input signal tr, tf = 0.4 ns (V DD = 3.3 V)
2. Blank: Under study
312
Design Manual A13826EJ6V0DM
APPENDIX K DATA
Table K-13. Recommended Load Capacitance Ranges of Output Buffers (@5.0 V)
Buffer Type
Normal type
Output Level
CMOS
Low-noise type
CMOS
I OL (mA)
3.0
Recommended Load
Capacitance Range (pF)
Example of
Corresponding Block
0 to 40
FO09
6.0
0 to 110
FO04
9.0
25 to 130
FO01
12.0
100 to 210
FO02
18.0
120 to 300
FO03
24.0
170 to 300
FO06
3.0
0 to 40
FE09
6.0
0 to 100
FE04
9.0
15 to 150
FE01
12.0
20 to 200
FE02
18.0
50 to 200
FE03
24.0
40 to 210
FE06
Table K-14. Recommended Load Capacitance Ranges of Output Buffers (@3.3 V)
Buffer Type
Normal type
Low-noise type
Output Level
CMOS
CMOS
I OL (mA)
Recommended Load
Capacitance Range (pF)
Example of
Corresponding Block
3.0
Under study
FO09
6.0
0 to 40
FO04
9.0
0 to 110
FO01
12.0
25 to 130
FO02
18.0
100 to 210
FO03
24.0
120 to 300
FO06
3.0
Under study
FE09
6.0
0 to 40
FE04
9.0
0 to 100
FE01
12.0
15 to 150
FE02
18.0
20 to 200
FE03
24.0
50 to 200
FE06
Design Manual A13826EJ6V0DM
313
APPENDIX K DATA
Table K-15. Reference Time Ranges for Simultaneous Operation (TYP.)
Buffer Type
Load Capacitance C L (pF)
0 ≤ CL ≤ 50
50 < C L ≤ 200
200 < CL ≤ 300
3.0 mA
≤ 2.5 ns
≤ 4.0 ns
≤ 6.0 ns
6.0 mA
≤ 3.0 ns
≤ 4.0 ns
≤ 6.0 ns
9.0 mA
≤ 3.0 ns
≤ 4.0 ns
≤ 6.0 ns
12.0 mA
≤ 3.0 ns
≤ 4.0 ns
≤ 6.0 ns
18.0 mA
≤ 3.0 ns
≤ 4.0 ns
≤ 6.0 ns
24.0 mA
≤ 3.0 ns
≤ 4.0 ns
≤ 6.0 ns
Table K-16. Permissible Number of Simultaneous Operation Pins Between 3 GND Pins (I OL = 12 mA)
(a) 5.0 V (CMOS level input)
Valid Number of GND
1
Output Load Capacitance (C L)
15 pF
30 pF
50 pF
100 pF
150 pF
200 pF
Note
13.0
8.5
6.3
4.8
4.3
3.8
3
19.5
12.5
10
7.5
6.5
6
(b) 5.0 V (TTL level and TTL/CMOS levels coexisting)
Valid Number of GND
Output Load Capacitance (C L)
15 pF
30 pF
50 pF
100 pF
150 pF
200 pF
1Note
5.2
4
2.8
1.9
1.6
1.5
3
8
5
4.5
3
2.5
2.5
100 pF
150 pF
200 pF
(c) 3.0 V and 3.3 V
Valid Number of GND
1
Output Load Capacitance (C L)
15 pF
30 pF
50 pF
Note
4.3
4.0
3.8
3.5
3.3
3.0
3
6.5
6
6
5.5
5
5
Note For a small-pin-count package
Remarks 1. Calculate the valid amount of capacitance not in the table by complementing linearly.
2. Count adjacent GND pins, including those sandwiching a corner on the layout, as one.
314
Design Manual A13826EJ6V0DM
APPENDIX K DATA
Table K-17. Coefficient of Number of Simultaneous Operation Pins
(a) 5.0 V
Output Level
CMOS normal type
CMOS low-noise type
I OL (mA)
Coefficient
Example of Corresponding Block
3.0
0.467
FO09, B00T
6.0
0.746
FO04, B00E
9.0
0.757
FO01, B008
12.0
1.000
FO02, B007
18.0
1.189
FO03, B009
24.0
1.266
FO06, B00H
3.0
0.287
FE09, BE0T
6.0
0.465
FE04, BE0E
9.0
0.483
FE01, BE08
12.0
0.500
FE02, BE07
18.0
0.530
FE03, BE09
24.0
0.625
FE06, BE0H
(b) 3.0 V and 3.3 V
Output Level
CMOS normal type
CMOS low-noise type
I OL (mA)
Coefficient
Example of Corresponding Block
3.0
0.395
FO09, B00T
6.0
0.575
FO04, B00E
9.0
0.618
FO01, B008
12.0
1.000
FO02, B007
18.0
1.076
FO03, B009
24.0
1.116
FO06, B00H
3.0
0.277
FE09, BE0T
6.0
0.380
FE04, BE0E
9.0
0.453
FE01, BE08
12.0
0.500
FE02, BE07
18.0
0.523
FE03, BE09
24.0
0.533
FE06, BE0H
Design Manual A13826EJ6V0DM
315
APPENDIX K DATA
Table K-18. CTS Blocks (Reference)
Block Name
Number of
Block Inserted
Stages
Number of Branches on Clock Line
32 to 128
FC42
2
F144
FC82
2
F148
128 to 1280
(33:1.70)
±0.20 ns
F144
×
FC84
4
F148
×
5120 or more
×
×
×
×
×
×
×
±0.30 ns
(33:1.70)
±0.20 ns
4
2560 to 5120
(33:2.40)
×
FC44
1280 to 2560
(85:1.40)
±0.15 ns
×
(33:2.10)
±0.35 ns
(85:1.80)
±0.35 ns
(85:2.60)
(85:3.00)
±0.15 ns
±0.25 ns
(165:3.40)
±0.40 ns
Remark Each symbol has the following meaning.
×: Cannot be used
: Can be used
: Preferred (recommended)
The values in parentheses represent the estimated number of inserted blocks (the first value), followed
by the estimated delay time. The value on the next line is the estimated clock skew value, which varies
slightly according to the conditions.
Table K-19. List of Resonator Evaluations
Material
Ceramic
Resonator
Frequency
Manufacturer
(MHz)
Murata Mfg.
Co., Ltd.
Product Name
Capacitor
16
CSA16.00MXZ040
External
32
Recommended External Constant
CIN(pF)
COUT(pF)
30
30
22
CSA32.00MXZ040
10
10
22
32
CSACW3200MX01
10
10
22
40
CSA40.00MXZ040
7
7
22
Internal
Rd(Ω)
2
CSTS0200MG06
2
CSTCC2.00MG0H6
–
–
1.5K
–
–
1.5K
4
CSTS0400MG06
–
–
680
4
CSTCC4.00MG0H6
–
–
680
8
CSTS0800MG06
–
–
220
Circuit
Configuration
Note 1
<1>
<2>
8
CSTCC8.00MG0H6
–
–
220
16
CST16.00MXW040
–
–
22
<1>
16
CSTCV16.00MXJ0C4
–
–
100
<2>
40
CSTCW4000MX01
–
–
22
Kyocera
4.00
PBRC4.00HR
–
–
3.3K
Corporation
8.00
PBRC8.00HR
Internal
–
–
1.5K
16.00
SSR16.00BR-MN1
–
–
330
20.00
SSR20.00BR-H8S
–
–
100
33.86
SSR33.86BR-ALPNote 2
–
–
–
<2>
<3>
Notes 1. The figures in this column correspond to the figures on Figure K-19 Oscillator Configuration Diagram.
2. Surface mount type. A 6.8 kΩ external feedback resistor is required for OSO7 (OSO1).
Remarks 1. Oscillation environment: VDD = 5.0 ±0.5 V, TA = –40 to +85°C
2. External feedback resistor of OSO9: 1 MΩ
316
Design Manual A13826EJ6V0DM
APPENDIX K DATA
Table K-20. Memory Blocks
(a) Single-port RAM
16
32
64
128
256
512
1K
2K
4
RB47
RB49
RB4B
RB4D
RB4F
RB4H
RB4M
RB4S
8
RB87
RB89
RB8M
10
16
RBC7
RBC9
20
32
RBH7
RBH9
40
RB8B
RB8D
RB8F
RB8H
RBAB
RBAD
RBAF
RBAH
RBCB
RBCD
RBCF
RBCH
RBEB
RBED
RBEF
RBEH
RBHB
RBHD
RBHF
RBHH
RBKB
RBKD
RBKF
RBKH
RBCM
(b) Dual-port RAM
16
32
64
128
256
512
4
R947
R949
R94B
R94D
R94F
R94H
8
R987
R989
R98B
R98D
R98F
R9AB
R9AD
R9C7
R9C9
R9CB
R9CD
R9EB
R9ED
10
16
20
32
40
R9H7
R9H9
R9CF
R9HB
R9KB
Design Manual A13826EJ6V0DM
317
[MEMO]
318
Design Manual A13826EJ6V0DM
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