DATA SHEET MOS INTEGRATED CIRCUIT µPD69A 4-BIT SINGLE-CHIP MICROCONTROLLER FOR INFRARED REMOTE CONTROL TRANSMISSION DESCRIPTION With its 2.0 V low-voltage operation, carrier generator for infrared remote control transmission, standby release function through key input, and programmable timer, the µPD69A is ideal for infrared remote control transmitters. A one-time PROM product, the µPD6P9, has also been provided for the µPD69A for program evaluation or smallquantity production. FEATURES • Program memory (ROM): 4,074 × 10 bits • Data memory (RAM): 128 × 4 bits • On-chip carrier generator for infrared remote control: Each high-/low-level width can be set from 250 ns to 64 µs (@ fX = 4 MHz operation) via modulo registers • 9-bit programmable timer: 1 channel • Instruction execution time: 16 µs (normal instruction execution @ fX = 4 MHz operation) 8 µs (high-speed instruction execution @ fX = 4 MHz operation) (mask option) • Stack level: 1 level (Stack RAM is multiplexed with data memory RF.) • I/O pins (KI/O): 8 • Input pins (KI): 4 • Sense input pins (S0, S2): 2 • S1/LED pin (I/O): 1 (when in output mode, this is the remote control transmission display pin) • Power supply voltage: VDD = 2.0 to 3.6 V VDD = 1.8 to 3.6 V (mask option) • Operating ambient temperature: TA = –40 to +85°C • Oscillator frequency: fX = 3.5 to 4.5 MHz • On-chip POC circuit and RAM retention detector • Capacitor for oscillator: 15 pF (mask option) APPLICATIONS Infrared remote control transmitters (for AV and household electrical appliances) The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all products and/or types are available in every country. Please check with NEC Electronics sales representative for availability and additional information. Document No. U16363EJ1V0DS00 (1st edition) Date Published November 2002 N CP(K) Printed in Japan © µPD69A ORDERING INFORMATION Part Number µPD69AMC-×××-5A4 Package 20-pin plastic SSOP (7.62 mm (300)) Remark ××× indicates ROM code suffix. PIN CONFIGURATION (TOP VIEW) 20-pin plastic SSOP (7.62 mm (300)) • µPD69AMC-×××-5A4 KI/O6 1 20 KI/O5 KI/O7 2 19 KI/O4 S0 3 18 KI/O3 S1/LED 4 17 KI/O2 REM 5 16 KI/O1 VDD 6 15 KI/O0 XOUT 7 14 KI3 XIN 8 13 KI2 GND 9 12 KI1 10 11 KI0 S2 Caution The pin numbers of KI and KI/O are in the reverse order of those in the µPD6600A, and 6124A. 2 Data Sheet U16363EJ1V0DS µPD69A BLOCK DIAGRAM Carrier generator REM CPU core 4 Port KI 4 KI0 to KI3 8 Port KI/O 8 KI/O0 to KI/O7 3 Port S 3 S0, S1/LED, S2 ROM 9-bit timer S1/LED RAM XIN System control XOUT VDD GND LIST OF FUNCTIONS µPD69A Item ROM capacity µPD6P9 4,074 × 10 bits Mask ROM One-time PROM RAM capacity 128 × 4 bits Stack 1 level (multiplexed with RF of RAM) I/O pins • • • • Number of keys • 32 • 56 (when extended by key extension input) Clock frequency Ceramic oscillation • fX = 3.5 to 4.5 MHz Instruction execution time 16 µs or 8 µsNote (@ fX = 4 MHz) Carrier frequency Each high-/low-level width can be set from 250 ns to 64 µs (@ fX = 4 MHz operation) via modulo registers Timer 9-bit programmable timer: 1 channel, timer clock: fX/64 POC circuit On-chip RAM retention detector On-chip Key input (KI): Key I/O (K I/O): Key extended input (S0, S1, S2): Remote control transmission display output (LED): 4 8 3 1 (multiplexed with S1 pin) Capacitor for oscillation (15 pF) Mask option Set to be used/not used in device Supply voltage VDD = 2.0 to 3.6 V or V DD = 1.8 to 3.6 VNote VDD = 2.2 to 3.6 V Operating ambient temperature T A = –40 to +85°C Package 20-pin plastic SSOP (7.62 mm (300)) Note Can be selected by mask option. Data Sheet U16363EJ1V0DS 3 µPD69A CONTENTS 1. PIN FUNCTIONS ............................................................................................................................ 1.1 List of Pin Functions .......................................................................................................... 1.2 Pin I/O Circuits .................................................................................................................... 1.3 Connection of Unused Pins .............................................................................................. 6 6 7 8 2. INTERNAL CPU FUNCTIONS ..................................................................................................... 2.1 Program Counter (PC) ........................................................................................................ 2.2 Stack Pointer (SP) ............................................................................................................... 2.3 Address Stack Register (ASR (RF)) ................................................................................. 2.4 Program Memory (ROM) .................................................................................................... 2.5 Data Memory (RAM) ............................................................................................................ 2.6 Data Pointer (DP) ................................................................................................................ 2.7 Accumulator (A) .................................................................................................................. 2.8 Arithmetic and Logic Unit (ALU) ...................................................................................... 2.9 Flags ..................................................................................................................................... 9 9 9 9 10 11 12 12 12 13 2.9.1 Status flag (F) ........................................................................................................................... 13 2.9.2 Carry flag (CY) .......................................................................................................................... 13 3. PORT REGISTERS (PX) .............................................................................................................. 14 3.1 KI/O Port (P0) ........................................................................................................................ 15 3.2 KI Port/Special Ports (P1) .................................................................................................. 15 3.3 3.2.1 KI port (P11: bits 4 to 7 of P1) ................................................................................................... 3.2.2 S0 port (bit 2 of P1) ................................................................................................................... 16 3.2.3 S1/LED (bit 3 of P1) .................................................................................................................. 16 3.2.4 S2 port (bit 1 of P1) ................................................................................................................... 16 Control Register 0 (P3) ....................................................................................................... 17 3.3.1 3.4 RAM retention flag (bit 3 of P3) ............................................................................................... 18 Control Register 1 (P4) ....................................................................................................... 19 4. TIMER .............................................................................................................................................. 4.1 Timer Configuration ........................................................................................................... 4.2 Timer Operation .................................................................................................................. 4.3 Carrier Output...................................................................................................................... 4.4 15 20 20 21 23 4.3.1 Carrier output generator ........................................................................................................... 23 4.3.2 Carrier output control ................................................................................................................ 24 Software Control of Timer Output .................................................................................... 26 5. STANDBY FUNCTION ................................................................................................................... 5.1 Outline of Standby Function ............................................................................................. 5.2 Standby Mode Setting and Release ................................................................................. 5.3 Standby Mode Release Timing .......................................................................................... 27 27 28 30 6. RESET ............................................................................................................................................. 31 4 Data Sheet U16363EJ1V0DS µPD69A 7. POC CIRCUIT ................................................................................................................................. 32 7.1 Functions of POC Circuit ................................................................................................... 33 7.2 Oscillation Check at Low Supply Voltage ........................................................................ 34 8. SYSTEM CLOCK OSCILLATOR .................................................................................................. 35 9. MASK OPTIONS ............................................................................................................................. 36 10. INSTRUCTION SET ....................................................................................................................... 10.1 Machine Language Output by Assembler ....................................................................... 10.2 Circuit Symbol Description ............................................................................................... 10.3 Mnemonic to/from Machine Language (Assembler Output) Contrast Table .............. 10.4 Accumulator Manipulation Instructions .......................................................................... 10.5 I/O Instructions .................................................................................................................... 10.6 Data Transfer Instructions ................................................................................................. 10.7 Branch Instructions ............................................................................................................ 10.8 Subroutine Instructions ..................................................................................................... 10.9 Timer Operation Instructions ............................................................................................ 10.10 Other ..................................................................................................................................... 37 37 38 39 43 46 47 49 50 51 54 11. ASSEMBLER RESERVED WORDS ............................................................................................ 56 11.1 Mask Option Directives ...................................................................................................... 56 11.1.1 OPTION and ENDOP quasi directives ..................................................................................... 56 11.1.2 Mask option definition quasi directives .................................................................................... 56 12. ELECTRICAL SPECIFICATIONS .................................................................................................. 57 13. CHARACTERISTIC CURVES (REFERENCE VALUES) (NORMAL INSTRUCTION EXECUTION) ...................................................................................... 61 14. APPLICATION CIRCUIT EXAMPLE ............................................................................................ 62 15. PACKAGE DRAWINGS .................................................................................................................. 65 16. RECOMMENDED SOLDERING CONDITIONS ........................................................................... 66 APPENDIX A. DEVELOPMENT TOOLS ............................................................................................ 67 APPENDIX B. FUNCTIONAL COMPARISON BETWEEN µPD69A AND OTHER PRODUCTS ......................................................................................... 68 APPENDIX C. EXAMPLE OF REMOTE-CONTROL TRANSMISSION FORMAT (in the case of NEC transmission format in command one-shot transmission mode) .............. 69 Data Sheet U16363EJ1V0DS 5 µPD69A 1. PIN FUNCTIONS 1.1 List of Pin Functions Pin No. Symbol Function 1 KI/O0 to KI/O7 8-bit I/O port. Input/output can be specified in 8-bit units. 2 In input mode, the use of a pull-down resistor can be 15 to 20 specified. In output mode, these pins can be used as key scan outputs from a key matrix. Output Format CMOS push-pullNote 1 After Reset High-level output 3 S0 Input port. Can also be used as a key return input from a key matrix. In input mode, the use of a pull-down resistor for the S0 and S1 ports can be specified by software in 2-bit units. If input mode is canceled by software, this pin is placed in OFF mode and enters a high-impedance state. 4 S1/LED I/O port. In input mode (S1), this pin can also be used as a key return input from a key matrix. The use of a pull-down resistor for the S0 and S1 ports can be specified by software in 2-bit units. In output mode (LED), this pin becomes the remote control transmission display output (active low). When the remote control carrier is output from the REM output, this pin outputs a low level from the LED output in synchronization with the REM signal. CMOS push-pull High-level output (LED) 5 REM Infrared remote control transmission output. This output is active high. Each carrier high-/low-level width can be freely set in a range of 250 ns to 64 µs (@ fX = 4 MHz) by software. CMOS push-pull Low-level output 6 VDD Power supply — — 7 8 XOUT XIN Pins for connecting ceramic resonators for the system clock. A capacitor (15 pF) for the oscillator can be specified by a mask option. — Low level (oscillation stopped) 9 GND GND — — 10 S2 Input port. The use of STOP mode release for the S2 port can be specified by software. When used as a key input from a key matrix, enable the use of STOP mode release (at this time, a pull-down resistor is connected internally.) When STOP mode release is disabled, this pin can be used as an input port that does not release the STOP mode even if the release condition is established (at this time, a pull-down resistor is not connected internally.) — Input (high-impedance, STOP mode release cannot be used) — Input (low-level) 11 to 14 KI0 to KI3Note 2 4-bit input port. These pins can also be used as a key return inputs from a key matrix. The use of a pull-down resistor can be specified by software in 4-bit units. — High-impedance (OFF mode) Notes 1. Be careful about this because the drive capacity of the low-level output side is held low. 2. In order to prevent malfunction, be sure to input a low level to one or more of pins KI0 to KI3 when POC is released by supply voltage rising (Can be left open. When open, leave the pull-down resistor connected). 6 Data Sheet U16363EJ1V0DS µPD69A 1.2 Pin I/O Circuits The I/O circuits of pins of the µPD69A are shown in partially simplified forms below. (1) K I/O0 to K I/O7 (4) S 0 VDD Data Input buffer Output latch P-ch OFF mode N-chNote Output disable Selector Standby release N-ch Pull-down flag Input buffer N-ch (5) S1/LED Note The drive capacity is held low. VDD REM output latch (2) K I0 to K I3 Standby release P-ch Output disable Input buffer N-ch Standby release Input buffer Pull-down flag N-ch N-ch Pull-down flag (3) REM (6) S 2 VDD Standby release Input buffer P-ch Data Output latch N-ch Carrier generator STOP release ON/OFF Data Sheet U16363EJ1V0DS N-ch 7 µPD69A 1.3 Connection of Unused Pins The following connections are recommended for unused pins. Table 1-1. Connection of Unused Pins Connection Pin Inside the Microcontroller KI/O Input mode Output mode REM — Outside the Microcontroller Leave open. High-level output — S1/LED Output mode (LED) setting S0 OFF mode setting S2 — K1 — Directly connect to GND. Caution The I/O mode and the pin output level are recommended to be fixed by setting them repeatedly in each loop of the program. 8 Data Sheet U16363EJ1V0DS µPD69A 2. INTERNAL CPU FUNCTIONS 2.1 Program Counter (PC): 12 Bits The program counter (PC) is a binary counter that holds the address information of the program memory. Figure 2-1. Program Counter Configuration PC PC11 PC10 PC9 PC8 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 The PC contains the address of the instruction that should be executed next. Normally, the counter contents are automatically incremented in accordance with the instruction length (byte count) each time an instruction is executed. However, when executing jump instructions (JMP, JC, JNC, JF, JNF), the PC contains the jump destination address written in the operand. When executing the subroutine call instruction (CALL), the call destination address written in the operand is entered in the PC after the PC contents at the time are saved in the address stack register (ASR). If the return instruction (RET) is executed after the CALL instruction is executed, the address saved in the ASR is restored to the PC. After reset, the value of the PC becomes “000H”. 2.2 Stack Pointer (SP): 1 Bit This is a 1-bit register that holds the status of the address stack register. The stack pointer contents are incremented when the call instruction (CALL) is executed and decremented when the return instruction (RET) is executed. When reset, the stack pointer contents are cleared to 0. When the stack pointer overflows (stack level 2 or more) or underflows, the CPU is defined as hung up, a system reset signal is generated, and the PC becomes 000H. As no instruction is available to set a value directly for the stack pointer, it is not possible to operate the pointer by means of a program. 2.3 Address Stack Register (ASR (RF)): 12 Bits The address stack register saves the return address of the program after a subroutine call instruction is executed. The lower 8 bits are allocated in RF of the data memory as a alternate-function RAM. The register holds the ASR value even after the RET instruction is executed. After reset, it holds the previous data (undefined when turning on the power). Caution If RF is accessed as the data memory, the higher 4 bits of the µPD69A become undefined. Figure 2-2. Address Stack Register Configuration RF ASR ASR11 ASR10 ASR9 ASR8 ASR7 ASR6 ASR5 ASR4 Data Sheet U16363EJ1V0DS ASR3 ASR2 ASR1 ASR0 9 µPD69A 2.4 Program Memory (ROM): 4,074 Steps × 10 Bits The ROM consists of 10 bits per step, and is addressed by the program counter. The program memory stores programs and table data, etc. The 22 steps from FEAH to FFFH of the µPD69A cannot be used in the test program area. Figure 2-3. Program Memory Map 10 bits 00 0H Page 0 3F FH 40 0H Page 1 7F FH 80 0H Page 2 BF F H C0 0 H FE 9 H FE A H Page 3 Note Test program area FF F H Note The unmounted area and test program area are designed so that a program or data placed in either of them by mistake is returned to the 000H address. 10 Data Sheet U16363EJ1V0DS µPD69A 2.5 Data Memory (RAM): 128 × 4 Bits The data memory, which is a static RAM consisting of 32 × 4 bits × 4 pages, is used to retain processed data. The data memory is sometimes processed in 8-bit units. R0 of page 0 can be used as the ROM data pointer. RF of page 0 is also used as the ASR. After reset, R0 of page 0 is cleared to 00H and R1 to RF of page 0 and pages 1 to 3 retain the previous data (undefined when turning on the power). Figure 2-4. Data Memory Configuration Pages 0 to 3 Note 1 R1n (higher 4 bits) R0n (lower 4 bits) →Note 2 R0 R10 R00 R1 R11 R01 R2 R12 R02 R3 R13 R03 R4 R14 R04 R5 R15 R05 R6 R16 R06 R7 R17 R07 R8 R18 R08 R9 R19 R09 RA R1A R0A RB R1B R0B RC R1C R0C RD R1D R0D RE R1E R0E →Note 3 RF R1F R0F Notes 1. Pages 0 to 3 can be switched using bits 0 and 1 of control register 0. 2. R0 of page 0 alternately functions as the ROM data pointer (refer to 2.6 Data Pointer (DP)). 3. RF of page 0 alternately functions as the PC address stack (refer to 2.3 Address Stack Register (ASR (RF)). Data Sheet U16363EJ1V0DS 11 µPD69A 2.6 Data Pointer (DP): 12 Bits The ROM data table can be referenced by setting the ROM address in the data pointer to call the ROM contents. The lower 8 bits of the ROM address are specified by R0 of the data memory; and the higher 4 bits by bits 4 to 7 of the P3 register (CR0). After reset, the pointer contents become 000H. Figure 2-5. Data Pointer Configuration P3 register P3 b7 b6 b5 b4 DP11 DP10 DP9 DP8 R10 DP7 DP6 R00 DP5 DP4 DP3 DP2 DP1 DP0 R0 2.7 Accumulator (A): 4 Bits The accumulator, which refers to a register consisting of 4 bits, plays a leading role in performing various operations. After reset, the accumulator contents are left undefined. Figure 2-6. Accumulator Configuration A3 A2 A1 A0 A 2.8 Arithmetic and Logic Unit (ALU): 4 Bits The arithmetic and logic unit (ALU), which refers to an arithmetic circuit consisting of 4 bits, executes simple (mainly logical) operations. 12 Data Sheet U16363EJ1V0DS µPD69A 2.9 Flags 2.9.1 Status flag (F) Pin and timer statuses can be checked by executing the STTS instruction to check the status flag. The status flag is set (to 1) in the following cases. • If the condition specified with the operand is met when the STTS instruction is executed • When standby mode is released. • When the release condition is met at the point of executing the HALT instruction. (In this case, the system does not enter the standby mode.) Conversely, the status flag is cleared (to 0) in the following cases: • If the condition specified with the operand is not met when the STTS instruction is executed. • When the status flag has been set (to 1), the HALT instruction executed, but the release condition is not met at the point of executing the HALT instruction. (In this case, the system does not enter the standby mode.) Table 2-1. Conditions for Status Flag (F) to Be Set by STTS Instruction Operand Value of STTS Instruction Condition for Status Flag (F) to Be Set b3 b2 b1 b0 0 0 0 0 High level is input to at least one of KI pins. 0 1 1 High level is input to at least one of KI pins. 1 1 0 High level is input to at least one of KI pins. 1 0 1 The down counter of the timer is 0. 1 Either of the combinations of b2, b1, and b0 above. [The following condition is added in addition to the above.] High level is input to at least one of S0Note 1, S 1Note 1, or S2Note 2 pins. Notes 1. The S0 and S1 pins must be set to input mode (bit 2 and bit 0 of the P4 register are set to 0 and 1, respectively). 2. The use of STOP mode release for the S2 pin must be enabled (bit 3 of the P4 register is set to 1). 2.9.2 Carry flag (CY) The carry flag is set (to 1) in the following cases: • If the ANL instruction or the XRL instruction is executed when bit 3 of the accumulator is 1 and bit 3 of the operand is 1. • If the RL instruction or the RLZ instruction is executed when bit 3 of the accumulator is 1. • If the INC instruction or the SCAF instruction is executed when the value of the accumulator is 0FH. The carry flag is cleared (to 0) in the following cases: • If the ANL instruction or the XRL instruction is executed when at least either bit 3 of the accumulator or bit 3 of the operand is 0. • If the RL instruction or the RLZ instruction is executed when bit 3 of the accumulator is 0. • If the INC instruction or the SCAF instruction is executed when the value of the accumulator is other than 0FH. • If the ORL instruction is executed. • When data is written to the accumulator by the MOV instruction or the IN instruction. Data Sheet U16363EJ1V0DS 13 µPD69A 3. PORT REGISTERS (PX) The KI/O port, the K I port, the special ports (S0, S1/LED, S2), and the control registers are treated as port registers. After reset, the port register values are as shown below. Figure 3-1. Port Register Configuration Port register After reset P0 FFH P10 KI/O7 P00 KI/O5 KI/O6 KI/O4 KI/O3 KI/O2 KI/O1 KI/O0 ××××11×1B Note 1 P1 P11 KI3 KI2 P01 KI1 KI0 S1/LED S0 S2 – 0000×000BNote 2 P3 (control register 0) P13 DP11 DP10 P03 DP9 RAM retention flag DP8 – ID1 ID0 P4 (control register 1) P14 – 26H P04 S0/S1 KI S2 S1/LED mode KI/O mode Pull-down Pull-down STOP release – S0 mode Notes 1. ×: Refers to the value based on the KI and S2 pin state. 2. ×: Refers to the value based on decrease of power supply voltage (0 when VDD ≤ V ID) Remark VID: RAM retention detection voltage Table 3-1. Relationship Between Ports and Reading/Writing Input Mode Port Name Read Output Mode Write Read Write KI/O Pin state Output latch Output latch Output latch KI Pin state — — — S0 Pin state — Note S1/LED Pin state — Pin state S2 Pin state — Note When in OFF mode, “1” is always read. 14 Data Sheet U16363EJ1V0DS — — — — µPD69A 3.1 K I/O Port (P0) The KI/O port is an 8-bit I/O port for key scan output. I/O mode is set by bit 1 of the P4 register. If a read instruction is executed, the pin state can be read in input mode, whereas the output latch contents can be read in output mode. If a write instruction is executed, data can be written to the output latch regardless of input or output mode. After reset, the port is placed in output mode and the value of the output latch (P0) becomes 1111 1111B. The KI/O port incorporates a pull-down resistor, allowing pull-down in input mode only. Caution When a key is double-pressed, a high-level output and a low-level output may conflict at the KI/O port. To avoid this, the low-level output current of the KI/O port is held low. Therefore, be careful when using the KI/O port for purposes other than key scan output. The KI/O port is designed so that even when connected directly to VDD within the supply voltage range (normal instruction execution: VDD = 2.0 to 3.6 V, high-speed instruction execution: VDD = 1.8 to 3.6 V), no problem occurs. Table 3-2. KI/O Port (P0) Bit b7 b6 b5 b4 b3 b2 b1 b0 Name KI/O7 KI/O6 KI/O5 KI/O4 KI/O3 KI/O2 KI/O1 KI/O0 b0 to b7: When reading: In input mode, the KI/O pin’s state is read. In output mode, the KI/O pin’s output latch contents are read. Data is written to the KI/O pin’s output latch regardless of input or output mode. When writing: 3.2 K I Port/Special Ports (P1) 3.2.1 K I port (P 11 : bits 4 to 7 of P1) The KI port is a 4-bit input port for key input. The pin state can be read. The use of a pull-down resistor for the KI port can be specified in 4-bit units by software using bit 5 of the P4 register. After reset, a pull-down resistor is connected. Table 3-3. KI/Special Port Register (P1) b1 : b2 : Bit b7 b6 b5 b4 b3 b2 b1 Name KI3 KI2 KI1 KI0 S1/LED S0 S2 b0 Fixed to “1” The state of the S2 pin is read (read only). In input mode, state of the S0 pin is read (read only). In OFF mode, this bit is fixed to 1. b3 : The state of the S1/LED pin is read regardless of input/output mode (read only). b4 to b7: The state of the KI pin is read (read only). Caution In order to prevent malfunction, be sure to input a low level to one or more of pins KI0 to KI3 when POC is released by supply voltage rising (Can be left open. When open, leave the pulldown resistor connected). Data Sheet U16363EJ1V0DS 15 µPD69A 3.2.2 S 0 port (bit 2 of P1) The S0 port is an input/OFF mode port. The pin state can be read by setting this port to input mode using bit 0 of the P4 register. In input mode, the use of a pull-down resistor for the S0 and S1/LED port can be specified in 2-bit units by software using bit 4 of the P4 register. If input mode is released (thus set to OFF mode), the pin becomes high-impedance but is configured so that through current does not flow internally. In OFF mode, 1 can be read regardless of the pin state. After reset, S0 is set to OFF mode, thus becoming high-impedance. 3.2.3 S 1/LED port (bit 3 of P1) The S1/LED port is an I/O port. Input or output mode can be set using bit 2 of the P4 resister. The pin state can be read in both input mode and output mode. When in input mode, the use of a pull-down resistor for the S 0 and S 1/LED ports can be specified in 2-bit units by software using bit 4 of the P4 register. When in output mode, the pull-down resistor is automatically disconnected and this pin becomes the remote control transmission display pin (refer to 4 TIMER). After reset, S1/LED is placed in output mode, and a high level is output. 3.2.4 S 2 port (bit 1 of P1) The S2 port is an input port. Use of STOP mode release for the S2 port can be specified by bit 3 of the P4 register. When using the pin as a key input from a key matrix, enable (bit 3 of the P4 register is set to 1) the use of STOP mode release (at this time, a pull-down resistor is connected internally.) When STOP mode release is disabled (bit 3 of the P4 register is set to 0), it can be used as an input port that does not release the STOP mode even if the release condition is met (at this time, a pull-down resistor is not connected internally.) The state of the pin can be read in both cases. After reset, S2 is set to input mode where the STOP mode release is disabled, and enters a high-impedance state. 16 Data Sheet U16363EJ1V0DS µPD69A 3.3 Control Register 0 (P3) Control register 0 consists of 8 bits. The contents that can be controlled are as shown below. After reset, the register becomes 0000 ×000BNote. Note ×: Refers to the value based on a decrease of power supply voltage (0 when VDD ≤ VID) Remark VID: RAM retention detection voltage Table 3-4. Control Register 0 (P3) Bit b7 b6 DP11 DP10 DP9 DP8 b3 RAM retention flag 0 0 0 0 0 Not retainable Fixed to 0 Specification of 1 1 1 1 1 Retainable PAGE0 to PAGE3 0 0 0 0 × Name Setting After reset b0 , b1: b3 : b5 b4 DP (Data Pointer) b2 — 0 b1 b0 ID1 ID0 0 0 Specify RAM pages 0 to 3. ID1 ID0 RAM 0 0 Page 0 0 1 Page 1 1 0 Page 2 1 1 Page 3 RAM retention flag. For function details, refer to 3.3.1 RAM retention flag (bit 3 of P3). b4 to b7: Specify the higher bits of the ROM data pointer (DP8 to DP11). Data Sheet U16363EJ1V0DS 17 µPD69A 3.3.1 RAM retention flag (bit 3 of P3) The RAM retention flag indicates whether the supply voltage has fallen below the level at which the contents of the RAM are lost while the battery is being exchanged or when the battery voltage has dropped. This flag is at bit 3 of control register 0 (P3). It is cleared to 0 if the supply voltage drops below the RAM retention detection voltage (VID). If this flag is 0, it can be judged that the RAM contents have been lost or that power has just been applied. This flag can be used to initialize the RAM via software. After initializing the RAM and writing the necessary data to it, set this RAM retention flag to 1 by software. At this time, 1 means that data has been set to the RAM. Figure 3-2. Supply Voltage Transition and Detection Voltage VDD POC detection voltage (VPOC) (Refer to 7. POC CIRCUIT) VPOC (A) VID RAM retention detection voltage (VID) (B) 0V t (1) (2) (3) (4) (5) (6) RAM retention flag Set to 1 Flag contents are read Flag contents are read (1) If the supply voltage rises after the battery has been set, and exceeds V POC (POC detection voltage), reset is cleared. Because the supply voltage rises from 0 V, which is lower than VID (RAM retention detection voltage), the RAM retention flag remains in the initial status 0. (2) The supply voltage has now risen to the level at which the device can operate. Write the necessary data to the RAM and set the RAM retention flag to 1. (3) The device is reset if the supply voltage drops below V POC . At point (A) in the above figure, the RAM retention flag remains 1 because the supply voltage is higher than VID at this point. (4) If the RAM retention flag is checked by software after reset has been cleared, it is 1. This means that the contents of the RAM have not been lost. It is therefore not necessary to initialize the RAM by software. (5) The device is reset if the supply voltage drops below V POC . At point (B) in the figure, the voltage is lower than V ID. Consequently, the RAM retention flag is cleared to 0. (6) If the RAM retention flag is checked by software after reset has been cleared, it is 0. This means that the contents of the RAM may have been lost. If this case, initialize the RAM by software. 18 Data Sheet U16363EJ1V0DS µPD69A 3.4 Control Register 1 (P4) Control register 1 consists of 8 bits. The contents that can be controlled are as shown below. After reset, the register becomes 0010 0110B. Table 3-5. Control Register 1 (P4) Bit b7 Name b6 b5 b4 KI S0/S1 — — 0 Fixed Fixed 1 to 0 to 0 ON ON 0 0 1 0 b3 S2 b2 b1 b0 S1/LED KI/O S0 Pull-down Pull-down STOP release mode Setting After reset OFF OFF mode mode S1 IN OFF Enable LED OUT IN 0 1 1 0 Disable b0: Specifies the input mode of the S0 port. 0 = OFF mode (high impedance); 1 = IN (input mode). b1: Specifies the I/O mode of the KI/O port. 0 = IN (input mode); 1 = OUT (output mode). b2: Specifies the I/O mode of the S1/LED port. 0 = S1 (input mode); 1 = LED (output mode). b3: Specified the use of STOP mode release by S2 port (with/without pull-down resistor). 0 = disable (without pull-down); 1 = enable (with pull-down). b4: Specifies the use of a pull-down resistor in S0/S1 port input mode. 0 = OFF (not used); 1 = ON (used) b5: Specifies the use of a pull-down resistor for the KI port. 0 = OFF (not used); 1 = ON (used). Remark In output mode or in OFF mode, all the pull-down resistors are automatically disconnected. Data Sheet U16363EJ1V0DS 19 µPD69A 4. TIMER 4.1 Timer Configuration The timer is the block used for creating a remote control transmission pattern. As shown in Figure 4-1, it consists of a 9-bit down counter (t8 to t0), a flag (t9) permitting the 1-bit timer output, and a zero detector. Figure 4-1. Timer Configuration T T1 t9 t8 T0 t7 t6 t5 t4 t3 t2 9-bit down counter Zero detector Carrier synchronous circuit 20 t0 fX/64 Timer operation end signal (HALT # ×101B release signal) S1/LED REM t1 Count clock Carrier signal Data Sheet U16363EJ1V0DS µPD69A 4.2 Timer Operation The timer starts (counting down) when a value other than 0 is set for the down counter with a timer manipulation instruction. The timer manipulation instructions for making the timer start operation are shown below: MOV T0, A MOV T1, A MOV T, #data10 MOV T, @R0 The down counter is decremented (–1) in the cycle of 64/fX. If the value of the down counter becomes 0, the zero detector generates the timer operation end signal to stop the timer operation. At this time, if the timer is in HALT mode (HALT #×101B) waiting for the timer to stop its operation, the HALT mode is released and the instruction following the HALT instruction is executed. The output of the timer operation end signal is continued while the down counter is 0 and the timer is stopped. The following relational expression applies between the timer’s output time and the down counter’s set value. (a) Normal instruction execution Timer output time = (Set value + 1) × 64/f X – 4/f X (b) High-speed instruction execution Timer output time = (Set value + 0.5) × 64/f X – 2/f X In addition, when the timer is set successively, the timer output time is also 4/fX (normal instruction execution) or 2/fX (high-speed instruction execution) shorter than the total time. An example is shown below. Example When fX = 4 MHz MOV T, #3FFH STTS #05H HALT #05H MOV T, #232H STTS #05H HALT #05H In the case above, the timer output time is as follows. (a) Normal instruction execution (Set value + 1) × 64/f X + (Set value + 1) × 64/fX – 4/f X = (511 + 1) × 64/4 + (50 + 1) × 64/4 – 4/4 = 9.007 ms (b) High-speed instruction execution (Set value + 0.5) × 64/f X + (Set value + 0.5) × 64/f X – 2/f X = (511 + 0.5) × 64/4 + (50 + 0.5) × 64/4 – 2/4 = 8.991 ms Data Sheet U16363EJ1V0DS 21 µPD69A By setting the flag (t9) that enables the timer output to 1, the timer can output its operation status from the S1/ LED pin and the REM pin. The REM pin can also output the carrier while the timer is in operation. Table 4-1. Timer Output (at t9 = 1) S 1/LED Pin REM Pin Timer operating Low level High level (or carrier outputNote) Timer halting High level Low level Note The carrier output results if bit 9 (CARY) of the high-level period setting modulo register (MOD1) is cleared (to 0). Figure 4-2. Timer Output (When Carrier Is Not Output) (a) Normal instruction execution 4/fX Timer output time: (Set value + 1) × 64/fX – 4/fX LED REM (b) High-speed instruction execution 2/fX Timer output time: (Set value + 0.5) × 64/fX – 2/fX LED REM 22 Data Sheet U16363EJ1V0DS µPD69A 4.3 Carrier Output 4.3.1 Carrier output generator The carrier generator consists of a 9-bit counter and two modulo registers for setting the high- and low-level periods (MOD1 and MOD0 respectively). Figure 4-3. Configuration of Remote Controller Carrier Generator M1 M11 M0 M10 M01 t9 t8 t7 t6 t5 t4 t3 t2 t1 t0 CARY Modulo register for setting the high-level period (MOD1) Carrier signal 0 t8 t7 t6 M00 t5 t4 t3 t2 t1 t0 Modulo register for setting the low-level period (MOD0)Note 1 Selector F/F Match Comparator 9-bit counter 2fX Multiplier fX Clear t9Note 2 fX Notes 1. Bit 9 of the modulo register for setting the low-level period (MOD0) is fixed to 0. 2. t9: Flag that enables timer output (timer block) (see Figure 4-1 Timer Configuration) The carrier duty ratio and carrier frequency can be determined by setting the high- and low-level widths using the respective modulo registers. Each of these widths can be set in a range of 250 ns to 64 µs (@ fX = 4 MHz). The system clock multiplied by 2 is used for the 9-bit counter input (8 MHz when fX = 4 MHz). MOD0 and MOD1 are read and written using timer manipulation instructions. MOV A, M00 MOV M00, A MOV M0, #data10 MOV A, M01 MOV M01, A MOV M1, #data10 MOV A, M10 MOV M10, A MOV M0, @R0 MOV A, M11 MOV M11, A MOV M1, @R0 The values of MOD0 and MOD1 can be calculated from the following expressions. MOD0 = (2 × fX × (1 – D) × T) – 1 MOD1 = (2 × fX × D × T) – 1 Caution Be sure to input values in range of 001H to 1FFH to MOD0 and MOD1. Remark D: Carrier duty ratio (0 < D < 1) fX: Input clock (MHz) T: Carrier cycle (µs) Data Sheet U16363EJ1V0DS 23 µPD69A 4.3.2 Carrier output control Remote controller carrier can be output from the REM pin by clearing (0) bit 9 (CARY) of the modulo register for setting the high-level period (MOD1). When performing carrier output, be sure to set the timer operation after setting the MOD0 and MOD1 values. Note that a malfunction may occur if the values of MOD0 and MOD1 are changed while carrier is being output from the REM pin. Executing the timer manipulation instruction starts the carrier output from the low level. If the timer’s down counter reaches 0 during carrier output, carrier output is stopped and the REM pin becomes low level. If the down counter reaches 0 while the carrier output is high level, carrier output will stop after first becoming low level following the set period of high level. Figure 4-4. Timer Output (When Carrier Is Output) (a) Normal instruction execution Timer manipulation instruction Timer output time: (Set value + 1) × 64/fX – 4/fX LED REM 4/fX tL tH Note 1 (b) High-speed instruction execution Timer manipulation instruction Timer output time: (Set value + 0.5) × 64fX – 2/fX LED REM 2/fX tL Note 2 tH Notes 1. If the down counter reaches 0 while the carrier output is high level, carrier output will stop after becoming low level. 2. The number of carrier clocks for high-speed instruction execution may be less than the number for normal instruction execution. 24 Data Sheet U16363EJ1V0DS µPD69A Output from the REM pin is as follows, in accordance with the values set to bit 9 (CARY) of MOD1 and the timer output enable flag (t9), and the value of the timer block’s 9-bit down counter (t0 to t8). Table 4-2. REM Pin Output MOD1 Bit 9 (CARY) Timer Output Enable Flag (Timer Block t9) 9-Bit Down Counter (Timer Block t0 to t8) REM Pin — — — 0 Low-level output 0 Other than 0 0 1 Carrier outputNote 1 High-level output Note Input values in the range of 001H to 1FFH to MOD0 and MOD1. Caution MOD0 and MOD1 must be set while the REM pin is low level (t9 = 0 or t 0 to t8 = 0). Table 4-3. Example of Carrier Frequency Settings (fX = 4 MHz) Setting Value MOD1 tH ( µs) tL (µs) T (µs) fC (kHz) Duty MOD0 01H 01H 0.25 0.25 0.5 2,000 1/2 07H 0BH 1.0 1.5 2.5 400 2/5 13H 13H 2.5 2.5 5.0 200 1/2 27H 27H 5.0 5.0 10 100 1/2 41H 41H 8.25 8.25 16.5 60.6 1/2 41H 85H 8.25 16.75 25 40 1/3 45H 89H 8.75 17.25 26.0 38.5 1/3 45H 8BH 8.75 17.5 26.25 38.10 1/3 45H 8CH 8.75 17.625 26.375 37.9 1/3 47H 91H 9.0 18.25 27.25 36.7 1/3 48H 94H 9.125 18.625 27.75 36.0 1/3 69H D5H 13.25 26.75 40.0 25 1/3 77H 77H 15.0 15.0 30.0 33.3 1/2 C7H C7H 25.0 25.0 50.0 20 1/2 FFH FFH 32.0 32.0 64.0 15.6 1/2 tH tL Carrier signal T Data Sheet U16363EJ1V0DS 25 µPD69A 4.4 Software Control of Timer Output The timer output can be controlled by software. As shown in Figure 4-5, a pulse with a minimum width of 64/fX – 4/fX can be output during normal instruction execution, and a pulse with a minimum width of 32/fX – 2/fX can be output during high-speed instruction execution. … Figure 4-5. Output of Pulse of 1-Instruction Cycle Width … MOV T, #0000000000B; low-level output from the REM pin MOV T, #1000000000B; high-level output from the REM pin … MOV T, #0000000000B; low-level output from the REM pin (a) Normal instruction execution 4/fX 64/fX – 4/fX LED REM (b) High-speed instruction execution 2/fX 32/fX – 2/fX LED REM 26 Data Sheet U16363EJ1V0DS µPD69A 5. STANDBY FUNCTION 5.1 Outline of Standby Function To save current consumption, two types of standby modes, i.e., HALT mode and STOP mode, have been provided available. In STOP mode, the system clock stops oscillation. At this time, the XIN and XOUT pins are fixed to a low level. In HALT mode, CPU operation halts, while the system clock continues oscillation. When in HALT mode, the timer (including REM output and LED output) operates. In either STOP mode or HALT mode, the statuses of the data memory, accumulator, and port registers, etc. immediately before the standby mode is set are retained. Therefore, make sure to set the port status for the system so that the current consumption of the whole system is suppressed before the standby mode is set. Table 5-1. Statuses During Standby Mode STOP Mode Setting instruction HALT instruction Clock oscillator Oscillation stopped CPU • Operation halted Data memory • Immediately preceding status retained Operation Accumulator statuses Flag Port register Timer HALT Mode Oscillation continued • Immediately preceding status retained F • 0 (When 1, the flag is not placed in the standby mode.) CY • Immediately preceding status retained • Immediately preceding status retained • Operation halted • Operable (The count value is reset to “0”) Cautions 1. Write the NOP instruction as the first instruction after STOP mode is released. 2. When standby mode is released, the status flag (F) is set (to 1). 3. If, at the point the standby mode has been set, its release condition is met, then the system does not enter the standby mode. However, the status flag (F) is set (1). Data Sheet U16363EJ1V0DS 27 µPD69A 5.2 Standby Mode Setting and Release The standby mode is set with the HALT #b3b 2b1b 0B instruction for both STOP mode and HALT mode. For the standby mode to be set, the status flag (F) is required to have been cleared (to 0). The standby mode is released by the release condition specified with the reset (POC) or the operand of HALT instruction. If the standby mode is released, the status flag (F) is set (to 1). Even when the HALT instruction is executed in the state that the status flag (F) has been set (to 1), the standby mode is not set. If the release condition is not met at this time, the status flag is cleared (to 0). If the release condition is met, the status flag remains set (to 1). Even in the case when the release condition has been already met at the point that the HALT instruction is executed, the standby mode is not set. Here, also, the status flag (F) is set (to 1). Caution Depending on the status of the status flag (F), the HALT instruction may not be executed. Be careful about this. For example, when setting HALT mode after checking the key status with the STTS instruction, the system does not enter HALT mode as long as the status flag (F) remains set (to 1) and thus sometimes performs an unintended operation. In this case, the intended operation can be realized by executing the STTS instruction immediately after setting the timer to clear (to 0) the status flag. STTS ;To check the KI pin status. #03H … Example T, #0xxH ;To set the timer STTS #05H … MOV HALT ;To clear the status flag (During this time, be sure not to execute an instruction that may set the status flag.) ;To set HALT mode #05H Table 5-2. Addresses Executed After Standby Mode Release Release Condition 28 Address Executed After Release Reset Address 0 Release condition shown in Table 5-3 The address following the HALT instruction Data Sheet U16363EJ1V0DS µPD69A Table 5-3. Standby Mode Setting (HALT #b3b2b1b0B) and Release Conditions Operand Value of HALT Instruction Setting Mode Precondition for Setup Release Condition b3 b2 b1 b0 0 0 0 0 STOP All KI/O pins are high-level output. High level is input to at least one of KI pins. 0 1 1 STOP All KI/O pins are high-level output. High level is input to at least one of KI pins. 1 1 0 STOPNote 1 The KI/O0 pin is high-level output. High level is input to at least one of KI pins. 1 Any of the STOP [The following condition is added in addition to the above.] combinations of — of S0, S1 and S2 pins Note 2. b2b1b0 above 0/1 1 0 High level is input to at least one 1 HALT — When the timer’s down counter is 0 Notes 1. When setting HALT #×110B, configure a key matrix by using the KI/O0 pin and the KI pin so that the standby mode can be released. 2. At least one of the S0, S1 and S2 pins (the pin used for releasing the standby mode) must be specified as follows: S0, S1 pins: Input mode (specified by bits 0 and 2 of the P4 register) S2 pin: Use of STOP mode release enabled (specified by bit 3 of the P4 register) Cautions 1. The internal reset takes effect when the HALT instruction is executed with an operand value other than that above or when the precondition has not been satisfied when executing the HALT instruction. 2. If STOP mode is set when the timer’s down counter is not 0 (timer operating), the system is placed in STOP mode only after all the 10 bits of the timer’s down counter and the timer output permit flag are cleared to 0. 3. Write the NOP instruction as the first instruction after STOP mode is released. Data Sheet U16363EJ1V0DS 29 µPD69A 5.3 Standby Mode Release Timing (1) STOP mode release timing Figure 5-1. STOP Mode Release by Release Condition HALT instruction (STOP mode) WaitNote Standby release signal Operation mode STOP mode Oscillation Oscillation stopped HALT mode Operation mode Oscillation Clock α : Oscillation growth time Note 284/fX + α (normal instruction execution), or 270/fX + α (high-speed instruction execution) Caution When a release condition is met in the STOP mode, the device is released from the STOP mode, and goes into a wait state. At this time, if the release condition is not held, the device goes into STOP mode again after the wait time has elapsed. Therefore, when releasing the STOP mode, it is necessary to hold the release condition longer than the wait time. (2) HALT mode release timing Figure 5-2. HALT Mode Release by Release Condition Standby release signal HALT instruction (HALT mode) Operation mode HALT mode Operation mode Oscillation Clock 30 Data Sheet U16363EJ1V0DS µPD69A 6. RESET A system reset is effected by the following causes: • When the POC circuit has detected low power-supply voltage • When the operand value is illegal or does not satisfy the precondition when the HALT instruction is executed • When the accumulator is 0H when the RLZ instruction is executed • When stack pointer overflows or underflows Table 6-1. Hardware Statuses After Reset • Reset by On-Chip POC Circuit During Operation • Reset by the On-Chip POC Circuit During • Reset by Other Factors Note 1 Standby Mode Hardware PC (12 bits) 000H SP (1 bit) 0B Data R0 = DP 000H memory R1 to RF Undefined Accumulator (A) Undefined Status flag (F) 0B Carry flag (CY) 0B Timer (10 bits) Port register 000H P0 FFH P1 ×××× 11×1BNote 2 Control register P3 0000×000BNote 3 P4 26H Notes 1. The following resets are available. • Reset when executing the HALT instruction (when the operand value is illegal or does not satisfy the precondition) • Reset when executing the RLZ instruction (when A = 0) • Reset by stack pointer’s overflow or underflow 2. ×: Refers to the value by the KI or S2 pin status. In order to prevent malfunction, be sure to input a low level to one or more of pins KI0 to KI3 when POC is released by supply voltage rising (Can be left open. When open, leave the pull-down resistor connected). 3. ×: Refers to the value based on a decrease of power supply voltage (0 when VDD ≤ VID). Remark VID: RAM retention detection voltage Data Sheet U16363EJ1V0DS 31 µPD69A 7. POC CIRCUIT The POC circuit monitors the power supply voltage and applies an internal reset to the microcontroller when the battery is replaced. Cautions 1. There are cases in which the POC circuit cannot detect a low power supply voltage of less than 1 ms. Therefore, if the power supply voltage has become low for a period of less than 1 ms, the POC circuit may malfunction because it does not generate an internal reset signal. 2. Clock oscillation is stopped by the resonator due to low power supply voltage before the POC circuit generates the internal reset signal. In this case, malfunction may result when the power supply voltage is recovered after the oscillation is stopped. This type of phenomenon takes place because the POC circuit does not generate an internal reset signal (because the power supply voltage recovers before the low power supply voltage is detected) even though the clock has stopped. If, by any chance, a malfunction has taken place, remove the battery for a short time and put it back. In most cases, normal operation will be resumed. 3. In order to prevent malfunction, be sure to input a low level to one or more of pins KI0 to KI3 when POC is released due to supply voltage rising (Can be left open. When open, leave the pull-down resistor connected). 32 Data Sheet U16363EJ1V0DS µPD69A 7.1 Functions of POC Circuit The POC circuit has the following functions: • Generates an internal reset signal when VDD ≤ V POC. • Cancels an internal reset signal when VDD > VPOC. Here, VDD: power supply voltage, VPOC: POC detection voltage. Figure 7-1. Timing at Which Internal Reset Signal Is Generated in POC Circuit (a) When normal POC detection voltage is selected VDD Operating ambient temperature TA = –40 to + 85°C 3.6 V Clock frequency fX = 3.5 to 4.5 MHz 2.0 V ←POC detection voltage VPOC = 1.85 V (TYP.)Note 3 VPOC Approx. 1.7 V 0V →t Internal reset signal Reset ↑ Note 1 Operation mode ↑ Reset Note 2 (b) When low POC detection voltage is selected VDD Operating ambient temperature TA = –40 to + 85°C 3.6 V Clock frequency fX = 3.5 to 4.5 MHz 1.8 V ←POC detection voltage VPOC = 1.7 V (TYP.)Note 4 VPOC Approx. 1.6 V 0V →t Internal reset signal Reset ↑ Note 1 Operation mode ↑ Reset Note 2 (See descriptions of notes on the following page.) Data Sheet U16363EJ1V0DS 33 µPD69A Notes 1. Actually, oscillation stabilization wait time must elapse before the circuit is switched to operation mode. The oscillation stabilization wait time is about 534/fX to 918/fX (when about 134 to 230 µs; @ fX = 4 MHz). 2. For the POC circuit to generate an internal reset signal when the power supply voltage has fallen, it is necessary for the power supply voltage to be kept less than the VPOC for the period of 1 ms or more. Therefore, in reality, there is the time lag of up to 1 ms until the reset takes effect. 3. The POC detection voltage (VPOC) varies between approximately 1.7 to 2.0 V; thus, the reset may be canceled at a power supply voltage smaller than the guaranteed range (VDD = 2.0 to 3.6 V). However, as long as the conditions for operating the POC circuit are met, the actual lowest operating power supply voltage becomes lower than the POC detection voltage. Therefore, there is no malfunction occurring due to a shortage of power supply voltage. However, malfunction for such reasons as the clock not oscillating due to low power supply voltage may occur (refer to Cautions 2 in 7 POC CIRCUIT). 4. The POC detection voltage (VPOC) varies between approximately 1.6 to 1.8 V; thus, the reset may be canceled at a power supply voltage smaller than the guaranteed range (VDD = 1.8 to 3.6 V). However, as long as the conditions for operating the POC circuit are met, the actual lowest operating power supply voltage becomes lower than the POC detection voltage. Therefore, there is no malfunction occurring due to a shortage of power supply voltage. However, malfunction for such reasons as the clock not oscillating due to low power supply voltage may occur (refer to Cautions 2 in 7 POC CIRCUIT). 7.2 Oscillation Check at Low Supply Voltage A reliable reset operation can be expected of the POC circuit if it satisfies the condition that the clock can oscillate even at low power supply voltage (the oscillation start voltage of the resonator being even lower than the POC detection voltage). Whether this condition is met or not can be checked by measuring the oscillation status in a product that actually includes a POC circuit, as follows. <1> Connect a storage oscilloscope to the XOUT pin so that the oscillation status can be measured. <2> Connect a power supply whose output voltage can be varied and then gradually raise the power supply voltage V DD from 0 V (making sure to avoid V DD > 3.6V). At first Note 1, the XOUT pin is 0 V regardless of the VDD. However, at the point that VDD reaches the POC detection voltageNote 2, the voltage of the XOUT pin jumps to about 0.5VDD. Maintain this power supply voltage for a while to measure the waveform of the XOUT pin. If by any chance the oscillation start voltage of the resonator is lower than the POC detection voltage, the growing oscillation of the XOUT pin can be confirmed within several ms after the VDD has reached the VPOC. Notes 1. While VDD < approx. 1.7 V (when normal POC detection voltage is selected), or while VDD < approx. 1.6 V (when low POC detection voltage is selected) 2. VPOC = 1.85 V (TYP.) (when normal POC detection voltage is selected), or VPOC = 1.7 V (TYP.) (when low POC detection voltage is selected) 34 Data Sheet U16363EJ1V0DS µPD69A 8. SYSTEM CLOCK OSCILLATOR The system clock oscillator includes oscillators for ceramic resonators (fX = 3.5 to 4.5 MHz). Figure 8-1. System Clock XOUT XIN GND Ceramic resonator The system clock oscillator stops oscillating when a reset is applied or in STOP mode. Caution When using the system clock oscillator, wire as follows in the area enclosed by the broken lines in the above figure to avoid an adverse effect from wiring capacitance. • Keep the wiring length as short as possible. • Do not cross the wiring with the other signal lines. Do not route the wiring near a signal line through which a high fluctuating current flows. • Always make the ground point of the oscillator capacitor the same potential as GND. Do not ground the capacitor to a ground pattern through which a high current flows. • Do not fetch signals from the oscillator. A capacitor (15 pF) for the oscillator can be incorporated via a mask option. Data Sheet U16363EJ1V0DS 35 µPD69A 9. MASK OPTIONS The following mask options are provided in the µPD69A. (1) Capacitor for oscillator • Not used • Used (15 pF) Note Note Under evaluation. Contact an NEC Electronics sales representative for details of the evaluation status. (2) Instruction execution time • Normal instruction execution: 16 µs (@ fX = 4 MHz) • High-speed instruction execution: 8 µs (@ fX = 4 MHz) (3) POC detection voltage • Normal POC detection voltage: 1.85 V (TYP.) (VDD = 2.0 to 3.6 V) • Low POC detection voltage: 1.7 V (TYP.) (VDD = 1.8 to 3.6 V) Remark The mask option must be specified in the mask option information form. 36 Data Sheet U16363EJ1V0DS µPD69A 10. INSTRUCTION SET 10.1 Machine Language Output by Assembler The bit length of the machine language of this product is 10 bits per word. However, the machine language that is output by the assembler is extended to 16 bits per word. As shown in the example below, the extension is made by inserting 3-bit extended bits (111) in two locations. Figure 10-1. Example of Assembler Output (10 Bits Extended to 16 Bits) <1> In the case of “ANL A, @R0H” 1 1 1 1 1 0 1 0 1 1 1 0 1 0 1 1 1 Extended bits 0 0 0 0 1 0 0 0 0 = FAF0 1 0 0 0 = E6F8 Extended bits <2> In the case of “OUT P0, #data8” 1 1 1 Extended bits 0 0 1 1 0 1 0 0 1 1 0 1 1 1 1 0 0 0 1 Extended bits Data Sheet U16363EJ1V0DS 37 µPD69A 10.2 Circuit Symbol Description A: 38 Accumulator ASR: Address stack register addr: Program memory address CY: Carry flag data4: 4-bit immediate data data8: 8-bit immediate data data10: 10-bit immediate data F: Status flag M0: Modulo register for setting the low-level period M00: Modulo register for setting the low-level period (lower 4 bits) M01: Modulo register for setting the low-level period (higher 4 bits) M1: Modulo register for setting the high-level period M10: Modulo register for setting the high-level period (lower 4 bits) M11: Modulo register for setting the high-level period (higher 4 bits) PC: Program Counter Pn: Port register pair (n = 0, 1, 3, 4) P0n: Port register (lower 4 bits) P1n: Port register (higher 4 bits) ROMn: Bit n of the program memory’s (n = 0 to 9) Rn: Register pair R0n: Data memory (General-purpose register; n = 0 to F) R1n: Data memory (General-purpose register; n = 0 to F) SP: Stack Pointer T: Timer register T0: Timer register (lower 4 bits) T1: Timer register (higher 4 bits) (×): Content addressed with × Data Sheet U16363EJ1V0DS µPD69A 10.3 Mnemonic to/from Machine Language (Assembler Output) Contrast Table Accumulator Operation Instructions Instruction Code Operand 1st Word Operation Instruction Instruction Length Cycle 3rd Word A, R0n FBEn (A) ← (A) A, R1n FAEn CY ← A3 • Rmn3 A, @R0H FAF0 (A) ← (A) ∨ ANL 2nd Word ∨ Mnemonic (Rmn) m = 0, 1 n = 0 to F 1 1 ((P13), (R0))7-4 CY ← A3 • ROM7 (A) ← (A) FBF0 ∨ A, @R0L ((P13), (R0))3-0 CY ← A3 • ROM3 FBF1 data4 (A) ← (A) ∨ A, #data4 data4 2 CY ← A3 • data4 3 ORL A, R0n FDEn (A) ← (A) ∨ (Rmn) m = 0, 1 n = 0 to F A, R1n FCEn CY ← 0 A, @R0H FCF0 1 (A) ← (A) ∨ ((P13), (R0))7-4 CY ← 0 A, @R0L (A) ← (A) ∨ ((P13), (R0))3-0 FDF0 CY ← 0 A, #data4 FDF1 data4 (A) ← (A) ∨ data4 2 CY ← 0 XRL A, R0n F5En (A) ← (A) ∨ (Rmn) m = 0, 1 n = 0 to F A, R1n F4En CY ← A3 • Rmn3 A, @R0H F4F0 (A) ← (A) ∨ ((P13), (R0))7-4 1 CY ← A3 • ROM7 A, @R0L (A) ← (A) ∨ ((P13), (R0))3-0 F5F0 CY ← A3 • ROM3 A, #data4 F5F1 data4 (A) ← (A) ∨ data4 2 CY ← A3 • data4 3 INC A F4F3 (A) ← (A) + 1 if (A) = 0 1 CY ← 1 else CY ← 1 RL A FCF3 (An+1) ← (A n), (A 0) ← (A3) RLZ A FEF3 if A = 0 CY ← A3 reset else (An+1) ← (An), (A0) ← (A3) CY ← A3 Data Sheet U16363EJ1V0DS 39 µPD69A I/O Instructions IN OUT ANL ORL XRL Mnemonic Instruction Code Operand 2nd Word 3rd Word A, P0n FFF8 + n — — (A) ← (Pmn) A, P1n FEF8 + n — — CY ← 0 (Pmn) ← (A) Remark m = 0, 1 n = 0, 1, 3, 4 m = 0, 1 n = 0, 1, 3, 4 P0n, A E5F8 + n — — P1n, A E4F8 + n — — A, P0n FBF8 + n — — (A) ← (A) (Pmn) m = 0, 1 n = 0, 1, 3, 4 A, P1n FAF8 + n — — CY ← A3 • Pmn3 A, P0n FDF8 + n — — (A) ← (A) ∨ (Pmn) m = 0, 1 n = 0, 1, 3, 4 A, P1n FCF8 + n — — CY ← 0 A, P0n F5F8 + n — — (A) ← (A) ∨ (Pmn) m = 0, 1 n = 0, 1, 3, 4 A, P1n F4F8 + n — — CY ← A3 • Pmn3 Instruction Code Operand 1st Word OUT Operation 1st Word Pn, #data8 E6F8 + n 2nd Word Instruction Instruction Length Cycle 1 1 Instruction Instruction ∨ Mnemonic Operation 3rd Word Length (Pn) ← data8 data8 n = 0, 1, 3, 4 2 Cycle 1 Pn: P1n to P0n are dealt with in pairs. Data Transfer Instruction Mnemonic Instruction Code Operand 1st Word MOV 2nd Word Operation Instruction Instruction Length Cycle 3rd Word A, R0n FFEn (A) ← (Rmn) A, R1n FEEn CY ← 0 A, @R0H FEF0 (A) ← ((P13), (R0))7-4 m = 0, 1 n = 0 to F 1 1 CY ← 0 A, @R0L (A) ← ((P13), (R0))3-0 FFF0 CY ← 0 Mnemonic A, #data4 FFF1 R0n, A E5En R1n, A E4En Instruction Code Operand Remark 40 2 (Rmn) ← (A) 1st Word MOV (A) ← data4 CY ← 0 data4 2nd Word m = 0, 1 n = 0 to F Operation Instruction Instruction Length Cycle 3rd Word Rn, #data8 E6En data8 — (R1n to R0n) ← data8 Rn, @R0 — — (R1n to R0n) ← ((P13), (R0))n = 1 to F E7En 1 Rn: R1n to R0n are handled in pairs. Data Sheet U16363EJ1V0DS n = 0 to F 2 1 1 µPD69A Branch Instructions Mnemonic Instruction Code Operand 1st Word JMP JC JNC JF JNF 2nd Word addr (Page 0) E8F1 addr addr (Page 1) E9F1 addr addr (Page 2) E8F4 addr addr (Page 3) E9F4 addr Operation PC ← addr if CY = 1 addr else PC ← PC + 2 addr addr Cycle 1 PC ← addr addr addr (Page 1) EAF1 addr (Page 3) EAF4 Instruction Length 2 addr (Page 0) ECF1 addr (Page 2) ECF4 Instruction 3rd Word PC ← addr addr (Page 0) EDF1 addr if CY = 0 addr (Page 1) EBF1 addr else PC ← PC + 2 addr (Page 2) EDF4 addr addr (Page 3) EBF4 addr addr (Page 0) EEF1 addr if F = 1 addr (Page 1) F0F1 addr else PC ← PC + 2 addr (Page 2) EEF4 addr addr (Page 3) F0F4 addr addr (Page 0) EFF1 addr if F = 0 addr (Page 1) F1F1 addr else PC ← PC + 2 addr (Page 2) EFF4 addr addr (Page 3) F1F4 addr PC ← addr PC ← addr Caution 0 to 3, which refer to PAGE0 to 3, are not written when describing mnemonics. Subroutine Instructions Mnemonic Instruction Code Operand 1st Word CALL RET Operation 2nd Word 3rd Word addr (Page 0) E6F2 E8F1 addr addr (Page 1) E6F2 E9F1 addr addr (Page 2) E6F2 E8F4 addr addr (Page 3) E6F2 E9F4 addr E8F2 Instruction Instruction Length Cycle SP ← SP + 1, ASR ← PC, PC ← addr 3 2 PC ← ASR, SP ← SP – 1 1 1 Caution 0 to 3, which refer to PAGE0 to 3, are not written when describing mnemonics. Data Sheet U16363EJ1V0DS 41 µPD69A Timer Operation Instructions Mnemonic Instruction Code Operand 1st Word MOV Mnemonic MOV 2nd Word Operation A, T0 FFFF (A) ← (Tn) A, T1 FEFF CY ← 0 A, M00 FFF6 (A) ← (M0n) A, M01 FEF6 CY ← 0 A, M10 FFF7 (A) → (M1n) A, M11 FEF7 CY → 0 T0, A E5FF (Tn) ← (A) T1, A F4FF (T) n ← 0 M00, A E5F6 (M0n) ← (A) M01, A E4F6 CY ← 0 M10, A E5F7 (M1n) ← (A) M11, A E4F7 CY ← 0 n = 0, 1 Instruction Length Cycle 1 1 Instruction Instruction n = 0, 1 n = 0, 1 n = 0, 1 n = 0, 1 n = 0, 1 Instruction Code Operand Instruction 3rd Word Operation 1st Word 2nd Word T, #data10 E6FF data10 3rd Word (T) ← data10 Length M0, #data10 E6F6 data10 (M0) ← data10 M1, #data10 E6F7 data10 (M1) ← data10 2 T, @R0 F4FF (T) ← ((P13), (R0)) M0, @R0 E7F6 (M0) ← ((P13), (R0)) M1, @R0 E7F7 (M1) ← ((P13), (R0)) Cycle 1 1 Others Mnemonic Instruction Code Operand 1st Word 2nd Word HALT #data4 E2F1 data4 Standby mode STTS #data4 E3F1 data4 if statuses match 3rd Word E3En FAF3 NOP 42 E0E0 F←1 F←1 F←0 if A = 0FH else 2 F←0 if statuses match else SCAF Instruction Length else R0n Instruction Operation 1 n = 0 to F CY ← 1 CY ← 0 PC ← PC + 1 Data Sheet U16363EJ1V0DS Cycle 1 µPD69A 10.4 Accumulator Manipulation Instructions ANL A, R0n ANL A, R1n 1 1 0 1 R4 0 R3 R2 R1 R0 <2> Cycle count: 1 <3> Function: (A) ← (A) ∨ <1> Instruction code: (Rmn) m = 0, 1 n = 0 to F CY ← A 3 • Rmn 3 The accumulator contents and the register Rmn contents are ANDed and the results are entered in the accumulator. ANL A, @R0H ANL A, @R0L <1> Instruction code: 1 1 0 1 0/1 1 0 0 0 0 <2> Cycle count: 1 <3> Function: (A) ← (A) ((P13), (R0)) 7-4 (in the case of ANL A, @R0H) ∨ CY ← A 3 • ROM 7 (A) ← (A) ((P13), (R0)) 3-0 (in the case of ANL A, @R0L) ∨ CY ← A 3 • ROM 3 The accumulator contents and the program memory contents specified by the control register P13 and register pair R10 to R00 are ANDed and the results are entered in the accumulator. If H is specified, b7, b6, b5 and b4 take effect. If L is specified, b3, b2, b1 and b0 take effect. • Program memory (ROM) organization b7 b9 b6 b5 b4 b8 H↓ b3 b2 b1 b0 L↓ Valid bits at the time of accumulator manipulation ANL A, #data4 <1> Instruction code: 1 1 0 1 1 1 0 0 0 1 <2> Cycle count: 1 <3> Function: (A) ← (A) 0 0 0 0 0 0 d3 d2 d1 d0 data4 ∨ CY ← A3 • data4 3 The accumulator contents and the immediate data are ANDed and the results are entered in the accumulator. Data Sheet U16363EJ1V0DS 43 µPD69A ORL A, R0n ORL A, R1n <1> Instruction code: 1 1 1 0 R4 0 R3 R2 R1 R0 <2> Cycle count: 1 <3> Function: (A) ← (A) ∨ (Rmn) m = 0, 1 n = 0 to F CY ← 0 The accumulator contents and the register Rmn contents are ORed and the results are entered in the accumulator. ORL A, @R0H ORL A, @R0L <1> Instruction code: 1 1 1 0 0/1 1 0 0 0 0 <2> Cycle count: 1 <3> Function: (A) ← (A) ∨ (P13), (R0)) 7-4 (in the case of ORL A, @R0H) (A) ← (A) ∨ (P13), (R0)) 3-0 (in the case of ORL A, @R0L) CY ← 0 The accumulator contents and the program memory contents specified by the control register P13 and register pair R10-R00 are ORed and the results are entered in the accumulator. If H is specified, b7, b6, b5 and b4 take effect. If L is specified, b3, b2, b1 and b0 take effect. ORL A, #data4 <1> Instruction code: 1 1 1 0 1 1 0 0 0 1 0 0 0 0 0 0 d3 d2 d1 d0 <2> Cycle count: 1 <3> Function: (A) ← (A) ∨ data4 CY ← 0 The accumulator contents and the immediate data are exclusive-ORed and the results are entered in the accumulator. XRL A, R0n XRL A, R1n <1> Instruction code: 1 0 1 0 R4 0 R3 R2 R1 R0 <2> Cycle count: 1 <3> Function: (A) ← (A) ∨ (Rmn) m = 0, 1 n = 0 to F CY ← A 3 • Rmn 3 The accumulator contents and the register Rmn contents are ORed and the results are entered in the accumulator. 44 Data Sheet U16363EJ1V0DS µPD69A XRL A, @R0H XRL A, @R0L <1> Instruction code: 1 0 1 0 0/1 1 0 0 0 0 <2> Cycle count: 1 <3> Function: (A) ← (A) ∨ (P13), (R0))7-4 (in the case of XRL A, @R0H) CY ← A 3 • ROM 7 (A) ← (A) ∨ (P13), (R0))3-0 (in the case of XRL A, @R0L) CY ← A 3 • ROM 3 The accumulator contents and the program memory contents specified by the control register P13 and register pair R10-R00 are exclusive-ORed and the results are entered in the accumulator. If H is specified, b7, b6, b5, and b4 take effect. If L is specified, b3, b2, b1, and b0 take effect. XRL A, #data4 <1> Instruction code: 1 0 1 0 1 1 0 0 0 1 0 0 0 0 0 0 d3 d2 d1 d0 <2> Cycle count: 1 <3> Function: (A) ← (A) ∨ data4 CY ← A 3 • data43 The accumulator contents and the immediate data are exclusive-ORed and the results are entered in the accumulator. INC A <1> Instruction code: 1 0 1 0 0 1 0 0 1 1 <2> Cycle count: 1 <3> Function: (A) ← (A) + 1 if A = 0 else CY ← 1 CY ← 0 The accumulator contents are incremented (+1). RL A <1> Instruction code: 1 1 1 0 0 1 0 0 1 1 <2> Cycle count: 1 <3> Function: (A n + 1) ← (An), (A 0) ← (A3) CY ← A 3 The accumulator contents are rotated anticlockwise bit by bit. RLZ A <1> Instruction code: 1 1 1 1 0 1 0 0 1 1 <2> Cycle count: 1 <3> Function: if A = 0 else reset (A n + 1) ← (An), (A 0) ←(A3) CY ← A 3 The accumulator contents are rotated anticlockwise bit by bit. If A = 0H at the time of command execution, an internal reset takes effect. Data Sheet U16363EJ1V0DS 45 µPD69A 10.5 I/O Instructions IN A, P0n IN A, P1n <1> Instruction code: 1 1 1 1 P4 1 1 P2 P1 P0 <2> Cycle count: 1 <3> Function: (A) ← (Pmn) m = 0, 1 n = 0, 1, 3, 4 CY ← 0 The port Pmn data is loaded (read) onto the accumulator. OUT P0n, A OUT P1n, A <1> Instruction code: 0 0 1 0 P4 1 1 P2 P1 P0 <2> Cycle count: 1 <3> Function: (Pmn) ← (A) m = 0, 1 n = 0, 1, 3, 4 The accumulator contents are transferred to port Pmn to be latched. ANL A, P0n ANL A, P1n <1> Instruction code: 1 1 0 1 P4 1 1 P2 P1 P0 <2> Cycle count: 1 <3> Function: (A) ← (A) (Pmn) m = 0, 1 n = 0, 1, 3, 4 ∨ CY ← A 3 • Pmn The accumulator contents and the port Pmn contents are ANDed and the results are entered in the accumulator. ORL A, P0n ORL A, P1n <1> Instruction code: 1 1 1 0 P4 1 1 P2 P1 P0 <2> Cycle count: 1 <3> Function: (A) ← (A) ∨ (Pmn) m = 0, 1 n = 0, 1, 3, 4 CY ← 0 The accumulator contents and the port Pmn contents are ORed and the results are entered in the accumulator. XRL A, P0n XRL A, P1n <1> Instruction code: 1 0 1 0 P4 1 1 P2 P1 P0 <2> Cycle count: 1 <3> Function: (A) ← (A) ∨ (Pmn) m = 0, 1 n = 0, 1, 3, 4 CY ← A 3 • Pmn The accumulator contents and the port Pmn contents are exclusive-ORed and the results are entered in the accumulator. 46 Data Sheet U16363EJ1V0DS µPD69A OUT Pn, #data8 <1> Instruction code: 0 0 1 1 0 1 1 P2 P1 P0 0 d7 d6 d5 d4 0 d3 d2 d1 d0 <2> Cycle count: 1 <3> Function: (Pn) ← data8 n = 0, 1, 3, 4 The immediate data is transferred to port Pn. In this case, port Pn refers to P1n to P0n operating in pairs. 10.6 Data Transfer Instructions MOV A, R0n MOV A, R1n <1> Instruction code: 1 1 1 1 R4 0 R3 R2 R1 R0 <2> Cycle count: 1 <3> Function: (A) ← (Rmn) m = 0, 1 n = 0 to F CY ← 0 The register Rmn contents are transferred to the accumulator. MOV A, @R0H <1> Instruction code: 1 1 1 1 0 1 0 0 0 0 <2> Cycle count: 1 <3> Function: (A) ← ((P13), (R0)) 7-4 CY ← 0 The higher 4 bits (b7 b6 b5 b4) of the program memory specified by control register P13 and register pair R10-R00 are transferred to the accumulator. b9 is ignored. MOV A, @R0L <1> Instruction code: 1 1 1 1 1 1 0 0 0 0 <2> Cycle count: 1 <3> Function: (A) ← ((P13), (R0)) 3-0 CY ← 0 The lower 4 bits (b3 b2 b1 b0) of the program memory specified by control register P13 and register pair R10 to R00 are transferred to the accumulator. b8 is ignored. • Program memory (ROM) contents @R0 H b9 b7 b6 @R0 L b5 b4 b8 b3 b2 b1 b0 MOV A, #data4 <1> Instruction code: 1 1 1 1 1 1 0 0 0 1 <2> Cycle count: 1 <3> Function: (A) ← data4 0 0 0 0 0 0 d3 d2 d1 d0 CY ← 0 The immediate data is transferred to the accumulator. Data Sheet U16363EJ1V0DS 47 µPD69A MOV R0n, A MOV R1n, A <1> Instruction code: 0 0 1 0 R4 0 R3 R2 R1 R0 <2> Cycle count: 1 <3> Function: (Rmn) ← (A) m = 0, 1 n = 0 to F The accumulator contents are transferred to register Rmn. MOV Rn, #data8 <1> Instruction code: 0 0 1 1 0 0 R3 R2 R1 R0 <2> Cycle count: 1 <3> Function: (R1n-R0n) ← data8 0 d7 d6 d5 d4 0 d3 d2 d1 d0 n = 0 to F The immediate data is transferred to the register. Using this instruction, registers operate as register pairs. The pair combinations are as follows: R0: R10 - R00 R1: R11 - R01 : RE: R1E - R0E RF: R1F - R0F Lower column Higher column MOV Rn, @R0 <1> Instruction code: 0 0 1 1 1 0 R3 R2 R1 R0 <2> Cycle count: 1 <3> Function: (R1n-R0n) ← ((P13), R0)) n = 1 to F The program memory contents specified by control register P13 and register pair R10 to R00 are transferred to register pair R1n to R0n. The program memory consists of 10 bits and has the following state after the transfer to the register. Program memory b9 b7 b6 b5 b4 b8 b3 b2 b1 b0 → b9 b7 @R0 b6 b5 R1n b4 b8 b3 b2 b1 b0 R0n The higher 2 to 4 bits of the program memory address are specified by the control register (P13). 48 Data Sheet U16363EJ1V0DS µPD69A 10.7 Branch Instructions The program memory consists of pages in steps of 1K (000H to 3FFH). However, as the assembler automatically performs page optimization, it is unnecessary to designate pages. The pages allowed for each product are as follows. µPD69A (ROM: 4K steps): Pages 0 to 3 µPD6P9 (PROM: 4K steps): Pages 0 to 3 JMP addr <1> Instruction code: Page 0 0 1 0 0 0 1 0 0 0 1 ; page 1 0 1 0 0 1 1 0 0 0 1 Page 2 0 1 0 0 0 1 0 1 0 0 ; page 3 0 1 0 0 1 1 0 1 0 0 a9 a7 a6 a5 a4 a8 a3 a2 a1 a0 <2> Cycle count: 1 <3> Function: PC ← addr The 10 bits (PC9-0) of the program counter are replaced directly by the specified address addr (a9 to a0). JC addr <1> Instruction code: Page 0 0 1 1 0 0 1 0 0 0 1 ; page 1 0 1 0 1 0 1 0 0 0 1 Page 2 0 1 1 0 0 1 0 1 0 0 ; page 3 0 1 0 1 0 1 0 1 0 0 a9 a7 a6 a5 a4 a8 a3 a2 a1 a0 <2> Cycle count: 1 <3> Function: if CY = 1 else PC ← addr PC ← PC + 2 If the carry flag CY is set (to 1), a jump is made to the address specified by addr (a9 to a0). JNC addr <1> Instruction code: Page 0 0 1 1 0 1 1 0 0 0 1 ; page 1 0 1 0 1 1 1 0 0 0 1 Page 2 0 1 1 0 1 1 0 1 0 0 ; page 3 0 1 0 1 1 1 0 1 0 0 a9 a7 a6 a5 a4 a8 a3 a2 a1 a0 <2> Cycle count: 1 <3> Function: if CY = 0 else PC ← addr PC ← PC + 2 If the carry flag CY is cleared (to 0), a jump is made to the address specified by addr (a9 to a0). JF addr <1> Instruction code: Page 0 0 1 1 1 0 1 0 0 0 1 ; page 1 1 0 0 0 0 1 0 0 0 1 Page 2 0 1 1 1 0 1 0 1 0 0 ; page 3 1 0 0 0 0 1 0 1 0 0 a9 a7 a6 a5 a4 a8 a3 a2 a1 a0 <2> Cycle count: 1 <3> Function: if F = 1 else PC ← addr PC ← PC + 2 If the status flag F is set (to 1), a jump is made to the address specified by addr (a9 to a0). Data Sheet U16363EJ1V0DS 49 µPD69A JNF addr <1> Instruction code: Page 0 0 1 1 1 1 1 0 0 0 1 ; page 1 1 0 0 0 1 1 0 0 0 1 Page 2 0 1 1 1 1 1 0 1 0 0 ; page 3 1 0 0 0 1 1 0 1 0 0 a9 a7 a6 a5 a4 a8 a3 a2 a1 a0 <2> Cycle count: 1 <3> Function: if F = 0 else PC ← addr PC ← PC + 2 If the status flag F is cleared (to 0), a jump is made to the address specified by addr (a9 to a0). 10.8 Subroutine Instructions The program memory consists of pages in steps of 1K (000H to 3FFH). However, as the assembler automatically performs page optimization, it is unnecessary to designate pages. The pages allowed for each product are as follows. µPD69A (ROM: 4K steps): Pages 0 to 3 µPD6P9 (PROM: 4K steps): Pages 0 to 3 CALL addr <1> Instruction code: 0 0 1 1 0 1 0 0 1 0 Page 0 0 1 0 0 0 1 0 0 0 1 ; page 1 0 1 0 0 1 1 0 0 0 1 Page 2 0 1 0 0 0 1 0 1 0 0 ; page 3 0 1 0 0 1 1 0 1 0 0 a9 a7 a6 a5 a4 a8 a3 a2 a1 a0 <2> Cycle count: 2 <3> Function: SP ← SP + 1 ASR ← PC PC ← addr Increments (+1) the stack pointer value and saves the program counter value in the address stack register. Then, enters the address specified by the operand addr (a9 to a0) into the program counter. If a carry is generated when the stack pointer value is incremented (+1), an internal reset takes effect. RET <1> Instruction code: 0 1 0 0 0 1 0 0 1 0 <2> Cycle count: 1 <3> Function: PC ← ASR SP ← SP – 1 Restores the value saved in the address stack register to the program counter. Then, decrements (–1) the stack pointer. If a borrow is generated when the stack pointer value is decremented (–1), an internal reset takes effect. 50 Data Sheet U16363EJ1V0DS µPD69A 10.9 Timer Operation Instructions MOV A, T0 MOV A, T1 <1> Instruction code: 1 1 1 1 0/1 1 1 1 1 1 <2> Cycle count: 1 <3> Function: (A) ← (Tn) n = 0, 1 CY ← 0 The timer register Tn contents are transferred to the accumulator. T1 corresponds to (t9, t8, t7, t6); T0 corresponds to (t5, t4, t3, t2). T t9 t8 t7 t6 T1 t5 t4 t3 t2 t1 t0 T0 ↓ MOV T, #data10 Can be set with MOV T, @R0 MOV A, M00 MOV A, M01 <1> Instruction code: 1 <2> Cycle count: 1 <3> Function: (A) ← (M0n) 1 1 1 0/1 1 0 1 1 0 n = 0, 1 CY ← 0 The modulo register M0n contents are transferred to the accumulator. M01 corresponds to (t9, t 8, t7, t6); M00 corresponds to (t5, t4, t3, t2). M0 t9 t8 t7 M01 t6 t5 t4 t3 M00 Can be set with t2 t1 t0 ↓ MOV M0, #data10 MOV M0, @R0 Data Sheet U16363EJ1V0DS 51 µPD69A MOV A, M10 MOV A, M11 <1> Instruction code: 1 1 1 1 0/1 1 0 1 1 1 <2> Cycle count: 1 <3> Function: (A) ← (M1n) n = 0, 1 CY ← 0 The modulo register M1n contents are transferred to the accumulator. M11 corresponds to (t9, t 8, t7, t6); M10 corresponds to (t5, t4, t3, t2). M1 t9 t8 t7 t6 M11 t5 t4 t3 t2 t1 t0 M10 ↓ MOV M1, #data10 Can be set with MOV M1, @R0 MOV T0, A MOV T1, A <1> Instruction code: 0 <2> Cycle count: 1 <3> Function: (Tn) ← (A) 0 1 0 0/1 1 1 1 1 1 n = 0, 1 The accumulator contents are transferred to the timer register Tn. T1 corresponds to (t9, t8, t7, t6); T0 corresponds to (t5, t4, t3, t2). After executing this instruction, if data is transferred to T1, t1 becomes 0; if data is transferred to T0, t0 becomes 0. MOV M00, A MOV M01, A <1> Instruction code: 0 0 1 0 0/1 1 0 1 1 0 <2> Cycle count: 1 <3> Function: (M0n) ← (A) n = 0, 1 CY ← 0 The accumulator contents are transferred to the modulo register M0n. M01 corresponds to (t9, t 8, t7, t6); M00 corresponds to (t5, t4, t3, t2). After executing this instruction, if data is transferred to M01, t1 becomes 0; if data is transferred to M00, t0 becomes 0. MOV M10, A MOV M11, A <1> Instruction code: 0 0 1 0 0/1 1 0 1 1 1 <2> Cycle count: 1 <3> Function: (M1n) ← (A) n = 0, 1 CY ← 0 The accumulator contents are transferred to the modulo register M1n. M11 corresponds to (t9, t 8, t7, t6); M10 corresponds to (t5, t4, t3, t2). After executing this instruction, if data is transferred to M11, t1 becomes 0; if data is transferred to M10, t0 becomes 0. 52 Data Sheet U16363EJ1V0DS µPD69A MOV T, #data10 <1> Instruction code: 0 0 1 1 0 1 1 1 1 1 t1 t9 t8 t7 t6 t0 t5 t4 t3 t2 <2> Cycle count: 1 <3> Function: (T) ← data10 The immediate data is transferred to the timer register T (t9 to t0). Remark The timer time is set as follows. (a) Normal instruction execution (Set value + 1) × 64/fX – 4/fX (b) High-speed instruction execution (Set value + 0.5) × 64/fX – 2/fX MOV M0, #data10 <1> Instruction code: 0 0 1 1 0 1 0 1 1 0 <2> Cycle count: 1 <3> Function: (M0) ← data10 t1 t9 t8 t7 t6 t0 t5 t4 t3 t2 The immediate data is transferred to the modulo register M0 (t9 to t0). MOV M1, #data10 <1> Instruction code: 0 0 1 1 0 1 0 1 1 1 t1 t9 t8 t7 t6 t0 t5 t4 t3 t2 <2> Cycle count: 1 <3> Function: (M1) ← data10 The immediate data is transferred to the modulo register M1 (t9 to t0). MOV T, @R0 <1> Instruction code: 0 0 1 1 1 1 1 1 1 1 <2> Cycle count: 1 <3> Function: (T) ← ((P13), (R0)) Transfers the program memory contents to the timer register T (t9 to t0) specified by the control register P13 and the register pair R10 to R00. The program memory, which consists of 10 bits, is placed in the following state after the transfer to the register. Timer T Program memory t1 t9 t8 t7 t6 t0 @R0 t5 t4 t3 t2 → t9 t8 t7 T1 t6 t5 t4 t3 t2 t1 t0 T0 The higher 2 to 4 bits of the program memory address are specified by the control register (P13). Caution When setting a timer value in the program memory, be sure to use the DT quasi directive. Data Sheet U16363EJ1V0DS 53 µPD69A MOV M0, @R0 <1> Instruction code: 0 0 1 1 1 1 0 1 1 0 <2> Cycle count: 1 <3> Function: (M0) ← ((P13), (R0)) Transfers the program memory contents to the modulo register M0 (t9 to t0) specified by the control register P13 and the register pair R10 to R00. The program memory, which consists of 10 bits, is placed in the following state after the transfer to the register. Modulo register M0 Program memory t1 t9 t8 t7 t6 t0 t5 t4 t3 t2 → t9 @R0 t8 t7 t6 t5 M01 t4 t3 t2 t1 t0 M00 The higher 2 to 4 bits of the program memory address are specified by the control register (P13). Caution When setting a timer value in the program memory, be sure to use the DT quasi directive. MOV M1, @R0 <1> Instruction code: 0 0 1 1 1 1 0 1 1 1 <2> Cycle count: 1 <3> Function: (M1) ← ((P13), (R0)) Transfers the program memory contents to the modulo register M1 (t9 to t0) specified by the control register P13 and the register pair R10 to R00. The program memory, which consists of 10 bits, is placed in the following state after the transfer to the register. Modulo register M1 Program memory t1 t9 t8 t7 t6 t0 t5 t4 t3 t2 @R0 → t9 t8 t7 M11 t6 t5 t4 t3 t2 t1 t0 M10 The higher 2 to 4 bits of the program memory address are specified by the control register (P13). Caution When setting a timer value in the program memory, be sure to use the DT quasi directive. 10.10 Other HALT #data4 <1> Instruction code: 0 0 0 1 0 1 0 0 0 1 0 0 0 0 0 0 d3 d2 d1 d0 <2> Cycle count: 1 <3> Function: Standby mode Places the CPU in standby mode. The condition for having the standby mode (HALT/STOP mode) canceled is specified by the immediate data. 54 Data Sheet U16363EJ1V0DS µPD69A STTS R0n <1> Instruction code: 0 0 0 1 1 0 R3 R2 R1 R0 <2> Cycle count: 1 <3> Function: if statuses match else F ← 0 F ← 1 n = 0 to F Compares the S0, S1, KI/O, KI, and TIMER statuses with the register R0n contents. If at least one of the statuses matches the bits that have been set, the status flag F is set (to 1). If none of them match, the status flag F is cleared (to 0). STTS #data4 <1> Instruction code: 0 0 0 1 1 1 0 0 0 1 <2> Cycle count: 1 <3> Function: if statuses match 0 0 0 0 0 0 d3 d2 d1 d0 else F ← 1 F ← 0 Compares the S0, S1, S 2, KI/O , KI, and TIMER statuses with the immediate data contents. If at least one of the statuses matches the bits that have been set, the status flag F is set (to 1). If none of them match, the status flag F is cleared (to 0). SCAF (Set Carry If ACC = F H) <1> Instruction code: 1 1 0 1 0 1 0 0 1 1 <2> Cycle count: 1 <3> Function: if CY ← 1 A = 0FH else CY ← 0 Sets the carry flag CY (to 1) if the accumulator contents are FH. The accumulator values after executing the SCAF instruction are as follows: Accumulator Value Before Execution Carry Flag After Execution ×××0 0000 0 (clear) ××01 0001 0 (clear) ×011 0011 0 (clear) 0111 0111 0 (clear) 1111 1111 1 (set) Remark ×: don’t care NOP <1> Instruction code: 0 0 0 0 0 0 0 0 0 0 <2> Cycle count: 1 <3> Function: PC ← PC + 1 No operation Data Sheet U16363EJ1V0DS 55 µPD69A 11. ASSEMBLER RESERVED WORDS 11.1 Mask Option Directives When creating a program in the µPD69A, it is necessary to use a mask option quasi directive in the assembler’s source program. 11.1.1 OPTION and ENDOP quasi directives The quasi directives from the OPTION quasi directive down to the ENDOP quasi directive are called the mask option definition block. The format of the mask option definition block is as follows. Format Symbol field Mnemonic field [Label:] OPTION Operand field Comment field [; Comment] : : ENDOP 11.1.2 Mask option definition quasi directives The quasi directives that can be used in the mask option definition block are listed in Table 11-1. The mask option definition can only be specified as follows. Be sure to specify the following quasi directives. Example Symbol field Mnemonic field Operand field Comment field OPTION USECAP ; Capacitor for oscillation ENDOP incorporated Table 11-1. Mask Option Definition Directives Name CAP Mask Option Definition Quasi Directive PRO File Address Value Data Value 2043H 01 USECAP (Capacitor for oscillation incorporated) NOUSECAP (Capacitor for oscillation not incorporated) 00 Remark The mask option must be specified in the mask option information form. 56 Data Sheet U16363EJ1V0DS µPD69A 12. ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings (TA = +25°C) Item Power supply voltage Symbol Input voltage VI Output voltage VO Output current, high Conditions Ratings Unit –0.3 to +3.8 V –0.3 to V DD + 0.3 V –0.3 to V DD + 0.3 V VDD IOHNote KI/O, K I, S0, S1, S2 REM LED Peak value –30 mA rms value –20 mA Peak value –7.5 mA –5 mA rms value One KI/O pin Peak value Total for LED and KI/O pins Output current, low IOL Note REM –13.5 mA rms value –9 mA Peak value –18 mA rms value –12 mA Peak value 7.5 mA 5 mA 7.5 mA 5 mA rms value LED Peak value rms value Operating ambient temperature TA –40 to +85 °C Storage temperature Tstg –65 to +150 °C Note The rms value should be calculated as follows: [rms value] = [Peak value] × √ Duty. Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. Recommended Power Supply Voltage Range (TA = –40 to +85°C) Item Power supply voltage Symbol VDD Conditions fX = 3.5 to 4.5 MHz When normal POC detection voltage is selected When low POC detection voltage is selected Data Sheet U16363EJ1V0DS MIN. TYP. MAX. Unit 2.0 3.0 3.6 V 1.8 3.0 3.6 V 57 µPD69A DC Characteristics (TA = –40 to +85°C, VDD = 1.8 to 3.6 V) Item MAX. Unit VDD V 0.65VDD VDD V 0 0.3V DD V 0 0.15VDD V 3 µA S 0, S 1 , S 2 VI = VDD, pull-down resistor not incorporated 3 µA IUL1 KI VI = 0 V –3 µA IUL2 KI/O VI = 0 V –3 µA IUL3 S 0, S 1 , S 2 V I = 0 V –3 µA Output voltage, high VOH1 REM, LED, KI/O IOH = –0.3 mA Output voltage, low VOL1 REM, LED IOL = 0.3 mA VOL2 KI/O IOL = 15 µA IOH1 REM VDD = 3.0 V, VOH = 1.0 V –5 –12 mA Input voltage, high Input voltage, low Input leakage current, high Input leakage current, low Output current, high Symbol Conditions MIN. VIH1 KI/O 0.7V DD VIH2 K I , S 0 , S1 , S 2 VIL1 KI/O VIL2 K I , S 0 , S1 , S 2 ILH1 KI VI = VDD, pull-down resistor not incorporated ILH2 TYP. 0.8V DD V 0.3 0.4 V V IOH2 KI/O VDD = 3.0 V, VOH = 2.2 V –2.5 –7 mA Output current, low IOL1 KI/O VDD = 3.0 V, VOL = 0.4 V 47 70 µA VDD = 3.0 V, VOL = 2.2 V 260 390 On-chip pull-down resistor R1 K I , S 0 , S1 , S 2 75 150 300 kΩ 250 500 kΩ 3.6 V µA R2 KI/O 130 Data retention power supply voltage VDDOR In STOP mode 0.9 RAM retention detection voltage VID When normal POC VDD = 2.0 to 3.6 V detection voltage is selected 1.4 1.5 V When low POC detection voltage is selected 1.2 1.5 V Supply current 58 VDD = 1.8 to 3.6 V IDD1 Operation mode fX = 4.0 MHz, VDD = 3 V ±10% 0.7 1.4 mA IDD2 HALT mode fX = 4.0 MHz, VDD = 3 V ±10% 0.65 1.3 mA IDD3 STOP mode VDD = 3 V ±10% 2.0 9.0 µA VDD = 3 V ±10%, T A = 25°C 1.8 3.0 µA Data Sheet U16363EJ1V0DS µPD69A AC Characteristics (TA = –40 to +85°C, VDD = 1.8 to 3.6 V) Item Symbol Command execution time tCY MIN. TYP. MAX. Unit When normal instruction execution is selected Conditions 14 16 18.5 µs When high-speed instruction execution is 7 8 9.25 µs selected KI, S0, S1, S2 high-level 10 µs In HALT mode 10 µs In STOP mode Note µs tH width When releasing standby mode Note 10 + 284/fX + oscillation growth time (normal instruction execution), 10 + 270/fX + oscillation growth time (high-speed instruction execution) Remark tCY = 64/fX (normal instruction execution), tCY = 32/fX (high-speed instruction execution)(fX: System clock oscillator frequency) POC Circuit (TA = –40 to +85°C) Item POC detection Symbol voltageNote VPOC Conditions MIN. When normal POC detection voltage is selected When low POC detection voltage is selected TYP. MAX. Unit 1.85 2.0 V 1.7 1.8 V Note Refers to the voltage with which the POC circuit releases an internal reset. If VPOC < VDD, the internal reset is released. From the time of VPOC ≥ VDD until the internal reset takes effect, a delay of up to 1 ms occurs. When the period of VPOC ≥ VDD lasts less than 1 ms, the internal reset may not take effect. System Clock Oscillator Characteristics (TA = –40 to +85°C, VDD = 1.8 to 3.6 V) Item Oscillator frequency (ceramic resonator) Symbol Conditions fX Data Sheet U16363EJ1V0DS MIN. TYP. MAX. Unit 3.5 4.0 4.5 MHz 59 µPD69A RECOMMENDED OSCILLATOR CONSTANT Ceramic Resonator (TA = –40 to +85°C) (without on-chip capacitor for oscillator specified by mask option) Manufacturer Part Number Frequency Recommended Constant (pF) (MHz) Murata Mfg. CSTLS3M50G53-B0 Co., Ltd. CSTLS3M50G56-B0 CSALA4M00G55-B0 3.5 4.0 CSTLS4M00G53-B0 C1 Oscillation Voltage Range (VDD) C2 Unnecessary (on-chip C type) 30 MIN. 2.0 Remark MAX. 3.6 – 30 Unnecessary (on-chip C type) CSTLS4M00G56-B0 CSTLS4M50G53-B0 4.5 CSTLS4M50G56-B0 TDK FCR3.52MC5 3.52 FCR4.0MC5 4.0 Kyocera KBR-3.64MKE 3.64 Unnecessary (on-chip C type) 4.0 Unnecessary (on-chip C type) KBR-3.64MSE KBR-4.0MKE KBR-4.0MSE Unnecessary (on-chip C type) 33 33 33 33 External circuit example XIN XOUT C1 C2 Caution These oscillator constants are reference values based on evaluation by the manufacturer of the resonator under a specific environment. If optimization of the oscillator characteristics is required for the actual application, apply to the resonator manufacturer for evaluation on the mounting circuit. The oscillation voltage and oscillation frequency only indicate the oscillator characteristics; the oscillator must be used within the ratings of the DC and AC characteristics specified under the internal operation conditions of the µPD69A. Remark The incorporation of the oscillation capacitor by a mask option is under evaluation. Contact an NEC Electronics sales representative for details of the evaluation status. 60 Data Sheet U16363EJ1V0DS µPD69A 13. CHARACTERISTIC CURVES (REFERENCE VALUES) (NORMAL INSTRUCTION EXECUTION) IOL vs. VOL (REM, LED) (TA = 25°C, VDD = 3.0 V) IDD vs. VDD (fx = 4 MHz) (TA = 25°C) 25 1 Low-level output current IOL [mA] Power supply current IDD [mA] 0.9 0.8 0.7 0.6 Operation mode 0.5 HALT mode 0.4 0.3 0.2 20 15 10 5 0.1 0 1.5 2 2.5 3 3.6 0 4 500 450 Low-level output current IOL [µ A] High-level output current IOH [mA] 3 IOL vs. VOL (KI/O) (TA = 25°C, VDD = 3.0 V) IOH vs. VOH (REM, LED, KI/O) (TA = 25°C, VDD = 3.0 V) − 18 − 16 − 14 − 12 − 10 −8 −6 −4 −2 0 VDD 2 Low-level output voltage VOL [V] Power supply voltage VDD [V] − 20 1 400 350 300 250 200 150 100 50 VDD − 1 VDD − 2 VDD − 3 0 High-level output voltage VOH [V] Data Sheet U16363EJ1V0DS 1 2 Low-level output voltage VOL [V] 3 61 µPD69A 14. APPLICATION CIRCUIT EXAMPLE Example of Application in System • Remote-control transmitter (48 keys; mode selection switch supported) + KI/O6 KI/O5 KI/O7 KI/O4 S0 KI/O3 S1/LED KI/O2 REM KI/O1 VDD KI/O0 XOUTNote 1 KI3Note 3 XINNote 1 KI2Note 3 GND KI1Note 3 S2Note 2 KI0Note 3 Mode selection switch Key matrix 8 × 6 = 48 keys Notes 1. When incorporation of a capacitor for oscillation has not been specified by a mask option. 2. S2: Set to disable for STOP mode release. 3. Connect pins KI0 to KI3 to pull-down resistors. 62 Data Sheet U16363EJ1V0DS µPD69A • Remote-control transmitter (56 keys accommodated) + KI/O6 KI/O5 KI/O7 KI/O4 S0 KI/O3 S1/LED KI/O2 REM KI/O1 VDD KI/O0 XOUTNote 1 KI3Note 3 XINNote 1 KI2Note 3 GND KI1Note 3 S2Note 2 KI0Note 3 Key matrix 8 × 7 = 56 keys Notes 1. When incorporation of a capacitor for oscillation has not been specified by a mask option. 2. S2: Set to enable for STOP mode release. 3. Connect pins KI0 to KI3 to pull-down resistors. Data Sheet U16363EJ1V0DS 63 µPD69A • Remote-control transmitter (56 keys supported, mode selection switch supported) Data can be read from the KI/O0 to KI/O7 pins by connecting a pull-up resistor of 50 kΩ and a switch to these pins (which then become high level when the switch is on and low level when off). Set the KI/O0 to KI/O7 pins to input mode at this time. Reading data from these pins enables multiple output data to be obtained for the same key input. A pull-up resistor can be connected to any of pins KI/O0 to KI/O7 (the figure below shows an example of when a pull-up resistor is connected to the KI/O5 pin). The mode may not be correctly read while a key is being pressed. VDD Mode selection switch + KI/O6 KI/O5 KI/O7 KI/O4 S0 KI/O3 S1/LED KI/O2 REM KI/O1 VDD XOUT KI/O0 Note 1 Note 3 KI3 XINNote 1 KI2Note 3 GND KI1Note 3 S2Note 2 KI0Note 3 Key matrix 8 × 7 = 56 keys Notes 1. When incorporation of a capacitor for oscillation has not been specified by a mask option. 2. S2: Set to enable for STOP mode release. 3. Connect pins KI0 to KI3 to pull-down resistors. 64 Data Sheet U16363EJ1V0DS µPD69A 15. PACKAGE DRAWINGS 20-PIN PLASTIC SSOP (7.62 mm (300)) 20 11 detail of lead end F G T P L U E 1 10 A H J I S N S K C D M M B NOTE Each lead centerline is located within 0.13 mm of its true position (T.P.) at maximum material condition. ITEM A MILLIMETERS 6.65±0.15 B 0.475 MAX. C 0.65 (T.P.) D +0.08 0.24 –0.07 E 0.1±0.05 F 1.3±0.1 G 1.2 H 8.1±0.2 I 6.1±0.2 J 1.0±0.2 K 0.17±0.03 L 0.5 M 0.13 N 0.10 P +5° 3° −3° T 0.25 U 0.6±0.15 S20MC-65-5A4-2 Remark The external dimensions and material of the ES version are the same as those of the mass produced version. Data Sheet U16363EJ1V0DS 65 µPD69A 16. RECOMMENDED SOLDERING CONDITIONS The µPD69A should be soldered and mounted under the following recommended conditions. For details of the recommended soldering conditions, refer to the document Semiconductor Device Mounting Technology Manual (C10535E). For soldering methods and conditions other than those recommended below, contact an NEC Electronics sales representatives. Table 16-1. Surface Mounting Type Soldering Conditions µ PD69AMC-×××-5A4: 20-pin plastic SSOP (7.62 mm (300)) Soldering Method Soldering Conditions Infrared reflow Package peak temperature: 235°C, Time: 30 seconds max. (at 210°C or higher), Count: Three times or less IR35-00-3 VPS Package peak temperature: 215°C, Time: 40 seconds max. (at 200°C or higher), Count: Three times or less VP15-00-3 Wave soldering Solder bath temperature: 260°C max., Time: 10 seconds max., Count: once, Preliminary heat temperature: 120°C max. (package surface temperature) WS60-00-1 Partial heating Pin temperature: 300°C max., Time: 3 sec. max. (per pin row) — Caution Do not use different soldering methods together (except for partial heating). 66 Recommended Condition Symbol Data Sheet U16363EJ1V0DS µPD69A APPENDIX A. DEVELOPMENT TOOLS An emulator is provided as an emulation tool and a PROM programmer and program adapter are provided as writing tools for the PROM product, the µPD6P9. Hardware • Emulator (EB-69Note 1, EB-69ANote 1, 2) Tool to emulate the µPD69A and 6P9. • Emulation probe (NP-20GSNote 1) Probe for 20-pin SOP/SSOP to connect the emulator to the target system. • Flexible board (EV-9500GS-20) 20-pin flexible board to facilitate the connection between the emulation probe and the target system. • PROM programmer (AF-9706Note 3, AF-9708Note 3, AF-9709 Note 3) PROM programmer supporting the µPD6P9. The µPD6P9 can be programmed by connecting the program adapter. • Program adapter (PA-61P34BMC) Adapter to program the µPD6P9. Use in combination with the AF-9706, AF-9708, and AF-9709. Notes 1. This is a product of Naito Densei Machida Mfg. Co., Ltd. For details, contact Naito Densei Machida Mfg. Co., Ltd. (TEL: +81-45-475-4191). 2. The EB-69A supports high-speed instruction execution (under development). 3. This is a product of Ando Electric Co., Ltd. For details, contact Ando Electric Co., Ltd. (TEL: +81-3-3733-1151). Software • Assembler (AS6133 Ver. 2.22 or later) Development tool for remote control transmitter software. Ordering Number List of AS6133 Host Machine PC-9800 series OS Supply Medium Ordering Number MS-DOS (Ver. 5.0 to Ver. 6.2) 3.5-inch 2HD µS5A13AS6133 MS-DOS (Ver. 6.0 to Ver. 6.22) 3.5-inch 2HC µS7B13AS6133 (CPU: 80,386 or more) IBM PC/AT compatible PC DOS (Ver. 6.1 to Ver. 6.3) Caution Although Ver.5.0 or later has a task swap function, this function cannot be used with this software. Data Sheet U16363EJ1V0DS 67 µPD69A APPENDIX B. FUNCTIONAL COMPARISON BETWEEN µPD69A AND OTHER PRODUCTS µPD67A Item 1,002 × 10 bits 32 × 4 bits ROM capacity RAM capacity µPD68A 2,026 × 10 bits Stack Key matrix Key extended input Clock frequency Timer 1 level (multiplexed with RF of RAM) 8 × 7 = 56 keys S0 to S 2 Ceramic oscillation • fX = 3.5 to 4.5 MHz Clock fX/64 Count start Writing count value Output value (Set value + 1) × 64/fX – 4/fX µPD69A 4,074 × 10 bits 128 × 4 bits (32 × 4 bits × 4 pages) Normal instruction execution: (Set value + 1) × 64/fX – 4/fX High-speed instruction execution: (Set value + 0.5) × 64/fX – 2/fX Carrier Frequency Each high-/low-level width can be set from 250 ns to 64 µs (@ fX = 4 MHz operation) via modulo registers (2 channels). Output start Synchronized with timer Instruction execution time 16 µs (fX = 4 MHz) Normal instruction execution: 16 µs (@ fX = 4 MHz) High-speed instruction execution: 8 µs (@ fX = 4 MHz) “MOV Rn, @R0” instruction n = 1 to F Standby Reset POC mode Release • HALT mode for timer only. condition • STOP mode for only releasing KI (HALT (KI/O high-level output or KI/O0 high-level output) instruction) Relation between HALT HALT instruction not executed when F = 1 instruction execution and status flag (F) POC circuit • Provided • Provided • Generates internal reset signal on detection • Generates internal reset signal on detection • VPOC = 1.85 V (TYP.) • Normal POC detection voltage: VPOC = 1.85 V (TYP.) • Low POC detection voltage: VPOC = 1.7 V (TYP.) RAM retention detector • Provided • Provided • VID = 1.4 V (TYP.) • Normal POC detection voltage: VID = 1.4 V (TYP.) • Low POC detection voltage: VID = 1.2 V (TYP.) Mask option Capacitor for oscillator (15 pF) • Capacitor for oscillator (15 pF) • High-speed instruction execution • Low POC detection voltage Supply voltage VDD = 2.0 to 3.6 V • Normal POC detection voltage: VDD = 2.0 to 3.6 V • Low POC detection voltage: VDD = 1.8 to 3.6 V Operating temperature TA = –40 to +85°C Package 20-pin plastic SSOP One-time PROM version 68 µPD6P9 Data Sheet U16363EJ1V0DS µPD69A APPENDIX C. EXAMPLE OF REMOTE-CONTROL TRANSMISSION FORMAT (in the case of NEC transmission format in command one-shot transmission mode) Caution When using the NEC transmission format, please apply to NEC Electronics for a custom code. (1) REM output waveform (From <2> on, the output is made only when the key is held down) REM output 58.5 to 76.5 ms <1> 108 ms <2> 108 ms Remark If the key is repeatedly pressed, the power consumption of the infrared light-emitting diode (LED) can be reduced by sending the reader code and the stop bit from the second time. (2) Enlarged waveform of <1> <3> REM output 9 ms 4.5 ms Custom code 8 bits 13.5 ms Leader code Custom code' 8 bits Data code 8 bits 18 to 36 ms Data code 8 bits Stop bit 1 bit 27 ms 58.5 to 76.5 ms (3) Enlarged waveform of <3> REM output 4.5 ms 9 ms 0.56 ms 1.125 ms 2.25 ms 0 1 13.5 ms 1 0 0 (4) Enlarged waveform of <2> REM output 2.25 ms 9 ms 11.25 ms Leader code Data Sheet U16363EJ1V0DS 0.56 ms Stop bit 69 µPD69A (5) Carrier waveform (enlarged waveform of each code’s high period) REM output 8.77 µ s 26.3 µ s 9 ms or 0.56 ms Carrier frequency: 38 kHz (6) Bit array of each code C0 C1 C2 C3 C4 C5 C6 C7 C0' C1' C2' C3' C4' C5' C6' C7' D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 = = = = = = = = C0 C1 C2 C3 C4 C5 C6 C7 or or or or or or or or Co C1 C2 C3 C4 C5 C6 C 7 Leader code Custom code Custom code' Data code Data code Caution To prevent malfunction with other systems when receiving data in the NEC transmission format, not only fully decode (make sure to check Data code as well) the total 32 bits of the 16-bit custom codes (Custom code, Custom code’) and the 16-bit data codes (Data code, Data code), but also check to make sure that no signals are present. 70 Data Sheet U16363EJ1V0DS µPD69A [MEMO] Data Sheet U16363EJ1V0DS 71 µPD69A NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to V DD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function. 72 Data Sheet U16363EJ1V0DS µPD69A Regional Information Some information contained in this document may vary from country to country. Before using any NEC Electronics product in your application, pIease contact the NEC Electronics office in your country to obtain a list of authorized representatives and distributors. They will verify: • Device availability • Ordering information • Product release schedule • Availability of related technical literature • Development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, AC supply voltages, and so forth) • Network requirements In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. NEC Electronics America, Inc. (U.S.) Santa Clara, California Tel: 408-588-6000 800-366-9782 Fax: 408-588-6130 800-729-9288 NEC Electronics (Europe) GmbH Duesseldorf, Germany Tel: 0211-65 03 01 Fax: 0211-65 03 327 • Sucursal en España Madrid, Spain Tel: 091-504 27 87 Fax: 091-504 28 60 • Succursale Française Vélizy-Villacoublay, France Tel: 01-30-67 58 00 Fax: 01-30-67 58 99 • Filiale Italiana Milano, Italy Tel: 02-66 75 41 Fax: 02-66 75 42 99 NEC Electronics Hong Kong Ltd. • Branch The Netherlands Eindhoven, The Netherlands Tel: 040-244 58 45 Fax: 040-244 45 80 NEC Electronics Hong Kong Ltd. Hong Kong Tel: 2886-9318 Fax: 2886-9022/9044 Seoul Branch Seoul, Korea Tel: 02-528-0303 Fax: 02-528-4411 • Tyskland Filial Taeby, Sweden Tel: 08-63 80 820 Fax: 08-63 80 388 NEC Electronics Shanghai, Ltd. • United Kingdom Branch Milton Keynes, UK Tel: 01908-691-133 Fax: 01908-670-290 NEC Electronics Taiwan Ltd. Shanghai, P.R. China Tel: 021-6841-1138 Fax: 021-6841-1137 Taipei, Taiwan Tel: 02-2719-2377 Fax: 02-2719-5951 NEC Electronics Singapore Pte. Ltd. Novena Square, Singapore Tel: 6253-8311 Fax: 6250-3583 J02.11 Data Sheet U16363EJ1V0DS 73 µPD69A MS-DOS is either a registered trademark or a trademark of Microsoft Corporation in the United States and/or other countries. PC/AT and PC DOS are trademarks of International Business Machines Corporation. These commodities, technology or software, must be exported in accordance with the export administration regulations of the exporting country. Diversion contrary to the law of that country is prohibited. • The information in this document is current as of September, 2002. The information is subject to change without notice. For actual design-in, refer to the latest publications of NEC Electronics data sheets or data books, etc., for the most up-to-date specifications of NEC Electronics products. Not all products and/or types are available in every country. Please check with NEC Electronics sales representative for availability and additional information. • No part of this document may be copied or reproduced in any form or by any means without prior written consent of NEC Electronics. NEC Electronics assumes no responsibility for any errors that may appear in this document. • NEC Electronics does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of NEC Electronics products listed in this document or any other liability arising from the use of such NEC Electronics products. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Electronics or others. • Descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software and information in the design of customer's equipment shall be done under the full responsibility of customer. NEC Electronics assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. • While NEC Electronics endeavors to enhance the quality, reliability and safety of NEC Electronics products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize risks of damage to property or injury (including death) to persons arising from defects in NEC Electronics products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment and anti-failure features. • NEC Electronics products are classified into the following three quality grades: "Standard", "Special" and "Specific". The "Specific" quality grade applies only to NEC Electronics products developed based on a customerdesignated "quality assurance program" for a specific application. The recommended applications of NEC Electronics product depend on its quality grade, as indicated below. Customers must check the quality grade of each NEC Electronics product before using it in a particular application. "Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots. "Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support). "Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. The quality grade of NEC Electronics products is "Standard" unless otherwise expressly specified in NEC Electronics data sheets or data books, etc. If customers wish to use NEC Electronics products in applications not intended by NEC Electronics, they must contact NEC Electronics sales representative in advance to determine NEC Electronics's willingness to support a given application. (Note) (1) "NEC Electronics" as used in this statement means NEC Electronics Corporation and also includes its majority-owned subsidiaries. (2) "NEC Electronics products" means any product developed or manufactured by or for NEC Electronics (as defined above). M8E 02. 11