DATA SHEET MOS INTEGRATED CIRCUIT µPD62A 4-BIT SINGLE-CHIP MICROCONTROLLER FOR INFRARED REMOTE CONTROL TRANSMISSION DESCRIPTION Due to its low-voltage 2.0 V operation, on-chip carrier generator for infrared remote control transmission, standby release function through key entry, and programmable timer, the µPD62A is ideal for infrared remote control transmitters. For the µPD62A, the one-time PROM product µPD6P4B has been made available for program evaluation or small-scale production. FEATURES • Program memory (ROM): 512 × 10 bits • Data memory (RAM): 32 × 4 bits • On-chip carrier generator for infrared remote control • 9-bit programmable timer: 1 channel • Command execution time: 8 µs (when operating at fX = 8 MHz: ceramic oscillation) • Stack levels: 1 (Stack RAM is also available for data memory RF.) • I/O pins (KI/O): 8 • Input pins (KI): 4 • Sense input pin (S0) • S1/LED pin (I/O): When in output mode, this is the remote control transmission display pin. • Power supply voltage: VDD = 2.0 to 3.6 V • Operating ambient temperature: TA = –40 to +85˚C • Oscillator frequency: fX = 2.4 to 8 MHz • POC (Power On Clear) circuit (Mask option) APPLICATION Infrared remote control transmitter (for AV and household electrical appliances) The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all devices/types available in every country. Please check with local NEC representative for availability and additional information. Document No. U14474EJ1V0DS00 (1st edition) Date Published November 1999 N CP(K) Printed in Japan © 1999 µPD62A ORDERING INFORMATION Part Number µPD62AMC-×××-5A4 Package 20-pin plastic SSOP (300 mils) Remark ××× indicates ROM code suffix. PIN CONFIGURATION (TOP VIEW) 20-pin Plastic SSOP (300 mils) • µPD62AMC-×××-5A4 KI/O6 1 20 KI/O5 KI/O7 2 19 KI/O4 S0 3 18 KI/O3 S1/LED 4 17 KI/O2 REM 5 16 KI/O1 VDD 6 15 KI/O0 XOUT 7 14 KI3 XIN 8 13 KI2 GND 9 12 KI1 10 11 KI0 RESET Caution The order of the KI and KI/O pin numbers is the reverse of that of the µPD6600A and 6124A. 2 Data Sheet U14474EJ1V0DS00 µPD62A BLOCK DIAGRAM Carrier generator REM CPU core Port KI 4 KI0-KI3 8 Port KI/O 8 KI/O0-KI/O7 2 Port S 2 S0, S1/LED ROM 9-bit timer S1/LED 4 RAM RESET System control XIN XOUT VDD GND LIST OF FUNCTIONS µPD62A Item ROM capacity µPD6P4B 512 × 10 bits 1002 × 10 bits Mask ROM One-time PROM RAM capacity 32 × 4 bits Stack 1 level (RAM also used as RF) I/O pins • • • • Number of keys • 32 keys • 48 keys (when extended by key extension input) • 96 keys (when extended by key extension input and diode) Clock frequency Ceramic oscillation • fX = 2.4 to 8 MHz Instruction execution time 8 µs (fX = 8 MHz) Carrier frequency fX/8, fX/16, fX/64, fX/96, fX /128, fX/192, no carrier (high level) Key input (KI): Key I/O (K I/O): Key extended input (S0, S1): Remote control transmission display output (LED): 4 8 2 1 (alternately functions as S1 pin) Timer 9-bit programmable timer: 1 channel POC circuit Mask option Internal Supply voltage VDD = 2.0 to 3.6 V VDD = 2.2 to 3.6 V (f X = 2.4 to 4 MHz) VDD = 2.7 to 3.6 V (f X = 4 to 8 MHz) Operating ambient temperature T A = –40 to +85°C Package • 20-pin plastic SSOP (300 mils) Data Sheet U14474EJ1V0DS00 • 20-pin plastic SOP (300 mils) • 20-pin plastic SSOP (300 mils) 3 µPD62A TABLE OF CONTENTS 1. PIN FUNCTIONS .......................................................................................................................... 6 1.1 List of Pin Functions ......................................................................................................................... 6 1.2 Pin Input/Output Circuits .................................................................................................................. 7 1.3 Recommended Connection of Unused Pins ................................................................................... 8 2. INTERNAL CPU FUNCTIONS ..................................................................................................... 9 2.1 Program Counter (PC) ...................................................................................................................... 9 2.2 Stack Pointer (SP) ............................................................................................................................. 9 2.3 Address Stack Register (ASR (RF)) ................................................................................................. 9 2.4 Program Memory (ROM) ................................................................................................................... 10 2.5 Data Memory (RAM) .......................................................................................................................... 10 2.6 Data Pointer (DP) ............................................................................................................................... 11 2.7 Accumulator (A) ................................................................................................................................ 11 2.8 Arithmetic and Logic Unit (ALU) ...................................................................................................... 12 2.9 Flags ................................................................................................................................................... 12 2.9.1 Status flag (F) .......................................................................................................................... 12 2.9.2 Carry flag (CY) ........................................................................................................................ 13 3. PORT REGISTERS (PX) .............................................................................................................. 14 3.1 3.2 KI/O Port (P0) ....................................................................................................................................... 15 KI Port/Special Ports (P1) ................................................................................................................. 16 3.2.1 KI port (P11: bits 4 to 7 of P1) .................................................................................................. 16 3.2.2 S0 port (bit 2 of P1) .................................................................................................................. 16 3.2.3 S1/LED (bit 3 of P1) ................................................................................................................. 16 3.3 Control Register 0 (P3) ..................................................................................................................... 17 3.4 Control Register 1 (P4) ..................................................................................................................... 18 4. TIMER ........................................................................................................................................... 19 4.1 Timer Configuration .......................................................................................................................... 19 4.2 Timer Operation ................................................................................................................................. 20 4.3 Carrier Output .................................................................................................................................... 21 4.4 Software Control of Timer Output ................................................................................................... 21 5. STANDBY FUNCTION ................................................................................................................. 22 5.1 Outline of Standby Function ............................................................................................................ 22 5.2 Standby Mode Setting and Release ................................................................................................. 23 5.3 Standby Mode Release Timing ........................................................................................................ 24 6. RESET PIN ................................................................................................................................... 26 7. POC CIRCUIT (MASK OPTION) .................................................................................................. 27 7.1 Functions of POC Circuit .................................................................................................................. 28 7.2 Oscillation Check at Low Supply Voltage ....................................................................................... 28 8. SYSTEM CLOCK OSCILLATOR ................................................................................................. 29 4 Data Sheet U14474EJ1V0DS00 µPD62A 9. INSTRUCTION SET ...................................................................................................................... 30 9.1 Machine Language Output by Assembler ....................................................................................... 30 9.2 Circuit Symbol Description .............................................................................................................. 31 9.3 Mnemonic to/from Machine Language (Assembler Output) Contrast Table ............................... 32 9.4 Accumulator Operation Instructions ............................................................................................... 36 9.5 Input/Output Instructions ................................................................................................................. 39 9.6 Data Transfer Instruction .................................................................................................................. 40 9.7 Branch Instructions .......................................................................................................................... 42 9.8 Subroutine Instructions .................................................................................................................... 43 9.9 Timer Operation Instructions ........................................................................................................... 44 9.10 Others ................................................................................................................................................. 45 10. ASSEMBLER RESERVED WORDS .......................................................................................... 47 10.1 Mask Option Directives .................................................................................................................... 47 10.1.1 OPTION and ENDOP directives ............................................................................................. 47 10.1.2 Mask option definition directive ............................................................................................... 47 11. ELECTRICAL SPECIFICATIONS .............................................................................................. 48 12. CHARACTERISTIC CURVES (REFERENCE VALUES) ........................................................... 52 13. APPLICATION CIRCUIT EXAMPLE .......................................................................................... 53 14. PACKAGE DRAWINGS ............................................................................................................. 54 15. RECOMMENDED SOLDERING CONDITIONS ......................................................................... 55 APPENDIX A. DEVELOPMENT TOOLS ......................................................................................... 56 APPENDIX B. FUNCTIONAL COMPARISON BETWEEN µPD62A AND OTHER SUBSERIES ... 57 APPENDIX C. EXAMPLE OF REMOTE-CONTROL TRANSMISSION FORMAT .......................... 58 Data Sheet U14474EJ1V0DS00 5 µPD62A 1. PIN FUNCTIONS 1.1 List of Pin Functions Pin No. Symbol Function After Format After Reset 1 2 15 to 20 KI/O0 to KI/O7 8-bit input/output port Input/output can be specified in 8-bit units. In input mode, a pull-down resistor is added. In output mode, these pins can be used as the key scan output of the key matrix. 3 S0 Input port Can also be used as the key return input of the key matrix. In input mode, the use of a pull-down resistor for the S0 and S1 ports can be specified by software in 2-bit units. If input mode is canceled by software, this pin is placed in OFF mode and enters the high-impedance state. 4 S1/LED Input/output port In input mode (S1), this pin can also be used as the key return input of the key matrix. The use of a pull-down resistor for the S0 and S1 ports can be specified by software in 2-bit units. In output mode (LED), it becomes the remote control transmission display output (active low). When the remote control carrier is output from the REM output, this pin outputs a low level from the LED output synchronously with the REM signal. CMOS push-pull High-level output (LED) 5 REM Infrared remote control transmission output. The output is active high. Carrier frequency: fX/8, fX/64, fX/96, high-level, fX/16, fX/128, fX/192 (software supporting) CMOS push-pull Low-level output 6 VDD Power supply — — 7 8 XOUT XIN These pins are connected to system clock ceramic resonators. — Low level (oscillation stopped) 9 GND Ground — — 10 RESET Normally, this pin is the system reset input. By inputting a low level, the CPU can be reset. When resetting with the POC circuit (mask option) a low level is output. A pull-up resistor is connected to this pin. — — 11 to 14 KI0 to K I3Note 2 4-bit input port These pins can be used as the key return input of the key matrix. The use of a pull-down resistor can be specified by software in 4-bit units. — CMOS push-pullNote 1 — High-level output High-impedance (OFF mode) Input (low-level) Notes 1. Be aware that the drive capability of the low-level output side is held low. 2. In order to prevent malfunction, be sure to input a low level to more than one of pins KI0 to KI3 when reset is released (when the RESET pin changes from low level to high level, or POC is released due to supply voltage startup). 6 Data Sheet U14474EJ1V0DS00 µPD62A 1.2 Pin Input/Output Circuits The input/output circuits of the µPD62A pins are shown in partially simplified forms below. (1) K I/O0 to K I/O7 (4) S 0 VDD Data Output latch Input buffer P-ch OFF mode N-chNote Output disable Selector Standby release N-ch Pull-down flag Input buffer N-ch (5) S1/LED VDD Note The drive capability is held low. REM output latch (2) K I0 to K I3 Standby release P-ch Output disable Input buffer N-ch Standby release Input buffer Pull-down flag N-ch N-ch Pull-down flag (3) REM (6) RESET VDD VDD P-ch P-ch Data Output latch N-ch Carrier generator Input buffer Internal reset signal other than POC N-ch POC circuit Data Sheet U14474EJ1V0DS00 Mask option 7 µPD62A 1.3 Recommended Connection of Unused Pins The following connections are recommended for unused pins. Table 1-1. Connections for Unused Pins Connection Pin Inside the Microcontroller KI/O Input mode Output mode — High-level output REM — S1/LED Output mode (LED) setting S0 OFF mode setting KI RESETNote Outside the Microcontroller Leave open — On-chip POC circuit Directly connect these pins to GND Leave open Note For application circuits requiring high reliability, be sure to design so that the RESET signal is input externally. Caution It is recommended that the I/O mode and the terminal output level are fixed by repeating the settings in each loop of the program. 8 Data Sheet U14474EJ1V0DS00 µPD62A 2. INTERNAL CPU FUNCTIONS 2.1 Program Counter (PC): 10 Bits This is a binary counter that holds the address information of the program memory. Figure 2-1. Program Counter Configuration PC PC9 PC8 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 The program counter contains the address of the instruction that should be executed next. Normally, the counter contents are automatically incremented in accordance with the instruction length (byte count) each time an instruction is executed. However, when executing JUMP instructions (JMP, JC, JNC, JF, JNF), the program counter contains the jump destination address written in the operand. When executing the subroutine call instruction (CALL), the call destination address written in the operand is entered in the PC after the PC contents at the time are saved in the address stack register (ASR). If the return instruction (RET) is executed after the CALL instruction is executed, the address saved in the ASR is restored to the PC. When reset, the value of the program counter becomes “000H”. 2.2 Stack Pointer (SP): 1 Bit This is a 1-bit register which holds the status of the address stack register. The stack pointer contents are incremented when the call instruction (CALL) is executed; they are decremented when the return instruction (RET) is executed. When reset, the stack pointer contents are cleared to 0. When the stack pointer overflows (stack level 2 or more) or underflows, the CPU is hung up and a system reset signal is generated, and the PC becomes “000H”. As no instruction is available to set a value directly for the stack pointer, it is not possible to operate the pointer by means of a program. 2.3 Address Stack Register (ASR (RF)): 10 Bits The address stack register saves the return address of the program after a subroutine call instruction is executed. The low-order 8 bits are configured as RAM that is also used as the data memory RF. The register holds the ASR value even after RET is executed. When reset, it holds the previous data (undefined on power application). Caution If RF is accessed as data memory, the high-order 2 bits of the ASR become undefined. Figure 2-2. Address Stack Register Configuration RF ASR ASR9 ASR8 ASR7 ASR6 ASR5 ASR4 ASR3 Data Sheet U14474EJ1V0DS00 ASR2 ASR1 ASR0 9 µPD62A 2.4 Program Memory (ROM): 512 steps × 10 bits The ROM consists of 10 bits per step, and is addressed by the program counter. The program memory stores programs and table data, etc. The 22 steps from 3EAH to 3FFH cannot be used in the test program area. Figure 2-3. Program Memory Map 10 bits 000H 0FFH 100H 1FFH 200H Unmounted areaNote 3E9H 3EAH 3FFH Test program areaNote Note The unmounted area and the test program area are so designed that a program or data placed in either of them by mistake is returned to the 000H address. 2.5 Data Memory (RAM): 32 × 4 Bits The data memory, which is a static RAM consisting of 32 × 4 bits, is used to retain processed data. The data memory is sometimes processed in 8-bit units. R0 can be used as the ROM data pointer. RF is also used as the ASR. When reset, R0 is cleared to “00H” and R1 to RF retain the previous data (undefined upon power application). 10 Data Sheet U14474EJ1V0DS00 µPD62A Figure 2-4. Data Memory Configuration R1n (high-order 4 bits) R0n (low-order 4 bits) →DP (refer to 2.6 Data Pointer (DP)) R0 R10 R00 R1 R11 R01 R2 R12 R02 R3 R13 R03 R4 R14 R04 R5 R15 R05 R6 R16 R06 R7 R17 R07 R8 R18 R08 R9 R19 R09 RA R1A R0A RB R1B R0B RC R1C R0C RD R1D R0D RE R1E R0E RF R1F R0F →ASR (refer to 2.3 Address Stack Register (ASR (RF))) 2.6 Data Pointer (DP): 10 Bits The ROM data table can be referenced by setting the ROM address in the data pointer to call the ROM contents. The low-order 8 bits of the ROM address are specified by R0 of the data memory; and the high-order 2 bits by bits 4 and 5 of the P3 register (CR0). When reset, the pointer contents become “000H”. Figure 2-5. Data Pointer Configuration P3 register P3 b5 b4 DP9 DP8 R10 DP7 DP6 R00 DP5 DP4 DP3 DP2 DP1 DP0 R0 2.7 Accumulator (A): 4 Bits The accumulator, which is a register consisting of 4 bits, plays a leading role in performing various operations. When reset, the accumulator contents become undefined. Figure 2-6. Accumulator Configuration A3 A2 A1 A0 Data Sheet U14474EJ1V0DS00 A 11 µPD62A 2.8 Arithmetic and Logic Unit (ALU): 4 Bits The arithmetic and logic unit (ALU), which is an arithmetic circuit consisting of 4 bits, executes simple manipulations with priority given to logical operations. 2.9 Flags 2.9.1 Status flag (F) Pin and timer statuses can be checked by executing the STTS instruction to check the status flag. The status flag is set (to 1) in the following cases. • If the condition specified with the operand is met when the STTS instruction has been executed • When standby mode is canceled. • When the cancelation condition is met at the point of executing the HALT instruction. (In this case, the system is not placed in standby mode.) Conversely, the status flag is cleared (to 0) in the following cases: • If the condition specified with the operand is not met when the STTS instruction has been executed. • When the status flag has been set (to 1), the HALT instruction executed, but the cancelation condition is not met at the point of executing the HALT instruction. (In this case, the system is not placed in standby mode.) Table 2-1. Conditions for Status Flag (F) to Be Set by STTS Instruction Operand Value of STTS Instruction b2 b1 b0 0 0 0 0 High level input to at least one of KI pins. 0 1 1 High level input to at least one of KI pins. 1 1 0 High level input to at least one of KI pins. 1 0 1 The down counter of the timer is 0. 1 12 Condition for Status Flag (F) to Be Set b3 Any combination of b2, b1, and b0 above. [The following condition is added in addition to the above.] High level input to at least one of S0 and S1 pins. Data Sheet U14474EJ1V0DS00 µPD62A 2.9.2 Carry flag (CY) The carry flag is set (to 1) in the following cases: • If the ANL instruction or the XRL instruction is executed when bit 3 of the accumulator is “1” and bit 3 of the operand is “1”. • If the RL instruction or the RLZ instruction is executed when bit 3 of the accumulator is “1”. • If the INC instruction or the SCAF instruction is executed when the value of the accumulator is 0FH. The carry flag is cleared (to 0) in the following cases: • If the ANL instruction or the XRL instruction is executed when at least either bit 3 of the accumulator or bit 3 of the operand is “0”. • If the RL instruction or the RLZ instruction is executed when bit 3 of the accumulator is “0”. • If the INC instruction or the SCAF instruction is executed when the value of the accumulator is other than 0FH. • If the ORL instruction is executed. • When data is written to the accumulator by the MOV instruction or the IN instruction. Data Sheet U14474EJ1V0DS00 13 µPD62A 3. PORT REGISTERS (PX) The KI/O port, the KI port, the special ports (S0, S1/LED), and the control registers are treated as port registers. The port register values after reset are shown below. Figure 3-1. Port Register Configuration Port Register After Reset P0 FFH P10 KI/O7 KI/O6 P00 KI/O5 KI/O4 KI/O3 KI/O2 KI/O1 KI/O0 × FHNote P1 P01 P11 KI3 KI2 KI1 KI0 S1/LED S0 1 1 P3 (Control register 0) 03H P03 P13 0 0 DP9 DP8 TCTL CARY MOD1 MOD0 P4 (Control register 1) 26H P14 0 Note P04 KI S0/S1 pull-down pull-down 0 S1/LED mode KI/O mode 0 S0 mode ×: Refers to the value based on the K I pin status. Table 3-1. Relationship Between Ports and Read/Write Port Name Input Mode Read Output Mode Write Read Write KI/O Pin status Output latch Output latch Output latch KI Pin status — S0 Pin status — Note — S1/LED Pin status — Pin status — — Note When in OFF mode, “1” is normally read. 14 Data Sheet U14474EJ1V0DS00 — µPD62A 3.1 K I/O Port (P0) The KI/O port is an 8-bit input/output port for key scan output. Input/output mode is set by bit 1 of the P4 register. If a read instruction is executed, the pin state can be read in input mode, whereas the output latch contents can be read in output mode. If the write instruction is executed, data can be written to the output latch regardless of input or output mode. When reset, the port is placed in output mode; and the value of the output latch (P0) becomes 1111 1111B. The KI/O port includes a pull-down resistor, allowing pull-down in input mode only. Caution If a key is double-pressed, a high-level output and a low-level output may coincide at the KI/O port. To avoid this, the low-level output current of the KI/O port is held low. Therefore, be careful when using the KI/O port for purposes other than key scan output. The KI/O port is so designed that, even when connected directly to VDD, within the normal supply voltage range (VDD = 2.0 to 3.6 V), no problem may occur. Table 3-2. KI/O Port (P0) Bit b7 b6 b5 b4 b3 b2 b1 b0 Name KI/O7 KI/O6 KI/O5 KI/O4 KI/O3 KI/O2 KI/O1 KI/O0 b0 to b7: Read: In input mode, the KI/O pin’s state is read. In output mode, the KI/O pin’s output latch contents are read. Write: Data is written to the KI/O pin’s output latch regardless of input or output mode. Data Sheet U14474EJ1V0DS00 15 µPD62A 3.2 K I Port/Special Ports (P1) 3.2.1 K I port (P 11 : bits 4 to 7 of P1) The KI port is a 4-bit input port for key entry. The pin status can be read at this port. Software can be used to set whether to connect a pull-down resistor at the KI port in 4-bit units by means of bit 5 of the P4 register. When reset, a pull-down resistor is connected. Table 3-3. KI/Special Port Register (P1) b2 : Bit b7 b6 b5 b4 b3 b2 b1 b0 Name KI3 KI2 KI1 KI0 S1/LED S0 (Fixed to 1) In input mode, the status of the S0 pin is read (Read only). In OFF mode, this bit is fixed to 1. b3 : The status of the S1/LED pin is read regardless of input/output mode (Read only). b4 to b7: The status of the KI pin is read (Read only). Caution In order to prevent malfunction, be sure to input a low level to more than one of pins KI0 to KI3 when reset is released (when the RESET pin changes from low level to high level, or POC is released due to supply voltage startup). 3.2.2 S 0 port (bit 2 of P1) The S0 port is the input/OFF mode port. The pin status can be read by setting this port to input mode with bit 0 of the P4 register. In input mode, software can be used to set whether to connect a pull-down resistor at the S0 and S1/LED ports in 2-bit units by means of bit 4 of the P4 register. If input mode is canceled (set to OFF mode), the pin becomes high-impedance, but the through current is stopped from flowing internally. In OFF mode, “1” can be read regardless of the pin status. When reset, this port is set to OFF mode and becomes high-impedance. 3.2.3 S 1/LED (bit 3 of P1) The S1/LED port is an input/output port. This port is set input or output mode by means of bit 2 of the P4 register. The pin status can be read in both input and output mode. In input mode, software can be used to set whether to connect a pull-down resistor at the S 0 and S 1 /LED ports in 2-bit units by means of bit 4 of the P4 register. In output mode, the pull-down resistor is automatically disconnected, and this port becomes the remote control transmission display pin (refer to 4. TIMER). When reset, this port is placed in output mode, and a high level is output. 16 Data Sheet U14474EJ1V0DS00 µPD62A 3.3 Control Register 0 (P3) Control register 0 consists of 8 bits. The contents that can be controlled are as shown below. When reset, this register becomes 0000 0011B. Table 3-4. Control Register 0 (P3) Bit b7 Name Set 0 value 1 After reset b6 b5 — — Fixed Fixed b4 b3 DP (Data pointer) TCTL DP9 DP8 0 0 1/1 b2 b1 b0 CARY MOD1 MOD0 ON to 0 to 0 1 1 1/2 OFF 0 0 0 0 0 0 Refer to Table 3-5. 1 1 b0 and b1: These bits specify the carrier frequency and duty ratio of the REM output. b2 : This bit specifies the availability of the carrier of the frequency specified by b0 and b1. “0” = ON (with carrier); “1” = OFF (without carrier; high level) b3 : This bit changes the carrier frequency and the timer clock’s frequency division ratio. “0” = 1/1 (carrier frequency: the specified value of b0 and b1; timer clock: f X/64) “1” = 1/2 (carrier frequency: half of the specified value of b0 and b1; timer clock: fX/128) Table 3-5. Timer Clock and Carrier Frequency Settings b3 0 0 b2 0 b1 b0 Timer Clock 0 0 0 1 fX/64 (Duty 1/2) 1 0 fX/96 (Duty 1/2) 1 1 fX/96 (Duty 1/3) 1 × × 0 0 0 0 1 fX/128 (Duty 1/2) 1 0 fX/192 (Duty 1/2) 1 1 fX/192 (Duty 1/3) × × Without carrier (high level) 1 fX/64 Carrier Frequency (Duty Ratio) fX/8 (Duty 1/2) Without carrier (high level) fX/128 fX/16 (Duty 1/2) b4 and b5: These bits specify the high-order 2 bits (DP8 and DP9) of the ROM data pointer. Remark ×: don’t care Data Sheet U14474EJ1V0DS00 17 µPD62A 3.4 Control Register 1 (P4) Control register 1 consists of 8 bits. The contents that can be controlled are as shown below. When reset, this register becomes 0010 0110B. Table 3-6. Control Register 1 (P4) Bit b7 Name b6 — — b5 b4 KI S0/S1 b3 — Pull-down Pull-down b2 b1 b0 S1/LED KI/O S0 mode mode mode Set 0 Fixed Fixed OFF OFF Fixed S1 IN OFF value 1 to 0 to 0 ON ON to “0” LED OUT IN 0 0 1 0 0 1 1 0 After reset b0: Specifies the input mode of the S0 port. “0” = OFF mode (high impedance); “1” = IN (input mode). b1: Specifies the I/O mode of the KI/O port. “0” = IN (input mode); “1” = OUT (output mode). b2: Specifies the I/O mode of the S1/LED port. “0” = S1 (input mode); “1” = LED (output mode). b4: Specifies the connection of a pull-down resistor in S0/S1 port input mode. “0” = OFF (not connected); “1” = ON (connected) b5: Specifies the connections of a pull-down resistor in KI port. “0” = OFF (not connected); “1” = ON (connected). Remark In output mode or in OFF mode, all the pull-down resistors are automatically disconnected. 18 Data Sheet U14474EJ1V0DS00 µPD62A 4. TIMER 4.1 Timer Configuration The timer is the block used for creating a remote control transmission pattern. As shown in Figure 4-1, it consists of a 9-bit down counter (t8 to t0), a flag (t9) enabling 1-bit timer output, and a zero-detection circuit. Figure 4-1. Timer Configuration t9 t8 T0 t7 t6 t5 t4 t3 t2 9-bit down counter t0 fX/64 fX/128 Timer operation end signal (HALT # ×101B release signal) S1/LED Carrier synchronous circuit REM t1 Count clock Selector Bit 3 of control register 0 (P3) T T1 Zero-detection circuit Bit 2 of control register 0 (P3) Carrier signal Data Sheet U14474EJ1V0DS00 19 µPD62A 4.2 Timer Operation The timer starts (counting down) when a value other than 0 is set for the down counter with a timer operation instruction. The timer operation instructions for making the timer start operation are shown below: MOV T0, A MOV T1, A MOV T, #data10 MOV T, @R0 The down counter is decremented (–1) in the cycle of 64/fX or 128/fXNote. If the value of the down counter becomes 0, the zero-detection circuit generates the timer operation end signal to stop the timer operation. At this time, if the timer is in HALT mode (HALT #×101B) waiting for the timer to stop its operation, the HALT mode is canceled and the instruction following the HALT instruction is executed. The output of the timer operation end signal is continued while the down counter is 0 and the timer is stopped. There is the following relational expression between the timer’s time and the down counter’s set value. Timer time = (Set value + 1) × 64/f X (or 128/fXNote) Note This becomes 128/fX if bit 3 of the control register is set (to 1). By setting 1 for the flag (t9) which enables the timer output, the timer can output its operation status from the S1/LED pin and the REM pin. The REM pin can also output the carrier while the timer is in operation. Table 4-1. Timer Output (at t9 = 1) Timer operating Timer halting S 1/LED Pin REM Pin L H H (or carrier output Note) L Note The carrier output results if bit 2 of control register 0 is cleared (to 0). Figure 4-2. Timer Output (When Carrier Is Not Output) Timer value: (set value + 1) × 64/fX (or 128/fX) LED REM 20 Data Sheet U14474EJ1V0DS00 µPD62A 4.3 Carrier Output The carrier for remote-controlled transmission can be output from the REM pin by clearing (to 0) bit 2 of control register 0. As shown in Figure 4-3, in the case where the timer stops when the carrier is at a high level, the carrier continues to be output until its next fall and then stops due to the function of the carrier synchronous circuit. When the timer starts operation, however, the high-level width of the first carrier may be shorter than the specified width. Figure 4-3. Timer Output (When Carrier Is Output) Timer value: (Set value+1) × 64/fX (or 128/fX) LED REM (at low-level start) Note 1 REM (at high-level start) Note 2 Notes 1. Error when the REM output ends: Lead by “the carrier’s low-level width” to lag by “the carrier’s highlevel width” 2. Error of the carrier’s high-level width: 0 to “the carrier’s high-level width” 4.4 Software Control of Timer Output The timer output can be controlled by software. As shown in Figure 4-4, a pulse with a minimum width of 1instruction cycle (64/fX) can be output. … Figure 4-4. Pulse Output of 1-Instruction Cycle Width … MOV T, #0000000000B; low-level output from the REM pin MOV T, #1000000000B; high-level output from the REM pin … MOV T, #0000000000B; low-level output from the REM pin 64/fX LED REM Data Sheet U14474EJ1V0DS00 21 µPD62A 5. STANDBY FUNCTION 5.1 Outline of Standby Function To save current consumption, two types of standby modes, HALT mode and STOP mode, are made available. In STOP mode, the system clock stops oscillation. At this time, the XIN and XOUT pins are fixed at a low level. In HALT mode, CPU operation halts, while the system clock continues oscillating. When in HALT mode, the timer (including REM output and LED output) operates. In either STOP mode or HALT mode, the statuses of the data memory, accumulator, and port register, etc. immediately before the standby mode was set are retained. Therefore, make sure to set the port status for the system so that the current consumption of the whole system is suppressed before the standby mode is set. Table 5-1. Statuses During Standby Mode STOP Mode Setting instruction HALT instruction Clock oscillation circuit Oscillation stopped CPU • Operation halted Data memory • Immediately preceding status retained Operation Accumulator • Immediately preceding status retained statuses Flag Port register Timer HALT Mode Oscillation continues F • 0 (When 1, the flag is not placed in the standby mode.) CY • Immediately preceding status retained • Immediately preceding status retained • Operation halted • Operable (The count value is reset to “0”) Cautions 1. Write the NOP instruction as the first instruction after STOP mode is canceled. 2. When standby mode is canceled, the status flag (F) is set (to 1). 3. If, at the point the standby mode has been set, its cancelation condition is met, then the system is not placed in the standby mode. However, the status flag (F) is set (1). 22 Data Sheet U14474EJ1V0DS00 µPD62A 5.2 Standby Mode Setting and Release The standby mode is set with the HALT #b3b 2b1b 0B instruction for both STOP mode and HALT mode. For the standby mode to be set, the status flag (F) is required to have been cleared (to 0). The standby mode is released by the release condition specified by the reset (RESET input; POC) or the HALT instruction operand. If the standby mode is released, the status flag (F) is set (to 1). Even when the HALT instruction is executed in a state in which the status flag (F) has been set (to 1), the standby mode is not set. If the release condition is not met at this time, the status flag is cleared (to 0). If the release condition is met, the status flag remains set (to 1). Even in the case when the release condition has already been met at the point that the HALT instruction is executed, the standby mode is not set. Here, also, the status flag (F) is set (to 1). Caution Depending on the status of the status flag (F), the HALT instruction may not be executed. Be careful about this. For example, when setting HALT mode after checking the key status with the STTS instruction, because the system does not enter HALT mode as long as the status flag (F) remains set (to 1), sometimes an unintended operation is performed. In this case, the intended operation can be realized by executing the STTS instruction immediately after the timer setting to clear (to 0) the status flag. #03H ;To check the KI pin status. MOV T, #0xxH ;To set the timer STTS #05H ;To clear the status flag STTS … … Example HALT (During this time, be sure not to execute an instruction that may set the status flag.) #05H ;To set HALT mode Table 5-2. Addresses Executed After Standby Mode Release Release Condition Address Executed After Release Reset 0 address Release condition shown in Table 5-3 The address following the HALT instruction Data Sheet U14474EJ1V0DS00 23 µPD62A Table 5-3. Standby Mode Settings (HALT #b3b2b1b0B) and Release Conditions Operand Value of HALT Instruction Setting Mode Setting Precondition Release Condition b3 b2 b1 b0 0 0 0 0 STOP All KI/O pins are high-level output. High level input to at least one of KI pins. 0 1 1 STOP All KI/O pins are high-level output. High level input to at least one of KI pins. 1 1 0 STOPNote 1 The KI/O0 pin is high-level output. High level input to at least one of KI pins. 1 Any combination of STOP [The following condition is added in addition to the above.] b2b1b0 above — High level input to at least one of S0 and S1 pins Note 2. 0/1 1 0 1 HALT — When the timer’s down counter is 0 Notes 1. When setting HALT #×110B, configure a key matrix by using the KI/O0 pin and the KI pin so that an internal reset takes effect at the time of program hang-up. 2. At least one of the S0 and S1 pins (the pin used for releasing standby) must be in input mode. (Note that an internal reset does not take effect even when both pins are in output mode.) Cautions 1. The internal reset takes effect when the HALT instruction is executed with an operand value other than that above or when the precondition has not been satisfied when executing the HALT instruction. 2. If STOP mode is set when the timer’s down counter is not 0 (timer operating), the system is placed in STOP mode only after all the 10 bits of the timer’s down counter and the timer output permit flag are cleared to 0. 3. Write the NOP instruction as the first instruction after STOP mode is released. 5.3 Standby Mode Release Timing (1) STOP mode release timing Figure 5-1. STOP Mode Cancelation by Release Condition HALT instruction (STOP mode) Wait (52/fX + α) Standby release signal Operating mode STOP mode Oscillation Oscillation stopped HALT mode Operating mode Oscillation Clock α : Oscillation growth time Caution When a release condition is established in the STOP mode, the device is released from the STOP mode, and goes into a wait state. At this time, if the release condition is not held, the device goes into STOP mode again after the wait time has elapsed. Therefore, when releasing the STOP mode, it is necessary to hold the release condition longer than the wait time. 24 Data Sheet U14474EJ1V0DS00 µPD62A Figure 5-2. STOP Mode Release by RESET Input HALT instruction (STOP mode) Wait (246 to 694)/fX + α 0 address start RESET STOP mode Operating mode Reset HALT mode Oscillation stopped Oscillation Operating mode Oscillation Clock α : Oscillation growth time (2) HALT mode release timing Figure 5-3. HALT Mode Release by Cancelation Condition Standby release signal HALT instruction (HALT mode) Operating mode HALT mode Operating mode Oscillation Clock Figure 5-4. HALT Mode Release by RESET Input HALT instruction (HALT mode) Wait (246 to 694)/fX + α 0 address start RESET Operating mode HALT mode Oscillation Reset HALT mode Oscillation stopped Operating mode Oscillation Clock α : Oscillation growth time Data Sheet U14474EJ1V0DS00 25 µPD62A 6. RESET PIN The system reset takes effect by inputting a low level to the RESET pin. While the RESET pin is at low level, the system clock oscillator is stopped and the XIN and XOUT pins are fixed to GND. If the RESET pin is raised from low level to high level, it executes the program from the 0 address after counting 246 to 694 of the system clock (fX). Figure 6-1. Reset Operation by RESET Input Wait (246 to 694)/fX + α 0 address start RESET Operating mode or standby mode Oscillation stopped HALT mode Operating mode α : Oscillation growth time The RESET pin outputs a low level when the POC circuit (mask option) is in operation. Caution When connecting a reset IC to the RESET pin, be sure to connect an IC of the N-ch open drain output type. Table 6-1. Hardware Statuses After Reset • RESET Input During Operation • RESET Input in Standby Mode • Reset by Internal POC Circuit During Operation • Reset by Internal POC Circuit in Standby • Reset by Other Factors Note 1 Mode Hardware PC (10 bits) 000H SP (1 bit) 0B Data R0 = DP 000H memory R1-RF Undefined Accumulator (A) Undefined Status flag (F) 0B Carry flag (CY) 0B Timer (10 bits) 000H Port register P0 FFH P1 ×FHNote 2 Control register P3 P4 Previous status retained 03H 26H Notes 1. The following resets are available. • Reset when executing the HALT instruction (when the operand value is illegal or does not satisfy the precondition) • Reset when executing the RLZ instruction (when A = 0) • Reset by stack pointer’s overflow or underflow 2. Refers to the value based on the KI pin status. In order to prevent malfunction, be sure to input a low level to more than one of pins KI0 to KI3 when reset is released (when the RESET pin changes from low level to high level, or POC is released due to supply voltage startup). 26 Data Sheet U14474EJ1V0DS00 µPD62A 7. POC CIRCUIT (MASK OPTION) The POC circuit monitors the power supply voltage and applies an internal reset in the microcontroller when the battery is replaced, etc. If the application circuit satisfies the following conditions, the POC circuit can be incorporated by the mask option. • High reliability is not required. • Clock frequency fX = 2.4 to 8 MHz • Operating ambient temperature TA = –40 to +85˚C Cautions 1. The one-time PROM product (µPD6P4B) already contains the POC circuit. 2. There are cases in which the POC circuit cannot detect a low power supply voltage of less than 1 ms. Therefore, if the power supply voltage has become low for a period of less than 1 ms, the POC circuit may malfunction because it does not generate an internal reset signal. 3. Clock oscillation is stopped by the resonator due to low power supply voltage before the POC circuit generates the internal reset signal. In this case, malfunction may result, for example when the power supply voltage is recovered after the oscillation is stopped. This type of phenomenon takes place because the POC circuit does not generate an internal reset signal (because the power supply voltage recovers before the low power supply voltage is detected) even though the clock has stopped. If, by any chance, a malfunction has taken place, remove the battery for a short time and put it back. In most cases, normal operation will be resumed. 4. If the application circuit does not satisfy the conditions above, design the application circuit so that the reset takes effect without failure within the power supply voltage range by means of an external reset circuit. 5. In order to prevent malfunction, be sure to input a low level to more than one of pins KI0 to KI3 when reset is released (when the RESET pin changes from low level to high level, or POC is released due to supply voltage startup). Remarks 1. It is recommended that the POC circuit be incorporated when the application circuit is an infrared remote-control transmitter for household appliances. 2. Even when a POC circuit is incorporated, the externally input RESET is valid with the OR condition; therefore, the POC circuit and the RESET input can be used at the same time. However, if the POC circuit detects a low power supply voltage, the RESET pin will be forced to low level; therefore, use an N-ch open drain output or NPN open collector output for the external reset circuit. Data Sheet U14474EJ1V0DS00 27 µPD62A 7.1 Functions of POC Circuit The POC circuit has the following functions: • Generating an internal reset signal when VDD ≤ VPOC. • Canceling an internal reset signal when VDD > VPOC. Here, VDD: power supply voltage, VPOC: POC-detected voltage. VDD Operating ambient temperature TA = –40 to +85°C 3.6 V Clock frequency fX = 2.4 to 8 MHz 2.0 V ←POC-detected voltage VPOC = 1.85 V (TYP.)Note 3 VPOC 1.7 V (approx.) 0V →t Internal reset signal Reset ↑ Note 1 Operating mode ↑ Reset Note 2 Notes 1. In reality, oscillation stabilization wait time must elapse before the circuit is switched to operating mode. The oscillation stabilization wait time is about 252/fX to 700/fX (about 70 to 190 µs: when f X = 3.64 MHz). 2. For the POC circuit to generate an internal reset signal when the power supply voltage has fallen, it is necessary for the power supply voltage to be kept less than the VPOC for a period of 1 ms or more. Therefore, in reality, there is a time lag of up to 1 ms until the reset takes effect. 3. The POC-detected voltage (VPOC) varies between about 1.7 to 2.0 V; thus, the reset may be canceled at a power supply voltage smaller than the assured range (VDD = 2.0 to 3.6 V). However, as long as the conditions for operating the POC circuit are met, the actual lowest operating power supply voltage becomes lower than the POC-detected voltage. Therefore, there is no malfunction occurring due to the shortage of power supply voltage. However, malfunction for such reasons as the clock not oscillating due to low power supply voltage may occur (refer to Cautions 3. in 7. POC CIRCUIT). 7.2 Oscillation Check at Low Supply Voltage A reliable reset operation can be expected of the POC circuit if it satisfies the condition that the clock can oscillate even at low power supply voltage (the oscillation start voltage of the resonator being even lower than the POCdetected voltage). Whether this condition is met or not can be checked by measuring the oscillation status on a product which actually contains a POC circuit, as follows. <1> Connect a storage oscilloscope to the X OUT pin so that the oscillation status can be measured. <2> Connect a power supply whose output voltage can be varied and then gradually raise the power supply voltage V DD from 0 V (making sure to avoid V DD > 3.6 V). At first (during VDD < 1.7 V (approx.)), the XOUT pin is 0 V regardless of the VDD. However, at the point that VDD reaches the POC-detected voltage (VPOC = 1.85 V (TYP.)), the voltage of the XOUT pin jumps to about 0.5 VDD. Maintain this power supply voltage for a while to measure the waveform of the XOUT pin. If, by any chance, the oscillation start voltage of the resonator is lower than the POC-detected voltage, the growing oscillation of the X OUT pin can be confirmed within several ms after the VDD has reached the VPOC. 28 Data Sheet U14474EJ1V0DS00 µPD62A 8. SYSTEM CLOCK OSCILLATOR The system clock oscillator configuration consists of a ceramic resonator oscillation circuit (fX = 2.4 to 8 MHz). Figure 8-1. System Clock µ PD62A XOUT XIN GND Ceramic resonator The system clock oscillator stops its oscillation when reset or in STOP mode. Caution When using the system clock oscillator, wire as follows in the area enclosed by the broken lines in the above figure to avoid an adverse effect from wiring capacitance. • Keep the wiring length as short as possible. • Do not cross the wiring with the other signal lines. Do not route the wire near a signal line through which a high fluctuating current flows. • Always make the ground point of the oscillator capacitor the same potential as the ground. Do not ground the capacitor to a ground pattern through which a high current flows. • Do not fetch signals from the oscillator. Data Sheet U14474EJ1V0DS00 29 µPD62A 9. INSTRUCTION SET 9.1 Machine Language Output by Assembler The bit length of the machine language of this product is 10 bits per word. However, the machine language that is output by the assembler is extended to 16 bits per word. As shown in the example below, the extension is made by inserting 3-bit extended bits (111) in two locations. Figure 9-1. Example of Assembler Output (10 Bits Extended to 16 Bits) <1> In the case of “ANL A, @R0H” 1 1 1 1 1 0 1 0 1 1 1 0 1 0 1 1 1 Extended bits 0 0 0 0 1 0 0 0 0 = FAF0 1 0 0 0 = E6F8 Extended bits <2> In the case of “OUT P0, #data8” 1 1 1 Extended bits 30 0 0 1 1 0 1 0 0 1 1 0 1 1 1 1 0 0 0 1 Extended bits Data Sheet U14474EJ1V0DS00 µPD62A 9.2 Circuit Symbol Description A: Accumulator ASR: Address Stack Register addr: Program memory address CY: Carry flag data4: 4-bit immediate data data8: 8-bit immediate data data10: 10-bit immediate data F: Status flag PC: Program Counter Pn: Port register pair (n = 0, 1, 3, 4) P0n: Port register (low-order 4 bits) P1n: Port register (high-order 4 bits) ROMn: Bit n of the program memory’s (n = 0 to 9) Rn: Register pair R0n: Data memory (General-purpose register; n = 0 to F) R1n: Data memory (General-purpose register; n = 0 to F) SP: Stack Pointer T: Timer register T0: Timer register (low-order 4 bits) T1: Timer register (high-order 4 bits) (×): Content addressed with × Data Sheet U14474EJ1V0DS00 31 µPD62A 9.3 Mnemonic to/from Machine Language (Assembler Output) Contrast Table Accumulator Operation Instructions Instruction Code Operand 1st Word Operation Instruction Instruction Length Cycle 3rd Word A, R0n FBEn (A) ← (A) A, R1n FAEn CY ← A3 • Rmn3 A, @R0H FAF0 (A) ← (A) (Rmn) m = 0, 1 n = 0 to F ∨ ANL 2nd Word ∨ Mnemonic 1 ((P13), (R0))7-4 CY ← A3 • ROM7 (A) ← (A) FBF0 ∨ A, @R0L ((P13), (R0))3-0 CY ← A3 • ROM3 FBF1 data4 (A) ← (A) ∨ A, #data4 data4 2 CY ← A3 • data43 ORL A, R0n FDEn (A) ← (A) ∨ (Rmn) m = 0, 1 n = 0 to F A, R1n FCEn CY ← 0 A, @R0H FCF0 1 (A) ← (A) ∨ ((P13), (R0))7-4 CY ← 0 A, @R0L (A) ← (A) ∨ ((P13), (R0))3-0 FDF0 CY ← 0 A, #data4 FDF1 data4 (A) ← (A) ∨ data4 2 CY ← 0 XRL A, R0n F5En (A) ← (A) ∨ (Rmn) m = 0, 1 n = 0 to F A, R1n F4En CY ← A3 • Rmn3 A, @R0H F4F0 1 (A) ← (A) ∨ ((P13), (R0))7-4 CY ← A3 • ROM7 A, @R0L (A) ← (A) ∨ ((P13), (R0))3-0 F5F0 CY ← A3 • ROM3 A, #data4 F5F1 data4 (A) ← (A) ∨ data4 2 CY ← A3 • data43 INC A F4F3 (A) ← (A) + 1 if (A) = 0 CY ← 1 else CY ← 1 RL A FCF3 (An+1) ← (A n), (A 0) ← (A3) RLZ A FEF3 if A = 0 CY ← A3 reset else (An+1) ← (An), (A0) ← (A 3) CY ← A3 32 Data Sheet U14474EJ1V0DS00 1 1 µPD62A Input/output Instructions Instruction Code Operand 1st Word IN OUT ANL ORL XRL Mnemonic Remark Operation FFF8 + n — — (A) ← (Pmn) A, P1n FEF8 + n — — CY ← 0 (Pmn) ← (A) m = 0, 1 n = 0, 1, 3, 4 m = 0, 1 n = 0, 1, 3, 4 P0n, A E5F8 + n — — P1n, A E4F8 + n — — A, P0n FBF8 + n — — (A) ← (A) A, P1n FAF8 + n — — CY ← A3 • Pmn3 A, P0n FDF8 + n — — (A) ← (A) ∨ (Pmn) m = 0, 1 n = 0, 1, 3, 4 A, P1n FCF8 + n — — CY ← 0 A, P0n F5F8 + n — — (A) ← (A) ∨ (Pmn) m = 0, 1 n = 0, 1, 3, 4 A, P1n F4F8 + n — — CY ← A3 • Pmn3 Pn, #data8 E6F8 + n 2nd Word Instruction Length Cycle 1 1 Instruction Instruction (Pmn) m = 0, 1 n = 0, 1, 3, 4 Instruction Code Operand Instruction 3rd Word A, P0n 1st Word OUT 2nd Word ∨ Mnemonic Operation 3rd Word Length (Pn) ← data8 data8 n = 0, 1, 3, 4 2 Cycle 1 Pn: P1n to P0n are dealt with in pairs. Data Transfer Instruction Mnemonic Instruction Code Operand 1st Word MOV 2nd Word Operation Instruction Instruction Length Cycle 3rd Word A, R0n FFEn (A) ← (Rmn) A, R1n FEEn CY ← 0 A, @R0H FEF0 (A) ← ((P13), (R0))7-4 m = 0, 1 n = 0 to F 1 1 CY ← 0 A, @R0L (A) ← ((P13), (R0))3-0 FFF0 CY ← 0 Mnemonic A, #data4 FFF1 R0n, A E5En R1n, A E4En Instruction Code Operand Remark 2 (Rmn) ← (A) 1st Word MOV (A) ← data4 CY ← 0 data4 2nd Word m = 0, 1 n = 0 to F Operation 1 Instruction Instruction Length Cycle 3rd Word Rn, #data8 E6En data8 — (R1n-R0n) ← data8 n = 0 to F 2 Rn, @R0 — — (R1n-R0n) ← ((P13), (R0)) n = 1 to F 1 E7En 1 Rn: R1n to R0n are dealt with in pairs. Data Sheet U14474EJ1V0DS00 33 µPD62A Branch Instructions Mnemonic Instruction Code Operand 1st Word JMP JC JNC JF JNF 2nd Word addr (Page 0) E8F1 addr addr (Page 1) E9F1 addr Operation Instruction Instruction Length Cycle 3rd Word PC ← addr 2 1 PC ← addr addr (Page 0) ECF1 addr if CY = 1 addr (Page 1) EAF1 addr else PC ← PC + 2 PC ← addr addr (Page 0) EDF1 addr if CY = 0 addr (Page 1) EBF1 addr else PC ← PC + 2 addr (Page 0) EEF1 addr if F = 1 addr (Page 1) F0F1 addr else PC ← PC + 2 addr (Page 0) EFF1 addr if F = 0 addr (Page 1) F1F1 addr else PC ← PC + 2 PC ← addr PC ← addr Caution 0 and 1, which refer to PAGE0 and 1, are not written when describing mnemonics. Subroutine Instructions Mnemonic Instruction Code Operand 1st Word CALL 2nd Word 3rd Word addr (Page 0) E6F2 E8F1 addr addr (Page 1) E6F2 E9F1 addr RET E8F2 Operation Instruction Instruction Length Cycle SP ← SP + 1, ASR ← PC, PC ← addr 3 2 PC ← ASR, SP ← SP – 1 1 1 Caution 0 and 1, which refer to PAGE0 and 1, are not written when describing mnemonics. Timer Operation Instructions Mnemonic Instruction Code Operand 1st Word MOV Mnemonic MOV 34 2nd Word 3rd Word FFFF A, T1 FEFF CY ← 0 T0, A E5FF (Tn) ← (A) T1, A F4FF (T) n ← 0 Instruction Code 1st Word 2nd Word T, #data10 E6FF data10 T, @R0 F4FF Instruction Length (A) ← (Tn) A, T0 Operand Instruction Operation n = 0, 1 1 Cycle 1 n = 0, 1 Operation Instruction Instruction Length Cycle 3rd Word (T) ← data10 (T) ← ((P13), (R0)) Data Sheet U14474EJ1V0DS00 1 1 µPD62A Others Mnemonic Instruction Code Operand 1st Word 2nd Word Operation Instruction Instruction Length Cycle 3rd Word HALT #data4 E2F1 data4 Standby mode STTS #data4 E3F1 data4 If statuses match R0n E3En If statuses match SCAF FAF3 If A = 0FH NOP E0E0 else else else 2 1 F←1 F←0 F←1 F←0 1 n = 0 to F CY ← 1 CY ← 0 PC ← PC + 1 Data Sheet U14474EJ1V0DS00 35 µPD62A 9.4 Accumulator Operation Instructions ANL A, R0n ANL A, R1n <1> Instruction code: 1 <2> Cycle count: 1 <3> Function: (A) ← (A) 1 0 1 R4 0 R3 R2 R1 R0 (Rmn) m = 0, 1 n = 0 to F ∨ CY ← A 3 • Rmn3 The accumulator contents and the register Rmn contents are ANDed and the results are entered in the accumulator. ANL A, @R0H ANL A, @R0L <1> Instruction code: 1 1 0 1 0/1 1 0 0 0 0 <2> Cycle count: 1 <3> Function: (A) ← (A) ((P13), (R0)) 7-4 (in the case of ANL A, @R0H) ∨ CY ← A 3 • ROM 7 ∨ (A) ← (A) ((P13), (R0)) 3-0 (in the case of ANL A, @R0L) CY ← A 3 • ROM 3 The accumulator contents and the program memory contents specified with the control register P13 and register pair R10-R00 are ANDed and the results are entered in the accumulator. If H is specified, b7, b6, b5, and b4 take effect. If L is specified, b3, b2, b1, and b0 take effect. • Program memory (ROM) organization b7 b9 b6 b5 b4 b8 b3 H↓ b2 b1 b0 L↓ Valid bits at the time of accumulator operation ANL A, #data4 <1> Instruction code: 1 1 0 1 1 1 0 0 0 1 0 0 0 0 0 0 d3 d2 d1 d0 1 <3> Function: (A) ← (A) ∨ <2> Cycle count: data4 CY ← A 3 • data43 The accumulator contents and the immediate data are ANDed and the results are entered in the accumulator. 36 Data Sheet U14474EJ1V0DS00 µPD62A ORL A, R0n ORL A, R1n <1> Instruction code: 1 1 1 0 R4 0 R3 R2 R1 R0 <2> Cycle count: 1 <3> Function: (A) ← (A) ∨ (Rmn) m = 0, 1 n = 0 to F CY ← 0 The accumulator contents and the register Rmn contents are ORed and the results are entered in the accumulator. ORL A, @R0H ORL A, @R0L <1> Instruction code: 1 1 1 0 0/1 1 0 0 0 0 <2> Cycle count: 1 <3> Function: (A) ← (A) ∨ (P13), (R0))7-4 (in the case of ORL A, @R0H) (A) ← (A) ∨ (P13), (R0))3-0 (in the case of ORL A, @R0L) CY ← 0 The accumulator contents and the program memory contents specified with the control register P13 and register pair R10-R00 are ORed and the results are entered in the accumulator. If H is specified, b7, b6, b5, and b4 take effect. If L is specified, b3, b2, b1, and b0 take effect. ORL A, #data4 <1> Instruction code: 1 1 1 0 1 1 0 0 0 1 0 0 0 0 0 0 d3 d2 d1 d0 <2> Cycle count: 1 <3> Function: (A) ← (A) ∨ data4 CY ← 0 The accumulator contents and the immediate data are exclusive-ORed and the results are entered in the accumulator. XRL A, R0n XRL A, R1n <1> Instruction code: 1 0 1 0 R4 0 R3 R2 R1 R0 <2> Cycle count: 1 <3> Function: (A) ← (A) ∨ (Rmn) m = 0, 1 n = 0 to F CY ← A 3 • Rmn3 The accumulator contents and the register Rmn contents are ORed and the results are entered in the accumulator. Data Sheet U14474EJ1V0DS00 37 µPD62A XRL A, @R0H XRL A, @R0L <1> Instruction code: 1 0 1 0 0/1 1 0 0 0 0 <2> Cycle count: 1 <3> Function: (A) ← (A) ∨ ((P13), (R0))7-4 (in the case of XRL A, @R0H) CY ← A 3 • ROM 7 (A) ← (A) ∨ ((P13), (R0))3-0 (in the case of XRL A, @R0L) CY ← A 3 • ROM 3 The accumulator contents and the program memory contents specified with the control register P13 and register pair R10-R00 are exclusive-ORed and the results are entered in the accumulator. If H is specified, b7, b6, b5, and b4 take effect. If L is specified, b3, b2, b1, and b0 take effect. XRL A, #data4 <1> Instruction code: 1 0 1 0 1 1 0 0 0 1 0 0 0 0 0 0 d3 d2 d1 d0 <2> Cycle count: 1 <3> Function: (A) ← (A) ∨ data4 CY ← A 3 • data43 The accumulator contents and the immediate data are exclusive-ORed and the results are entered in the accumulator. INC A <1> Instruction code: 1 0 1 0 0 1 0 0 1 1 <2> Cycle count: 1 <3> Function: (A) ← (A) + 1 If A = 0 else CY ← 1 CY ← 0 The accumulator contents are incremented (+1). RL A <1> Instruction code: 1 1 1 0 0 1 0 0 1 1 <2> Cycle count: 1 <3> Function: (A n + 1) ← (An), (A 0) ← (A 3) CY ← A 3 The accumulator contents are rotated anticlockwise bit by bit. RLZ A <1> Instruction code: 1 1 1 1 0 1 0 0 1 1 <2> Cycle count: 1 <3> Function: If A = 0 else reset (A n + 1) ← (An), (A 0) ←(A3) CY ← A 3 The accumulator contents are rotated anticlockwise bit by bit. If A = 0H at the time of command execution, an internal reset takes effect. 38 Data Sheet U14474EJ1V0DS00 µPD62A 9.5 Input/Output Instructions IN A, P0n IN A, P1n <1> Instruction code: 1 1 1 1 P4 1 1 P2 P1 P0 <2> Cycle count: 1 <3> Function: (A) ← (Pmn) m = 0, 1 n = 0, 1, 3, 4 CY ← 0 The port Pmn data is loaded (read) onto the accumulator. OUT P0n, A OUT P1n, A <1> Instruction code: 0 0 1 0 P4 1 1 P2 P1 P0 <2> Cycle count: 1 <3> Function: (Pmn) ← (A) m = 0, 1 n = 0, 1, 3, 4 The accumulator contents are transferred to port Pmn to be latched. ANL A, P0n ANL A, P1n <1> Instruction code: 1 1 0 1 P4 1 1 P2 P1 P0 <2> Cycle count: 1 <3> Function: (A) ← (A) (Pmn) m = 0, 1 n = 0, 1, 3, 4 ∨ CY ← A 3 • Pmn The accumulator contents and the port Pmn contents are ANDed and the results are entered in the accumulator. ORL A, P0n ORL A, P1n <1> Instruction code: 1 1 1 0 P4 1 1 P2 P1 P0 <2> Cycle count: 1 <3> Function: (A) ← (A) ∨ (Pmn) m = 0, 1 n = 0, 1, 3, 4 CY ← 0 The accumulator contents and the port Pmn contents are ORed and the results are entered in the accumulator. XRL A, P0n XRL A, P1n <1> Instruction code: 1 0 1 0 P4 1 1 P2 P1 P0 <2> Cycle count: 1 <3> Function: (A) ← (A) ∨ (Pmn) m = 0, 1 n = 0, 1, 3, 4 CY ← A 3 • Pmn The accumulator contents and the port Pmn contents are exclusive-ORed and the results are entered in the accumulator. Data Sheet U14474EJ1V0DS00 39 µPD62A OUT Pn, #data8 <1> Instruction code: 0 0 1 1 0 1 1 P2 P1 P0 : 0 d7 d6 d5 d4 0 d3 d2 d1 d0 <2> Cycle count: 1 <3> Function: (Pn) ← data8 n = 0, 1, 3, 4 The immediate data is transferred to port Pn. In this case, port Pn refers to P1n-P 0n operating in pairs. 9.6 Data Transfer Instruction MOV A, R0n MOV A, R1n <1> Instruction code: 1 1 1 1 R4 0 R3 R2 R1 R0 <2> Cycle count: 1 <3> Function: (A) ← (Rmn) m = 0, 1 n = 0 to F CY ← 0 The register Rmn contents are transferred to the accumulator. MOV A, @R0H <1> Instruction code: 1 1 1 1 0 1 0 0 0 0 <2> Cycle count: 1 <3> Function: (A) ← ((P13), (R0)) 7-4 CY ← 0 The high-order 4 bits (b7 b 6 b5 b4) of the program memory specified with control register P13 and register pair R10-R00 are transferred to the accumulator. b9 is ignored. MOV A, @R0L <1> Instruction code: 1 1 1 1 1 1 0 0 0 0 <2> Cycle count: 1 <3> Function: (A) ← ((P13), (R0)) 3-0 CY ← 0 The low-order 4 bits (b3 b 2 b1 b0) of the program memory specified with control register P13 and register pair R10-R00 are transferred to the accumulator. b8 is ignored. • Program memory (ROM) contents @R0 H b9 b7 b6 b5 @R0 L b4 b8 b3 b2 b1 b0 MOV A, #data4 <1> Instruction code: : <2> Cycle count: <3> Function: 1 1 1 1 1 1 0 0 0 1 0 0 0 0 0 0 d3 d2 d1 d0 1 (A) ← data4 CY ← 0 The immediate data is transferred to the accumulator. 40 Data Sheet U14474EJ1V0DS00 µPD62A MOV R0n, A MOV R1n, A <1> Instruction code: 0 0 1 0 R4 0 R3 R2 R1 R0 <2> Cycle count: 1 <3> Function: (Rmn) ← (A) m = 0, 1 n = 0 to F The accumulator contents are transferred to register Rmn. MOV Rn, #data8 <1> Instruction code: : 0 0 1 1 0 0 R3 R2 R1 R0 0 d7 d6 d5 d4 0 d3 d2 d1 d0 <2> Cycle count: 1 <3> Function: (R1n-R0n) ← data8 n = 0 to F The immediate data is transferred to the register. Using this instruction, registers operate as register pairs. The pair combinations are as follows: R0 : R10 - R00 R1 : R11 - R01 : RE : R 1E - R0E RF : R1F - R0F Lower column Higher column MOV Rn, @R0 <1> Instruction code: 0 0 1 1 1 0 R3 R2 R1 R0 <2> Cycle count: 1 <3> Function: (R1n-R0n) ← ((P13), R0)) n = 1 to F The program memory contents specified with control register P13 and register pair R10-R00 are transferred to register pair R1n-R0n. The program memory consists of 10 bits and has the following state after the transfer to the register. Program memory b9 b7 b6 b5 b4 b8 b3 b2 b1 b0 → b9 b7 @R0 b6 b5 R1n b4 b8 b3 b2 b1 b0 R0n The high-order 2 bits of the program memory address is specified with the control register (P13). Data Sheet U14474EJ1V0DS00 41 µPD62A 9.7 Branch Instructions The program memory consists of pages in steps of 1K (000H to 3FFH). However, as the assembler automatically performs page optimization, it is unnecessary to designate pages. The pages allowed for each product are as follows. µPD62A (ROM: 0.5 K steps): page 0 µPD6P4B (PROM: 1 K steps) : page 0 JMP addr <1> Instruction code: page 0 0 1 0 0 0 1 0 0 0 1 ; page 1 0 1 0 0 1 1 0 0 0 1 a9 a7 a6 a5 a4 a8 a3 a2 a1 a0 <2> Cycle count: 1 <3> Function: PC ← addr The 10 bits (PC9-0) of the program counter are replaced directly by the specified address addr (a9 to a0). JC addr <1> Instruction code: page 0 0 1 1 0 0 1 0 0 0 1 ; page 1 0 1 0 1 0 1 0 0 0 1 a9 a7 a6 a5 a4 a8 a3 a2 a1 a0 <2> Cycle count: 1 <3> Function: If CY = 1 else PC ← addr PC ← PC + 2 If the carry flag CY is set (to 1), a jump is made to the address specified with addr (a9 to a0). JNC addr <1> Instruction code: page 0 0 1 1 0 1 1 0 0 0 1 ; page 1 0 1 0 1 1 1 0 0 0 1 a9 a7 a6 a5 a4 a8 a3 a2 a1a0 <2> Cycle count: 1 <3> Function: If CY = 0 PC ← addr PC ← PC + 2 else If the carry flag CY is cleared (to 0), a jump is made to the address specified with addr (a9 to a 0). JF addr <1> Instruction code: page 0 0 1 1 1 0 1 0 0 0 1 ; page 1 1 0 0 0 0 1 0 0 0 1 a9 a7 a6 a5 a4 a8 a3 a2 a1 a0 <2> Cycle count: 1 <3> Function: If F = 1 PC ← addr PC ← PC + 2 else If the status flag F is set (to 1), a jump is made to the address specified with addr (a9 to a0). JNF addr <1> Instruction code: page 0 0 1 1 1 1 1 0 0 0 1 ; page 1 1 0 0 0 1 1 0 0 0 1 a9 a7 a6 a5 a4 a8 a3 a2 a1 a0 <2> Cycle count: 1 <3> Function: If F = 0 else PC ← addr PC ← PC + 2 If the status flag F is cleared (to 0), a jump is made to the address specified with addr (a9 to a 0). 42 Data Sheet U14474EJ1V0DS00 µPD62A 9.8 Subroutine Instructions The program memory consists of pages in steps of 1K (000H to 3FFH). However, as the assembler automatically performs page optimization, it is unnecessary to designate pages. The pages allowed for each product are as follows. µPD62A (ROM: 0.5 K steps): page 0 µPD6P4B (PROM: 1 K steps): page 0 CALL addr <1> Instruction code: 0 0 1 1 0 1 0 0 1 0 page 0 0 1 0 0 0 1 0 0 0 1 ; page 1 0 1 0 0 1 1 0 0 0 1 a9 a7 a6 a5 a4 a8 a3 a2 a1 a0 <2> Cycle count: 2 <3> Function: SP ← SP + 1 ASR ← PC PC ← addr The stack pointer value is incremented (+1) and the program counter value is saved in the address stack register. Then, the address specified with the operand addr (a9 to a0) is entered in the program counter. If a carry is generated when the stack pointer value is incremented (+1), an internal reset takes effect. RET <1> Instruction code: 0 1 0 0 0 1 0 0 1 0 <2> Cycle count: 1 <3> Function: PC ← ASR SP ← SP – 1 The value saved in the address stack register is restored to the program counter. Then, the stack pointer is decremented (–1) . If a borrow is generated when the stack pointer value is decremented (–1), an internal reset takes effect. Data Sheet U14474EJ1V0DS00 43 µPD62A 9.9 Timer Operation Instructions MOV A, T0 MOV A, T1 <1> Instruction code: 1 1 1 1 0/1 1 1 1 1 1 <2> Cycle count: 1 <3> Function: (A) ← (Tn) n = 0, 1 CY ← 0 The timer Tn contents are transferred to the accumulator. T1 corresponds to (t9, t8, t7, t6); T0 corresponds to (t5, t4, t3, t2). T t9 t8 t7 t6 T1 t5 t4 t3 t2 t1 t0 T0 ↓ MOV T, #data10 Can be set with MOV T, @R0 MOV T0, A MOV T1, A <1> Instruction code: 0 0 1 0 0/1 1 1 1 1 1 <2> Cycle count: 1 <3> Function: (Tn) ← (A) n = 0, 1 The accumulator contents are transferred to the timer register Tn. T1 corresponds to (t9, t8, t7, t6); T0 corresponds to (t5, t4, t3, t2). After executing this instruction, if data is transferred to T1, t1 becomes 0; if data is transferred to T0, t0 becomes 0. MOV T, #data10 <1> Instruction code: 0 0 1 1 0 1 1 1 1 1 <2> Cycle count: 1 <3> Function: (T) ← data10 t1 t9 t8 t7 t6 t0 t5 t4 t3 t2 The immediate data is transferred to the timer register T (t9-t0). Remark The timer time is set with (set value + 1) × 64/f X or 128/fX. 44 Data Sheet U14474EJ1V0DS00 µPD62A MOV T, @R0 <1> Instruction code: 0 0 1 1 1 1 1 1 1 1 <2> Cycle count: 1 <3> Function: (T) ← ((P13), (R0)) The program memory contents are transferred to the timer register T (t9 to t0) specified with the control register P13 and the register pair R10-R00. The program memory, which consists of 10 bits, is placed in the following state after being transferred to the register. Timer Program memory t9 t1 t8 t7 t6 t0 T t5 t4 t3 → t2 @R0 t9 t8 t7 T1 t6 t5 t4 t3 t2 t1 t0 T0 The high-order 2 bits of the program memory address are specified with the control register (P13). Caution When setting a timer value in the program memory, be sure to use the DT directive. 9.10 Others HALT #data4 <1> Instruction code: : 0 0 0 1 0 1 0 0 0 1 0 0 0 0 0 0 d3 d2 d1 d0 <2> Cycle count: 1 <3> Function: Standby mode Places the CPU in standby mode. The condition for having the standby mode (HALT/STOP mode) canceled is specified with the immediate data. STTS R0n <1> Instruction code: 0 0 0 1 1 0 R3 R2 R1 R0 <2> Cycle count: 1 <3> Function: If statuses match else F ← 0 F ← 1 n = 0 to F The S0, S1, KI/O , KI, and TIMER statuses are compared with the register R0n contents. If at least one of the statuses coincides with the bits that have been set, the status flag F is set (to 1). If none of them coincide, the status flag F is cleared (to 0). Data Sheet U14474EJ1V0DS00 45 µPD62A STTS #data4 <1> Instruction code: 0 0 0 1 1 1 0 0 0 1 : 0 0 0 0 0 0 d3 d2 d1 d0 <2> Cycle count: 1 <3> Function: if statuses match else F ← 1 F ← 0 The S0, S1, KI/O, KI, and TIMER statuses are compared with the immediate data contents. If at least one of the statuses coincides with the bits that have been set, the status flag F is set (to 1). If none of them coincide, the status flag F is cleared (to 0). SCAF (Set Carry If ACC = F H) <1> Instruction code: 1 1 0 1 0 1 0 0 1 1 <2> Cycle count: 1 <3> Function: if CY ← 1 A = 0FH else CY ← 0 The carry flag CY is set (to 1) if the accumulator contents are FH. The accumulator values after executing the SCAF instruction are as follows: Accumulator Value Before execution Carry Flag After execution ×××0 0000 0 (clear) ××01 0001 0 (clear) ×011 0011 0 (clear) 0111 0111 0 (clear) 1111 1111 1 (set) Remark ×: don’t care NOP <1> Instruction code: 0 0 0 0 0 0 0 0 0 0 <2> Cycle count: 1 <3> Function: PC ← PC + 1 No operation 46 Data Sheet U14474EJ1V0DS00 µPD62A 10. ASSEMBLER RESERVED WORDS 10.1 Mask Option Directives When creating the µPD62A program, it is necessary to use a mask option directive in the assembler’s source program to specify a mask option. 10.1.1 OPTION and ENDOP directives The assembler directives from the OPTION directive to the ENDOP directive are called the mask option definition block. The format of the mask option definition block is as follows: Format Symbol field Mnemonic field [Label:] OPTION Operand field Comment field [; Comment] : : ENDOP 10.1.2 Mask option definition directive The assembler directives that can be used in the mask option definition block are listed in Table 10-1. An example of the mask option definition is shown below. Example Symbol field Mnemonic field Operand field Comment field OPTION USEPOC ; POC circuit incorporated ENDOP Table 10-1. List of Mask Option Definition Directives Name POC PRO File Mask Option Definition Directive USEPOC (With POC circuit) Address Value Data Value 2044H 01 NOUSEPOC (Without POC circuit) Data Sheet U14474EJ1V0DS00 00 47 µPD62A 11. ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings (TA = +25˚C) Parameter Power supply voltage Symbol Input voltage VI Output voltage VO Output current, high Conditions Rating Unit –0.3 to +3.8 V –0.3 to VDD +0.3 V –0.3 to VDD +0.3 V VDD IOHNote KI/O, K I, S0, S1, RESET REM LED Peak value –30 mA rms –20 mA Peak value –7.5 mA –5 mA rms One KI/O pin Peak value Total of LED and KI/O pins Output current, low IOL Note REM –13.5 mA rms –9 mA Peak value –18 mA rms –12 mA Peak value 7.5 mA 5 mA rms LED Peak value rms 7.5 mA 5 mA Operating ambient temperature TA –40 to +85 ˚C Storage temperature Tstg –65 to +150 ˚C Note The rms value should be calculated as follows: [rms value] = [Peak value] × √ Duty. Caution Product quality may suffer if the absolute rating is exceeded even momentarily for any parameter. That is, the absolute maxumum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure the absolute maximum ratings are not exceeded. Recommended Power Supply Voltage Range (TA = –40 to +85˚C) Parameter Power supply voltage 48 Symbol VDD Conditions fX = 2.4 to 8 MHz Data Sheet U14474EJ1V0DS00 MIN. TYP. MAX. Unit 2.0 3.0 3.6 V µPD62A DC Characteristics (TA = –40 to +85˚C, VDD = 2.0 to 3.6 V) Parameter Input voltage, high Input voltage, low Input leakage current, Symbol MAX. Unit 0.8 VDD VDD V KI/O 0.7 VDD VDD V K I , S 0 , S1 0.65 VDD VDD V RESET VIH2 VIH3 MIN. TYP. VIL1 RESET 0 0.2 VDD V VIL2 KI/O 0 0.3 VDD V VIL3 K I , S 0 , S1 0 0.15 VDD V ILIH1 KI VI = VDD, pull-down resistor not incorporated 3 µA ILIH2 S 0, S 1 VI = VDD, pull-down resistor not incorporated 3 µA ILIL1 KI VI = 0 V –3 µA high Input leakage current, Conditions VIH1 ILIL2 KI/O VI = 0 V –3 µA ILIL3 S 0, S 1 VI = 0 V –3 µA Output voltage, high VOH1 REM, LED, KI/O IOH = –0.3 mA Output voltage, low VOL1 REM, LED IOL = 0.3 mA 0.3 V VOL2 KI/O IOL = 15 µA IOH1 REM VDD = 3.0 V, VOH = 1.0 V –5 low Output current, high 0.8 VDD V 0.4 V –12 mA IOH2 KI/O VDD = 3.0 V, VOH = 2.2 V –2.5 –7 mA Output current, low IOL1 KI/O VDD = 3.0 V, VOL = 0.4 V 30 70 µA VDD = 3.0 V, VOL = 2.2 V 100 390 On-chip pull-up resistor R1 RESET 25 50 On-chip pull-down R2 RESET 2.5 resistor R3 K I , S 0 , S1 75 250 µA 100 kΩ 5 15 kΩ 150 300 kΩ 500 kΩ 3.6 V R4 KI/O 130 Data retention power supply voltage VDDDR In STOP mode 0.9 Supply currentNote IDD1 Operating fX = 8.0 MHz, VDD = 3 V ± 10% 0.8 1.6 mA mode fX = 4.0 MHz, VDD = 3 V ± 10% 0.7 1.4 mA IDD2 IDD3 HALT mode STOP mode fX = 8.0 MHz, VDD = 3 V ± 10% 0.75 1.5 mA fX = 4.0 MHz, VDD = 3 V ± 10% 0.65 1.3 mA VDD = 3 V ± 10%, When POC circuit incorporated by mask option 1.9 9.0 µA VDD = 3 V ± 10%, TA = 25˚C, When POC circuit incorporated by mask option 1.9 5.0 µA Note The current flowing to the on-chip pull-up resistors is not included. Data Sheet U14474EJ1V0DS00 49 µPD62A AC Characteristics (TA = –40 to +85˚C, VDD = 2.0 to 3.6 V) Parameter Symbol Test Conditions Instruction execution time tCY KI, S0, S1 high-level width RESET low-level width MIN. TYP. 7.9 MAX. Unit 27 µs 10 µs When releasing In HALT mode 10 µs standby mode In STOP mode Note µs 10 µs tH tRSL Note 10 + 52/fX + oscillation growth time Remark tCY = 64/fX (fX: System clock oscillation frequency) POC Circuit (mask optionNote 1) (TA = –40 to +85˚C) Parameter POC-detected voltageNote 2 Symbol Test Conditions MIN. VPOC TYP. MAX. Unit 1.85 2.0 V Notes 1. Operates effectively under the conditions of fX = 2.4 to 8 MHz. 2. Refers to the voltage at which the POC circuit cancels an internal reset. If VPOC < VDD, the internal reset is released. From the time of VPOC ≥ VDD until the internal reset takes effect, a delay of up to 1 ms occurs. When the period of VPOC ≥ VDD lasts less than 1 ms, the internal reset may not take effect. System Clock Oscillator Characteristics (TA = –40 to +85˚C, VDD = 2.0 to 3.6 V) Parameter Oscillation frequency Symbol Conditions fX (ceramic resonator) 50 Data Sheet U14474EJ1V0DS00 MIN. TYP. MAX. Unit 2.4 3.64 8.0 MHz µPD62A Recommended Ceramic Resonator (TA = –40 to +85°C) Manufacturer TDK Corp. Murata Mfg. Co., Ltd Part Number Frequency Recommended Constant (MHz) C1 [pF] C2 [pF] FCR3.52MC5 3.52 FCR3.58MC5 3.58 FCR3.64MC5 3.64 FCR3.84MC5 3.84 FCR4.0MC5 4.0 FCR6.0MC5 6.0 FCR8.0MC5 8.0 CSA2.50MG040 2.5 Unnecessary (C-containing type) 100 CST2.50MG040 CSA3.52MG 3.52 3.58 3.64 30 30 30 Unnecessary (C-containing type) CSTS0364MG03 3.84 30 30 Unnecessary (C-containing type) CST3.84MGW CST0384MG03 4.0 30 30 Unnecessary (C-containing type) CST4.00MGW CSTS0400MG03 6.0 30 30 Unnecessary (C-containing type) CST6.00MGW CSTS0600MG03 CSA8.00MTZ 30 30 CST3.64MGW CSA6.00MG 3.6 Unnecessary (C-containing type) CST0358MG03 CSA4.00MG 2.0 Remark Unnecessary (C-containing type) CST3.58MGW CSA3.84MG MAX. 100 30 CSTS0352MG03 CSA3.64MG MIN. Unnecessary (C-containing type) CST3.52MGW CSA3.58MG Power Supply Voltage [V] 8.0 30 CST8.00MTW 30 Unnecessary (C-containing type) CSTS0800MG03 An external circuit example XIN C1 XOUT C2 Data Sheet U14474EJ1V0DS00 51 µPD62A 12. CHARACTERISTICS CURVES (REFERENCE VALUES) IDD vs VDD (fx = 8 MHz) (TA = 25°C) 1 1 0.9 0.9 Power supply current IDD [mA] Power supply current IDD [mA] IDD vs VDD (fx = 4 MHz) (TA = 25°C) 0.8 0.7 0.6 Operating mode 0.5 HALT mode 0.4 0.3 0.2 0.6 0.5 2 2.5 3 3.6 0.3 0.2 0 1.5 4 − 20 High-level output current IOH [mA] 25 Low-level output current IOL [mA] 2 2.5 3 3.6 4 Power supply voltage VDD [V] IOL vs VOL (REM, LED) (TA = 25°C, VDD = 3.0 V) 20 15 10 5 IOH vs VOH (REM, LED, KI/O) (TA = 25°C, VDD = 3.0 V) − 18 − 16 − 14 − 12 − 10 −8 −6 −4 −2 0 1 2 3 Low-level output voltage VOL [V] 500 450 400 350 300 250 200 150 100 50 0 1 2 Low-level output voltage VOL [V] 0 VDD VDD − 1 VDD − 2 High-level output voltage VOH [V] IOL vs VOL (KI/O) (TA = 25°C, VDD = 3.0 V) Low-level output current IOL [µ A] HALT mode 0.4 Power supply voltage VDD [V] 52 Operating mode 0.7 0.1 0.1 0 1.5 0.8 3 Data Sheet U14474EJ1V0DS00 VDD − 3 µPD62A 13. APPLICATION CIRCUIT EXAMPLE Example of Application to System • Remote-control transmitter (40 keys; mode selection switch accommodated) + + KI/O6 KI/O5 KI/O7 KI/O4 S0 KI/O3 S1/LED KI/O2 REM KI/O1 VDD KI/O0 XOUT KI3 XIN KI2 GND KI1 RESET KI0 Mode selection switch Key matrix 8 × 5 = 40 keys • Remote-control transmitter (48 keys accommodated) + + KI/O6 KI/O5 KI/O7 KI/O4 S0 KI/O3 S1/LED KI/O2 REM KI/O1 VDD KI/O0 XOUT KI3 XIN KI2 GND KI1 RESET KI0 Key matrix 8 × 6 = 48 keys Remark When the POC circuit of the mask option is used effectively, it is not necessary to connect the capacitor enclosed in the broken lines. Data Sheet U14474EJ1V0DS00 53 µPD62A 14. PACKAGE DRAWINGS 20 PIN PLASTIC SSOP (300 mil) 20 11 detail of lead end F G T P L U E 1 10 A H I J S N S K C D M M B NOTE ITEM Each lead centerline is located within 0.12 mm of its true position (T.P.) at maximum material condition. MILLIMETERS A 6.65±0.15 B 0.475 MAX. C 0.65 (T.P.) D 0.24 +0.08 −0.07 E 0.1±0.05 F 1.3±0.1 G 1.2 H 8.1±0.2 I J 6.1±0.2 1.0±0.2 K L 0.17±0.03 0.5 M 0.13 N 0.10 P 3° +5° −3° T U 0.25 0.6±0.15 S20MC-65-5A4-1 Remark The dimensions and materials of the ES model are the same as those of the mass production model. 54 Data Sheet U14474EJ1V0DS00 µPD62A 15. RECOMMENDED SOLDERING CONDITIONS The µPD62A should be soldered and mounted under the following recommended conditions. For the details of the recommended soldering conditions, refer to the document Semiconductor Device Mounting Technology Manual (C10535E). For soldering methods and conditions other than those recommended below, contact your NEC sales representatives. Table 15-1. Surface Mounting Type Soldering Conditions µ PD62AMC-×××-5A4: 20-pin plastic SSOP (300 mils) Soldering Method Soldering Conditions Recommended Condition Symbol Infrared reflow Package peak temperature: 235°C; Time: 30 seconds max. (at 210°C or higher); Count: three times or less IR35-00-3 VPS Package peak temperature: 215°C; Time: 40 seconds. max. (at 200°C or higher); Count: Three times or less VP15-00-3 Wave soldering Solder bath temperature: 260°C max.; Time: 10 seconds max.; Count: once; Preheating temperature: 120°C max. (package surface temperature) WS60-00-1 Partial heating Pin temperature: 300°C or less; Time: 3 seconds max. (per pin row) — Caution Do not use different soldering methods together (except for partial heating). Data Sheet U14474EJ1V0DS00 55 µPD62A APPENDIX A. DEVELOPMENT TOOLS An emulator is provided for emulating the µPD62A. Hardware • Emulator (EB-6133Note) Used to emulate the µPD62A. Note This is a product made by Naito Densei Machida Mfg. Co., Ltd. For details, contact Naito Densei Machida Mfg. Co., Ltd. (+81-44-822-3813). Software • Assembler (AS6133) • This is a development tool for remote control transmitter software. Part Number List of AS6133 Host Machine OS Supply Medium Part Number MS-DOS (Ver. 5.0 to Ver. 6.2) 3.5-inch 2HD µS5A13AS6133 IBM PC/AT and compatibles MS-DOS (Ver. 6.0 to Ver. 6.22) 3.5-inch 2HC µS7B13AS6133 PC-9800 series (CPU: 80386 or more) PC DOS (Ver. 6.1 to Ver. 6.3) Caution Although Ver.5.0 or later has a task swap function, this function cannot be used with this software. 56 Data Sheet U14474EJ1V0DS00 µPD62A APPENDIX B. FUNCTIONAL COMPARISON BETWEEN µPD62A AND OTHER SUBSERIES Item µPD62A 512 × 10 bits ROM capacity µPD63A 768 × 10 bits µPD64 µPD6134 1002 × 10 bits 1002 × 10 bits µPD6600A 512 × 10 bits RAM capacity 32 × 4 bits 32 × 5 bits Stack 1 level (also used as RF of RAM) 3 levels (also used for RAM) Key matrix 8 × 6 = 48 keys 8 × 4 = 32 keys S0 (S-IN) input Read by P01 register (standby release function available) Read by left shift instruction S1/LED (S-OUT) I/O (standby release function available) Output Clock frequency Ceramic oscillation Ceramic oscillation • fX = 2.4 to 8 MHz Timer Carrier • fX = 2.4 to 8 MHz • fX = 2.4 to 4 MHz (with POC circuit) Clock fX/64, fX/128 Count start Writing count value Frequency • fX/8, fX/64, fX/96 (timer clock: fX/64) • fX/16, fX/128, fX/192 (timer clock: fX/128) • No carrier Output start Synchronized with timer • fX = 300 kHz to 1 MHz • fX = 400 to 500 kHz • fX = 300 to 500 kHz (with POC circuit) fX/8, fX/16 fX/8 Writing count value and P1 register value • fX, fX/8, fX/12 (timer clock: fX/8) • fX/2, fX/16, fX/24 (timer clock: fX/16) • No carrier • fX/8, fX/12 Asynchronized with timer Instruction execution time 8 µs (fX = 8 MHz) 8 µs (fX = 1 MHz) 16 µs (fX = 500 kHz) Relative branch instruction None Provided Left shift instruction None Provided “MOV Rn, @RO” instruction n = 1 to F n = 0 to F Standby mode (HALT instruction) HALT mode for timer only. STOP mode for only releasing KI (KI/O high-level output or KI/O0 high-level output) HALT/STOP mode set by P1 register value Relationship between HALT instruction execution and status flag (F) HALT instruction not executed when F = 1 HALT instruction executed regardless of status of F Reset function by charging/ discharging capacitor None Provided POC circuit Mask option Low level output to RESET pin on detection Provided (low-voltage detection circuit) Low level output to S-OUT pin on detection Mask option POC circuit only (set by software in circuits other than POC circuit) • Pull-down resistor • Variable duty • Runaway detection Supply voltage VDD = 2.0 to 3.6 V VDD = 1.8 to 3.6 V VDD = 2.2 to 3.6 V Operating temperature • TA = –40 to +85°C TA = –20 to +70°C Package • 20-pin plastic • 20-pin plastic • 20-pin plastic SOP SSOP SOP • 20-pin plastic SSOP One-time PROM model µPD6P4B • TA = –40 to +85°C • TA = –20 to +70°C (with POC circuit) µPD61P34B Data Sheet U14474EJ1V0DS00 • 20-pin plastic SOP • 20-pin plastic shrink DIP µPD61P24 57 µPD62A APPENDIX C. EXAMPLE OF REMOTE-CONTROL TRANSMISSION FORMAT (NEC transmission format in command one-shot transmission mode) Caution When using the NEC transmission format, apply for a custom code at NEC. (1) REM output waveform (From <2>, the output is made only when the key is continually pressed.) REM output 58.5 to 76.5 ms <1> 108 ms <2> 108 ms Remark If the key is repeatedly pressed, the power consumption of the infrared light-emitting diode (LED) can be reduced by sending the reader code and the stop bit from the second time. (2) Enlarged waveform of <1> <3> REM output 9 ms 4.5 ms Custom code 8 bits 13.5 ms Leader code Custom code' 8 bits Data code 8 bits 18 to 36 ms Data code 8 bits Stop bit 1 bit 27 ms 58.5 to 76.5 ms (3) Enlarged waveform of <3> REM output 4.5 ms 9 ms 0.56 ms 1.125 ms 2.25 ms 0 1 13.5 ms (4) Enlarged waveform of <2> REM output 2.25 ms 9 ms 11.25 ms Leader code 58 Data Sheet U14474EJ1V0DS00 0.56 ms Stop bit 1 0 0 µPD62A (5) Carrier waveform (enlarged waveform of each code’s high period) REM output 8.77 µ s 26.3 µ s 9 ms or 0.56 ms Carrier frequency : 38 kHz (6) Bit array of each code C0 C1 C2 C3 C4 C5 C6 C7 C0' C1' C2' C3' C4' C5' C6' C7' D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 = = = = = = = = C0 C1 C2 C3 C4 C5 C6 C7 or or or or or or or or Co C 1 C2 C 3 C4 C 5 C6 C 7 Leader code Custom code Custom code' Data code Data code Caution To prevent malfunction with other systems when receiving data in the NEC transmission format, not only fully decode (make sure to check Data code as well) the total 32 bits of the 16-bit custom codes (Custom code, Custom code’) and the 16-bit data codes (Data code, Data code) but also check to make sure that no signals exist. Data Sheet U14474EJ1V0DS00 59 µPD62A NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to V DD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function. 60 Data Sheet U14474EJ1V0DS00 µPD62A Regional Information Some information contained in this document may vary from country to country. Before using any NEC product in your application, please contact the NEC office in your country to obtain a list of authorized representatives and distributors. They will verify: • Device availability • Ordering information • Product release schedule • Availability of related technical literature • Development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, AC supply voltages, and so forth) • Network requirements In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. NEC Electronics Inc. (U.S.) NEC Electronics (Germany) GmbH NEC Electronics Hong Kong Ltd. Santa Clara, California Tel: 408-588-6000 800-366-9782 Fax: 408-588-6130 800-729-9288 Benelux Office Eindhoven, The Netherlands Tel: 040-2445845 Fax: 040-2444580 Hong Kong Tel: 2886-9318 Fax: 2886-9022/9044 NEC Electronics Hong Kong Ltd. Velizy-Villacoublay, France Tel: 01-30-67 58 00 Fax: 01-30-67 58 99 Seoul Branch Seoul, Korea Tel: 02-528-0303 Fax: 02-528-4411 NEC Electronics (France) S.A. NEC Electronics Singapore Pte. Ltd. Milton Keynes, UK Tel: 01908-691-133 Fax: 01908-670-290 Spain Office Madrid, Spain Tel: 91-504-2787 Fax: 91-504-2860 United Square, Singapore 1130 Tel: 65-253-8311 Fax: 65-250-3583 NEC Electronics Italiana s.r.l. NEC Electronics (Germany) GmbH Milano, Italy Tel: 02-66 75 41 Fax: 02-66 75 42 99 Scandinavia Office Taeby, Sweden Tel: 08-63 80 820 Fax: 08-63 80 388 NEC Electronics (France) S.A. NEC Electronics (Germany) GmbH Duesseldorf, Germany Tel: 0211-65 03 02 Fax: 0211-65 03 490 NEC Electronics (UK) Ltd. NEC Electronics Taiwan Ltd. Taipei, Taiwan Tel: 02-2719-2377 Fax: 02-2719-5951 NEC do Brasil S.A. Electron Devices Division Rodovia Presidente Dutra, Km 214 07210-902-Guarulhos-SP Brasil Tel: 55-11-6465-6810 Fax: 55-11-6465-6829 J99.1 Data Sheet U14474EJ1V0DS00 61 µPD62A MS-DOS is either a registered trademark or a trademark of Microsoft Corporation in the United States and/or other countries. PC/AT and PC DOS are trademarks of International Business Machines Corporation. The export of this product from Japan is regulated by the Japanese government. To export this product may be prohibited without governmental license, the need for which must be judged by the customer. The export or re-export of this product from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales representative. • The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. • No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. • NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. • Descriptions of circuits, software, and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software, and information in the design of the customer's equipment shall be done under the full responsibility of the customer. NEC Corporation assumes no responsibility for any losses incurred by the customer or third parties arising from the use of these circuits, software, and information. • While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. • NEC devices are classified into the following three quality grades: "Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a customer designated “quality assurance program“ for a specific application. The recommended applications of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device before using it in a particular application. Standard: Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) Specific: Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact an NEC sales representative in advance. M7 98.8