APPLICATION NOTE 7542 Group Clock Asynchronous Serial I/O (UART) 1.0 Abstract The following article introduces and shows an application example of clock asynchronous (UART) of serial I/O1. 2.0 Introduction The explanation of this issue is applied to the following condition: Applicable MCU: 7542 Group REJ05B0023-0100Z May 2003 Page 1 of 8 7542 Group Clock Asynchronous Serial I/O (UART) 3.0 Contents For clock asynchronous serial I/O (UART), the baud rate and transfer formats used by a transmitter and receiver must be identical. In the 7542 Group, eight serial data transfer formats can be selected. Also, as for the serial I/O2, since it has an equivalent function to serial I/O1, the application example of the following serial I/O1 is applicable for serial I/O2. 3.1 Data Transfer Rate The transfer bit rate is calculated by the following formula; ● When the internal clock is selected (when baud rate generator is used) Transfer bit rate [bps] = Division ratio *1 f(XIN) ✕ (BRG1 setting value *2 + 1) ✕ 16 Division ratio* 1 : “1” or “4” is selected (set by bit 0 of serial I/O1 control register) BRG1 setting value* 2 : 0 to 255 (00 16 to FF 16) is set ● When the external clock is selected Transfer bit rate [bps] = Clock input to SCLK1 pin/16 Table 1 shows the setting example of baud rate generator and transfer bit rate values. Table 1 Setting example of baud rate generator1 (BRG1) and transfer bit rate values BRG count source BRG1 set value f(X IN ) / 4 255 (FF 16) f(X IN ) / 4 127 (7F16) 600 f(X IN ) / 4 f(X IN ) / 4 63 (3F 16) 31 (1F 16) 1200 1953.125 f(X IN ) / 4 15 (0F 16) 2400 4800 3906.25 7812.5 f(X IN ) / 4 7 (07 16) 9600 15625 f(X IN ) / 4 3 (03 16) 19200 31250 f(X IN ) / 4 1 (01 16) 38400 62500 f(X IN) f(X IN) 3 (03 16) 1 (01 16) 76800 125000 f(X IN) 0 (00 16) 153600 307200 250000 500000 REJ05B0023-0100Z Transfer bit rate (bps) At f(X IN) = 4.9152 MHz At f(X IN) = 8 MHz 300 May 2003 488.28125 976.5625 Page 2 of 8 7542 Group Clock Asynchronous Serial I/O (UART) 3.2 UART Setting Method Figure 1 and Figure 2 show the setting method for UART of serial I/O1. Process 1: Stop and initialize serial I/O. b7 b0 0 0 Serial I/O1 control register (SIO1CON) [Address 1A16] Transmit operation stop and initialization Receive operation stop and initialization Process 2: Disable serial I/O1 transmit/receive interrupt. b7 b0 0 0 Interrupt control register 1 (ICON1) [Address 3E16] Serial I/O1 receive interrupt disabled Serial I/O1 transmit interrupt disabled Process 3: Set serial I/O1 control register. b7 1 0 b0 Serial I/O1 control register (SIO1CON) [Address 1A16] BRG count source selected (set in internal clock selected) 0: f(XIN) 1: f(XIN)/4 Serial I/O1 synchronous clock selected (Note 1) 0: BRG output/16 1: External clock input/16 Transmit interrupt source selected 0: When transmit buffer has emptied 1: When transmit shift operation is completed Transmit enable selected 0: Transmit disabled (at half-duplex communication receive) 1: Transmit enabled (at full-duplex communication) (Note 2) Receive enable selected 0: Receive disabled (at half-duplex communication transmit) 1: Receive enabled (at full-duplex communication) (Note 2) Clock asynchronous serial I/O Serial I/O1 enabled (P10–P12 pins operate as serial I/O1 pins)(Note 3) Note 1: Setting of serial I/O1 synchronous clock selection bit is as follows; “0”: P12 pin can be used as a normal I/O pin “1”: P12 pin is used as an input pin for an external clock. 2: When data transmission is executed at the state that an external clock input is selected as the synchronous clock, set “1” to the transmit enable bit while the SCLK1 is “H” state. 3: When clock asynchronous (UART) serial I/O is selected, P13 pin can be used as a normal I/O pin. Figure 1 Setting method for UART of serial I/O1 (1) REJ05B0023-0100Z May 2003 Page 3 of 8 7542 Group Clock Asynchronous Serial I/O (UART) Process 4: Set UART control register. b7 b0 UART1 control register (UART1CON) [Address 1B16] Select character length 0: 8 bits 1: 7 bits Select parity enable 0: Parity disabled 1: Parity enabled Select parity (valid only when parity is enabled) 0: Even parity 1: Odd parity Select stop bit length 0: 1 stop bit 1: 2 stop bits Select P11/TxD1 P-channel output disable (in output mode) 0: CMOS output 1: N-channel open-drain output Process 5: When BRG output/16 is selected as synchronous clock, set value to baud rate generator. Baud rate generator1 (BRG1) [Address 1C16] Set baud rate value Process 6: In order not to execute the no requested interrupt processing, set “0” (no requested) to the serial I/O1 transmit/receive interrupt request bit. b7 b0 0 0 Interrupt request register 1 (IREQ1) [Address 3C16] No serial I/O1 receive interrupt request issued No serial I/O1 transmit interrupt request issued Process 7: When the interrupt is used, set “1” (interrupt enabled) to the serial I/O1 transmit/ receive interrupt enable bit. b7 b0 1 1 Interrupt control register 1 (ICON1) [Address 3E16] Serial I/O1 receive interrupt enabled Serial I/O1 transmit interrupt enabled Process 8: When transmitting, start serial data transmission (Note). Transmit/Receive buffer register1 (TB1/RB1) [Address 1816] Set transmit data Note: When data transmission is executed at the state that an external clock input is selected as the synchronous clock, set the transmit data while the SCLK1 is “H” state. Figure 2 Setting method for UART of serial I/O1 (2) REJ05B0023-0100Z May 2003 Page 4 of 8 7542 Group Clock Asynchronous Serial I/O (UART) 3.3 Communication Using UART of Serial I/O (Transmit/Receive) Outline : 2-byte data is transmitted and received, using UART. Port P00 is used for communication control. Specifications : •The Serial I/O1 (UART selected ) is used. •Transfer bit rate : 9600 bps (f(X IN) = 4.9152 MHz divided by 512) •Communication control using port P0 0 (output level of port P0 0 is controlled by software) •2-byte data is transferred from the transmitter to the receiver at 10 ms intervals which the timer generates. Figure 3 shows a connection diagram, Figure 4 shows a timing chart, Figure 5 shows the control procedure of transmitter, and Figure 6 shows an example of control procedure of receiver. Receiver Transmitter P00 P00 RXD1 TxD1 7542 Group 7542 Group Figure 3 Connection diagram ..... P00 TXD1 ST D0 D1 D2 D3 D4 D5 D6 D7 SP(2) ST D0 D1 D2 D3 D4 D5 D6 D7 SP(2) ST D0 ..... 10 ms Figure 4 Timing chart REJ05B0023-0100Z May 2003 Page 5 of 8 7542 Group Clock Asynchronous Serial I/O (UART) RESET Initialization SEI CLD CLT Set serial I/O1 control register 0 1 SIO1CON(Address 1A16) 1 0 0 1 0 BRG count source: f(XIN)/4 Synchronous clock: BRG output/16 Transmit interrupt source: When transmit buffer has emptied Transmit enabled Receive disabled UART Serial I/O1 enabled Set UART1 control register 01 0 0 UART1CON(Address 1B16) Character length: 8 bits Parity disabled Stop bit length: 2 bits TXD1: CMOS output Set baud rate generator BRG1(Address 1C16) “0716” Set the communication control port P00 to the output mode. 10 ms elapsed ? (generated by timer) N Y Set “1” to the communication control port P00. Write the first-byte transmission data to the transmit/receive buffer register1 TB1/RB1(Address 1816) Transmit buffer has emptied? (checked by b0 of SIO1STS (address 1916)) N Y Write the second-byte transmission data to the transmit/receive buffer register1 TB1/RB1(Address 1816) Transmit buffer has emptied? (checked by b0 of SIO1STS (address 1916)) N Y Transmit shift has completed? (checked by b2 of SIO1STS (address 1916)) N Y Set “0” to the communication control port P00. Figure 5 Control procedure of transmitter REJ05B0023-0100Z May 2003 Page 6 of 8 7542 Group Clock Asynchronous Serial I/O (UART) RESET Initialization SEI CLD CLT Set serial I/O1 control register 10 1 0 0 1 SIO1CON(Address 1A16) BRG count source: f(XIN)/4 Synchronous clock: BRG output/16 Transmit disabled Receive enabled UART Serial I/O1 enabled Set UART1 control register 1 0 0 UART1CON(Address 1B16) Character length: 8 bits Parity disabled Stop bit length: 2 bits Set baud rate generator1 “0716” BRG1(Address1C 1C BRG(Address 1616 )) Set the communication control port P00 to the input mode. Receive buffer is full? (checked by b1 of SIO1STS (address 1916)) N Y Read the first-byte transmission data from the transmit/receive buffer register1 TB1/RB1(Address 1816) Error occurs? (checked by b6 of SIO1STS (address 1916)) Y N Receive buffer is full? (checked by b1 of SIO1STS (address 1916)) N Y Read the second-byte transmission data from the transmit/receive buffer register1 TB1/RB1(Address 1816) Error occurs? (checked by b6 of SIO1STS (address 1916)) Y N Error processing N Communication control port P00 = “0” ? Y Figure 6 Control procedure of receiver REJ05B0023-0100Z May 2003 Page 7 of 8 7542 Group Clock Asynchronous Serial I/O (UART) 4.0 Reference Renesas Technology Corporation Semiconductor Home Page http://www.renesas.com/en/740 REJ05B0023-0100Z May 2003 Page 8 of 8 Keep safety first in your circuit designs! ● Renesas Technology Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. 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