NSC CGS2536TV

CGS2536V
Commercial Quad 1 to 4 Clock Drivers
CGS2536TV
Industrial Quad 1 to 4 Clock Drivers
General Description
Features
These Clock Generation and Support clock drivers are specifically designed for driving memory arrays requiring large
fanouts while operating at high speeds.
This device meets the rise and fall time requirements of the
90 MHz and 100 MHz Pentium TM procrssors.
The CGS2536 I/O structures are CMOS. The outputs are
separated into two banks of eight. One bank consists of
divide by two outputs, the other, straight-through buffers.
Within each bank, half the outputs are inverting, the other
half non-inverting.
The CGS2536 specification guarantees part-to-part skew
variation.
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Guaranteed:
Ð 1.0 ns rise and fall times while driving 12 inches of
50X microstrip terminated with 25 pF
Ð 350 ps pin-to-pin skew (tOSLH and tOSHL)
650 ps part-to-part variation on positive or negative
transition
Operates with either 3.3V or 5.0V supply
Inputs 5V tolerant with VCC in 3.3V range
Symmetric output current drive: 24 mA IOH/IOL
Industrial temperature of b40§ C to a 85§ C
Symmetric package orientation
Large fanout for memory driving applications
Guaranteed 2 kV ESD protection
Implemented on National’s ABT family process
28-pin PLCC for optimum skew performance
Connection Diagrams
Pin Assignment for 28-Pin PLCC
TL/F/12325 – 1
CGS2536
Truth Table
Input
Output
In 0
ABCD Out (0) d 2
In 1
ABCD Out (1) d 2
In 2
ABCD Out (2)
In 3
ABCD Out (3)
PentiumTM is a trademark of Intel Corporation.
C1995 National Semiconductor Corporation
TL/F/12325
TL/F/12325 – 2
RRD-B30M105/Printed in U. S. A.
CGS2536V Commercial Quad 1 to 4 Clock Drivers
CGS2536TV Industrial Quad 1 to 4 Clock Drivers
September 1995
Absolute Maximum Ratings
Recommended Operating
Conditions
(Note)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage (VCC)
Input Voltage (VI)
Input Current
Current Applied to Output
(High/Low)
Operating Temperature
Industrial Grade
Commercial grade
Supply Voltage
VCC 4.5V to 5.5V
VCC 3.0V to 3.6V
Maximum Input Rise/Fall Time (0.8V to 2.0V)
5 ns
Free Air Operating Temperature
Commercial
0§ C to a 70§ C
b 40§ C to a 85§ C
Industrial
7.0V
7.0V
b 30 mA
Twice the Rated IOH/IOL
Note: The Absolute Maximum Ratings are those values beyond which the
safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the DC and AC Electrical
Characteristics tables are not guaranteed at the absolute maximum ratings.
The Recommended Operating Conditions will define the conditions for actual device operation.
b 40§ C to a 85§ C
0§ C to a 70§ C
b 65§ C to a 150§ C
Storage Temperature Range
Airflow
0 LFM
225 LFM
500 LFM
900 LFM
Typical iJA
62§ C/W
43§ C/W
34§ C/W
27§ C/W
DC Electrical Characteristics
Over recommended operating free air temperature range. All typical values are measured at VCC e 5V, TA e 25§ C.
Symbol
VIH
VIL
Parameter
Conditions
Input High Level Voltage
Input Low Level Voltage
VCC
(V)
Min
3.0
2.1
4.5
3.15
5.5
3.85
0.9
1.35
5.5
1.65
Input Clamp Voltage
II e b18 mA
4.5
High Level Output Voltage
IOH e b50 mA
3.0
2.9
4.5
4.4
5.5
5.4
Low Level Output Voltage
IOL e 50 mA
IOL e 24 mA
II
2.46
3.76
5.5
4.76
0.1
0.1
5.5
0.1
3.0
0.44
4.5
0.44
5.5
0.44
High Level Input Current
Low Level Input Current
VIL e 0V
IOLD
Minimum Dynamic Output Current*
VOLD e 1.65V (max)
VOLD e 0.9V (max)
5.5
75
3.0**
36
VOHD e 3.85V (min)
VOHD e 2.1V (min)
5.5
b 75
3.0**
b 25
ICC
CIN
Minimum Dynamic Output Current*
Supply Current
Input Capacitance
5.5
7
3.6
1
5.5
b5
5.5
2
5
V
V
mA
mA
mA
mA
mA
3.6
75
5.5
235
5.0
*Maximum test duration 2.0 ms, one output loaded at a time.
**At VCC e 3.3V, IOLD e 55 mA min; @ VCC e 3.6V, IOLD e 64 mA min
At VCC e 3.3V, IOHD e b 58 mA min; @ VCC e 3.6V, IOHD e b 66 mA min
V
V
4.5
IIL
V
V
3.0
IIH
@
Max Input Voltage
3.0
VIH e 7V
VIH e VCC
VIH e VCC
IOHD
Input Current
b 1.2
4.5
Units
V
3.0
VOH
VOL
Max
4.5
VIK
IOH e b24 mA
Typ
5
mA
pF
AC Electrical Characteristics (Notes 1, 2, and 3)
Over recommended operating free air temperature range. All typical values are measured at VCC e 5V, TA e 25§ C.
CGS2536
Symbol
Parameter
VCC
(V)
(Note 8)
TA e a 25§ C
CL e 50 pF, RL e 500X
Min
Typ
Max
TA e b40§ C to a 85§ C
(Note 4)
CL e 50 pF, RL e 500X
Min
Typ
Units
Max
fmax
Frequency Maximum
3.0
5.0
100
125
tPLH
Low-to-High Propagation Delay
CK to On
3.3
5.0
7.25
5.0
7.25
5.0
ns
tPHL
High-to-Low Propagation Delay
CK to On
3.3
5.0
5.5
4.5
5.5
4.5
ns
tOSLH
Maximum Skew Common Edge
Output-to-Output Variation (Notes 1, 3)
3.3
5.0
150
150
350
350
300
300
350
350
ps
tOSHL
Maximum Skew Common Edge
Output-to-Output Variation (Notes 1, 3)
3.3
5.0
150
150
350
350
300
300
350
350
ps
trise,
tfall
Rise/Fall Time
(from 0.8V/2.0V to 2.0V/0.8V) (Note 5)
3.3
5.0
4.5
3.5
4.5
3.5
ns
trise,
tfall
Rise/Fall Time
(from 0.8V/2.0V to 2.0V/0.8V) (Note 6)
3.3
5.0
0.8
0.4
1.0
0.6
ns
trise,
tfall
Rise/Fall Time
(from 0.8V/2.0V to 2.0V/0.8V) (Note 7)
3.3
5.0
1.0
0.7
1.0
0.9
ns
tHigh
Pulse Width Duration High (Notes 2, 3)
3.3
5.0
4.0
4.0
4.0
4.0
tLow
Pulse Width Duration Low (Notes 2, 3)
3.3
5.0
4.0
4.0
4.0
4.0
tPVLH
Part-to-Part Variation of
Low-to-High Transitions
3.3
5.0
650
650
650
650
tPVHL
Part-to-Part Variation of
High-to-Low Transitions
3.3
5.0
650
650
650
650
MHz
ns
ps
Note 1: Output-to-Output Skew is defined as the absolute value of the difference between the actual propagation delay for any outputs within the same packaged
device. The specifications apply to any outputs switching in the same direction either LOW to HIGH (tOSLH) or HIGH to LOW (tOSHL).
Note 2: Time high is measured with outputs at 2.0V or above. Time low is measured with outputs at 0.8V or below. Input waveform characteristics for tHigh, tLow
measurement: f e 66.67 MHz, duty cycle e 50%.
Note 3: The input waveform has a rise and fall time transition time of 2.5 ns (10% to 90%).
Note 4: Industrial range ( b 40§ C to a 85§ C) limits apply to the commercial temperature range (0§ C to a 70§ C).
Note 5: These Rise and Fall times are measured with CL e 50 pF, RL e 500X (see Figure 3 ).
Note 6: These Rise and Fall times are measured with CL e 25 pF, RL e 500X (see Figure 3 ), and are guaranteed by design.
Note 7: These Rise and Fall times are measured driving 12 inches of 50X microstrip terminated with equivalent CL e 25 pF (see Figure 4 ), and are guaranteed by
design.
Note 8: Voltage Range 5.0 is 5.0V g 0.5V, 3.3 is 3.3V g 0.3V.
Note 9: For increased output drive, output pins may be connected together when the corresponding input pins are connected together.
3
Timing Information
TL/F/12325 – 3
FIGURE 1. Buffer Waveforms
TL/F/12325 – 6
FIGURE 2. Divide by 2 Waveforms
TL/F/12325 – 8
FIGURE 3. A.C. Load (Reference Notes 5, 6)
CL e Total Load Including Probes
TL/F/12325 – 9
FIGURE 4. A.C. Load (Reference Note 7)
CL e Total Load Including Probes
4
The propagation delay of the 74AC00 gates and the toggle
frequency of the 74VHC164 limit the maximum frequency of
operation. Equivalent logic elements that have faster propagation delays can be substituted for the NAND gates and
shift register. For example, a generic GAL22V10-5 could be
programmed as the NAND gates that drive the CGS2536.
Power On Requirements
DETAILED DESCRIPTION
The divide by two block of the CGS2536 is accomplished
using two negative-edge-triggered flip-flops. During poweron, the inverting flip-flop causes outputs Aout1 through
Dout1 to be High. The non-inverting flip-flop causes outputs
Aout0 through Dout0 to be Low. Two flip-flops are used to
achieve minimum skew between the non-inverting and inverting outputs.
To guarantee that the flip-flops power-up out of phase, the
IN0 and IN1 pins must be held low while power is applied to
VCC. IN0 and IN1 must remain low until VCC t 3V.
Figure 1 CIRCUIT DESCRIPTION
Assumptions:
1. VCC is applied simultaneously to the crystal oscillator,
CGS2536, 74AC00, and 74VHC164.
2. A system power-on reset is ‘‘Low’’ long enough for VCC
and the crystal oscillator to stabilize.
At power-on, assertion (low) of the system power-on reset
clears the outputs of the 74VHC164 serial to parallel converter.
As a result, nodes C and E are low ensuring power-on requirements for the CGS2536 are met. When the system
power-on reset is de-asserted, the eighth positive-goingedge received by the 74VHC164 causes node C to go high.
Node C remains high as long as power is applied. However,
node D still remains high due to the oscillator output (A)
being low. Node E stays low until the next positive-goingedge of the oscillator. Thus, a full positive half-cycle of the
oscillator is seen by the IN1 and IN0 inputs, which ensures
that both flip-flops of the divide by two toggle.
Application Hints
In a typical user environment IN0 and IN1 inputs may be
connected common. Power is applied simultaneously to the
crystal oscillator and the CGS2536. If the oscillator output
does not deliver a clean first negative-going-edge to the IN0
and IN1 inputs, only one flip-flop may toggle.
Even if the user delays application of VCC to the CGS2536,
a false trigger may occur. Simply gating the oscillator to the
IN0 and IN1 inputs will not guarantee correct operation,
since a ‘‘runt’’ pulse may propagate through the gate and
toggle only one of the flip-flops.
Figure 1 shows a circuit that delivers ‘‘runt-free’’ negativegoing-edges to the IN0 and IN1 inputs. This circuit ensures
that the first clocking pulse seen by the IN0 and IN1 inputs
consists of a full positive half-cycle of the crystal oscillator.
Figure 2 shows the waveforms from the synchronizing circuit.
TL/F/12325 – 4
TL/F/12325 – 5
5
CGS2534/35/36/37
Memory Array Driving
Also this larger fan-out helps to save board space since for
every one of these drivers, two conventional buffers were
typically being used.
Another feature associated with these clock drivers is a
350 ps pin-to-pin skew specification. The minimum skew
specification allows high speed memory system designers
to optimize the performance of their memory sub-system by
operating at higher frequencies without having concerns
about output-to-output (bank-to-bank) synchronization problem which are associated with driving high capacitive loads
(Point B).
The diagram below depicts a ‘‘2534/35/36/37’’ a memory
subsystem operating at high speed with large memory capacity. The address bus is common to both the memory and
the CPU and I/Os.
These drivers can operate beyond 125 MHz, and are also
available in 3V – 5V TTL/CMOS versions with large current
drive .
In order to minimize the total load on the address bus, quite
often memory arrays are driven by buffers while having the
inputs of the buffers tied together. Although this practice
was feasible in the conventional memory designs, in today’s
high speed, large buswidth designs which require address
fetching at higher speeds, this technique produces many
undesired results such as cross-talk and over/undershoot.
CGS2534/35/36/37 Quad 1 to 4 clock drivers were designed specifically to address these application issues on
high speed, large memory arrays systems.
These drivers are optimized to drive large loads, with 3.5 ns
propagation delays. These drivers produce less noise while
reducing the total capacitive loading on the address bus by
having only four inputs tied together (see the diagram below, point A). This helps to minimize the overshoot and undershoot by having only four outputs being switched simultaneously.
Device
VCC
I/O
Output Configuration
2534
5
TTL
2535
3 or 5
CMOS
Inverting quad 1–4
Non-inverting quad 1–4
2536
3 or 5
CMOS
Inverting, Non-inverting, d 2
2537
5
TTL
Inverting quad 1–4 with series 8X output resistors
TL/F/12325 – 7
6
Ordering Information (Contact NSC Marketing for specific date of availability)
CGS
253x
T
V
Family
Clock Generation and Support
Packaging
V e PCC
Device Type
2534
2535
2536
2537
Grade
Blank e Commercial
T e Industrial
7
CGS2536V Commercial Quad 1 to 4 Clock Drivers
CGS2536TV Industrial Quad 1 to 4 Clock Drivers
Physical Dimensions inches (millimeters)
28-Lead Molded Plastic Leaded Chip Carrier
Order Number CGS2536V or CGS2536TV
NS Package Number V28A
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