CY7C1361B CY7C1363B PRELIMINARY 256K x 36/512K x 18 Flow-through SRAM Features Functional Description • Supports 133-MHz bus operations • 256K x 36/512K x 18 common I/O • Fast clock-to-output times — 6.5 ns (for 133-MHz device) The CY7C1361B and CY7C1363B are 3.3V, 256K x 36 and 512K x 18 Synchronous Flowthrough SRAMs, respectively, designed to interface with high-speed microprocessors with minimal glue logic. Maximum access delay from the clock rise is 6.5 ns (133-MHz device). A two-bit on-chip wraparound burst counter captures the first address in a burst sequence and automatically increments the address for the rest of the burst access. — 7.5 ns (for 117-MHz device) • • • • • • • • • — 8.5 ns (for 100-MHz device) Two-bit wrap-around counter supporting either interleaved or linear burst sequences Separate processor and controller address strobes provide direct interface with the processor and external cache controller Synchronous self-timed writes Asynchronous output enable Single 3.3V power supply Supports 3.3V or 2.5V I/Os JEDEC-standard pinout Available as a 100-pin TQFP, 119-ball BGA, and 165-ball fBGA — Both 2 and 3 Chip Enable Options for TQFP[1] IEEE 1149.1 JTAG-compatible Boundary Scan — 119-ball BGA and 165-ball fBGA The CY7C1361B/CY7C1363B supports either the interleaved or linear burst sequences, selected by the MODE input pin. A HIGH selects an interleaved burst sequence, while a LOW selects a linear burst sequence. Burst accesses can be initiated by asserting either the Processor Address Strobe (ADSP) or the Controller Address Strobe (ADSC) at clock rise. Address advancement through the burst sequence is controlled by the ADV input. Byte write operations are qualified with the Byte Write Select (BWa,b,c,d for CY7C1361B and BWa,b for CY7C1363B) inputs. A Global Write Enable (GW) overrides all byte write inputs and writes data to all four bytes. All writes are conducted with on-chip synchronous self-timed write circuitry. Three synchronous Chip Selects (CE1, CE2, CE3[1]) and an asynchronous output enable (OE) provide for easy bank selection and output three-state control. Logic Block Diagram D REG. CE Data-In Q CLK ADV AX DQX 7C1361B A[17:0] DQa,b,c,d DQPX DQPa,b,c,d BWX BWa,b,c,d Ax GW CE1 CE2 CE 3 BWE 7C1363B BWx A[18:0] MODE ADSP DQa,b ADSC DQPa,b ZZ BWa,b OE CONTROL and WRITE LOGIC 256Kx36/ 512Kx18 MEMORY ARRAY DQx DQPx Selection Guide 7C1361B-133 7C1363B-133 Maximum Access Time Maximum Operating Current Commercial Maximum CMOS Standby Current 7C1361B-117 7C1363B-117 7C1361B-100 7C1363B-100 Unit 6.5 7.5 8.5 ns 250 220 180 mA 30 30 30 mA Note: 1. CE3 not available on 2 Chip Enable TQFP package or 119 BGA. Cypress Semiconductor Corporation Document #: 38-05302 Rev. ** • 3901 North First Street • San Jose • CA 95134 • 408-943-2600 Revised August 16, 2002 CY7C1361B CY7C1363B PRELIMINARY Pin Configurations CY7C1363B (512K x 18) 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 MODE A A A A A1 A0 NC NC VSS VDD NC A A A A A A A A NC DQPb NC DQb NC DQb VDDQ VDDQ VSSQ VSSQ NC DQb NC DQb DQb DQb DQb DQb VSSQ VSSQ VDDQ VDDQ DQb DQb DQb DQb VSS/DNU[2] VSS VDD NC NC VDD VSS ZZ DQb DQa DQb DQa VDDQ VDDQ VSSQ VSSQ DQb DQa DQb DQa DQPb DQa NC DQa VSSQ VSSQ VDDQ VDDQ NC DQa NC DQa NC DQPa NC NC VSS VDD NC A A A A A A A A CY7C1361B (256K X 36) 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 MODE A A A A A1 A0 DQPc DQc DQc VDDQ VSSQ DQc DQc DQc DQc VSSQ VDDQ DQc DQc VSS/DNU[2] VDD NC VSS DQd DQd VDDQ VSSQ DQd DQd DQd DQd VSSQ VDDQ DQd DQd DQPd 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 A A CE1 CE2 BWd BWc BWb BWa CE3 VDD VSS CLK GW BWE OE ADSC ADSP ADV A A A A CE1 CE2 NC NC BWb BWa CE3 VDD VSS CLK GW BWE OE ADSC ADSP ADV A A 100-pin TQFP (3 Chip Enable) A NC NC VDDQ VSSQ NC DQPa DQa DQa VSSQ VDDQ DQa DQa VSS NC VDD ZZ DQa DQa VDDQ VSSQ DQa DQa NC NC VSSQ VDDQ NC NC NC Note: 2. Pin 14 may be connected to VSS or left disconnected. Pin 14 should not be connected to VDD. This is consistent with industry standards. Document #: 38-05302 Rev. ** Page 2 of 29 CY7C1361B CY7C1363B PRELIMINARY Pin Configurations (continued) NC NC VSS VDD NC NC A A A A A A A MODE A A A A A1 A0 Document #: 38-05302 Rev. ** 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 NC DQPb NC DQb NC DQb VDDQ VDDQ VSSQ VSSQ NC DQb NC DQb DQb DQb DQb DQb VSSQ VSSQ VDDQ VDDQ DQb DQb DQb DQb V /DNU[2] SS VSS VDD NC NC VDD VSS ZZ DQb DQa DQb DQa VDDQ VDDQ VSSQ VSSQ DQb DQa DQb DQa DQPb DQa NC DQa VSSQ VSSQ VDDQ VDDQ NC DQa NC DQa NC DQPa 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 CY7C1363B (512K x 18) 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 A NC NC VDDQ VSSQ NC DQPDQ DQa DQa VSSQ VDDQ DQa DQa VSS NC VDD ZZ DQa DQa VDDQ VSSQ DQa DQa NC NC VSSQ VDDQ NC NC NC NC NC A A A A A A A CY7C1361B (256K X 36) 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 DQPc DQc DQc VDDQ VSSQ DQc DQc DQc DQc VSSQ VDDQ DQc DQc VSS/DNU[2] VDD NC VSS DQd DQd VDDQ VSSQ DQd DQd DQd DQd VSSQ VDDQ DQd DQd DQPd MODE A A A A A1 A0 NC NC VSS VDD 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 A A CE1 CE2 BWd BWc BWb BWa A VDD VSS CLK GW BWE OE ADSC ADSP ADV A A A A CE1 CE2 NC NC BWb BWa A VDD VSS CLK GW BWE OE ADSC ADSP ADV A A 100-pin TQFP (2 Chip Enable) Page 3 of 29 CY7C1361B CY7C1363B PRELIMINARY Pin Configurations (continued) 165-ball TQFP fBGA (3 Chip Enable with JTAG) CY7C1360B (256K x 36) 1 2 3 4 5 6 7 8 9 10 11 A B C D E F G H J K L M N P E(288) A CE1 BWc BWb CE3 BWE ADSC ADV A NC R NC A CE2 BWd BWa CLK GW OE ADSP A E(144) DQPc DQc NC DQc VDDQ VSS VSS VSS VSS VSS VSS VSS VDD VDDQ VDDQ VSS VDD VDDQ NC DQb DQPb DQb DQc DQc VDDQ VDD VSS VSS VSS VDD VDDQ DQb DQb DQc DQc VDDQ VDD VSS VSS VSS VDD VDDQ DQb DQb DQc VSS DQd DQc VSS DQd VDDQ NC VDDQ VDD VDD VDD VSS VSS VSS VSS VSS VSS VSS VSS VSS VDD VDD VDD VDDQ NC VDDQ DQb NC DQa DQb ZZ DQa DQd DQd VDDQ VDD VSS VSS VSS VDD VDDQ DQa DQa DQd DQd VDDQ VDD VSS VSS VSS VDD VDDQ DQa DQa DQd DQPd DQd NC VDDQ VDDQ VDD VSS VSS NC VSS E(18) VSS NC VDD VSS VDDQ VDDQ DQa NC DQa DQPa NC E(72) A A TDI A1 TDO A A A A MODE E(36) A A TMS A0 TCK A A A A CY7C1362B (512K x 18) 1 2 3 4 5 6 7 8 9 10 11 A B C D E F G H J K L M N P E(288) A CE1 BWb NC CE3 BWE ADSC ADV A A R NC A CE2 NC BWa CLK GW OE ADSP A E(144) NC NC NC DQb VDDQ VSS VSS VSS VSS VSS VSS VSS VDD VDDQ VDDQ VSS VDD VDDQ NC NC DQPa DQa NC DQb VDDQ VDD VSS VSS VSS VDD VDDQ NC DQa NC DQb VDDQ VDD VSS VSS VSS VDD VDDQ NC DQa NC VSS DQb DQb VSS NC VDDQ NC VDDQ VDD VDD VDD VSS VSS VSS VSS VSS VSS VSS VSS VSS VDD VDD VDD VDDQ NC VDDQ NC NC DQa DQa ZZ NC DQb NC VDDQ VDD VSS VSS VSS VDD VDDQ DQa NC DQb NC VDDQ VDD VSS VSS VSS VDD VDDQ DQa NC DQb DQPb NC NC VDDQ VDDQ VDD VSS VSS NC VSS E(18) VSS NC VDD VSS VDDQ VDDQ DQa NC NC NC NC E(72) A A TDI A1 TDO A A A A MODE E(36) A A TMS A0 TCK A A A A Document #: 38-05302 Rev. ** Page 4 of 29 CY7C1361B CY7C1363B PRELIMINARY Pin Configurations (continued) 119-ball BGA (2 Chip Enable with JTAG) CY7C1361B (256K x 36) 1 2 A VDDQ A 3 A 4 ADSP 5 A 6 A B NC CE2 A ADSC 7 VDDQ A A NC C NC A A VDD A A NC D DQc DQPc VSS NC VSS DQPb DQb E DQc DQc VSS CE1 VSS DQb DQb F VDDQ DQc VSS OE VSS DQb VDDQ G H J DQc DQc VDDQ DQc DQc VDD BWc VSS NC ADV GW VDD BWb VSS NC DQb DQb VDD DQb DQb VDDQ K L M DQd DQd VDDQ DQd DQd DQd VSS BWd VSS CLK NC BWE VSS BWa VSS DQa DQa DQa DQa DQa VDDQ N DQd DQd VSS A1 VSS DQa DQa P DQd DQPd VSS A0 VSS DQPa DQa R NC VDD NC A NC NC A NC MODE T A A A NC ZZ U VDDQ TMS TDI TCK TDO NC VDDQ CY7C1363B (512K x 18) 1 2 3 4 5 6 7 A VDDQ A A ADSP A A VDDQ B NC CE2 A ADSC A A NC C NC A A VDD A A NC D DQb NC VSS NC VSS DQPa NC E NC DQb VSS CE1 VSS NC DQa F VDDQ NC VSS OE VSS DQa VDDQ G H J NC DQb VDDQ DQb NC VDD BWb VSS NC ADV GW VDD VSS VSS NC NC DQb VDD DQa NC VDDQ K L NC DQb DQb NC VSS VSS CLK NC VSS BWa NC DQa DQa NC M VDDQ DQb VSS BWE VSS NC VDDQ N DQb NC VSS A1 VSS DQa NC P NC DQPb VSS A0 VSS NC DQa R NC A MODE VDD NC A NC T U NC VDDQ A TMS A TDI NC TCK A TDO A NC ZZ VDDQ Document #: 38-05302 Rev. ** Page 5 of 29 PRELIMINARY CY7C1361B CY7C1363B Pin Definitions Pin Name I/O Pin Description A0 A1 A InputSynchronous Address Inputs used to select one of the address locations. Sampled at the rising edge of the CLK if ADSP or ADSC is active LOW, and CE1, CE2, and CE3 are sampled active. A[1:0] feed the two-bit counter. BWa BWb BWc BWd InputSynchronous Byte Write Select Inputs, active LOW. Qualified with BWE to conduct byte writes to the SRAM. Sampled on the rising edge of CLK. GW InputSynchronous Global Write Enable Input, active LOW. When asserted LOW on the rising edge of CLK, a global write is conducted (ALL bytes are written, regardless of the values on BWa,b,c,d and BWE). BWE InputSynchronous Byte Write Enable Input, active LOW. Sampled on the rising edge of CLK. This signal must be asserted LOW to conduct a byte write. CLK InputClock Clock Input. Used to capture all synchronous inputs to the device. Also used to increment the burst counter when ADV is asserted LOW, during a burst operation. CE1 InputSynchronous Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE2 and CE3 to select/deselect the device. ADSP is ignored if CE1 is HIGH. CE2 InputSynchronous Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction with CE1 and CE3 to select/deselect the device. CE3 InputSynchronous Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE1 and CE2 to select/deselect the device. Not available on 100-pin TQFP, 2 Chip Enable or 119-ball BGA. OE InputAsynchronous Output Enable, asynchronous input, active LOW. Controls the direction of the I/O pins. When LOW, the I/O pins behave as outputs. When deasserted HIGH, I/O pins are three-stated, and act as input data pins. OE is masked during the first clock of a read cycle when emerging from a deselected state. ADV InputSynchronous Advance Input signal, active LOW, sampled on the rising edge of CLK. When asserted, it automatically increments the address in a burst cycle. ADSP InputSynchronous Address Strobe from Processor, active LOW, sampled on the rising edge of CLK. When asserted LOW, A is captured in the address registers. A[1:0] are also loaded into the burst counter. When ADSP and ADSC are both asserted, only ADSP is recognized. ADSP is ignored when CE1 is deasserted HIGH. ADSC InputSynchronous Address Strobe from Controller, active LOW, sampled on the rising edge of CLK. When asserted LOW, A[x:0] is captured in the address registers. A[1:0] are also loaded into the burst counter. When ADSP and ADSC are both asserted, only ADSP is recognized. MODE InputStatic Selects burst order. When tied to GND selects linear burst sequence. When tied to VDDQ or left floating selects interleaved burst sequence. This is a strap pin and should remain static during device operation. ZZ InputAsynchronous ZZ “sleep” Input. This active HIGH input places the device in a non-time critical “sleep” condition with data integrity preserved. This pin may be left disconnected for normal operation DQa DQb DQc DQd I/OSynchronous Bidirectional Data I/O lines. As inputs, they feed into an on-chip data register that is triggered by the rising edge of CLK. As outputs, they deliver the data contained in the memory location specified by A during the previous clock rise of the read cycle. The direction of the pins is controlled by OE. When OE is asserted LOW, the pins behave as outputs. When HIGH, DQx and DQPx are placed in a three-state condition. DQPa DQPb DQPc DQPd I/OSynchronous Bidirectional Data I/O lines. As inputs, they feed into an on-chip data register that is triggered by the rising edge of CLK. As outputs, they deliver the data contained in the memory location specified by A during the previous clock rise of the read cycle. The direction of the pins is controlled by OE. When OE is asserted LOW, the pins behave as outputs. When HIGH, DQa–DQd and DQPa–DQPd are placed in a three-state condition. TDO TDI JTAG Serial Output, Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK. If this pin Synchronous is not used, it should be disconnected. JTAG Serial Input, Synchronous Document #: 38-05302 Rev. ** Serial data-In to the JTAG circuit. Sampled on the rising edge of TCK. If this pin is not used, it may be connected to VSS, VDD or disconnected. Page 6 of 29 CY7C1361B CY7C1363B PRELIMINARY Pin Definitions I/O Pin Description TMS Pin Name Test Mode Select, Synchronous This pin controls the Test Access Port state machine. Sampled on the rising edge of TCK. If this pin is tied not used, it may be connected to VSS, VDD or disconnected. TCK JTAG-Clock Clock input to the JTAG circuitry. If this pin is tied not used, it may be connected to VSS, VDD or disconnected. VDD Power Supply Power supply inputs to the core of the device. Should be connected to 3.3V power supply. VSS VSS/DNU Ground VDDQ I/O Power Supply VSSQ I/O Ground NC Ground for the core of the device. Should be connected to ground of the system. Ground/Do Not Use This pin should be connected to VSS or left disconnected. This pin should not be tied to VDD, VDDQ, or a switching signal. – Power supply for the I/O circuitry. Should be connected to a 3.3V or 2.5V power supply. Ground for the I/O circuitry. Should be connected to ground of the system. No Connects. Functional Description Single Read Accesses This access is initiated when the following conditions are satisfied at clock rise: (1) ADSP or ADSC is asserted LOW, (2) CE1, CE2, CE3 are all asserted active, and (3) the write signals (GW, BWE) are all deasserted HIGH. ADSP is ignored if CE1 is HIGH. The address presented to the address inputs is stored into the address advancement logic and the Address Register while being presented to the memory core. If the OE input is asserted LOW, the requested data will be available at the data outputs a maximum to tCDV after clock rise. ADSP is ignored if CE1 is HIGH. Single Write Accesses Initiated by ADSP This access is initiated when both of the following conditions are satisfied at clock rise: (1) ADSP is asserted LOW, and (2) CE1, CE2, CE3 are all asserted active. The address presented is loaded into the address register and the address advancement logic while being delivered to the RAM core. The write signals (GW, BWE, and BWx) and ADV inputs are ignored during this first clock cycle. If the write inputs are asserted active (see Write Cycle Descriptions table for appropriate states that indicate a write) on the next clock rise, the appropriate data will be latched and written into the device. The CY7C1361B/CY7C1363B provides byte write capability that is described in the Write Cycle Description table. Asserting the Byte Write Enable input (BWE) with the selected Byte Write (BWa,b,c,d for CY7C1361B and BWa,b for CY7C1363B) input will selectively write to only the desired bytes. Bytes not selected during a byte write operation will remain unaltered. All I/Os are three-stated during a byte write. Because the CY7C1361B/CY7C1363B is a common I/O device, the Output Enable (OE) must be deasserted HIGH before presenting data to the DQx inputs. Doing so will three-state the output drivers. As a safety precaution, DQx are automatically three-stated whenever a write cycle is detected, regardless of the state of OE. Single Write Accesses Initiated by ADSC ADSC write accesses are initiated when the following conditions are satisfied: (1) ADSC is asserted LOW, (2) ADSP is Document #: 38-05302 Rev. ** deasserted HIGH, (3) CE1, CE2, CE3 are all asserted active, and (4) the appropriate combination of the write inputs (GW, BWE, and BWx) are asserted active to conduct a write to the desired byte(s). ADSC is ignored if ADSP is active LOW. The address presented to A[18:0] is loaded into the address register and the address advancement logic while being delivered to the RAM core. The ADV input is ignored during this cycle. If a global write is conducted, the data presented to the DQx is written into the corresponding address location in the RAM core. If a byte write is conducted, only the selected bytes are written. Bytes not selected during a byte write operation will remain unaltered. All I/Os are three-stated during a byte write. Because the CY7C1361B/CYC7C1363B is a common I/O device, the Output Enable (OE) must be deasserted HIGH before presenting data to the DQx inputs. Doing so will three-state the output drivers. As a safety precaution, DQx are automatically three-stated whenever a write cycle is detected, regardless of the state of OE. Burst Sequences The CY7C1361B/CY7C1363B provides a two-bit wraparound counter, fed by A[1:0], that implements either an interleaved or linear burst sequence. to support processors that follow a linear burst sequence. The burst sequence is user selectable through the MODE input. Asserting ADV LOW at clock rise will automatically increment the burst counter to the next address in the burst sequence. Both read and write burst operations are supported. Interleaved Burst Sequence First Address Second Address Third Address Fourth Address A[1:0] A[1:0] A[1:0] A[1:0] 00 01 10 11 01 00 11 10 10 11 00 01 11 10 01 00 Page 7 of 29 CY7C1361B CY7C1363B PRELIMINARY Sleep Mode Linear Burst Sequence First Address Second Address Third Address The ZZ input pin is an asynchronous input. Asserting ZZ HIGH places the SRAM in a power conservation “sleep” mode. Two clock cycles are required to enter into or exit from this “sleep” mode. While in this mode, data integrity is guaranteed. Accesses pending when entering the “sleep” mode are not considered valid nor is the completion of the operation guaranteed. The device must be deselected prior to entering the “sleep” mode. CE1, CE2, CE3, ADSP, and ADSC must remain inactive for the duration of tZZREC after the ZZ input returns LOW. Leaving ZZ unconnected defaults the device into an active state. Fourth Address A[1:0] A[1:0] A[1:0] A[1:0] 00 01 10 11 01 10 11 00 10 11 00 01 11 00 01 10 ZZ Mode Electrical Characteristics Parameter Description Test Conditions ICCZZ Snooze mode standby current ZZ > VDD − 0.2V tZZS Device operation to ZZ ZZ > VDD − 0.2V tZZREC ZZ recovery time ZZ < 0.2V Min. Max. Unit 35 mA 2tCYC ns 2tCYC ns Cycle Descriptions[3, 4, 5] Next Cycle Add. Used ZZ CE3 CE2 CE1 ADSP ADSC ADV OE DQ Write X X 1 X 0 X X Hi-Z X Unselected None L Unselected None L 1 X 0 0 X X X Hi-Z X Unselected None L X 0 0 0 X X X Hi-Z X Unselected None L 1 X 0 1 0 X X Hi-Z X Unselected None L X 0 0 1 0 X X Hi-Z X Begin Read External L 0 1 0 0 X X X Hi-Z X Begin Read External L 0 1 0 1 0 X X Hi-Z Read Continue Read Next L X X X 1 1 0 1 Hi-Z Read Continue Read Next L X X X 1 1 0 0 DQ Read Continue Read Next L X X 1 X 1 0 1 Hi-Z Read Continue Read Next L X X 1 X 1 0 0 DQ Read Suspend Read Current L X X X 1 1 1 1 Hi-Z Read Suspend Read Current L X X X 1 1 1 0 DQ Read Suspend Read Current L X X 1 X 1 1 1 Hi-Z Read Suspend Read Current L X X 1 X 1 1 0 DQ Read Begin Write Current L X X X 1 1 1 X Hi-Z Write Begin Write Current L X X 1 X 1 1 X Hi-Z Write Begin Write External L 0 1 0 1 0 X X Hi-Z Write Continue Write Next L X X X 1 1 0 X Hi-Z Write Continue Write Next L X X 1 X 1 0 X Hi-Z Write Suspend Write Current L X X X 1 1 1 X Hi-Z Write Suspend Write Current L X X 1 X 1 1 X Hi-Z Write ZZ “sleep” None H X X X X X X X Hi-Z X Note: 3. X = ”don't care”, 1 = HIGH, 0 = LOW. 4. The SRAM always initiates a read cycle when ADSP asserted, regardless of the state of GW, BWE, or BWx. Writes may occur only on subsequent clocks after the ADSP or with the assertion of ADSC. As a result, OE must be driven HIGH prior to the start of the write cycle to allow the outputs to three-state. OE is a “Don't Care” for the remainder of the write cycle. 5. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle DQ = High-Z when OE is inactive or when the device is deselected, and DQ = data when OE is active. Document #: 38-05302 Rev. ** Page 8 of 29 CY7C1361B CY7C1363B PRELIMINARY Write Cycle Description[3] Function (1361B) GW BWE BWd BWc BWb BWa Read 1 1 X X X X Read 1 0 1 1 1 1 Write Byte 0 – DQa 1 0 1 1 1 0 Write Byte 1 – DQb 1 0 1 1 0 1 Write Bytes 1, 0 1 0 1 1 0 0 Write Byte 2 – DQc 1 0 1 0 1 1 Write Bytes 2, 0 1 0 1 0 1 0 Write Bytes 2, 1 1 0 1 0 0 1 Write Bytes 2, 1, 0 1 0 1 0 0 0 Write Byte 3 – DQd 1 0 0 1 1 1 Write Bytes 3, 0 1 0 0 1 1 0 Write Bytes 3, 1 1 0 0 1 0 1 Write Bytes 3, 1, 0 1 0 0 1 0 0 Write Bytes 3, 2 1 0 0 0 1 1 Write Bytes 3, 2, 0 1 0 0 0 1 0 Write Bytes 3, 2, 1 1 0 0 0 0 1 Write All Bytes 1 0 0 0 0 0 Write All Bytes 0 X X X X X GW BWE BWb BWa Read 1 1 X X Read 1 0 1 1 Write Byte 0 – DQa and DQPa 1 0 1 0 Write Byte 1 – DQb and DQPb 1 0 0 1 Write All Bytes 1 0 0 0 Write All Bytes 0 X X X Function (1363B) IEEE 1149.1 Serial Boundary Scan (JTAG) The CY7C1361B/63B incorporates a serial boundary scan Test Access Port (TAP) in the FBGA package only. The TQFP package does not offer this functionality. This port operates in accordance with IEEE Standard 1149.1-1900, but does not have the set of functions required for full 1149.1 compliance. These functions from the IEEE specification are excluded because their inclusion places an added delay in the critical speed path of the SRAM. Note that the TAP controller functions in a manner that does not conflict with the operation of other devices using 1149.1 fully compliant TAPs. The TAP operates using JEDEC-standard 2.5V I/O logic levels. in a reset state which will not interfere with the operation of the device. Test Access Port–Test Clock The test clock is used only with the TAP controller. All inputs are captured on the rising edge of TCK. All outputs are driven from the falling edge of TCK. Test Mode Select The TMS input is used to give commands to the TAP controller and is sampled on the rising edge of TCK. It is allowable to leave this pin unconnected if the TAP is not used. The pin is pulled up internally, resulting in a logic HIGH level. Disabling the JTAG Feature Test Data-In (TDI) It is possible to operate the SRAM without using the JTAG feature. To disable the TAP controller, TCK must be tied LOW (VSS) to prevent clocking of the device. TDI and TMS are internally pulled up and may be unconnected. They may alternately be connected to VDD through a pull-up resistor. TDO should be left unconnected. Upon power-up, the device will come up The TDI pin is used to serially input information into the registers and can be connected to the input of any of the registers. The register between TDI and TDO is chosen by the instruction that is loaded into the TAP instruction register. For information on loading the instruction register, see the TAP Controller State Diagram. TDI is internally pulled up and can Document #: 38-05302 Rev. ** Page 9 of 29 PRELIMINARY CY7C1361B CY7C1363B be unconnected if the TAP is unused in an application. TDI is connected to the Most Significant Bit (MSB) on any register. on the SRAM package. The MSB of the register is connected to TDI, and the LSB is connected to TDO. Test Data Out (TDO) Identification (ID) Register The TDO output pin is used to serially clock data-out from the registers. The output is active depending upon the current state of the TAP state machine (see TAP Controller State Diagram). The output changes on the falling edge of TCK. TDO is connected to the Least Significant Bit (LSB) of any register. The ID register is loaded with a vendor-specific, 32-bit code during the Capture-DR state when the IDCODE command is loaded in the instruction register. The IDCODE is hardwired into the SRAM and can be shifted out when the TAP controller is in the Shift-DR state. The ID register has a vendor code and other information described in the Identification Register Definitions table. Performing a TAP Reset A Reset is performed by forcing TMS HIGH (VDD) for five rising edges of TCK. This RESET does not affect the operation of the SRAM and may be performed while the SRAM is operating. At power-up, the TAP is reset internally to ensure that TDO comes up in a high-Z state. TAP Registers Registers are connected between the TDI and TDO pins and allow data to be scanned into and out of the SRAM test circuitry. Only one register can be selected at a time through the instruction registers. Data is serially loaded into the TDI pin on the rising edge of TCK. Data is output on the TDO pin on the falling edge of TCK. Instruction Register TAP Instruction Set Eight different instructions are possible with the three-bit instruction register. All combinations are listed in the Instruction Code table. Three of these instructions are listed as RESERVED and should not be used. The other five instructions are described in detail below. The TAP controller used in this SRAM is not fully compliant to the 1149.1 convention because some of the mandatory 1149.1 instructions are not fully implemented. The TAP controller cannot be used to load address, data, or control signals into the SRAM and cannot preload the Input or Output buffers. The SRAM does not implement the 1149.1 commands EXTEST or INTEST or the PRELOAD portion of SAMPLE/PRELOAD; rather it performs a capture of the Inputs and Output ring when these instructions are executed. Three-bit instructions can be serially loaded into the instruction register. This register is loaded when it is placed between the TDI and TDO pins as shown in the TAP Controller Block Diagram. Upon power-up, the instruction register is loaded with the IDCODE instruction. It is also loaded with the IDCODE instruction if the controller is placed in a reset state as described in the previous section. Instructions are loaded into the TAP controller during the Shift-IR state when the instruction register is placed between TDI and TDO. During this state, instructions are shifted through the instruction register through the TDI and TDO pins. To execute the instruction once it is shifted in, the TAP controller needs to be moved into the Update-IR state. When the TAP controller is in the CaptureIR state, the two least significant bits are loaded with a binary “01” pattern to allow for fault isolation of the board level serial test path. EXTEST Bypass Register EXTEST is a mandatory 1149.1 instruction which is to be executed whenever the instruction register is loaded with all 0s. EXTEST is not implemented in the TAP controller, and therefore this device is not compliant to the 1149.1 standard. To save time when serially shifting data through registers, it is sometimes advantageous to skip certain states. The bypass register is a single-bit register that can be placed between TDI and TDO pins. This allows data to be shifted through the SRAM with minimal delay. The bypass register is set LOW (VSS) when the BYPASS instruction is executed. The TAP controller does recognize an all-0 instruction. When an EXTEST instruction is loaded into the instruction register, the SRAM responds as if a SAMPLE/PRELOAD instruction has been loaded. There is one difference between the two instructions. Unlike the SAMPLE/PRELOAD instruction, EXTEST places the SRAM outputs in a High-Z state. Boundary Scan Register IDCODE The boundary scan register is connected to all the input and output pins on the SRAM. Several no connect (NC) pins are also included in the scan register to reserve pins for higher density devices. The x36 configuration has a xx-bit-long register, and the x18 configuration has a yy-bit-long register. The IDCODE instruction causes a vendor-specific, 32-bit code to be loaded into the instruction register. It also places the instruction register between the TDI and TDO pins and allows the IDCODE to be shifted out of the device when the TAP controller enters the Shift-DR state. The IDCODE instruction is loaded into the instruction register upon power-up or whenever the TAP controller is given a test logic reset state. The boundary scan register is loaded with the contents of the RAM Input and Output ring when the TAP controller is in the Capture-DR state and is then placed between the TDI and TDO pins when the controller is moved to the Shift-DR state. The EXTEST, SAMPLE/PRELOAD and SAMPLE Z instructions can be used to capture the contents of the Input and Output ring. The Boundary Scan Order tables show the order in which the bits are connected. Each bit corresponds to one of the bumps Document #: 38-05302 Rev. ** SAMPLE Z The SAMPLE Z instruction causes the boundary scan register to be connected between the TDI and TDO pins when the TAP controller is in a Shift-DR state. It also places all SRAM outputs into a High-Z state. Page 10 of 29 PRELIMINARY SAMPLE/PRELOAD SAMPLE/PRELOAD is a 1149.1 mandatory instruction. The PRELOAD portion of this instruction is not implemented, so the TAP controller is not fully 1149.1-compliant. When the SAMPLE/PRELOAD instructions are loaded into the instruction register and the TAP controller is in the Capture-DR state, a snapshot of data on the inputs and output pins is captured in the boundary scan register. The user must be aware that the TAP controller clock can only operate at a frequency up to 10 MHz, while the SRAM clock operates more than an order of magnitude faster. Because there is a large difference in the clock frequencies, it is possible that during the Capture-DR state, an input or output will undergo a transition. The TAP may then try to capture a signal while in transition (metastable state). This will not harm the device, but there is no guarantee as to the value that will be captured. Repeatable results may not be possible. To guarantee that the boundary scan register will capture the correct value of a signal, the SRAM signal must be stabilized long enough to meet the TAP controller’s capture set-up plus hold times (tCS and tCH). The SRAM clock input might not be captured correctly if there is no way in a design to stop (or slow) the clock during a SAMPLE/PRELOAD instruction. If this Document #: 38-05302 Rev. ** CY7C1361B CY7C1363B is an issue, it is still possible to capture all other signals and simply ignore the value of the CK and CK# captured in the boundary scan register. Once the data is captured, it is possible to shift out the data by putting the TAP into the Shift-DR state. This places the boundary scan register between the TDI and TDO pins. Note that since the PRELOAD part of the command is not implemented, putting the TAP into the Update to the Update-DR state while performing a SAMPLE/PRELOAD instruction will have the same effect as the Pause-DR command. BYPASS When the BYPASS instruction is loaded in the instruction register and the TAP is placed in a Shift-DR state, the bypass register is placed between the TDI and TDO pins. The advantage of the BYPASS instruction is that it shortens the boundary scan path when multiple devices are connected together on a board. Reserved These instructions are not implemented but are reserved for future use. Do not use these instructions. Page 11 of 29 CY7C1361B CY7C1363B PRELIMINARY TAP Controller State Diagram[6] 1 TEST-LOGIC RESET 0 TEST-LOGIC/ IDLE 1 1 1 SELECT DR-SCAN SELECT IR-SCAN 0 0 1 1 CAPTURE-DR CAPTURE-DR 0 0 0 SHIFT-DR 0 SHIFT-IR 1 1 1 EXIT1-DR 1 EXIT1-IR 0 0 PAUSE-DR 0 0 PAUSE-IR 1 1 0 0 EXIT2-DR EXIT2-IR 1 1 UPDATE-DR 1 0 UPDATE-IR 1 0 Note: 6. The 0/1 next to each state represents the value at TMS at the rising edge of TCK. Document #: 38-05302 Rev. ** Page 12 of 29 CY7C1361B CY7C1363B PRELIMINARY TAP Controller Block Diagram 0 Bypass Register Selection Circuitry 2 1 0 Selection Circuitry Instruction Register TDO TDI 31 30 29 . . 2 1 0 1 0 Identification Register x . . . . 2 Boundary Scan Register TCK TAP Controller TMS TAP Electrical Characteristics Over the Operating Range[7, 8] Parameter VOH1 VOH2 Description Output HIGH Voltage Output HIGH Voltage Test Conditions Min. Max. Unit IOH = –2.0 mA, VDDQ = 3.3V 2.0 V IOH = –2.0 mA, VDDQ = 2.5V 1.7 V IOH = –100 µA, VDDQ = 3.3V 2.0 V IOH = –100 µA, VDDQ = 2.5V 2.0 V VOL1 Output LOW Voltage IOL = 2.0 mA 0.7 V VOL2 Output LOW Voltage IOL = 100 µA 0.2 V VIH Input HIGH Voltage VDDQ = 3.3V 2.0 VDD + 0.3 V VDDQ = 2.5V 1.7 VIL Input LOW Voltage IX Input Load Current GND ≤ VI ≤ VDDQ TAP AC Switching Characteristics Over the Operating Range Parameter Description V –0.3 0.7 V –30 30 µA [9, 10] Min. Max. 100 Unit tTCYC TCK Clock Cycle Time ns tTF TCK Clock Frequency tTH TCK Clock HIGH 40 ns tTL TCK Clock LOW 40 ns tTMSS TMS Set-up to TCK Clock Rise 10 ns tTDIS TDI Set-up to TCK Clock Rise 10 ns tCS Capture Set-up to TCK Rise 10 ns 10 MHz Set-up Times Notes: 7. All voltages referenced to ground. 8. Overshoot: VIH(AC) < VDD + 1.5V for t < tTCYC/2; undershoot: VIL(AC) < −0.5V for t < tTCYC/2; power-up: VIH < 3.6V and VDD < 3.135V and VDDQ < 1.4V for t < 200 ms. 9. tCS and tCH refer to the set-up and hold time requirements of latching data from the boundary scan register. 10. Test conditions are specified using the load in TAP AC test conditions. tR/tF = 1. Document #: 38-05302 Rev. ** Page 13 of 29 CY7C1361B CY7C1363B PRELIMINARY TAP AC Switching Characteristics Over the Operating Range (continued)[9, 10] Parameter Description Min. Max. Unit Hold Times tTMSH TMS Hold after TCK Clock Rise 10 ns tTDIH TDI Hold after Clock Rise 10 ns tCH Capture Hold after Clock Rise 10 ns Output Times tTDOV TCK Clock LOW to TDO Valid tTDOX TCK Clock LOW to TDO Invalid 20 0 ns ns TAP Timing and Test Conditions 1.5V/1.25V ALL INPUT PULSES 2.5/3.0V 1.5/1.25V 50Ω 0V TDO Z0 = 50Ω CL = 20 pF tTH (a) GND Test Clock TCK tTCYC tTMSS tTMSH tTL Test Mode Select TMS tTDIS tTDIH Test Data-In TDI Test Data-Out TDO tTDOV tTDOX Identification Register Definitions Instruction Field Value Description Revision Number (31:28) TBD Reserved for version number Device Depth (27:23) TBD Defines depth of SRAM Device Width (22:18) TBD Defines with of the SRAM Cypress Device ID (17:12) TBD Reserved for future use Cypress JEDEC ID (11:1) TBD Allows unique identification of SRAM vendor ID Register Presence (0) TBD Indicate the presence of an ID register Document #: 38-05302 Rev. ** Page 14 of 29 CY7C1361B CY7C1363B PRELIMINARY Scan Register Sizes Register Name Bit Size Instruction 3 Bypass 1 ID 32 Boundary Scan TBD Identification Codes Instruction Code Description EXTEST 000 Captures the Input/Output ring contents. Places the boundary scan register between the TDI and TDO. Forces all SRAM outputs to High-Z state. This instruction is not 1149.1-compliant. IDCODE 001 Loads the ID register with the vendor ID code and places the register between TDI and TDO. This operation does not affect SRAM operation. SAMPLE Z 010 Captures the Input/Output contents. Places the boundary scan register between TDI and TDO. Forces all SRAM output drivers to a High-Z state. RESERVED 011 Do Not Use: This instruction is reserved for future use. SAMPLE/PRELOAD 100 Captures the Input/Output ring contents. Places the boundary scan register between TDI and TDO. Does not affect the SRAM operation. This instruction does not implement 1149.1 preload function and is therefore not 1149.1-compliant. RESERVED 101 Do Not Use: This instruction is reserved for future use. RESERVED 110 Do Not Use: This instruction is reserved for future use. BYPASS 111 Places the bypass register between TDI and TDO. This operation does not affect SRAM operation. Boundary Scan Order Boundary Scan Order (continued) Bit # Signal Name 119-Ball ID 165-Ball ID Bit # Signal Name 119-Ball ID 165-Ball ID 1 TBD TBD TBD 23 TBD TBD TBD 2 TBD TBD TBD 24 TBD TBD TBD 3 TBD TBD TBD 25 TBD TBD TBD 4 TBD TBD TBD 26 TBD TBD TBD 5 TBD TBD TBD 27 TBD TBD TBD 6 TBD TBD TBD 28 TBD TBD TBD 7 TBD TBD TBD 29 TBD TBD TBD 8 TBD TBD TBD 30 TBD TBD TBD 9 TBD TBD TBD 31 TBD TBD TBD 10 TBD TBD TBD 32 TBD TBD TBD 11 TBD TBD TBD 33 TBD TBD TBD 12 TBD TBD TBD 34 TBD TBD TBD 13 TBD TBD TBD 35 TBD TBD TBD 14 TBD TBD TBD 36 TBD TBD TBD 15 TBD TBD TBD 37 TBD TBD TBD 16 TBD TBD TBD 38 TBD TBD TBD 17 TBD TBD TBD 39 TBD TBD TBD 18 TBD TBD TBD 40 TBD TBD TBD 19 TBD TBD TBD 41 TBD TBD TBD 20 TBD TBD TBD 42 TBD TBD TBD 21 TBD TBD TBD 43 TBD TBD TBD 22 TBD TBD TBD 44 TBD TBD TBD Document #: 38-05302 Rev. ** Page 15 of 29 CY7C1361B CY7C1363B PRELIMINARY Boundary Scan Order (continued) Boundary Scan Exit Order (x18) (continued) Bit # Signal Name 119-Ball ID 165-Ball ID Bit # Signal Name 119-Ball ID 165-Ball ID 45 TBD TBD TBD 12 TBD TBD TBD 46 TBD TBD TBD 13 TBD TBD TBD 47 TBD TBD TBD 14 TBD TBD TBD 48 TBD TBD TBD 15 TBD TBD TBD 49 TBD TBD TBD 16 TBD TBD TBD 50 TBD TBD TBD 17 TBD TBD TBD 51 TBD TBD TBD 18 TBD TBD TBD 52 TBD TBD TBD 19 TBD TBD TBD 53 TBD TBD TBD 20 TBD TBD TBD 54 TBD TBD TBD 21 TBD TBD TBD 55 TBD TBD TBD 22 TBD TBD TBD 56 TBD TBD TBD 23 TBD TBD TBD 57 TBD TBD TBD 24 TBD TBD TBD 58 TBD TBD TBD 25 TBD TBD TBD 59 TBD TBD TBD 26 TBD TBD TBD 60 TBD TBD TBD 27 TBD TBD TBD 61 TBD TBD TBD 28 TBD TBD TBD 62 TBD TBD TBD 29 TBD TBD TBD 63 TBD TBD TBD 30 TBD TBD TBD 64 TBD TBD TBD 31 TBD TBD TBD 65 TBD TBD TBD 32 TBD TBD TBD 66 TBD TBD TBD 33 TBD TBD TBD 67 TBD TBD TBD 34 TBD TBD TBD 68 TBD TBD TBD 35 TBD TBD TBD 69 TBD TBD TBD 36 TBD TBD TBD 70 TBD TBD TBD 37 TBD TBD TBD 38 TBD TBD TBD Boundary Scan Exit Order (x18) 39 TBD TBD TBD Bit # Signal Name 119-Ball ID 165-Ball ID 40 TBD TBD TBD 1 TBD TBD TBD 41 TBD TBD TBD 2 TBD TBD TBD 42 TBD TBD TBD 3 TBD TBD TBD 43 TBD TBD TBD 4 TBD TBD TBD 44 TBD TBD TBD 5 TBD TBD TBD 45 TBD TBD TBD 6 TBD TBD TBD 46 TBD TBD TBD 7 TBD TBD TBD 47 TBD TBD TBD 8 TBD TBD TBD 48 TBD TBD TBD 9 TBD TBD TBD 49 TBD TBD TBD 10 TBD TBD TBD 50 TBD TBD TBD 11 TBD TBD TBD 51 TBD TBD TBD Document #: 38-05302 Rev. ** Page 16 of 29 CY7C1361B CY7C1363B PRELIMINARY Maximum Ratings Current into Outputs (LOW)......................................... 20 mA (Above which the useful life may be impaired. For user guidelines only, not tested.) Static Discharge Voltage.......................................... > 2001V (per MIL-STD-883, Method 3015) Storage Temperature .................................–65°C to +150°C Latch-up Current.................................................... > 200 mA Ambient Temperature with Power Applied............................................. –55°C to +125°C Operating Range Supply Voltage on VDD Relative to GND..... –0.5V to +4.6V n DC to Outputs in High-Z State[12] ........ –0.5V to VDDQ + 0.5V DC Input Voltage[12] ............................ –0.5V to VDDQ + 0.5V Range Ambient Temperature[11] Com’l 0°C to +70°C VDD/VDDQ 3.135 - 3.6V / 3.135 - 3.6V or 2.375 - 2.9V Electrical Characteristics Over the Operating Range Parameter Description VDD Power Supply Voltage VDDQ I/O Supply Voltage VOH VOL VIH VIL Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage[12] Test Conditions Min. Max. Unit 3.135 3.6 V VDDQ = 3.3V 3.135 VDD V VDDQ = 2.5V 2.375 2.9 V VDD = Min., IOH = −4.0 mA, VDDQ = 3.3V 2.4 V VDD = Min., IOH = −1.0 mA, VDDQ = 2.5V 2.0 V VDD = Min., IOH = 8.0 mA, VDDQ = 3.3V 0.4 V VDD = Min., IOH = 1.0 mA, VDDQ = 2.5V 0.4 V VDDQ + 0.3V V VDDQ = 3.3V 2.0 VDDQ = 2.5V 1.7 VDDQ = 3.3V –0.3 0.8 VDDQ = 2.5V –0.3 0.7 –5 5 µA GND ≤ VI ≤ VDDQ V V IX Input Load Current except ZZ and MODE IOZ Output Leakage Current GND ≤ VI ≤ VDDQ, Output Disabled –5 5 µA IZZ Input Current of MODE and ZZ pins –30 30 µA IDD VDD Operating Supply Current 7.5-ns cycle, 133 MHz 250 mA 8.8-ns cycle, 113 MHz 220 mA 10-ns cycle, 100 MHz 180 mA ISB1 Automatic CS Power-down Current—TTL Inputs VDD = Max., IOUT = 0 mA, f = fMAX = 1/tCYC Max. VDD, Device Deselected, VIN > VIH or VIN < VIL f = fMAX = 1/tCYC 7.5-ns cycle, 133 MHz TBD mA 8.8-ns cycle, 113 MHz TBD mA 10-ns cycle, 100 MHz TBD mA 30 mA ISB2 Automatic CS Max. VDD, Device Deselected, Power-down VIN < 0.3V or VIN > VDDQ – 0.3V, f Current—CMOS Inputs = 0 ISB3 Automatic CS Max. VDD, Device Deselected, or 7.5-ns cycle, 133 MHz Power-down VIN < 0.3V or VIN > VDDQ – 0.3V 8.8-ns cycle, 113 MHz Current—CMOS Inputs f = fMAX = 1/tCYC 10-ns cycle, 100 MHz TBD mA TBD mA TBD mA Automatic CS Power-down Current—TTL Inputs TBD mA ISB4 Max. VDD, Device Deselected, VIN > VIH or VIN < VIL, f = 0 Notes: 11. TA is the case temperature. 12. Minimum voltage equals –2.0V for pulse durations of less than 20 ns. Document #: 38-05302 Rev. ** Page 17 of 29 CY7C1361B CY7C1363B PRELIMINARY Capacitance[12] Parameter Description CIN Input Capacitance CCLK Clock Input Capacitance CI/O Input/Output Capacitance Test Conditions Max. Unit 4 pF 4 pF 4 pF TA = 25°C, f = 1 MHz, VDD = VDDQ = 3.3V AC Test Loads and Waveforms 3.0V/2.5V OUTPUT R = 317/1667Ω ALL INPUT PULSES OUTPUT Z0 = 50Ω RL = 50Ω VL = 1.5V/2.5V (a) 5 pF INCLUDING JIG AND SCOPE 3.0/2.5V 90% 10% [13] 90% 10% 1.5/1.25V GND R = 351/1538Ω ≤ 3V/ns ≤ 3V/ns (c) (b) Thermal Resistance Parameter Description QJA Thermal Resistance (Junction to Ambient) QJC Thermal Resistance (Junction to Case) Test Conditions Still Air, soldered on a 4.25 x 1.125 inch, 4-layer printed circuit board BGA Typ. fBGA Typ. TQFP Typ. Unit Notes 25 27 25 °C/W 14 6 6 9 °C/W 14 Notes: 13. TA is the case temperature. 14. Input waveform should have a slew rate of > 1 V/ns. 15. Tested initially and after any design or process change that may affect these parameters. Document #: 38-05302 Rev. ** Page 18 of 29 CY7C1361B CY7C1363B PRELIMINARY Switching Characteristics Over the Operating Range[16, 17, 18,19] -133 Parameter Description Min. -117 Max. Min. -100 Max. Min. Max. Unit Clock tCYC Clock Cycle Time 7.5 8.5 FMAX Maximum Operating Frequency tCH Clock HIGH 3.0 3.2 4.0 ns tCL Clock LOW 3.0 3.2 4.0 ns 133 10.0 117 ns 100 MHz Output Times tCO Data Output Valid After CLK Rise 6.5 7.5 8.5 ns tEOV OE LOW to Output Valid[17] 3.5 3.5 3.5 ns tDOH Data Output Hold After CLK Rise tCHZ Clock to High-Z[17] 0 tCLZ Clock to Low-Z[17] 0 tEOHZ OE HIGH to Output High-Z[17, 18] tEOLZ [17, 18] OE LOW to Output Low-Z 2.0 2.0 3.5 0 2.0 3.5 0 3.5 0 ns 3.5 0 3.5 ns ns 3.5 ns 0 0 0 ns Set-up Times tAS Address Set-up Before CLK Rise 1.5 1.5 1.5 ns tDS Data Input Set-up Before CLK Rise 1.5 1.5 1.5 ns tADS ADSP, ADSC Set-up Before CLK Rise 1.5 1.5 1.5 ns tWES WE, BWSx Set-up Before CLK Rise 1.5 1.5 1.5 ns tADVS ADV Set-up Before CLK Rise 1.5 1.5 1.5 ns tCES Chip Select Set-up 1.5 1.5 1.5 ns tAH Address Hold After CLK Rise 0.5 0.5 0.5 ns tDH Data Input Hold After CLK Rise 0.5 0.5 0.5 ns tADH ADSP, ADSC Hold After CLK Rise 0.5 0.5 0.5 ns tWEH WE, BWx Hold After CLK Rise 0.5 0.5 0.5 ns tADVH ADV Hold after CLK Rise 0.5 0.5 0.5 ns tCEH Chip Select Hold After CLK Rise 0.5 0.5 0.5 ns Hold Times Notes: 16. Unless otherwise noted, test conditions assume signal transition time of 1 ns or less, timing reference levels of 1.5V or 1.25V, input pulse levels of 0 to 3.0V, and output loading of the specified IOL/IOH and load capacitance. Shown in (a), (b), and (c) of AC Test Loads. 17. tCHZ, tCLZ, tOEV, tEOLZ, and tEOHZ are specified with a load capacitance of 5 pF as in (b) of AC Test Loads. Transition is measured ± 200 mV from steady-state voltage. 18. At any given voltage and temperature, tEOHZ is less than tEOLZ and tCHZ is less than tCLZ. 19. AC parameters may exceed minimums and maximums during the first 20 microseconds of operation. Document #: 38-05302 Rev. ** Page 19 of 29 CY7C1361B CY7C1363B PRELIMINARY Timing Diagrams Write Cycle Timing[20, 21] Single Write Burst Write Pipelined Write tCH Unselected tCYC CLK tADH tADS tCL ADSP ignored with CE1 inactive ADSP tADH tADS ADSC initiated write ADSC tADVH tADVS ADV tAS ADD ADV Must Be Inactive for ADSP Write WD1 WD3 WD2 tAH GW tWS tWH WE tCES tWH tWS tCEH CE1 masks ADSP CE1 tCES tCEH Unselected with CE2 CE2 CE3 tCES tCEH OE tDH tDS Data- High-Z In 1a 1a 2a = UNDEFINED 2b 2c 2d 3a High-Z = DON’T CARE Notes: 20. WE is the combination of BWE, BWx, and GW to define a write cycle (see Write Cycle Description table). 21. WDx stands for Write Data to Address X. Document #: 38-05302 Rev. ** Page 20 of 29 CY7C1361B CY7C1363B PRELIMINARY Timing Diagrams (continued) Read Cycle Timing[20, 22] Burst Read Single Read tCYC Unselected tCH Pipelined Read CLK tADH tADS tCL ADSP ignored with CE1 inactive ADSP tADS ADSC initiated read ADSC tADVS tADH Suspend Burst ADV tADVH tAS ADD RD1 RD3 RD2 tAH GW tWS tWS tWH WE tCES tCEH tWH CE1 masks ADSP CE1 Unselected with CE2 CE2 tCES tCEH CE3 tCES OE Data Out tCEH tEOV tCDV tOEHZ tDOH 2a 1a 1a 2b 2c 2c 2d 3a tCLZ tCHZ = DON’T CARE = UNDEFINED Note: 22. RDx stands for Read Data from Address X. Document #: 38-05302 Rev. ** Page 21 of 29 CY7C1361B CY7C1363B PRELIMINARY Timing Diagrams (continued) Read/Write Timing[23] tCYC tCH tCL CLK tAH tAS ADD A B D C tADH tADS ADSP tADH tADS ADSC tADVH tADVS ADV tCEH tCES CE1 tCEH tCES CE tWEH tWES WE ADSP ignored with CE1 HIGH OE tEOHZ tCLZ Data Q(A) In/Out Q(B) Q (B+1) Q (B+2) Q (B+3) Q(B) D(C) D (C+1) D (C+2) D (C+3) Q(D) tCDV tDOH tCHZ = DON’T CARE = UNDEFINED Note: 23. Device originally deselected. WE is the combination of BWE, BWx, and GW to define a write cycle (see Write Cycle Description table). CE is the combination of CE2 and CE3. All chip selects need to be active in order to select the device. RAx stands for Read Address X, WAx stands for Write Address X, Dx stands for Data-in X, Qx stands for Data-out X. Document #: 38-05302 Rev. ** Page 22 of 29 CY7C1361B CY7C1363B PRELIMINARY Timing Diagrams (continued) Pipeline Timing tCH tCYC tCL CLK tAS ADD RD1 tADS RD2 RD3 WD1 RD4 WD2 WD3 WD4 tADH ADSC initiated Reads ADSC ADSP initiated Reads ADSP ADV tCEH tCES CE1 CE tWEH tWES WE ADSP ignored with CE1 HIGH OE tCLZ Data In/Out 1a Out 2a Out 3a Out 4a Out 1a In 2a In 3a In 4a D(C) In tCDV tDOH Back to Back Reads tCHZ Back to Back Writes = DON’T CARE Document #: 38-05302 Rev. ** = UNDEFINED Page 23 of 29 CY7C1361B CY7C1363B PRELIMINARY Timing Diagrams (continued) OE Switching Waveforms OE tEOV tEOHZ Three-state I/Os tEOLZ ZZ Mode Timing [24, 25] CLK ADSP HIGH ADSC CE1 CE2 LOW HIGH CE3 ZZ ICC tZZS ICC(active) ICCZZ I/Os tZZREC Three-state Notes: 24. Device must be deselected when entering ZZ mode. See Cycle Description for all possible signal conditions to deselect the device. 25. I/Os are in three-state when exiting ZZ sleep mode. Document #: 38-05302 Rev. ** Page 24 of 29 CY7C1361B CY7C1363B PRELIMINARY Ordering Information Speed (MHz) 133 Ordering Code CY7C1361B-133AC Package Name Package Type A101 100-lead Thin Quad Flat Pack, 3 Chip Enable A101 100-lead Thin Quad Flat Pack, 2 Chip Enable Operating Range Commercial CY7C1363B-133AC CY7C1361B-133AJC CY7C1363B-133AJC CY7C1361B-133BGC BG119 119-ball BGA BB165A 165-ball fBGA CY7C1363B-133BGC CY7C1361B-133BZC CY7C1363B-133BZC 117 CY7C1361B-117AC A101 100-lead Thin Quad Flat Pack, 3 Chip Enable A101 100-lead Thin Quad Flat Pack, 2 Chip Enable CY7C1363B-117AC CY7C1361B-117AJC CY7C1363B-117AJC CY7C1361B-117BGC BG119 119-ball BGA BB165 165-ball fBGA CY7C1363B-117BGC CY7C1361B-117BZC CY7C1363B-117BZC 100 CY7C1361B-100AC A101 100-lead Thin Quad Flat Pack, 3 Chip Enable A101 100-lead Thin Quad Flat Pack, 2 Chip Enable CY7C1363B-100AC CY7C1361B-100AJC CY7C1363B-100AJC CY7C1361B-100BGC BG119 119-ball BGA BB165 165-ball fBGA CY7C1363B-100BGC CY7C1361B-100BZC CY7C1363B-100BZC Document #: 38-05302 Rev. ** Page 25 of 29 PRELIMINARY CY7C1361B CY7C1363B Package Diagrams 100-pin Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm) A101 51-85050-A Document #: 38-05302 Rev. ** Page 26 of 29 PRELIMINARY CY7C1361B CY7C1363B Package Diagrams (continued) 119-ball BGA (14 x 22 x 2.4) BG119 51-85115-*A Document #: 38-05302 Rev. ** Page 27 of 29 PRELIMINARY CY7C1361B CY7C1363B Package Diagrams (continued) 165-ball FBGA (13 x 15 x 1.2 mm) BB165A 51-85122-*B All product and company names mentioned in this document are the trademarks of their respective holders. Document #: 38-05302 Rev. ** Page 28 of 29 © Cypress Semiconductor Corporation, 2002. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. CY7C1361B CY7C1363B PRELIMINARY Document Title: CY7C1361B/CY7C1363B 256K x 36/512K x 18 Flow-through SRAM Document Number: 38-05302 REV. ECN No. Issue Date Orig. of Change ** 116857 06/24/02 RCS Document #: 38-05302 Rev. ** Description of Change New Data Sheet Page 29 of 29