ETC CY7C1302V25

CY7C1302V25
9-Mb Pipelined SRAM with QDR™ Architecture
Features
Functional Description
• Separate independent read and write data ports
— Supports concurrent transactions
• 167-MHz clock for high bandwidth
— 2.5-ns clock-to-valid access time
• Two-word burst on all accesses
• Double data rate (DDR) interfaces on both read and
write ports (data transferred at 333 MHz) @ 167 MHz
• Two input clocks (K and K)[1] for precise DDR timing
— SRAM uses rising edges only
• Two output clocks (C and C) account for clock skew
and flight time mismatches
• Single multiplexed address input bus latches address
inputs for both read and write ports
• Separate port selects for depth expansion
• Synchronous internally self-timed writes
• 2.5V core power supply with HSTL inputs and outputs[1]
• 13 × 15 mm – 1.0-mm pitch FBGA package, 165 ball
(11 × 15 matrix)
• Variable-drive HSTL output buffers
• Expanded HSTL output voltage (1.4V–1.9V)
• JTAG interface
• Variable impedance HSTL
The CY7C1302V25 is a 2.5V synchronous pipelined SRAM
with QDR™ architecture. QDR architecture consists of two
separate ports to access the memory array. The Read port has
dedicated Data Outputs to support Read operations and the
Write Port has dedicated Data inputs to support Write operations. Access to each port is accomplished through a common
address bus. The Read address is latched on the rising edge
of the K[1] clock and the Write address is latched on the rising
edge of K[1] clock. QDR has separate data inputs and data
outputs to completely eliminate the need to “turn-around” the
data bus required with common I/O devices. Accesses to the
CY7C1302V25 Read and Write ports are completely
independent of one another. All accesses are initiated
synchronously on the rising edge of the positive input clock
(K)[1]. In order to maximize data throughput, both Read and
Write ports are equipped with DDR interfaces. Therefore, data
can be transferred into the device on every rising edge of both
input clocks (K and K)[1] and out of the device on every rising
edge of the output clock (C and C) thereby maximizing performance while simplifying system design.
Depth expansion is accomplished with Port Select inputs for
each port. This allows the ports to operate independently.
All synchronous inputs pass through input registers controlled
by the input clocks (K and K)[1]. All data outputs pass through
output registers controlled by the output clocks (C or C). Writes
occur with on-chip synchronous self-timed write circuitry.
Logic Block Diagram
D[17:0]
18
Write Add. Decode
Address
Register
Al17:0]
18
K[1]
K[1]
CLK
Gen.
256Kx18
Memory
Array
Write
Data Reg
Read Add. Decode
Write
Data Reg
256Kx18
Memory
Array
Address
Register
Control
Logic
Read Data Reg.
36
Vref
WPS
BWS0
18
Reg.
Control
Logic
18
Reg. 18
Reg.
BWS1
18
A[17:0]
18
RPS
C
C
18
Q[17:0]
Note:
1. K and K inputs require VIH to be greater than VREF + 0.5V and VIL to be less than VREF – 0.5V. This is a subset of JEDEC standards for HSTL I/Os.
Cypress Semiconductor Corporation
Document #: 38-05260 Rev. *B
•
3901 North First Street
•
San Jose, CA 95134
•
408-943-2600
Revised November 12, 2002
CY7C1302V25
Selection Guide
7C1302V25-167
7C1302V25-133
7C1302V25-100
Maximum Operating Frequency (MHz)
167
133
100
Maximum Operating Current (mA)
550
450
330
Pin Configuration
CY7C1302V25
(Top View)
1
2
3
4
5
6
7
8
9
10
11
A
NC
Gnd/
144M
NC/ 36M
WPS
BWS1
K
NC
RPS
NC/ 18M
Gnd/
72M
NC
B
NC
Q9
D9
A
NC
K
BWS0
A
NC
NC
Q8
C
NC
NC
D10
VSS
A
A
A
VSS
NC
Q7
D8
D
NC
D11
Q10
VSS
VSS
VSS
VSS
VSS
NC
NC
D7
E
NC
NC
Q11
VDDQ
VSS
VSS
VSS
VDDQ
NC
D6
Q6
F
NC
Q12
D12
VDDQ
VDD
VSS
VDD
VDDQ
NC
NC
Q5
G
NC
D13
Q13
VDDQ
VDD
VSS
VDD
VDDQ
NC
NC
D5
H
NC
VREF
VDDQ
VDDQ
VDD
VSS
VDD
VDDQ
VDDQ
VREF
ZQ
J
NC
NC
D14
VDDQ
VDD
VSS
VDD
VDDQ
NC
Q4
D4
K
NC
NC
Q14
VDDQ
VDD
VSS
VDD
VDDQ
NC
D3
Q3
L
NC
Q15
D15
VDDQ
VSS
VSS
VSS
VDDQ
NC
NC
Q2
M
NC
NC
D16
VSS
VSS
VSS
VSS
VSS
NC
Q1
D2
N
NC
D17
Q16
VSS
A
A
A
VSS
NC
NC
D1
P
NC
NC
Q17
A
A
C
A
A
NC
D0
Q0
R
TDO
TCK
A
A
A
C
A
A
A
TMS
TDI
Pin Definitions
Name
I/O
Description
D[17:0]
InputSynchronous
Data input signals, sampled on the rising edge of K and K[1] clocks during valid
write operations.
WPS
InputSynchronous
Write Port Select, active LOW. Sampled on the rising edge of the K[1] clock. When
asserted active, a write operation is initiated. Deasserting will deselect the Write port.
Deselecting the Write port will cause D[17:0] to be ignored.
BWS0, BWS1
InputSynchronous
Byte Write Select 0 and 1, active LOW. Sampled on the rising edge of the K and K[1]
clocks during write operations. Used to select which byte is written into the device during
the current portion of the write operations. Bytes not written remain unaltered. BWS0
controls D[8:0] while BWS1 controls D[17:9]. BWS0 and BWS1 are sampled on the same
edge as D[17:0]. Deselecting a Byte Write Select will cause the corresponding byte of
data to be ignored and not written into the device.
A[17:0]
InputSynchronous
Address Inputs. Sampled on the rising edge of both the K and K[1] clocks during active
read and write operations. These address inputs are multiplexed for both Read and
Write operations. The Read address is latched on the rising edge of the positive input
clock (K)[1] and the Write address is latched on the rising edge of the negative input
clock (K)[1]. Internally, the device is organized 256K × 36. Therefore, only 18 address
inputs are needed to access the entire memory array. These inputs are ignored when
the appropriate port is deselected. Therefore, on the rising edge of the positive input
clock (K)[1], these inputs are ignored if the Read port is deselected. These inputs are
ignored on the rising edge of the negative input clock (K)[1] when the Write port is
deselected.
Document #: 38-05260 Rev. *B
Page 2 of 19
CY7C1302V25
Pin Definitions (continued)
Name
I/O
Description
Q[17:0]
OutputsSynchronous
Data Output Signals. These pins drive out the requested data during a Read operation.
Valid data is driven out on the rising edge of both the C and C clocks during Read
operations. When the Read port is deselected, Q[17:0] are automatically three-stated.
RPS
InputSynchronous
Read Port Select, active LOW. Sampled on the rising edge of positive input clock (K)[1].
When active, a Read operation is initiated. Deasserting will cause the Read port to be
deselected. When deselected, the pending access is allowed to complete and the output
drivers are automatically three-stated following the next rising edge of the C clock. The
CY7C1302V25 is organized internally as 256K × 36. Each read access consists of a
burst of two sequential 18-bit transfers.
C
InputClock
Positive Output Clock Input. C is used in conjunction with C to clock out the Read
data from the device. C and C can be used together to deskew the flight times of various
devices on the board back to the controller. See application example for further details.
C
InputClock
Negative Output Clock Input. C is used in conjunction with C to clock out the Read
data from the device. C and C can be used together to deskew the flight times of various
devices on the board back to the controller. See application example for further details.
K
InputClock
Positive Input Clock Input. The rising edge of K is used to capture synchronous inputs
to the device and to drive out data through Q[17:0] when in single clock mode. All
accesses are initiated on the rising edge of K.[1]
K
InputClock
Negative Input Clock Input. K is used to capture synchronous inputs being presented
to the device and to drive out data through Q[17:0] when in single clock mode.[1]
ZQ
Input
Output Impedance Matching Input. This input is used to tune the device outputs to
the system data bus impedance. Q[17:0] output impedance are set to 0.2 x RQ, where
RQ is a resistor connected between ZQ and ground. Alternately, this pin can be
connected directly to VDD, which enables the minimum impedance mode. This pin
cannot be connected directly to GND or left unconnected.
TDO
Output
TCK
Input
TCK pin for JTAG.
TDI
Input
TDI pin for JTAG.
TMS
Input
TMS pin for JTAG.
NC/18M
Input
Address expansion for 18M. This is not connected to the die.
NC/36M
Input
Address expansion for 36M. This is not connected to the die.
GND/72M
Input
Address expansion for 72M. This should be tied LOW on the CY7C1302V25.
GND/144M
Input
Address expansion for 144M. This should be tied LOW on the CY7C1302V25.
NC
TDO for JTAG.
Not Connect Pins. These are not connected to the die.
VREF
InputReference
Reference Voltage Input. Static input used to set the reference level for HSTL inputs
and Outputs as well as A/C measurement points.
VDD
Power Supply
Power supply inputs to the core of the device. Should be connected to 2.5V power
supply.
VSS
Ground
VDDQ
Power Supply
Ground for the device. Should be connected to ground of the system.
Power supply inputs for the outputs of the device. Should be connected to 1.5V
power supply.
Introduction
Functional Overview
The CY7C1302V25 is a Synchronous Pipelined Burst SRAM
equipped with both a Read Port and a Write Port. The Read
port is dedicated to Read operations and the Write Port is
dedicated to Write operations. Data flows into the SRAM
through the Write port and out through the Read Port. The
CY7C1302V25 multiplexes the address inputs in order to
Document #: 38-05260 Rev. *B
minimize the number of address pins required. The
CY7C1302V25 latches the Read address on the rising edge
of the positive input clock (K)[1] and latches the Write address
on the rising edge of the negative input clock (K)[1]. By having
separate Read and Write ports, the CY7C1302V25 completely
eliminates the need to “turn-around” the data bus and avoids
any possible data contention, thereby simplifying system
design.
Page 3 of 19
CY7C1302V25
Accesses for both ports are initiated by the positive input clock
(K)[1]. All synchronous input timing is referenced from the
rising edge of the input clocks (K and K)[1] and all output timing
is referenced to the output clocks (C and C) or (K and K)[1]
when in single clock mode.
All synchronous data inputs (D[17:0]) inputs pass through input
registers controlled by the input clocks (K and K)[1]. All
synchronous data outputs (Q[17:0]) outputs pass through
output registers controlled by the rising edge of the output
clocks (C and C)
All synchronous control (RPS, WPS, BWS0, BWS1) inputs
pass through input registers controlled by the rising edge of
the input clocks (K and K)[1].
Read Operations
Read operations are initiated by asserting RPS active at the
rising edge of the positive input clock (K)[1]. The address
presented to A[17:0] is stored in the Read address register.
Because the CY7C1302V25 is a 36-bit memory, it will access
two 18-bit data words with each read operation. Following the
next K[1] clock rise the data is available to be latched out of the
device, triggered by the C clock. On the following C clock rise
the corresponding lower order word of data is driven onto the
Q[17:0]. On the subsequent rising edge of C the higher order
data word is driven onto the Q[17:0]. The requested data will be
valid 2.5 ns from the rising edge of the output clock (C or C,
167-MHz device). With the separate Input and Output ports
and the internal logic determining when the device should
drive the data bus, the QDR architecture has eliminated the
need for an output enable input to control the state of the
output drivers.
Read accesses can be initiated on every rising edge of the
Positive Input Clock (K)[1]. Doing so will pipeline the data flow
such that data is transferred out of the device on every rising
edge of the output clocks (C and C). The CY7C1302V25 will
deliver the most recent data for the address location being
accessed. This includes forwarding data when a Read and
Write transactions to the same address location are initiated
on the same clock rise.
When the read port is deselected, the CY7C1302V25 will first
complete the pending read transactions. Synchronous internal
circuitry will automatically three-state the outputs following the
next rising edge of the Positive Output Clock (C). This will
allow for a seamless transition between devices without the
insertion of wait states.
The CY7C1302V25 is equipped with internal logic that
synchronously controls the state of the output drivers. The
logic inside the device determines when the output drivers
need to be active or inactive. This advanced logic eliminates
the need for an Asynchronous Output Enable (OE) since the
device will automatically enable/disable the output drivers
during the proper cycles. The CY7C1302V25 will automatically power-up in a deselected state with the outputs in a three
state condition.
Write Operations
Write operations are initiated by asserting WPS active at the
rising edge of the Positive Input Clock (K)[1]. On the same
clock rise (K)[1] the data presented to D[17:0] is stored into the
lower 18-bit Write Data register provided BWS[1:0] are both
asserted active. On the subsequent rising edge of the
Document #: 38-05260 Rev. *B
Negative Input Clock (K)[1], the information presented to A[17:0]
is latched and stored in the Write Address Register and the
information presented to D[17:0] is also stored into the upper
18-bit Write Data Register provided BWS[1:0] are both
asserted active. The 36 bits of data are then written into the
memory array at the specified location.
Write accesses can be initiated on every rising edge of the
positive clock. Doing so will pipeline the data flow such that 18
bits of data can be transferred into the device on every rising
edge of the input clocks (K and K)[1].
Byte Write operations are supported by the CY7C1302V25. A
write operation is initiated by selecting the write port using
WPS. The bytes that are written are determined by BWS0 and
BWS1 which are sampled with each set of 18-bit data word.
Asserting the appropriate Byte Write Select input during the
data portion of a write will allow the data being presented to be
latched and written into the device. Deasserting the Byte Write
Select input during the data portion of a write will allow the data
stored in the device for that byte to remain unaltered. This
feature can be used to simplify READ/MODIFY/WRITE operations to a Byte Write operation.
When deselected, the write port will ignore all inputs.
Single Clock Mode
The CY7C1302V25 can be used with a single clock mode. In
this mode the device will recognize only the pair of input clocks
(K and K)[1] that control both the input and output registers.
This operation is identical to the operation if the device had
zero skew between the K/K[1] and C/C clocks. All timing
parameters remain the same in this mode. To use this mode
of operation, the user must tie C and C to VDD. During
power-up, the device will sense the single clock input and
operating in either single clock or double clock mode. The
clock mode should not be changed during device operation.
Concurrent Transactions
The Read and Write ports on the CY7C1302V25 operate
completely independently of one another. Since each port
latches the address inputs on different clock edges, the user
can read or write to any location, regardless of the transaction
on the other port. Should the Read and Write ports access the
same location on the rising edge of the positive input clock, the
information presented to the D[17:0] will be forwarded to the
Q[17:0] such that no latency is required to access valid data
when operated at or below 100 MHz. Coherency is conducted
on cycle boundaries. Once the second word of data is latched
into the device, the write operation is considered completed.
At this point, any access to that address location will receive
that data until altered by a subsequent Write operation.
Coherency is not maintained for Write operations initiated in
the cycle after a Read. The data forwarding feature is not
available for operation above 100 MHz.
Depth Expansion
The CY7C1302V25 has a Port Select input for each port. This
allows for easy depth expansion. Both Port Selects are
sampled on the rising edge of the Positive Input Clock only
(K)[1]. Each port select input can deselect the specified port.
Deselecting a port will not affect the other port. All pending
transactions (Read and Write) will be completed prior to the
device being deselected.
Page 4 of 19
CY7C1302V25
Programmable Impedance
An external resistor, RQ, must be connected between the ZQ
pin on the SRAM and VSS to allow the SRAM to adjust its
output driver impedance. The value of RQ must be 5X the
value of the intended line impedance driven by the SRAM, The
allowable range of RQ to guarantee impedance matching with
a tolerance of ±10% is between 175Ω and 350Ω, with
VDDQ=1.5V. The output impedance is adjusted every 1024
cycles to adjust for drifts in supply voltage and temperature.
Application Example
Memory
Controller
Q
Din
Add.
Cntr.
CLK/CLK (input)
D
18
18
Q
C/C
K/K
Cntr.
Add.
18
Q
C/C
K/K[1]
Cntr.
Add.
D
VTERM = VREF/2
SRAM #4
SRAM #1
R = 50Ω
18
72
72
2
CLK/CLK (output)
2
R = 50Ω
VT = VREF/2
Truth Table
[2, 3, 4, 5, 6]
Address
Used
RPS
K[1]
Deselected
–
H
L–H
Read Port is deselected. Outputs three-state following next rising edge of
negative input clock (K)[1] if in single clock mode, or C if using C and C as
the output clocks.
Begin Read
External
L
L–H
Read operation initiated. Addresses are stored in the Read Address Register.
Following the next K[1] clock rise the first (lower order) 18-bit word will be
available to be driven out onto Q[17:0] gated by the rising edge of the output
clock C. On the subsequent rising edge of the negative output clock (C) the
second (higher order) 18-bit word is driven out onto Q[17:0].
Deselected
–
H
L–H
WPS deselects Write Port. All Write Port inputs are ignored during this clock
rise and the subsequent rising edge of the negative input clock (K)[1].
L
L–H
Write operation initiated. The information presented to D[17:0] is stored in the
Write Data Register. On the subsequent rising edge of the negative input
clock (K)[1] the device will latch the addresses presented to A[17:0] and the
data presented to D[17:0]]. The entire 36 bits of information will then be written
into the memory array. See Write Description table for byte write information.
BWS0
BWS1
K[1]
K[1]
Comments
Write Initiated
L
L
L–H
–
Both bytes (D[17:0]) are written into the lower order 18-bit write buffer
device during this portion of a write operation.
Write Completed –
Write initiated on
previous K[1] clock rise
L
L
–
L–H
Both bytes (D[17:0]) are written into the higher order 18-bit write buffer
device during this portion of a write operation. The contents of the
entire 36-bits write buffer are written into the memory array.
Operation
Begin Write
External on
next rising
edge of K[1]
Write Descriptions
Operation
Comments
[7]
Notes:
2. X = ”Don't Care,” H = Logic HIGH, L = Logic LOW.
3. Device will power-up deselected and the outputs in a three-state condition.
4. BWS0 and BWS1 asserted active LOW during all cycles. For byte write operations, see Write Description Table.
[1]
5. Data inputs are registered at (K and K) rising edges. Data outputs are delivered on C and C rising edges, except when in single clock mode.
6. It is recommended that K = K# and C = C# when clock is stopped. This is not essential, but permits most rapid restart by overcoming transmission line charging
symmetrically.
7. Assumes a Write cycle was initiated per the Write Port Cycle Description Truth Table. BWS0 and BWS1 can be altered on different portions of a write cycle, as
long as the set-up and hold requirements are achieved.
Document #: 38-05260 Rev. *B
Page 5 of 19
CY7C1302V25
Write Descriptions (continued)[7]
BWS0
BWS1
K[1]
K[1]
Comments
Write Initiated
L
H
L–H
–
Only Byte 0 (D[8:0]) is written into the lower order 18-bit write buffer of
the device during this portion of a write operation. Byte 1 (D[17:9])
remains unaltered.
Write Completed –
Write initiated on
previous K[1] clock rise
L
H
–
L–H
Only Byte 0 (D[8:0]) is written into the higher order 18-bit write buffer
of the device during this portion of a write operation. Byte 1 (D[17:9])
remains unaltered. Byte 0 is then written into the memory array.
Write Initiated
H
L
L–H
–
Only Byte 1 (D[17:9]) is written into the lower order 18-bit write buffer
of the device during this portion of a write operation. Byte 0 (D[8:0])
remains unaltered
Write Completed –
Write initiated on
previous K[1] clock rise
H
L
–
L–H
Only Byte 1 (D[17:9]) is written into the higher order 18-bit write buffer
of the device during this portion of a write operation. Byte 0(D[8:0])
remains unaltered. Byte 0 is then written into the memory array.
Write — NO–OP
H
H
L–H
–
No data is written into the device during this portion of a write
operation.
Write — NO–OP
H
H
–
L–H
No data is written into the device during this portion of a write
operation.
Operation
IEEE 1149.1 Serial Boundary Scan
(JTAG–FBGA only)
The CY7C1302V25 incorporates a serial boundary scan test
access port (TAP) in the FBGA package only. The TQFP
package does not offer this functionality. This port operates in
accordance with IEEE Standard 1149.1-1900, but does not
have the set of functions required for full 1149.1 compliance.
These functions from the IEEE specification are excluded
because their inclusion places an added delay in the critical
speed path of the SRAM. Note that the TAP controller
functions in a manner that does not conflict with the operation
of other devices using 1149.1 fully compliant TAPs. The TAP
operates using JEDEC standard 2.5V I/O logic levels.
Disabling the JTAP Feature
It is possible to operate the SRAM without using the JTAG
feature. To disable the TAP controller, TCK must be tied LOW
(VSS) to prevent clocking of the device. TDI and TMS are internally pulled up and may be unconnected. They may alternately
be connected to VDD through a pull-up resistor. TDO should
be left unconnected. Upon power-up, the device will come up
in a reset state which will not interfere with the operation of the
device.
Test Access Port (TAP) – Test Clock
The test clock is used only with the TAP controller. All inputs
are captured on the rising edge of TCK. All outputs are driven
from the falling edge of TCK.
Test Mode Select
The TMS input is used to give commands to the TAP controller
and is sampled on the rising edge of TCK. It is allowable to
leave this pin unconnected if the TAP is not used. The pin is
pulled up internally, resulting in a logic HIGH level.
Test Data-In (TDI)
The TDI pin is used to serially input information into the
registers and can be connected to the input of any of the
registers. The register between TDI and TDO is chosen by the
instruction that is loaded into the TAP instruction register. For
Document #: 38-05260 Rev. *B
information on loading the instruction register, see the TAP
Controller State Diagram. TDI is internally pulled up and can
be unconnected if the TAP is unused in an application. TDI is
connected to the Most Significant Bit (MSB) on any register.
Test Data-Out (TDO)
The TDO output pin is used to serially clock data-out from the
registers. The output is active depending upon the current
state of the TAP state machine (see TAP Controller State
Diagram). The output changes on the falling edge of TCK.
TDO is connected to the Least Significant Bit (LSB) of any
register.
Performing a TAP Reset
A RESET is performed by forcing TMS HIGH (VDD) for five
rising edges of TCK. This RESET does not affect the operation
of the SRAM and may be performed while the SRAM is
operating. At power-up, the TAP is reset internally to ensure
that TDO comes up in a High-Z state.
TAP Registers
Registers are connected between the TDI and TDO pins and
allow data to be scanned into and out of the SRAM test
circuitry. Only one register can be selected at a time through
the instruction register. Data is serially loaded into the TDI pin
on the rising edge of TCK. Data is output on the TDO pin on
the falling edge of TCK.
Instruction Register
Three-bit instructions can be serially loaded into the instruction
register. This register is loaded when it is placed between the
TDI and TDO pins as shown in the TAP Controller Block
Diagram. Upon power-up, the instruction register is loaded
with the IDCODE instruction. It is also loaded with the IDCODE
instruction if the controller is placed in a reset state as
described in the previous section.
When the TAP controller is in the Capture-IR state, the two
least significant bits are loaded with a binary “01” pattern to
allow for fault isolation of the board level serial test data path.
Page 6 of 19
CY7C1302V25
Bypass Register
To save time when serially shifting data through registers, it is
sometimes advantageous to skip certain chips. The bypass
register is a single-bit register that can be placed between TDI
and TDO pins. This allows data to be shifted through the
SRAM with minimal delay. The bypass register is set LOW
(VSS) when the BYPASS instruction is executed.
Boundary Scan Register
The boundary scan register is connected to all the input and
output pins on the SRAM. Several no connect (NC) pins are
also included in the scan register to reserve pins for higher
density devices.
The boundary scan register is loaded with the contents of the
RAM Input and Output ring when the TAP controller is in the
Capture-DR state and is then placed between the TDI and
TDO pins when the controller is moved to the Shift-DR state.
The EXTEST, SAMPLE/PRELOAD and SAMPLE Z instructions can be used to capture the contents of the Input and
Output ring.
The Boundary Scan Order tables show the order in which the
bits are connected. Each bit corresponds to one of the bumps
on the SRAM package. The MSB of the register is connected
to TDI, and the LSB is connected to TDO.
Identification (ID) Register
The ID register is loaded with a vendor-specific, 32-bit code
during the Capture-DR state when the IDCODE command is
loaded in the instruction register. The IDCODE is hardwired
into the SRAM and can be shifted out when the TAP controller
is in the Shift-DR state. The ID register has a vendor code and
other information described in the Identification Register
Definitions table.
TAP Instruction Set
Eight different instructions are possible with the three-bit
instruction register. All combinations are listed in the
Instruction Codes table. Three of these instructions are listed
as RESERVED and should not be used. The other five instructions are described in detail below.
The TAP controller used in this SRAM is not fully compliant to
the 1149.1 convention because some of the mandatory 1149.1
instructions are not fully implemented. The TAP controller
cannot be used to load address, data or control signals into the
SRAM and cannot preload the Input or output buffers. The
SRAM does not implement the 1149.1 commands EXTEST or
INTEST or the PRELOAD portion of SAMPLE/PRELOAD;
rather it performs a capture of the Inputs and Output ring when
these instructions are executed.
Instructions are loaded into the TAP controller during the
Shift-IR state when the instruction register is placed between
TDI and TDO. During this state, instructions are shifted
through the instruction register through the TDI and TDO pins.
To execute the instruction once it is shifted in, the TAP
controller needs to be moved into the Update-IR state.
EXTEST
EXTEST is a mandatory 1149.1 instruction which is to be
executed whenever the instruction register is loaded with all
0s. EXTEST is not implemented in the CY7C1304 TAP
controller, and therefore this device is not compliant to the
1149.1 standard.
Document #: 38-05260 Rev. *B
The TAP controller does recognize an all-0 instruction. When
an EXTEST instruction is loaded into the instruction register,
the SRAM responds as if a SAMPLE/PRELOAD instruction
has been loaded.
IDCODE
The IDCODE instruction causes a vendor-specific, 32-bit code
to be loaded into the instruction register. It also places the
instruction register between the TDI and TDO pins and allows
the IDCODE to be shifted out of the device when the TAP
controller enters the Shift-DR state. The IDCODE instruction
is loaded into the instruction register upon power-up or
whenever the TAP controller is given a test logic reset state.
SAMPLE Z
The SAMPLE Z instruction causes the boundary scan register
to be connected between the TDI and TDO pins when the TAP
controller is in a Shift-DR state.
SAMPLE/PRELOAD
SAMPLE/PRELOAD is a 1149.1 mandatory instruction. The
PRELOAD portion of this instruction is not implemented, so
the CY7C1302V25 TAP controller is not fully 1149.1compliant.
When the SAMPLE/PRELOAD instruction is loaded into the
instruction register and the TAP controller is in the Capture-DR
state, a snapshot of data on the inputs and output pins is
captured in the boundary scan register.
The user must be aware that the TAP controller clock can only
operate at a frequency up to 10 MHz, while the SRAM clock
operates more than an order of magnitude faster. Because
there is a large difference in the clock frequencies, it is
possible that during the Capture-DR state, an input or output
will undergo a transition. The TAP may then try to capture a
signal while in transition (metastable state). This will not harm
the device, but there is no guarantee as to the value that will
be captured. Repeatable results may not be possible.
To guarantee that the boundary scan register will capture the
correct value of a signal, the SRAM signal must be stabilized
long enough to meet the TAP controller’s capture set-up plus
hold times (tCS and tCH). The SRAM clock input might not be
captured correctly if there is no way in a design to stop (or
slow) the clock during a SAMPLE/PRELOAD instruction. If this
is an issue, it is still possible to capture all other signals and
simply ignore the value of the K[1], K[1], C and C captured in
the boundary scan register.
Once the data is captured, it is possible to shift out the data by
putting the TAP into the Shift-DR state. This places the
boundary scan register between the TDI and TDO pins.
Note that since the PRELOAD part of the command is not
implemented, putting the TAP into the Update-DR state while
performing a SAMPLE/PRELOAD instruction will have the
same effect as the Pause-DR command.
Bypass
When the BYPASS instruction is loaded in the instruction
register and the TAP is placed in a Shift-DR state, the bypass
register is placed between the TDI and TDO pins. The
advantage of the BYPASS instruction is that it shortens the
boundary scan path when multiple devices are connected
together on a board.
Page 7 of 19
CY7C1302V25
Reserved
These instructions are not implemented but are reserved for
future use. Do not use these instructions.
TAP Controller State Diagram
1[8]
TEST-LOGIC
RESET
0
0
TEST-LOGIC/
IDLE
1
1
1
SELECT
DR-SCAN
SELECT
IR-SCAN
0
0
1
1
CAPTURE-DR
CAPTURE-DR
0
0
0
SHIFT-DR
0
SHIFT-IR
1
1
1
EXIT1-DR
1
EXIT1-IR
0
0
PAUSE-DR
0
0
PAUSE-IR
1
1
0
0
EXIT2-DR
EXIT2-IR
1
1
UPDATE-DR
1
0
UPDATE-IR
1
0
Note:
8. The 0/1 next to each state represents the value at TMS at the rising edge of TCK.
Document #: 38-05260 Rev. *B
Page 8 of 19
CY7C1302V25
TAP Controller Block Diagram
0
Bypass Register
Selection
Circuitry
2
TDI
1
0
Selection
Circuitry
TDO
Instruction Register
31 30 29
.
.
2
1
0
Identification Register
.
68 .
.
.
2
1
0
Boundary Scan Register
TCK
TMS
TAP Controller
TAP Electrical Characteristics Over the Operating Range[9, 10, 11]
Parameter
Description
Test Conditions
Min.
VOH1
Output HIGH Voltage
IOH = −2.0 mA
1.7
VOH2
Output HIGH Voltage
IOH = −100 µA
2.1
VOL1
Output LOW Voltage
IOL = 2.0 mA
VOL2
Output LOW Voltage
IOL = 100 µA
VIH
Input HIGH Voltage
VIL
Input LOW Voltage
IX
Input and Output Load Current
GND ≤ VI ≤ VDDQ
TAP AC Switching Characteristics Over the Operating Range
Parameter
Description
Max.
Unit
V
V
0.7
V
0.2
V
1.7
VDD + 0.3
V
–0.3
0.7
V
−5
5
µA
[12, 13]
Min.
Max.
100
Unit
tTCYC
TCK Clock Cycle Time
ns
tTF
TCK Clock Frequency
tTH
TCK Clock HIGH
40
ns
tTL
TCK Clock LOW
40
ns
TMS Set-up to TCK Clock Rise
10
ns
10
MHz
Set-up Times
tTMSS
Notes:
9. All voltage referenced to ground.
10. Overshoot: VIH(AC) < VDD+1.5V for t < tTCYC/2; undershoot: VIL(AC) < 0.5V for t < tTCYC/2; power-up: VIH < 2.6V and VDD < 2.4V and VDDQ < 1.4V for t < 200 ms.
11. These characteristics pertain to the TAP inputs (TMS, TCK, TDI and TDO). Parallel load levels are specified in the Electrical Characteristics Table.
12. Test conditions are specified using the load in TAP AC test conditions. tR/tF= 1 ns.
13. tCS and tCH refer to the set-up and hold time requirements of latching data from the boundary scan register.
tTDIS
TDI Set-up to TCK Clock Rise
Document #: 38-05260 Rev. *B
10
ns
Page 9 of 19
CY7C1302V25
TAP AC Switching Characteristics Over the Operating Range (continued)[12, 13]
Parameter
tCS
Description
Min.
Max.
Unit
Capture Set-up to TCK Rise
10
ns
tTMSH
TMS Hold after TCK Clock Rise
10
ns
tTDIH
TDI Hold after Clock Rise
10
ns
tCH
Capture Hold after Clock Rise
10
ns
Hold Times
Output Times
tTDOV
TCK Clock LOW to TDO Valid
tTDOX
TCK Clock LOW to TDO Invalid
20
0
ns
ns
TAP Timing and Test Conditions[12]
1.25V
50Ω
ALL INPUT PULSES
TDO
2.5V
Z0 =50Ω
1.25V
CL =20 pF
0V
GND
tTH
(a)
tTL
Test Clock
TCK
tTCYC
tTMSS
tTMSH
Test Mode Select
TMS
tTDIS
tTDIH
Test Data-In
TDI
Test Data-Out
TDO
tTDOX
Document #: 38-05260 Rev. *B
tTDOV
Page 10 of 19
CY7C1302V25
Identification Register Definitions
Instruction Field
Value (CY7C1302V25)
Revision Number (31:29)
000
Cypress Device ID (28:12)
01011010010010110
Cypress JEDEC ID (11:1)
00000110100
ID Register Presence (0)
1
Description
Version number.
Defines the type of SRAM.
Allows unique identification of SRAM vendor.
Indicate the presence of an ID register.
Scan Register Sizes
Register Name
Bit Size
Instruction
3
Bypass
1
ID
32
Boundary Scan
69
Instruction Codes
Code
Description
EXTEST
Instruction
000
Captures the Input/Output ring contents. Places the boundary scan register between the TDI
and TDO. This instruction is not 1149.1 compliant. The EXTEST command implemented by
the CY7C1302V25 device will NOT place the output buffers into a High-Z condition. If the
output buffers need to be High-Z condition, this can be accomplished by deselecting the
Read port.
IDCODE
001
Loads the ID register with the vendor ID code and places the register between TDI and TDO.
This operation does not affect SRAM operation.
SAMPLE Z
010
Captures the Input/Output contents. Places the boundary scan register between TDI and TDO.
The SAMPLEZ command implemented by the CY7C1302V25 device will place the output
buffers into a High-Z condiditon.
RESERVED
011
Do Not Use: This instruction is reserved for future use.
SAMPLE/PRELOAD
100
Captures the Input/Output ring contents. Places the boundary scan register between TDI and
TDO. Does not affect the SRAM operation. This instruction does not implement 1149.1 preload
function and is therefore not 1149.1 compliant.
RESERVED
101
Do Not Use: This instruction is reserved for future use.
RESERVED
110
Do Not Use: This instruction is reserved for future use.
BYPASS
111
Places the bypass register between TDI and TDO. This operation does not affect SRAM
operation.
Boundary Scan Order (#1 exits device first)
Bit #
Signal Name
Bump ID
Boundary Scan Order (#1 exits device first) (continued)
Bit #
Signal Name
Bump ID
1
C
6R
14
D2
11M
2
C
6P
15
Q2
11L
3
A
6N
16
D3
10K
4
A
7P
17
Q3
11K
5
A
7N
18
D4
11J
6
A
7R
19
ZQ
11H
7
A
8R
20
Q4
10J
8
A
8P
21
D5
11G
9
A
9R
22
Q5
11F
10
D0
10P
23
D6
10E
11
Q0
11P
24
Q6
11E
12
D1
11N
25
D7
11D
13
Q1
10M
26
Q7
10C
Document #: 38-05260 Rev. *B
Page 11 of 19
CY7C1302V25
Boundary Scan Order (#1 exits device first) (continued)
Bit #
Signal Name
Bump ID
27
D8
11C
28
Q8
11B
29
Reserved
12A (Don’t Care)
30
GND/72M
10A
31
NC/18M(1)
9A (Read as 1, 18 Mb)
32
A
8B
33
A
7C
34
A
6C
35
RPS
8A
36
BWS0
7B
37
K
6B
38
K
6A
39
BWS1
5A
40
WPS
4A
41
A
5C
42
A
4B
43
NC/36M(1)
3A
44
GND/144M
2A
45
Reserved
1A (Don’t Care)
46
D9
3B
47
Q9
2B
48
D10
3C
49
Q10
3D
50
D11
2D
51
Q11
3E
52
D12
3F
53
Q12
2F
54
D13
2G
55
Q13
3G
56
D14
3J
57
Q14
3K
58
D15
3L
59
Q15
2L
60
D16
3M
61
Q16
3N
62
D17
2N
63
Q17
3P
64
A
3R
65
A
4R
66
A
4P
67
A
5P
68
A
5N
69
A
5R
Document #: 38-05260 Rev. *B
Page 12 of 19
CY7C1302V25
DC Input Voltage[14] .............................–0.5V to VDDQ + 0.5V
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.)
Storage Temperature ....................................–65C to +150C
Ambient Temperature with
Power Applied................................................–55C to +125C
Current into Outputs (LOW)......................................... 20 mA
Static Discharge Voltage.......................................... > 2001V
(per MIL-STD-883, Method 3015)
Latch-up Current.................................................... > 200 mA
Operating Range
Supply Voltage on VDD Relative to GND........ –0.5V to +3.6V
DC Voltage Applied to Outputs
in High-Z State[14] ............................... –0.5V to VDDQ + 0.5V
Range
Com’l
Ambient
Temperature[15]
VDD
VDDQ
0°C to +70°C
2.5 ±100 mV
1.4V to 1.9V
Electrical Characteristics Over the Operating Range
Parameter
Description
Test Conditions
VDD
Power Supply Voltage
VDDQ
I/O Supply Voltage
VOH
Output HIGH Voltage
IOH = −2.0 mA, nominal impedance
VOL
Output LOW Voltage
IOL = 2.0 mA, nominal impedance
VIH[1]
Input HIGH Voltage
Unit
2.6
V
1.4
1.9
V
VDDQ/2 + 0.3
VDDQ
V
VSS
VDDQ/2 – 0.3
V
VDDQ+0.3
V
–0.3
VREF – 0.1
V
–5
5
µA
–5
5
µA
0.68
0.9
V
VDD = Max., IOUT = 0 mA, 6.0-ns cycle, 167 MHz
f = fMAX = 1/tCYC
7.5-ns cycle, 133 MHz
550
mA
450
mA
10-ns cycle, 100 MHz
330
mA
Max. VDD, Both Ports
6.0-ns cycle, 167 MHz
Deselected, VIN ≥ VIH or 7.5-ns cycle, 133 MHz
VIN ≤ VIL f = fMAX = 1/tCYC,
10-ns cycle, 100 MHz
Inputs Static
100
mA
80
mA
60
mA
Input LOW
IX
Input Load Current
IOZ
Output Leakage Current GND ≤ VI ≤ VDDQ, Output Disabled
VREF
Input Reference Voltage Typical value = 0.75V
IDD
VDD Operating Supply
Voltage[14]
Automatic
Power-down
Current
Max.
2.4
VREF + 0.1
VIL[1]
ISB1
Min.
GND ≤ VI ≤ VDDQ
Capacitance[16]
Parameter
Description
CIN
Input Capacitance
CCLK
Clock Input Capacitance
CO
Output Capacitance
Test Conditions
TA = 25°C, f = 1 MHz,
VDD = 2.5V
VDDQ = 1.5V
Max.
Unit
TBD
pF
TBD
pF
TBD
pF
Notes:
14. Minimum voltage equals −2.0V for pulse duration less than 20 ns.
15. TA is the “Instant On” case temperature.
16. Tested initially and after any design or process change that may affect these parameters.
Document #: 38-05260 Rev. *B
Page 13 of 19
CY7C1302V25
AC Test Loads and Waveforms
VDDQ/2
VDDQ/2
VREF
VREF
OUTPUT
Z0 = 50Ω
Device
Under
Test
ZQ
RQ=
250Ω
RL = 50Ω
VREF = 0.75V
VDDQ/2
R = 50Ω
ALL INPUT PULSES
1.25V
0.75V
OUTPUT
Device
Under
Test ZQ
(a)
INCLUDING
JIG AND
SCOPE
5 pF
[17]
0.25V
RQ=
250Ω
(b)
Switching Characteristics Over the Operating Range[16, 17, 18, 19]
-167
Parameter
tCYC
Description
K[1] Clock and C Clock Cycle Time
C/C)[1]
Min.
Max.
-133
Min.
Max.
-100
Min.
Max.
Unit
6.0
7.5
10.0
ns
tKH
Input Clock (K/K and
HIGH
2.4
3.2
3.5
ns
tKL
Input Clock (K/K and C/C)[1] LOW
2.4
3.2
3.5
ns
tKHKH
K/K[1]
2.7
3.3
3.4
4.1
4.4
5.4
ns
tKHCH
K/K[1] Clock Rise to C/C clock Rise (rising edge to rising edge) 0.0
2.0
0.0
2.5
0.0
3.0
ns
tCO
C/C Clock Rise (or K/K[1] in single clock mode) to Data Valid[18]
2.5
3.0
ns
tDOH
Data Output Hold After Output C/C clock Rise (Active to Active) 1.2
K/K[1]
Clock Rise to
Clock Rise and C/C to C/C Rise
(rising edge to rising edge)
3.0
1.2
1.2
ns
Set-up Times
tSA
Address Set-up to Clock (K and K)[1] Rise
0.7
0.8
1.0
ns
tSC
Control Set-up to Clock (K and K)[1] Rise (RPS, WPS, BWS0,
BWS1)
0.7
0.8
1.0
ns
tSD
D[17:0] Set-up to Clock (K and K)[1] Rise
0.7
0.8
1.0
ns
tHA
Address Hold after Clock (K and K)[1] Rise
0.7
0.8
1.0
ns
tHC
Control Hold after Clock (K and K)[1] Rise (RPS, WPS, BWS0,
BWS1)
D[17:0] Hold after Clock (K and K)[1] Rise
0.7
0.8
1.0
ns
0.7
0.8
1.0
ns
Hold Times
tHD
Output Times
tCHZ
Clock (C and C) Rise to High-Z (Active to High-Z)[18, 19]
tCLZ
Clock (C and C) Rise to Low-Z[18, 19]
2.5
1.2
3.0
1.2
3.0
1.2
ns
ns
Notes:
17. Unless otherwise noted, test conditions assume signal transition time of 2 V/ns, timing reference levels of 0.75V, Vref = 0.75V, RQ = 250Ω, VDDQ = 1.5V, input
pulse levels of 0.25V to 1.25V, and output loading of the specified IOL/IOH and load capacitance shown in (a) of AC Test Loads.
18. tCHZ, tCLZ, are specified with a load capacitance of 5 pF as in (b) of AC Test Loads. Transition is measured ± 100 mV from steady-state voltage.
19. At any given voltage and temperature tCHZ is less than tCLZ and tCHZ is less than tCO.
Document #: 38-05260 Rev. *B
Page 14 of 19
CY7C1302V25
Switching Waveforms
Read/Deselect Sequence
tCYC
tKHKH
tKL
tKHKH
K[1]
tKH
tKL
K[1]
tKH
tSA
A[17:0]
A
B
tSC
C
tHA
tHC
RPS
Data Out
tCO
Q(A)
Q(A+1)
Q(B)
Q(B+1)
Q(C)
Q(C+1)
tCHZ tCLZ
tKHCH
C
tCO
tDOH
C
Device originally deselected.
Activity on the Write Port is unknown.
Document #: 38-05260 Rev. *B
tDOH
= DON’T CARE
= UNDEFINED
Page 15 of 19
CY7C1302V25
Switching Waveforms (continued)
Write/Deselect Sequence
tCYC
tKL
[1]
K
tKH
tKL
K[1]
tSA
A[17:0]
A
B
tSC
C
tHA
tHC
WPS
tSC
tHC
BWSx
Data In
D(A)
D(A+1)
D(B)
D(B+1)
D(C)
tSD
BWSx is both BWS0 and BWS1
C and C reference to Data Outputs and do not affect Writes. Activity on the
Read Port is unknown.
BWSx LOW=Valid, Byte writes allowed, see Byte write table for details.
= UNDEFINED
= DON’T CARE
Document #: 38-05260 Rev. *B
D(C+1)
tHD
Page 16 of 19
CY7C1302V25
Switching Waveforms (continued)
ead/Write/Deselect Sequence
K[1]
K[1]
A[17:0]
E
A
B
B
G
C
D
WPS
RPS
BWSx
D[17:0]
D(A)
D(A+1)
D(B)
D(B+1)
D(C)
D(C+1)
D(D)
D(D+1)
Write Data Forwarded
Q[17:0]
Q(E)
Q(E+1)
Q(B)
Q(B+1)
Q(G)
Q(G+1)
C
C
Read Port previously deselected.
Any port select can deselect the port.
BWS[1:0] both assumed active.
= DON’T CARE
= UNDEFINED
Ordering Information
Speed
(MHz)
Ordering Code
167
CY7C1302V25-167BZC/
133
CY7C1302V25-133BZC/
100
CY7C1302V25-100BZC/
Document #: 38-05260 Rev. *B
Package
Name
BB165A
Package Type
13 x 15 mm FBGA
Operating
Range
Commercial
Page 17 of 19
CY7C1302V25
Package Diagram
165-ball FBGA (13 x 15 x 1.2 mm) BB165A
51-85122-*C
QDR RAMs and Quad Data Rate RAMs comprise a new family of products developed by Cypress, Hitachi, IDT, Micron, NEC,
and Samsung technology. QDR is a trademark of the QDR Consortium. All product and company names mentioned in this
document are the trademarks of their respective holders.
Document #: 38-05260 Rev. *B
Page 18 of 19
© Cypress Semiconductor Corporation, 2002. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
CY7C1302V25
Document History Page
Document Title: CY7C1302V25 9-Mb Pipelined SRAM with QDR™ Architecture
Document Number: 38-05260
REV.
ECN NO.
Issue Date
Orig. of
Change
Description of Change
**
113867
03/06/02
DSG
Change from Spec number: 38-00924 to 38-05260
*A
115192
05/20/02
RCS
Changed Status From Advanced to Final
Highlighted K and K VIH and VIL requirements
Highlighted data forwarding functionality at 100 MHz
*B
119342
11/13/02
HGK
Removed “Advance Information” tag
Document #: 38-05260 Rev. *B
Page 19 of 19